2 * tegra_i2s.c - Tegra I2S driver
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010 - NVIDIA, Inc.
7 * Based on code copyright/by:
9 * Copyright (c) 2009-2010, NVIDIA Corporation.
10 * Scott Peterson <speterson@nvidia.com>
12 * Copyright (C) 2010 Google, Inc.
13 * Iliyan Malchev <malchev@google.com>
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * version 2 as published by the Free Software Foundation.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
31 #include <linux/clk.h>
32 #include <linux/module.h>
33 #include <linux/debugfs.h>
34 #include <linux/device.h>
35 #include <linux/platform_device.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
39 #include <mach/iomap.h>
40 #include <sound/core.h>
41 #include <sound/pcm.h>
42 #include <sound/pcm_params.h>
43 #include <sound/soc.h>
45 #include "tegra_das.h"
46 #include "tegra_i2s.h"
48 #define DRV_NAME "tegra-i2s"
50 static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
52 __raw_writel(val, i2s->regs + reg);
55 static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
57 return __raw_readl(i2s->regs + reg);
60 #ifdef CONFIG_DEBUG_FS
61 static int tegra_i2s_show(struct seq_file *s, void *unused)
63 #define REG(r) { r, #r }
69 REG(TEGRA_I2S_STATUS),
70 REG(TEGRA_I2S_TIMING),
71 REG(TEGRA_I2S_FIFO_SCR),
72 REG(TEGRA_I2S_PCM_CTRL),
73 REG(TEGRA_I2S_NW_CTRL),
74 REG(TEGRA_I2S_TDM_CTRL),
75 REG(TEGRA_I2S_TDM_TX_RX_CTRL),
79 struct tegra_i2s *i2s = s->private;
82 for (i = 0; i < ARRAY_SIZE(regs); i++) {
83 u32 val = tegra_i2s_read(i2s, regs[i].offset);
84 seq_printf(s, "%s = %08x\n", regs[i].name, val);
90 static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
92 return single_open(file, tegra_i2s_show, inode->i_private);
95 static const struct file_operations tegra_i2s_debug_fops = {
96 .open = tegra_i2s_debug_open,
99 .release = single_release,
102 static void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
104 char name[] = DRV_NAME ".0";
106 snprintf(name, sizeof(name), DRV_NAME".%1d", id);
107 i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
108 i2s, &tegra_i2s_debug_fops);
111 static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
114 debugfs_remove(i2s->debug);
117 static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
121 static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
126 static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
129 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
131 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
132 case SND_SOC_DAIFMT_NB_NF:
138 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
139 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
140 case SND_SOC_DAIFMT_CBS_CFS:
141 i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
143 case SND_SOC_DAIFMT_CBM_CFM:
149 i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK |
150 TEGRA_I2S_CTRL_LRCK_MASK);
151 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
152 case SND_SOC_DAIFMT_DSP_A:
153 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
154 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
156 case SND_SOC_DAIFMT_DSP_B:
157 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
158 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
160 case SND_SOC_DAIFMT_I2S:
161 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
162 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
164 case SND_SOC_DAIFMT_RIGHT_J:
165 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
166 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
168 case SND_SOC_DAIFMT_LEFT_J:
169 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
170 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
179 static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
180 struct snd_pcm_hw_params *params,
181 struct snd_soc_dai *dai)
183 struct device *dev = substream->pcm->card->dev;
184 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
186 int ret, sample_size, srate, i2sclock, bitcnt;
188 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
189 switch (params_format(params)) {
190 case SNDRV_PCM_FORMAT_S16_LE:
191 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
194 case SNDRV_PCM_FORMAT_S24_LE:
195 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
198 case SNDRV_PCM_FORMAT_S32_LE:
199 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
206 srate = params_rate(params);
208 /* Final "* 2" required by Tegra hardware */
209 i2sclock = srate * params_channels(params) * sample_size * 2;
211 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
213 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
217 bitcnt = (i2sclock / (2 * srate)) - 1;
218 if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
220 reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
222 if (i2sclock % (2 * srate))
223 reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
226 clk_enable(i2s->clk_i2s);
228 tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
230 tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
231 TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
232 TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
235 clk_disable(i2s->clk_i2s);
240 static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
242 i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
243 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
246 static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
248 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
249 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
252 static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
254 i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
255 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
258 static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
260 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
261 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
264 static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
265 struct snd_soc_dai *dai)
267 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
270 case SNDRV_PCM_TRIGGER_START:
271 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
272 case SNDRV_PCM_TRIGGER_RESUME:
274 clk_enable(i2s->clk_i2s);
276 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
277 tegra_i2s_start_playback(i2s);
279 tegra_i2s_start_capture(i2s);
281 case SNDRV_PCM_TRIGGER_STOP:
282 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
283 case SNDRV_PCM_TRIGGER_SUSPEND:
284 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
285 tegra_i2s_stop_playback(i2s);
287 tegra_i2s_stop_capture(i2s);
290 clk_disable(i2s->clk_i2s);
299 static int tegra_i2s_probe(struct snd_soc_dai *dai)
301 struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
303 dai->capture_dma_data = &i2s->capture_dma_data;
304 dai->playback_dma_data = &i2s->playback_dma_data;
309 static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
310 .set_fmt = tegra_i2s_set_fmt,
311 .hw_params = tegra_i2s_hw_params,
312 .trigger = tegra_i2s_trigger,
315 struct snd_soc_dai_driver tegra_i2s_dai[] = {
317 .name = DRV_NAME ".0",
318 .probe = tegra_i2s_probe,
322 .rates = SNDRV_PCM_RATE_8000_96000,
323 .formats = SNDRV_PCM_FMTBIT_S16_LE,
328 .rates = SNDRV_PCM_RATE_8000_96000,
329 .formats = SNDRV_PCM_FMTBIT_S16_LE,
331 .ops = &tegra_i2s_dai_ops,
332 .symmetric_rates = 1,
335 .name = DRV_NAME ".1",
336 .probe = tegra_i2s_probe,
340 .rates = SNDRV_PCM_RATE_8000_96000,
341 .formats = SNDRV_PCM_FMTBIT_S16_LE,
346 .rates = SNDRV_PCM_RATE_8000_96000,
347 .formats = SNDRV_PCM_FMTBIT_S16_LE,
349 .ops = &tegra_i2s_dai_ops,
350 .symmetric_rates = 1,
354 static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
356 struct tegra_i2s * i2s;
357 char clk_name[12]; /* tegra-i2s.0 */
358 struct resource *mem, *memregion, *dmareq;
361 if ((pdev->id < 0) ||
362 (pdev->id >= ARRAY_SIZE(tegra_i2s_dai))) {
363 dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
368 * FIXME: Until a codec driver exists for the tegra DAS, hard-code a
369 * 1:1 mapping between audio controllers and audio ports.
371 ret = tegra_das_connect_dap_to_dac(TEGRA_DAS_DAP_ID_1 + pdev->id,
372 TEGRA_DAS_DAP_SEL_DAC1 + pdev->id);
374 dev_err(&pdev->dev, "Can't set up DAP connection\n");
377 ret = tegra_das_connect_dac_to_dap(TEGRA_DAS_DAC_ID_1 + pdev->id,
378 TEGRA_DAS_DAC_SEL_DAP1 + pdev->id);
380 dev_err(&pdev->dev, "Can't set up DAC connection\n");
384 i2s = kzalloc(sizeof(struct tegra_i2s), GFP_KERNEL);
386 dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
390 dev_set_drvdata(&pdev->dev, i2s);
392 snprintf(clk_name, sizeof(clk_name), DRV_NAME ".%d", pdev->id);
393 i2s->clk_i2s = clk_get_sys(clk_name, NULL);
394 if (IS_ERR(i2s->clk_i2s)) {
395 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
396 ret = PTR_ERR(i2s->clk_i2s);
400 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
402 dev_err(&pdev->dev, "No memory resource\n");
407 dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
409 dev_err(&pdev->dev, "No DMA resource\n");
414 memregion = request_mem_region(mem->start, resource_size(mem),
417 dev_err(&pdev->dev, "Memory region already claimed\n");
422 i2s->regs = ioremap(mem->start, resource_size(mem));
424 dev_err(&pdev->dev, "ioremap failed\n");
429 i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
430 i2s->capture_dma_data.wrap = 4;
431 i2s->capture_dma_data.width = 32;
432 i2s->capture_dma_data.req_sel = dmareq->start;
434 i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
435 i2s->playback_dma_data.wrap = 4;
436 i2s->playback_dma_data.width = 32;
437 i2s->playback_dma_data.req_sel = dmareq->start;
439 i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
441 ret = snd_soc_register_dai(&pdev->dev, &tegra_i2s_dai[pdev->id]);
443 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
448 tegra_i2s_debug_add(i2s, pdev->id);
455 release_mem_region(mem->start, resource_size(mem));
457 clk_put(i2s->clk_i2s);
464 static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
466 struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
467 struct resource *res;
469 snd_soc_unregister_dai(&pdev->dev);
471 tegra_i2s_debug_remove(i2s);
475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
476 release_mem_region(res->start, resource_size(res));
478 clk_put(i2s->clk_i2s);
485 static struct platform_driver tegra_i2s_driver = {
488 .owner = THIS_MODULE,
490 .probe = tegra_i2s_platform_probe,
491 .remove = __devexit_p(tegra_i2s_platform_remove),
494 static int __init snd_tegra_i2s_init(void)
496 return platform_driver_register(&tegra_i2s_driver);
498 module_init(snd_tegra_i2s_init);
500 static void __exit snd_tegra_i2s_exit(void)
502 platform_driver_unregister(&tegra_i2s_driver);
504 module_exit(snd_tegra_i2s_exit);
506 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
507 MODULE_DESCRIPTION("Tegra I2S ASoC driver");
508 MODULE_LICENSE("GPL");
509 MODULE_ALIAS("platform:" DRV_NAME);