2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/time.h>
29 #include <linux/fsl/mxs-dma.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/saif.h>
35 #include <asm/mach-types.h>
36 #include <mach/hardware.h>
41 static struct mxs_saif *mxs_saif[2];
44 * SAIF is a little different with other normal SOC DAIs on clock using.
46 * For MXS, two SAIF modules are instantiated on-chip.
47 * Each SAIF has a set of clock pins and can be operating in master
48 * mode simultaneously if they are connected to different off-chip codecs.
49 * Also, one of the two SAIFs can master or drive the clock pins while the
50 * other SAIF, in slave mode, receives clocking from the master SAIF.
51 * This also means that both SAIFs must operate at the same sample rate.
53 * We abstract this as each saif has a master, the master could be
54 * himself or other saifs. In the generic saif driver, saif does not need
55 * to know the different clkmux. Saif only needs to know who is his master
56 * and operating his master to generate the proper clock rate for him.
57 * The master id is provided in mach-specific layer according to different
61 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
62 int clk_id, unsigned int freq, int dir)
64 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
77 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
78 * is provided by other SAIF, we provide a interface here to get its master
80 * Note that the master could be himself.
82 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
84 return mxs_saif[saif->master_id];
88 * Set SAIF clock and MCLK
90 static int mxs_saif_set_clk(struct mxs_saif *saif,
96 struct mxs_saif *master_saif;
98 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
100 /* Set master saif to generate proper clock */
101 master_saif = mxs_saif_get_master(saif);
105 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
107 /* Checking if can playback and capture simutaneously */
108 if (master_saif->ongoing && rate != master_saif->cur_rate) {
110 "can not change clock, master saif%d(rate %d) is ongoing\n",
111 master_saif->id, master_saif->cur_rate);
115 scr = __raw_readl(master_saif->base + SAIF_CTRL);
116 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
117 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
122 * The SAIF clock should be either 384*fs or 512*fs.
123 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
124 * For 32x mclk, set saif clk as 512*fs.
125 * For 48x mclk, set saif clk as 384*fs.
127 * If MCLK is not used, we just set saif clk to 512*fs.
129 clk_prepare_enable(master_saif->clk);
131 if (master_saif->mclk_in_use) {
132 if (mclk % 32 == 0) {
133 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
134 ret = clk_set_rate(master_saif->clk, 512 * rate);
135 } else if (mclk % 48 == 0) {
136 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
137 ret = clk_set_rate(master_saif->clk, 384 * rate);
139 /* SAIF MCLK should be either 32x or 48x */
140 clk_disable_unprepare(master_saif->clk);
144 ret = clk_set_rate(master_saif->clk, 512 * rate);
145 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
148 clk_disable_unprepare(master_saif->clk);
153 master_saif->cur_rate = rate;
155 if (!master_saif->mclk_in_use) {
156 __raw_writel(scr, master_saif->base + SAIF_CTRL);
161 * Program the over-sample rate for MCLK output
163 * The available MCLK range is 32x, 48x... 512x. The rate
164 * could be from 8kHz to 192kH.
166 switch (mclk / rate) {
168 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
171 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
174 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
177 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
180 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
183 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
186 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
189 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
192 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
198 __raw_writel(scr, master_saif->base + SAIF_CTRL);
204 * Put and disable MCLK.
206 int mxs_saif_put_mclk(unsigned int saif_id)
208 struct mxs_saif *saif = mxs_saif[saif_id];
214 stat = __raw_readl(saif->base + SAIF_STAT);
215 if (stat & BM_SAIF_STAT_BUSY) {
216 dev_err(saif->dev, "error: busy\n");
220 clk_disable_unprepare(saif->clk);
222 /* disable MCLK output */
223 __raw_writel(BM_SAIF_CTRL_CLKGATE,
224 saif->base + SAIF_CTRL + MXS_SET_ADDR);
225 __raw_writel(BM_SAIF_CTRL_RUN,
226 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
228 saif->mclk_in_use = 0;
233 * Get MCLK and set clock rate, then enable it
235 * This interface is used for codecs who are using MCLK provided
238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
241 struct mxs_saif *saif = mxs_saif[saif_id];
244 struct mxs_saif *master_saif;
250 __raw_writel(BM_SAIF_CTRL_SFTRST,
251 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
253 /* FIXME: need clear clk gate for register r/w */
254 __raw_writel(BM_SAIF_CTRL_CLKGATE,
255 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
257 master_saif = mxs_saif_get_master(saif);
258 if (saif != master_saif) {
259 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
263 stat = __raw_readl(saif->base + SAIF_STAT);
264 if (stat & BM_SAIF_STAT_BUSY) {
265 dev_err(saif->dev, "error: busy\n");
269 saif->mclk_in_use = 1;
270 ret = mxs_saif_set_clk(saif, mclk, rate);
274 ret = clk_prepare_enable(saif->clk);
278 /* enable MCLK output */
279 __raw_writel(BM_SAIF_CTRL_RUN,
280 saif->base + SAIF_CTRL + MXS_SET_ADDR);
286 * SAIF DAI format configuration.
287 * Should only be called when port is inactive.
289 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
293 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
295 stat = __raw_readl(saif->base + SAIF_STAT);
296 if (stat & BM_SAIF_STAT_BUSY) {
297 dev_err(cpu_dai->dev, "error: busy\n");
301 scr0 = __raw_readl(saif->base + SAIF_CTRL);
302 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
303 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
307 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
308 case SND_SOC_DAIFMT_I2S:
309 /* data frame low 1clk before data */
310 scr |= BM_SAIF_CTRL_DELAY;
311 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
313 case SND_SOC_DAIFMT_LEFT_J:
314 /* data frame high with data */
315 scr &= ~BM_SAIF_CTRL_DELAY;
316 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
317 scr &= ~BM_SAIF_CTRL_JUSTIFY;
323 /* DAI clock inversion */
324 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
325 case SND_SOC_DAIFMT_IB_IF:
326 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
327 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
329 case SND_SOC_DAIFMT_IB_NF:
330 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
331 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
333 case SND_SOC_DAIFMT_NB_IF:
334 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
335 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
337 case SND_SOC_DAIFMT_NB_NF:
338 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
339 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
344 * Note: We simply just support master mode since SAIF TX can only
346 * Here the master is relative to codec side.
347 * Saif internally could be slave when working on EXTMASTER mode.
348 * We just hide this to machine driver.
350 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
351 case SND_SOC_DAIFMT_CBS_CFS:
352 if (saif->id == saif->master_id)
353 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
355 scr |= BM_SAIF_CTRL_SLAVE_MODE;
357 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
366 static int mxs_saif_startup(struct snd_pcm_substream *substream,
367 struct snd_soc_dai *cpu_dai)
369 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
370 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
372 /* clear error status to 0 for each re-open */
373 saif->fifo_underrun = 0;
374 saif->fifo_overrun = 0;
376 /* Clear Reset for normal operations */
377 __raw_writel(BM_SAIF_CTRL_SFTRST,
378 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
380 /* clear clock gate */
381 __raw_writel(BM_SAIF_CTRL_CLKGATE,
382 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
388 * Should only be called when port is inactive.
389 * although can be called multiple times by upper layers.
391 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
392 struct snd_pcm_hw_params *params,
393 struct snd_soc_dai *cpu_dai)
395 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
399 /* mclk should already be set */
400 if (!saif->mclk && saif->mclk_in_use) {
401 dev_err(cpu_dai->dev, "set mclk first\n");
405 stat = __raw_readl(saif->base + SAIF_STAT);
406 if (stat & BM_SAIF_STAT_BUSY) {
407 dev_err(cpu_dai->dev, "error: busy\n");
412 * Set saif clk based on sample rate.
413 * If mclk is used, we also set mclk, if not, saif->mclk is
414 * default 0, means not used.
416 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
418 dev_err(cpu_dai->dev, "unable to get proper clk\n");
422 scr = __raw_readl(saif->base + SAIF_CTRL);
424 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
425 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
426 switch (params_format(params)) {
427 case SNDRV_PCM_FORMAT_S16_LE:
428 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
430 case SNDRV_PCM_FORMAT_S20_3LE:
431 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
432 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
434 case SNDRV_PCM_FORMAT_S24_LE:
435 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
436 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
443 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
445 scr &= ~BM_SAIF_CTRL_READ_MODE;
448 scr |= BM_SAIF_CTRL_READ_MODE;
451 __raw_writel(scr, saif->base + SAIF_CTRL);
455 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
456 struct snd_soc_dai *cpu_dai)
458 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
460 /* enable FIFO error irqs */
461 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
462 saif->base + SAIF_CTRL + MXS_SET_ADDR);
467 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
468 struct snd_soc_dai *cpu_dai)
470 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
471 struct mxs_saif *master_saif;
474 master_saif = mxs_saif_get_master(saif);
479 case SNDRV_PCM_TRIGGER_START:
480 case SNDRV_PCM_TRIGGER_RESUME:
481 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
482 dev_dbg(cpu_dai->dev, "start\n");
484 clk_enable(master_saif->clk);
485 if (!master_saif->mclk_in_use)
486 __raw_writel(BM_SAIF_CTRL_RUN,
487 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
490 * If the saif's master is not himself, we also need to enable
491 * itself clk for its internal basic logic to work.
493 if (saif != master_saif) {
494 clk_enable(saif->clk);
495 __raw_writel(BM_SAIF_CTRL_RUN,
496 saif->base + SAIF_CTRL + MXS_SET_ADDR);
499 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
501 * write a data to saif data register to trigger
504 __raw_writel(0, saif->base + SAIF_DATA);
507 * read a data from saif data register to trigger
510 __raw_readl(saif->base + SAIF_DATA);
513 master_saif->ongoing = 1;
515 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
516 __raw_readl(saif->base + SAIF_CTRL),
517 __raw_readl(saif->base + SAIF_STAT));
519 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
520 __raw_readl(master_saif->base + SAIF_CTRL),
521 __raw_readl(master_saif->base + SAIF_STAT));
523 case SNDRV_PCM_TRIGGER_SUSPEND:
524 case SNDRV_PCM_TRIGGER_STOP:
525 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
526 dev_dbg(cpu_dai->dev, "stop\n");
528 /* wait a while for the current sample to complete */
529 delay = USEC_PER_SEC / master_saif->cur_rate;
531 if (!master_saif->mclk_in_use) {
532 __raw_writel(BM_SAIF_CTRL_RUN,
533 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
536 clk_disable(master_saif->clk);
538 if (saif != master_saif) {
539 __raw_writel(BM_SAIF_CTRL_RUN,
540 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
542 clk_disable(saif->clk);
545 master_saif->ongoing = 0;
555 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
556 #define MXS_SAIF_FORMATS \
557 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
558 SNDRV_PCM_FMTBIT_S24_LE)
560 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
561 .startup = mxs_saif_startup,
562 .trigger = mxs_saif_trigger,
563 .prepare = mxs_saif_prepare,
564 .hw_params = mxs_saif_hw_params,
565 .set_sysclk = mxs_saif_set_dai_sysclk,
566 .set_fmt = mxs_saif_set_dai_fmt,
569 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
571 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
573 snd_soc_dai_set_drvdata(dai, saif);
578 static struct snd_soc_dai_driver mxs_saif_dai = {
580 .probe = mxs_saif_dai_probe,
584 .rates = MXS_SAIF_RATES,
585 .formats = MXS_SAIF_FORMATS,
590 .rates = MXS_SAIF_RATES,
591 .formats = MXS_SAIF_FORMATS,
593 .ops = &mxs_saif_dai_ops,
596 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
598 struct mxs_saif *saif = dev_id;
601 stat = __raw_readl(saif->base + SAIF_STAT);
602 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
603 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
606 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
607 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
608 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
609 saif->base + SAIF_STAT + MXS_CLR_ADDR);
612 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
613 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
614 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
615 saif->base + SAIF_STAT + MXS_CLR_ADDR);
618 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
619 __raw_readl(saif->base + SAIF_CTRL),
620 __raw_readl(saif->base + SAIF_STAT));
625 static int __devinit mxs_saif_probe(struct platform_device *pdev)
627 struct device_node *np = pdev->dev.of_node;
628 struct resource *iores, *dmares;
629 struct mxs_saif *saif;
630 struct mxs_saif_platform_data *pdata;
634 if (!np && pdev->id >= ARRAY_SIZE(mxs_saif))
637 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
642 struct device_node *master;
643 saif->id = of_alias_get_id(np, "saif");
647 * If there is no "fsl,saif-master" phandle, it's a saif
648 * master. Otherwise, it's a slave and its phandle points
651 master = of_parse_phandle(np, "fsl,saif-master", 0);
653 saif->master_id = saif->id;
655 saif->master_id = of_alias_get_id(master, "saif");
656 if (saif->master_id < 0)
657 return saif->master_id;
661 pdata = pdev->dev.platform_data;
662 if (pdata && !pdata->master_mode)
663 saif->master_id = pdata->master_id;
665 saif->master_id = saif->id;
668 if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) {
669 dev_err(&pdev->dev, "get wrong master id\n");
673 mxs_saif[saif->id] = saif;
675 saif->clk = clk_get(&pdev->dev, NULL);
676 if (IS_ERR(saif->clk)) {
677 ret = PTR_ERR(saif->clk);
678 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
683 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685 saif->base = devm_request_and_ioremap(&pdev->dev, iores);
687 dev_err(&pdev->dev, "ioremap failed\n");
689 goto failed_get_resource;
692 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
695 * TODO: This is a temporary solution and should be changed
696 * to use generic DMA binding later when the helplers get in.
698 ret = of_property_read_u32(np, "fsl,saif-dma-channel",
699 &saif->dma_param.chan_num);
701 dev_err(&pdev->dev, "failed to get dma channel\n");
702 goto failed_get_resource;
705 saif->dma_param.chan_num = dmares->start;
708 saif->irq = platform_get_irq(pdev, 0);
711 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
713 goto failed_get_resource;
716 saif->dev = &pdev->dev;
717 ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0,
720 dev_err(&pdev->dev, "failed to request irq\n");
721 goto failed_get_resource;
724 saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
725 if (saif->dma_param.chan_irq < 0) {
726 ret = saif->dma_param.chan_irq;
727 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
729 goto failed_get_resource;
732 platform_set_drvdata(pdev, saif);
734 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
736 dev_err(&pdev->dev, "register DAI failed\n");
737 goto failed_get_resource;
740 ret = mxs_pcm_platform_register(&pdev->dev);
742 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
743 goto failed_pdev_alloc;
749 snd_soc_unregister_dai(&pdev->dev);
756 static int __devexit mxs_saif_remove(struct platform_device *pdev)
758 struct mxs_saif *saif = platform_get_drvdata(pdev);
760 mxs_pcm_platform_unregister(&pdev->dev);
761 snd_soc_unregister_dai(&pdev->dev);
767 static const struct of_device_id mxs_saif_dt_ids[] = {
768 { .compatible = "fsl,imx28-saif", },
771 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
773 static struct platform_driver mxs_saif_driver = {
774 .probe = mxs_saif_probe,
775 .remove = __devexit_p(mxs_saif_remove),
779 .owner = THIS_MODULE,
780 .of_match_table = mxs_saif_dt_ids,
784 module_platform_driver(mxs_saif_driver);
786 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
787 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
788 MODULE_LICENSE("GPL");