2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM8994_NUM_DRC 3
42 #define WM8994_NUM_EQ 3
47 } wm8994_vu_bits[] = {
48 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
49 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
50 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
51 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
52 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
53 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
54 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
55 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
56 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
57 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
59 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
60 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
61 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
62 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
63 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
64 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
65 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
66 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
67 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
68 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
69 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
70 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
71 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
72 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
73 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
74 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
77 static int wm8994_drc_base[] = {
83 static int wm8994_retune_mobile_base[] = {
84 WM8994_AIF1_DAC1_EQ_GAINS_1,
85 WM8994_AIF1_DAC2_EQ_GAINS_1,
86 WM8994_AIF2_EQ_GAINS_1,
89 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
91 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
92 struct wm8994 *control = codec->control_data;
106 case WM8994_INTERRUPT_STATUS_1:
107 case WM8994_INTERRUPT_STATUS_2:
108 case WM8994_INTERRUPT_RAW_STATUS_2:
111 case WM8958_DSP2_PROGRAM:
112 case WM8958_DSP2_CONFIG:
113 case WM8958_DSP2_EXECCONTROL:
114 if (control->type == WM8958)
123 if (reg >= WM8994_CACHE_SIZE)
125 return wm8994_access_masks[reg].readable != 0;
128 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
130 if (reg >= WM8994_CACHE_SIZE)
134 case WM8994_SOFTWARE_RESET:
135 case WM8994_CHIP_REVISION:
136 case WM8994_DC_SERVO_1:
137 case WM8994_DC_SERVO_READBACK:
138 case WM8994_RATE_STATUS:
141 case WM8958_DSP2_EXECCONTROL:
142 case WM8958_MIC_DETECT_3:
143 case WM8994_DC_SERVO_4E:
150 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
155 BUG_ON(reg > WM8994_MAX_REGISTER);
157 if (!wm8994_volatile(codec, reg)) {
158 ret = snd_soc_cache_write(codec, reg, value);
160 dev_err(codec->dev, "Cache write to %x failed: %d\n",
164 return wm8994_reg_write(codec->control_data, reg, value);
167 static unsigned int wm8994_read(struct snd_soc_codec *codec,
173 BUG_ON(reg > WM8994_MAX_REGISTER);
175 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
176 reg < codec->driver->reg_cache_size) {
177 ret = snd_soc_cache_read(codec, reg, &val);
181 dev_err(codec->dev, "Cache read from %x failed: %d\n",
185 return wm8994_reg_read(codec->control_data, reg);
188 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
190 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
200 switch (wm8994->sysclk[aif]) {
201 case WM8994_SYSCLK_MCLK1:
202 rate = wm8994->mclk[0];
205 case WM8994_SYSCLK_MCLK2:
207 rate = wm8994->mclk[1];
210 case WM8994_SYSCLK_FLL1:
212 rate = wm8994->fll[0].out;
215 case WM8994_SYSCLK_FLL2:
217 rate = wm8994->fll[1].out;
224 if (rate >= 13500000) {
226 reg1 |= WM8994_AIF1CLK_DIV;
228 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
232 wm8994->aifclk[aif] = rate;
234 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
235 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
241 static int configure_clock(struct snd_soc_codec *codec)
243 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
246 /* Bring up the AIF clocks first */
247 configure_aif_clock(codec, 0);
248 configure_aif_clock(codec, 1);
250 /* Then switch CLK_SYS over to the higher of them; a change
251 * can only happen as a result of a clocking change which can
252 * only be made outside of DAPM so we can safely redo the
256 /* If they're equal it doesn't matter which is used */
257 if (wm8994->aifclk[0] == wm8994->aifclk[1])
260 if (wm8994->aifclk[0] < wm8994->aifclk[1])
261 new = WM8994_SYSCLK_SRC;
265 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
266 WM8994_SYSCLK_SRC, new);
270 snd_soc_dapm_sync(&codec->dapm);
275 static int check_clk_sys(struct snd_soc_dapm_widget *source,
276 struct snd_soc_dapm_widget *sink)
278 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
281 /* Check what we're currently using for CLK_SYS */
282 if (reg & WM8994_SYSCLK_SRC)
287 return strcmp(source->name, clk) == 0;
290 static const char *sidetone_hpf_text[] = {
291 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
294 static const struct soc_enum sidetone_hpf =
295 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
297 static const char *adc_hpf_text[] = {
298 "HiFi", "Voice 1", "Voice 2", "Voice 3"
301 static const struct soc_enum aif1adc1_hpf =
302 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
304 static const struct soc_enum aif1adc2_hpf =
305 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
307 static const struct soc_enum aif2adc_hpf =
308 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
310 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
311 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
312 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
313 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
314 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
316 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
318 #define WM8994_DRC_SWITCH(xname, reg, shift) \
319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
320 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
321 .put = wm8994_put_drc_sw, \
322 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
324 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
325 struct snd_ctl_elem_value *ucontrol)
327 struct soc_mixer_control *mc =
328 (struct soc_mixer_control *)kcontrol->private_value;
329 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
332 /* Can't enable both ADC and DAC paths simultaneously */
333 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
334 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
335 WM8994_AIF1ADC1R_DRC_ENA_MASK;
337 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
339 ret = snd_soc_read(codec, mc->reg);
345 return snd_soc_put_volsw(kcontrol, ucontrol);
348 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
350 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
351 struct wm8994_pdata *pdata = wm8994->pdata;
352 int base = wm8994_drc_base[drc];
353 int cfg = wm8994->drc_cfg[drc];
356 /* Save any enables; the configuration should clear them. */
357 save = snd_soc_read(codec, base);
358 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
359 WM8994_AIF1ADC1R_DRC_ENA;
361 for (i = 0; i < WM8994_DRC_REGS; i++)
362 snd_soc_update_bits(codec, base + i, 0xffff,
363 pdata->drc_cfgs[cfg].regs[i]);
365 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
366 WM8994_AIF1ADC1L_DRC_ENA |
367 WM8994_AIF1ADC1R_DRC_ENA, save);
370 /* Icky as hell but saves code duplication */
371 static int wm8994_get_drc(const char *name)
373 if (strcmp(name, "AIF1DRC1 Mode") == 0)
375 if (strcmp(name, "AIF1DRC2 Mode") == 0)
377 if (strcmp(name, "AIF2DRC Mode") == 0)
382 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
387 struct wm8994_pdata *pdata = wm8994->pdata;
388 int drc = wm8994_get_drc(kcontrol->id.name);
389 int value = ucontrol->value.integer.value[0];
394 if (value >= pdata->num_drc_cfgs)
397 wm8994->drc_cfg[drc] = value;
399 wm8994_set_drc(codec, drc);
404 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
405 struct snd_ctl_elem_value *ucontrol)
407 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
408 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
409 int drc = wm8994_get_drc(kcontrol->id.name);
411 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
416 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
418 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
419 struct wm8994_pdata *pdata = wm8994->pdata;
420 int base = wm8994_retune_mobile_base[block];
421 int iface, best, best_val, save, i, cfg;
423 if (!pdata || !wm8994->num_retune_mobile_texts)
438 /* Find the version of the currently selected configuration
439 * with the nearest sample rate. */
440 cfg = wm8994->retune_mobile_cfg[block];
443 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
444 if (strcmp(pdata->retune_mobile_cfgs[i].name,
445 wm8994->retune_mobile_texts[cfg]) == 0 &&
446 abs(pdata->retune_mobile_cfgs[i].rate
447 - wm8994->dac_rates[iface]) < best_val) {
449 best_val = abs(pdata->retune_mobile_cfgs[i].rate
450 - wm8994->dac_rates[iface]);
454 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
456 pdata->retune_mobile_cfgs[best].name,
457 pdata->retune_mobile_cfgs[best].rate,
458 wm8994->dac_rates[iface]);
460 /* The EQ will be disabled while reconfiguring it, remember the
461 * current configuration.
463 save = snd_soc_read(codec, base);
464 save &= WM8994_AIF1DAC1_EQ_ENA;
466 for (i = 0; i < WM8994_EQ_REGS; i++)
467 snd_soc_update_bits(codec, base + i, 0xffff,
468 pdata->retune_mobile_cfgs[best].regs[i]);
470 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
473 /* Icky as hell but saves code duplication */
474 static int wm8994_get_retune_mobile_block(const char *name)
476 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
478 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
480 if (strcmp(name, "AIF2 EQ Mode") == 0)
485 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 struct wm8994_pdata *pdata = wm8994->pdata;
491 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
492 int value = ucontrol->value.integer.value[0];
497 if (value >= pdata->num_retune_mobile_cfgs)
500 wm8994->retune_mobile_cfg[block] = value;
502 wm8994_set_retune_mobile(codec, block);
507 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol)
510 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
511 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
512 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
514 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
519 static const char *aif_chan_src_text[] = {
523 static const struct soc_enum aif1adcl_src =
524 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
526 static const struct soc_enum aif1adcr_src =
527 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
529 static const struct soc_enum aif2adcl_src =
530 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
532 static const struct soc_enum aif2adcr_src =
533 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
535 static const struct soc_enum aif1dacl_src =
536 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
538 static const struct soc_enum aif1dacr_src =
539 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
541 static const struct soc_enum aif2dacl_src =
542 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
544 static const struct soc_enum aif2dacr_src =
545 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
547 static const char *osr_text[] = {
548 "Low Power", "High Performance",
551 static const struct soc_enum dac_osr =
552 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
554 static const struct soc_enum adc_osr =
555 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
557 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
558 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
559 WM8994_AIF1_ADC1_RIGHT_VOLUME,
560 1, 119, 0, digital_tlv),
561 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
562 WM8994_AIF1_ADC2_RIGHT_VOLUME,
563 1, 119, 0, digital_tlv),
564 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
565 WM8994_AIF2_ADC_RIGHT_VOLUME,
566 1, 119, 0, digital_tlv),
568 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
569 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
570 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
571 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
573 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
574 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
575 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
576 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
578 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
579 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
580 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
581 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
582 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
583 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
585 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
586 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
588 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
589 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
590 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
592 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
593 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
594 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
596 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
597 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
598 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
600 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
601 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
602 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
604 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
606 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
608 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
610 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
612 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
613 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
615 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
616 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
618 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
619 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
621 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
622 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
624 SOC_ENUM("ADC OSR", adc_osr),
625 SOC_ENUM("DAC OSR", dac_osr),
627 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
628 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
629 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
630 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
632 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
633 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
634 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
635 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
637 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
638 6, 1, 1, wm_hubs_spkmix_tlv),
639 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
640 2, 1, 1, wm_hubs_spkmix_tlv),
642 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
643 6, 1, 1, wm_hubs_spkmix_tlv),
644 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
645 2, 1, 1, wm_hubs_spkmix_tlv),
647 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
648 10, 15, 0, wm8994_3d_tlv),
649 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
651 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
652 10, 15, 0, wm8994_3d_tlv),
653 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
655 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
656 10, 15, 0, wm8994_3d_tlv),
657 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
661 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
662 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
666 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
668 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
670 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
673 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
675 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
677 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
679 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
681 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
684 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
686 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
688 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
690 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
692 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
696 static const char *wm8958_ng_text[] = {
697 "30ms", "125ms", "250ms", "500ms",
700 static const struct soc_enum wm8958_aif1dac1_ng_hold =
701 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
702 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
704 static const struct soc_enum wm8958_aif1dac2_ng_hold =
705 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
706 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
708 static const struct soc_enum wm8958_aif2dac_ng_hold =
709 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
710 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
712 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
713 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
715 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
716 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
717 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
718 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
719 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
722 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
723 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
724 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
725 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
726 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
729 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
730 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
731 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
732 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
733 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
737 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
738 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
740 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
744 static int clk_sys_event(struct snd_soc_dapm_widget *w,
745 struct snd_kcontrol *kcontrol, int event)
747 struct snd_soc_codec *codec = w->codec;
750 case SND_SOC_DAPM_PRE_PMU:
751 return configure_clock(codec);
753 case SND_SOC_DAPM_POST_PMD:
754 configure_clock(codec);
761 static void vmid_reference(struct snd_soc_codec *codec)
763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
765 pm_runtime_get_sync(codec->dev);
767 wm8994->vmid_refcount++;
769 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
770 wm8994->vmid_refcount);
772 if (wm8994->vmid_refcount == 1) {
773 /* Startup bias, VMID ramp & buffer */
774 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
775 WM8994_STARTUP_BIAS_ENA |
776 WM8994_VMID_BUF_ENA |
777 WM8994_VMID_RAMP_MASK,
778 WM8994_STARTUP_BIAS_ENA |
779 WM8994_VMID_BUF_ENA |
780 (0x3 << WM8994_VMID_RAMP_SHIFT));
782 /* Main bias enable, VMID=2x40k */
783 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
785 WM8994_VMID_SEL_MASK,
786 WM8994_BIAS_ENA | 0x2);
792 static void vmid_dereference(struct snd_soc_codec *codec)
794 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
796 wm8994->vmid_refcount--;
798 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
799 wm8994->vmid_refcount);
801 if (wm8994->vmid_refcount == 0) {
802 /* Switch over to startup biases */
803 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
805 WM8994_STARTUP_BIAS_ENA |
806 WM8994_VMID_BUF_ENA |
807 WM8994_VMID_RAMP_MASK,
809 WM8994_STARTUP_BIAS_ENA |
810 WM8994_VMID_BUF_ENA |
811 (1 << WM8994_VMID_RAMP_SHIFT));
813 /* Disable main biases */
814 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
816 WM8994_VMID_SEL_MASK, 0);
819 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
820 WM8994_LINEOUT1_DISCH |
821 WM8994_LINEOUT2_DISCH,
822 WM8994_LINEOUT1_DISCH |
823 WM8994_LINEOUT2_DISCH);
827 /* Switch off startup biases */
828 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
830 WM8994_STARTUP_BIAS_ENA |
831 WM8994_VMID_BUF_ENA |
832 WM8994_VMID_RAMP_MASK, 0);
835 pm_runtime_put(codec->dev);
838 static int vmid_event(struct snd_soc_dapm_widget *w,
839 struct snd_kcontrol *kcontrol, int event)
841 struct snd_soc_codec *codec = w->codec;
844 case SND_SOC_DAPM_PRE_PMU:
845 vmid_reference(codec);
848 case SND_SOC_DAPM_POST_PMD:
849 vmid_dereference(codec);
856 static void wm8994_update_class_w(struct snd_soc_codec *codec)
858 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
860 int source = 0; /* GCC flow analysis can't track enable */
863 /* Only support direct DAC->headphone paths */
864 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
865 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
866 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
870 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
871 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
872 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
876 /* We also need the same setting for L/R and only one path */
877 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
879 case WM8994_AIF2DACL_TO_DAC1L:
880 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
881 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
883 case WM8994_AIF1DAC2L_TO_DAC1L:
884 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
885 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
887 case WM8994_AIF1DAC1L_TO_DAC1L:
888 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
889 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
892 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
897 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
899 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
904 dev_dbg(codec->dev, "Class W enabled\n");
905 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
907 WM8994_CP_DYN_SRC_SEL_MASK,
908 source | WM8994_CP_DYN_PWR);
909 wm8994->hubs.class_w = true;
912 dev_dbg(codec->dev, "Class W disabled\n");
913 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
914 WM8994_CP_DYN_PWR, 0);
915 wm8994->hubs.class_w = false;
919 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
920 struct snd_kcontrol *kcontrol, int event)
922 struct snd_soc_codec *codec = w->codec;
923 struct wm8994 *control = codec->control_data;
924 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
930 switch (control->type) {
933 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
940 case SND_SOC_DAPM_PRE_PMU:
941 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
942 if ((val & WM8994_AIF1ADCL_SRC) &&
943 (val & WM8994_AIF1ADCR_SRC))
944 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
945 else if (!(val & WM8994_AIF1ADCL_SRC) &&
946 !(val & WM8994_AIF1ADCR_SRC))
947 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
949 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
950 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
952 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
953 if ((val & WM8994_AIF1DACL_SRC) &&
954 (val & WM8994_AIF1DACR_SRC))
955 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
956 else if (!(val & WM8994_AIF1DACL_SRC) &&
957 !(val & WM8994_AIF1DACR_SRC))
958 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
960 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
961 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
963 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
965 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
967 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
968 WM8994_AIF1DSPCLK_ENA |
969 WM8994_SYSDSPCLK_ENA,
970 WM8994_AIF1DSPCLK_ENA |
971 WM8994_SYSDSPCLK_ENA);
972 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
973 WM8994_AIF1ADC1R_ENA |
974 WM8994_AIF1ADC1L_ENA |
975 WM8994_AIF1ADC2R_ENA |
976 WM8994_AIF1ADC2L_ENA);
977 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
978 WM8994_AIF1DAC1R_ENA |
979 WM8994_AIF1DAC1L_ENA |
980 WM8994_AIF1DAC2R_ENA |
981 WM8994_AIF1DAC2L_ENA);
984 case SND_SOC_DAPM_POST_PMU:
985 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
986 snd_soc_write(codec, wm8994_vu_bits[i].reg,
988 wm8994_vu_bits[i].reg));
991 case SND_SOC_DAPM_PRE_PMD:
992 case SND_SOC_DAPM_POST_PMD:
993 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
995 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
998 val = snd_soc_read(codec, WM8994_CLOCKING_1);
999 if (val & WM8994_AIF2DSPCLK_ENA)
1000 val = WM8994_SYSDSPCLK_ENA;
1003 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1004 WM8994_SYSDSPCLK_ENA |
1005 WM8994_AIF1DSPCLK_ENA, val);
1012 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1013 struct snd_kcontrol *kcontrol, int event)
1015 struct snd_soc_codec *codec = w->codec;
1022 case SND_SOC_DAPM_PRE_PMU:
1023 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1024 if ((val & WM8994_AIF2ADCL_SRC) &&
1025 (val & WM8994_AIF2ADCR_SRC))
1026 adc = WM8994_AIF2ADCR_ENA;
1027 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1028 !(val & WM8994_AIF2ADCR_SRC))
1029 adc = WM8994_AIF2ADCL_ENA;
1031 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1034 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1035 if ((val & WM8994_AIF2DACL_SRC) &&
1036 (val & WM8994_AIF2DACR_SRC))
1037 dac = WM8994_AIF2DACR_ENA;
1038 else if (!(val & WM8994_AIF2DACL_SRC) &&
1039 !(val & WM8994_AIF2DACR_SRC))
1040 dac = WM8994_AIF2DACL_ENA;
1042 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1044 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1045 WM8994_AIF2ADCL_ENA |
1046 WM8994_AIF2ADCR_ENA, adc);
1047 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1048 WM8994_AIF2DACL_ENA |
1049 WM8994_AIF2DACR_ENA, dac);
1050 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1051 WM8994_AIF2DSPCLK_ENA |
1052 WM8994_SYSDSPCLK_ENA,
1053 WM8994_AIF2DSPCLK_ENA |
1054 WM8994_SYSDSPCLK_ENA);
1055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1056 WM8994_AIF2ADCL_ENA |
1057 WM8994_AIF2ADCR_ENA,
1058 WM8994_AIF2ADCL_ENA |
1059 WM8994_AIF2ADCR_ENA);
1060 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1061 WM8994_AIF2DACL_ENA |
1062 WM8994_AIF2DACR_ENA,
1063 WM8994_AIF2DACL_ENA |
1064 WM8994_AIF2DACR_ENA);
1067 case SND_SOC_DAPM_POST_PMU:
1068 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1069 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1071 wm8994_vu_bits[i].reg));
1074 case SND_SOC_DAPM_PRE_PMD:
1075 case SND_SOC_DAPM_POST_PMD:
1076 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1077 WM8994_AIF2DACL_ENA |
1078 WM8994_AIF2DACR_ENA, 0);
1079 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1080 WM8994_AIF2ADCL_ENA |
1081 WM8994_AIF2ADCR_ENA, 0);
1083 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1084 if (val & WM8994_AIF1DSPCLK_ENA)
1085 val = WM8994_SYSDSPCLK_ENA;
1088 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1089 WM8994_SYSDSPCLK_ENA |
1090 WM8994_AIF2DSPCLK_ENA, val);
1097 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1098 struct snd_kcontrol *kcontrol, int event)
1100 struct snd_soc_codec *codec = w->codec;
1101 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1104 case SND_SOC_DAPM_PRE_PMU:
1105 wm8994->aif1clk_enable = 1;
1107 case SND_SOC_DAPM_POST_PMD:
1108 wm8994->aif1clk_disable = 1;
1115 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1116 struct snd_kcontrol *kcontrol, int event)
1118 struct snd_soc_codec *codec = w->codec;
1119 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1122 case SND_SOC_DAPM_PRE_PMU:
1123 wm8994->aif2clk_enable = 1;
1125 case SND_SOC_DAPM_POST_PMD:
1126 wm8994->aif2clk_disable = 1;
1133 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1134 struct snd_kcontrol *kcontrol, int event)
1136 struct snd_soc_codec *codec = w->codec;
1137 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1140 case SND_SOC_DAPM_PRE_PMU:
1141 if (wm8994->aif1clk_enable) {
1142 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1143 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1144 WM8994_AIF1CLK_ENA_MASK,
1145 WM8994_AIF1CLK_ENA);
1146 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1147 wm8994->aif1clk_enable = 0;
1149 if (wm8994->aif2clk_enable) {
1150 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1151 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1152 WM8994_AIF2CLK_ENA_MASK,
1153 WM8994_AIF2CLK_ENA);
1154 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1155 wm8994->aif2clk_enable = 0;
1160 /* We may also have postponed startup of DSP, handle that. */
1161 wm8958_aif_ev(w, kcontrol, event);
1166 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1167 struct snd_kcontrol *kcontrol, int event)
1169 struct snd_soc_codec *codec = w->codec;
1170 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1173 case SND_SOC_DAPM_POST_PMD:
1174 if (wm8994->aif1clk_disable) {
1175 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1176 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1177 WM8994_AIF1CLK_ENA_MASK, 0);
1178 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1179 wm8994->aif1clk_disable = 0;
1181 if (wm8994->aif2clk_disable) {
1182 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1183 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1184 WM8994_AIF2CLK_ENA_MASK, 0);
1185 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1186 wm8994->aif2clk_disable = 0;
1194 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1195 struct snd_kcontrol *kcontrol, int event)
1197 late_enable_ev(w, kcontrol, event);
1201 static int micbias_ev(struct snd_soc_dapm_widget *w,
1202 struct snd_kcontrol *kcontrol, int event)
1204 late_enable_ev(w, kcontrol, event);
1208 static int dac_ev(struct snd_soc_dapm_widget *w,
1209 struct snd_kcontrol *kcontrol, int event)
1211 struct snd_soc_codec *codec = w->codec;
1212 unsigned int mask = 1 << w->shift;
1214 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1219 static const char *hp_mux_text[] = {
1224 #define WM8994_HP_ENUM(xname, xenum) \
1225 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1226 .info = snd_soc_info_enum_double, \
1227 .get = snd_soc_dapm_get_enum_double, \
1228 .put = wm8994_put_hp_enum, \
1229 .private_value = (unsigned long)&xenum }
1231 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1232 struct snd_ctl_elem_value *ucontrol)
1234 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1235 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1236 struct snd_soc_codec *codec = w->codec;
1239 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1241 wm8994_update_class_w(codec);
1246 static const struct soc_enum hpl_enum =
1247 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1249 static const struct snd_kcontrol_new hpl_mux =
1250 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1252 static const struct soc_enum hpr_enum =
1253 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1255 static const struct snd_kcontrol_new hpr_mux =
1256 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1258 static const char *adc_mux_text[] = {
1263 static const struct soc_enum adc_enum =
1264 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1266 static const struct snd_kcontrol_new adcl_mux =
1267 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1269 static const struct snd_kcontrol_new adcr_mux =
1270 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1272 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1273 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1274 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1275 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1276 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1277 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1280 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1281 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1282 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1283 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1284 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1285 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1288 /* Debugging; dump chip status after DAPM transitions */
1289 static int post_ev(struct snd_soc_dapm_widget *w,
1290 struct snd_kcontrol *kcontrol, int event)
1292 struct snd_soc_codec *codec = w->codec;
1293 dev_dbg(codec->dev, "SRC status: %x\n",
1295 WM8994_RATE_STATUS));
1299 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1300 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1302 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1306 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1307 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1309 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1313 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1314 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1316 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1320 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1321 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1323 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1327 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1328 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1330 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1332 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1334 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1336 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1340 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1341 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1343 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1345 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1347 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1349 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1353 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1354 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1355 .info = snd_soc_info_volsw, \
1356 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1357 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1359 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1360 struct snd_ctl_elem_value *ucontrol)
1362 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1363 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1364 struct snd_soc_codec *codec = w->codec;
1367 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1369 wm8994_update_class_w(codec);
1374 static const struct snd_kcontrol_new dac1l_mix[] = {
1375 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1377 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1379 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1381 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1383 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1387 static const struct snd_kcontrol_new dac1r_mix[] = {
1388 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1390 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1392 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1394 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1396 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1400 static const char *sidetone_text[] = {
1401 "ADC/DMIC1", "DMIC2",
1404 static const struct soc_enum sidetone1_enum =
1405 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1407 static const struct snd_kcontrol_new sidetone1_mux =
1408 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1410 static const struct soc_enum sidetone2_enum =
1411 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1413 static const struct snd_kcontrol_new sidetone2_mux =
1414 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1416 static const char *aif1dac_text[] = {
1417 "AIF1DACDAT", "AIF3DACDAT",
1420 static const struct soc_enum aif1dac_enum =
1421 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1423 static const struct snd_kcontrol_new aif1dac_mux =
1424 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1426 static const char *aif2dac_text[] = {
1427 "AIF2DACDAT", "AIF3DACDAT",
1430 static const struct soc_enum aif2dac_enum =
1431 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1433 static const struct snd_kcontrol_new aif2dac_mux =
1434 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1436 static const char *aif2adc_text[] = {
1437 "AIF2ADCDAT", "AIF3DACDAT",
1440 static const struct soc_enum aif2adc_enum =
1441 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1443 static const struct snd_kcontrol_new aif2adc_mux =
1444 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1446 static const char *aif3adc_text[] = {
1447 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1450 static const struct soc_enum wm8994_aif3adc_enum =
1451 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1453 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1454 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1456 static const struct soc_enum wm8958_aif3adc_enum =
1457 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1459 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1460 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1462 static const char *mono_pcm_out_text[] = {
1463 "None", "AIF2ADCL", "AIF2ADCR",
1466 static const struct soc_enum mono_pcm_out_enum =
1467 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1469 static const struct snd_kcontrol_new mono_pcm_out_mux =
1470 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1472 static const char *aif2dac_src_text[] = {
1476 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1477 static const struct soc_enum aif2dacl_src_enum =
1478 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1480 static const struct snd_kcontrol_new aif2dacl_src_mux =
1481 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1483 static const struct soc_enum aif2dacr_src_enum =
1484 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1486 static const struct snd_kcontrol_new aif2dacr_src_mux =
1487 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1489 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1490 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1491 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1492 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1495 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1496 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1497 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1498 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1499 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1500 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1501 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1502 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1503 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1504 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1506 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1507 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1508 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1509 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1510 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1511 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1512 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1513 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1514 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1515 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1517 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1520 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1521 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1522 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1523 SND_SOC_DAPM_PRE_PMD),
1524 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1525 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1526 SND_SOC_DAPM_PRE_PMD),
1527 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1528 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1529 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1530 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1531 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1532 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1533 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1536 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1537 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1538 dac_ev, SND_SOC_DAPM_PRE_PMU),
1539 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1540 dac_ev, SND_SOC_DAPM_PRE_PMU),
1541 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1542 dac_ev, SND_SOC_DAPM_PRE_PMU),
1543 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1544 dac_ev, SND_SOC_DAPM_PRE_PMU),
1547 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1548 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1549 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1550 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1551 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1554 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1555 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1556 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1557 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1558 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1561 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1562 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1563 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1566 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1567 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1568 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1569 SND_SOC_DAPM_INPUT("Clock"),
1571 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1572 SND_SOC_DAPM_PRE_PMU),
1573 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1574 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1576 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1577 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1579 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1580 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1581 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1583 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1584 0, SND_SOC_NOPM, 9, 0),
1585 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1586 0, SND_SOC_NOPM, 8, 0),
1587 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1588 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1589 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1590 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1591 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1592 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1594 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1595 0, SND_SOC_NOPM, 11, 0),
1596 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1597 0, SND_SOC_NOPM, 10, 0),
1598 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1599 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1600 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1601 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1602 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1603 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1605 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1606 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1607 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1608 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1610 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1611 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1612 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1613 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1615 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1616 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1617 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1618 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1620 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1621 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1623 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1624 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1625 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1626 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1628 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1629 SND_SOC_NOPM, 13, 0),
1630 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1631 SND_SOC_NOPM, 12, 0),
1632 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1633 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1634 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1635 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1636 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1637 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1639 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1640 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1641 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1642 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1644 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1645 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1646 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1648 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1649 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1651 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1653 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1654 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1655 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1656 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1658 /* Power is done with the muxes since the ADC power also controls the
1659 * downsampling chain, the chip will automatically manage the analogue
1660 * specific portions.
1662 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1663 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1665 SND_SOC_DAPM_POST("Debug log", post_ev),
1668 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1669 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1672 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1673 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1674 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1675 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1676 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1679 static const struct snd_soc_dapm_route intercon[] = {
1680 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1681 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1683 { "DSP1CLK", NULL, "CLK_SYS" },
1684 { "DSP2CLK", NULL, "CLK_SYS" },
1685 { "DSPINTCLK", NULL, "CLK_SYS" },
1687 { "AIF1ADC1L", NULL, "AIF1CLK" },
1688 { "AIF1ADC1L", NULL, "DSP1CLK" },
1689 { "AIF1ADC1R", NULL, "AIF1CLK" },
1690 { "AIF1ADC1R", NULL, "DSP1CLK" },
1691 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1693 { "AIF1DAC1L", NULL, "AIF1CLK" },
1694 { "AIF1DAC1L", NULL, "DSP1CLK" },
1695 { "AIF1DAC1R", NULL, "AIF1CLK" },
1696 { "AIF1DAC1R", NULL, "DSP1CLK" },
1697 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1699 { "AIF1ADC2L", NULL, "AIF1CLK" },
1700 { "AIF1ADC2L", NULL, "DSP1CLK" },
1701 { "AIF1ADC2R", NULL, "AIF1CLK" },
1702 { "AIF1ADC2R", NULL, "DSP1CLK" },
1703 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1705 { "AIF1DAC2L", NULL, "AIF1CLK" },
1706 { "AIF1DAC2L", NULL, "DSP1CLK" },
1707 { "AIF1DAC2R", NULL, "AIF1CLK" },
1708 { "AIF1DAC2R", NULL, "DSP1CLK" },
1709 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1711 { "AIF2ADCL", NULL, "AIF2CLK" },
1712 { "AIF2ADCL", NULL, "DSP2CLK" },
1713 { "AIF2ADCR", NULL, "AIF2CLK" },
1714 { "AIF2ADCR", NULL, "DSP2CLK" },
1715 { "AIF2ADCR", NULL, "DSPINTCLK" },
1717 { "AIF2DACL", NULL, "AIF2CLK" },
1718 { "AIF2DACL", NULL, "DSP2CLK" },
1719 { "AIF2DACR", NULL, "AIF2CLK" },
1720 { "AIF2DACR", NULL, "DSP2CLK" },
1721 { "AIF2DACR", NULL, "DSPINTCLK" },
1723 { "DMIC1L", NULL, "DMIC1DAT" },
1724 { "DMIC1L", NULL, "CLK_SYS" },
1725 { "DMIC1R", NULL, "DMIC1DAT" },
1726 { "DMIC1R", NULL, "CLK_SYS" },
1727 { "DMIC2L", NULL, "DMIC2DAT" },
1728 { "DMIC2L", NULL, "CLK_SYS" },
1729 { "DMIC2R", NULL, "DMIC2DAT" },
1730 { "DMIC2R", NULL, "CLK_SYS" },
1732 { "ADCL", NULL, "AIF1CLK" },
1733 { "ADCL", NULL, "DSP1CLK" },
1734 { "ADCL", NULL, "DSPINTCLK" },
1736 { "ADCR", NULL, "AIF1CLK" },
1737 { "ADCR", NULL, "DSP1CLK" },
1738 { "ADCR", NULL, "DSPINTCLK" },
1740 { "ADCL Mux", "ADC", "ADCL" },
1741 { "ADCL Mux", "DMIC", "DMIC1L" },
1742 { "ADCR Mux", "ADC", "ADCR" },
1743 { "ADCR Mux", "DMIC", "DMIC1R" },
1745 { "DAC1L", NULL, "AIF1CLK" },
1746 { "DAC1L", NULL, "DSP1CLK" },
1747 { "DAC1L", NULL, "DSPINTCLK" },
1749 { "DAC1R", NULL, "AIF1CLK" },
1750 { "DAC1R", NULL, "DSP1CLK" },
1751 { "DAC1R", NULL, "DSPINTCLK" },
1753 { "DAC2L", NULL, "AIF2CLK" },
1754 { "DAC2L", NULL, "DSP2CLK" },
1755 { "DAC2L", NULL, "DSPINTCLK" },
1757 { "DAC2R", NULL, "AIF2DACR" },
1758 { "DAC2R", NULL, "AIF2CLK" },
1759 { "DAC2R", NULL, "DSP2CLK" },
1760 { "DAC2R", NULL, "DSPINTCLK" },
1762 { "TOCLK", NULL, "CLK_SYS" },
1765 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1766 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1767 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1769 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1770 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1771 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1773 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1774 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1775 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1777 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1778 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1779 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1781 /* Pin level routing for AIF3 */
1782 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1783 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1784 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1785 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1787 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1788 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1789 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1790 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1791 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1792 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1793 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1796 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1797 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1798 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1799 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1800 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1802 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1803 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1804 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1805 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1806 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1808 /* DAC2/AIF2 outputs */
1809 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1810 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1811 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1812 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1813 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1814 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1816 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1817 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1818 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1819 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1820 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1821 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1823 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1824 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1825 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1826 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1828 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1831 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1832 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1833 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1834 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1835 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1836 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1837 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1838 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1841 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1842 { "Left Sidetone", "DMIC2", "DMIC2L" },
1843 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1844 { "Right Sidetone", "DMIC2", "DMIC2R" },
1847 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1848 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1850 { "SPKL", "DAC1 Switch", "DAC1L" },
1851 { "SPKL", "DAC2 Switch", "DAC2L" },
1853 { "SPKR", "DAC1 Switch", "DAC1R" },
1854 { "SPKR", "DAC2 Switch", "DAC2R" },
1856 { "Left Headphone Mux", "DAC", "DAC1L" },
1857 { "Right Headphone Mux", "DAC", "DAC1R" },
1860 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1861 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1862 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1863 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1864 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1865 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1866 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1867 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1868 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1871 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1872 { "DAC1L", NULL, "DAC1L Mixer" },
1873 { "DAC1R", NULL, "DAC1R Mixer" },
1874 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1875 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1878 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1879 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1880 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1881 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1882 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1883 { "MICBIAS1", NULL, "CLK_SYS" },
1884 { "MICBIAS1", NULL, "MICBIAS Supply" },
1885 { "MICBIAS2", NULL, "CLK_SYS" },
1886 { "MICBIAS2", NULL, "MICBIAS Supply" },
1889 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1890 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1891 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1892 { "MICBIAS1", NULL, "VMID" },
1893 { "MICBIAS2", NULL, "VMID" },
1896 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1897 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1898 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1900 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1901 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1902 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1903 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1905 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1906 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1908 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1911 /* The size in bits of the FLL divide multiplied by 10
1912 * to allow rounding later */
1913 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1923 static int wm8994_get_fll_config(struct fll_div *fll,
1924 int freq_in, int freq_out)
1927 unsigned int K, Ndiv, Nmod;
1929 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1931 /* Scale the input frequency down to <= 13.5MHz */
1932 fll->clk_ref_div = 0;
1933 while (freq_in > 13500000) {
1937 if (fll->clk_ref_div > 3)
1940 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1942 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1944 while (freq_out * (fll->outdiv + 1) < 90000000) {
1946 if (fll->outdiv > 63)
1949 freq_out *= fll->outdiv + 1;
1950 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1952 if (freq_in > 1000000) {
1953 fll->fll_fratio = 0;
1954 } else if (freq_in > 256000) {
1955 fll->fll_fratio = 1;
1957 } else if (freq_in > 128000) {
1958 fll->fll_fratio = 2;
1960 } else if (freq_in > 64000) {
1961 fll->fll_fratio = 3;
1964 fll->fll_fratio = 4;
1967 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1969 /* Now, calculate N.K */
1970 Ndiv = freq_out / freq_in;
1973 Nmod = freq_out % freq_in;
1974 pr_debug("Nmod=%d\n", Nmod);
1976 /* Calculate fractional part - scale up so we can round. */
1977 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1979 do_div(Kpart, freq_in);
1981 K = Kpart & 0xFFFFFFFF;
1986 /* Move down to proper range now rounding is done */
1989 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1994 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1995 unsigned int freq_in, unsigned int freq_out)
1997 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1998 struct wm8994 *control = codec->control_data;
1999 int reg_offset, ret;
2001 u16 reg, aif1, aif2;
2002 unsigned long timeout;
2005 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
2006 & WM8994_AIF1CLK_ENA;
2008 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2009 & WM8994_AIF2CLK_ENA;
2024 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2025 was_enabled = reg & WM8994_FLL1_ENA;
2029 /* Allow no source specification when stopping */
2032 src = wm8994->fll[id].src;
2034 case WM8994_FLL_SRC_MCLK1:
2035 case WM8994_FLL_SRC_MCLK2:
2036 case WM8994_FLL_SRC_LRCLK:
2037 case WM8994_FLL_SRC_BCLK:
2043 /* Are we changing anything? */
2044 if (wm8994->fll[id].src == src &&
2045 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2048 /* If we're stopping the FLL redo the old config - no
2049 * registers will actually be written but we avoid GCC flow
2050 * analysis bugs spewing warnings.
2053 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2055 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2056 wm8994->fll[id].out);
2060 /* Gate the AIF clocks while we reclock */
2061 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2062 WM8994_AIF1CLK_ENA, 0);
2063 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2064 WM8994_AIF2CLK_ENA, 0);
2066 /* We always need to disable the FLL while reconfiguring */
2067 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2068 WM8994_FLL1_ENA, 0);
2070 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2071 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2072 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2073 WM8994_FLL1_OUTDIV_MASK |
2074 WM8994_FLL1_FRATIO_MASK, reg);
2076 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
2078 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2080 fll.n << WM8994_FLL1_N_SHIFT);
2082 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2083 WM8994_FLL1_REFCLK_DIV_MASK |
2084 WM8994_FLL1_REFCLK_SRC_MASK,
2085 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2088 /* Clear any pending completion from a previous failure */
2089 try_wait_for_completion(&wm8994->fll_locked[id]);
2091 /* Enable (with fractional mode if required) */
2093 /* Enable VMID if we need it */
2095 switch (control->type) {
2097 vmid_reference(codec);
2100 if (wm8994->revision < 1)
2101 vmid_reference(codec);
2109 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2111 reg = WM8994_FLL1_ENA;
2112 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2113 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2116 if (wm8994->fll_locked_irq) {
2117 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2118 msecs_to_jiffies(10));
2120 dev_warn(codec->dev,
2121 "Timed out waiting for FLL lock\n");
2127 switch (control->type) {
2129 vmid_dereference(codec);
2132 if (wm8994->revision < 1)
2133 vmid_dereference(codec);
2141 wm8994->fll[id].in = freq_in;
2142 wm8994->fll[id].out = freq_out;
2143 wm8994->fll[id].src = src;
2145 /* Enable any gated AIF clocks */
2146 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2147 WM8994_AIF1CLK_ENA, aif1);
2148 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2149 WM8994_AIF2CLK_ENA, aif2);
2151 configure_clock(codec);
2156 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2158 struct completion *completion = data;
2160 complete(completion);
2165 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2167 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2168 unsigned int freq_in, unsigned int freq_out)
2170 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2173 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2174 int clk_id, unsigned int freq, int dir)
2176 struct snd_soc_codec *codec = dai->codec;
2177 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2186 /* AIF3 shares clocking with AIF1/2 */
2191 case WM8994_SYSCLK_MCLK1:
2192 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2193 wm8994->mclk[0] = freq;
2194 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2198 case WM8994_SYSCLK_MCLK2:
2199 /* TODO: Set GPIO AF */
2200 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2201 wm8994->mclk[1] = freq;
2202 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2206 case WM8994_SYSCLK_FLL1:
2207 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2208 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2211 case WM8994_SYSCLK_FLL2:
2212 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2213 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2216 case WM8994_SYSCLK_OPCLK:
2217 /* Special case - a division (times 10) is given and
2218 * no effect on main clocking.
2221 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2222 if (opclk_divs[i] == freq)
2224 if (i == ARRAY_SIZE(opclk_divs))
2226 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2227 WM8994_OPCLK_DIV_MASK, i);
2228 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2229 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2231 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2232 WM8994_OPCLK_ENA, 0);
2239 configure_clock(codec);
2244 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2245 enum snd_soc_bias_level level)
2247 struct wm8994 *control = codec->control_data;
2248 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2251 case SND_SOC_BIAS_ON:
2254 case SND_SOC_BIAS_PREPARE:
2257 case SND_SOC_BIAS_STANDBY:
2258 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2259 pm_runtime_get_sync(codec->dev);
2261 switch (control->type) {
2263 if (wm8994->revision < 4) {
2264 /* Tweak DC servo and DSP
2265 * configuration for improved
2267 snd_soc_write(codec, 0x102, 0x3);
2268 snd_soc_write(codec, 0x56, 0x3);
2269 snd_soc_write(codec, 0x817, 0);
2270 snd_soc_write(codec, 0x102, 0);
2275 if (wm8994->revision == 0) {
2276 /* Optimise performance for rev A */
2277 snd_soc_write(codec, 0x102, 0x3);
2278 snd_soc_write(codec, 0xcb, 0x81);
2279 snd_soc_write(codec, 0x817, 0);
2280 snd_soc_write(codec, 0x102, 0);
2282 snd_soc_update_bits(codec,
2283 WM8958_CHARGE_PUMP_2,
2290 if (wm8994->revision < 2) {
2291 snd_soc_write(codec, 0x102, 0x3);
2292 snd_soc_write(codec, 0x5d, 0x7e);
2293 snd_soc_write(codec, 0x5e, 0x0);
2294 snd_soc_write(codec, 0x102, 0x0);
2299 /* Discharge LINEOUT1 & 2 */
2300 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2301 WM8994_LINEOUT1_DISCH |
2302 WM8994_LINEOUT2_DISCH,
2303 WM8994_LINEOUT1_DISCH |
2304 WM8994_LINEOUT2_DISCH);
2310 case SND_SOC_BIAS_OFF:
2311 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2312 wm8994->cur_fw = NULL;
2314 pm_runtime_put(codec->dev);
2318 codec->dapm.bias_level = level;
2322 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2324 struct snd_soc_codec *codec = dai->codec;
2325 struct wm8994 *control = codec->control_data;
2333 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2334 aif1_reg = WM8994_AIF1_CONTROL_1;
2337 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2338 aif1_reg = WM8994_AIF2_CONTROL_1;
2344 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2345 case SND_SOC_DAIFMT_CBS_CFS:
2347 case SND_SOC_DAIFMT_CBM_CFM:
2348 ms = WM8994_AIF1_MSTR;
2354 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2355 case SND_SOC_DAIFMT_DSP_B:
2356 aif1 |= WM8994_AIF1_LRCLK_INV;
2357 case SND_SOC_DAIFMT_DSP_A:
2360 case SND_SOC_DAIFMT_I2S:
2363 case SND_SOC_DAIFMT_RIGHT_J:
2365 case SND_SOC_DAIFMT_LEFT_J:
2372 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2373 case SND_SOC_DAIFMT_DSP_A:
2374 case SND_SOC_DAIFMT_DSP_B:
2375 /* frame inversion not valid for DSP modes */
2376 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2377 case SND_SOC_DAIFMT_NB_NF:
2379 case SND_SOC_DAIFMT_IB_NF:
2380 aif1 |= WM8994_AIF1_BCLK_INV;
2387 case SND_SOC_DAIFMT_I2S:
2388 case SND_SOC_DAIFMT_RIGHT_J:
2389 case SND_SOC_DAIFMT_LEFT_J:
2390 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2391 case SND_SOC_DAIFMT_NB_NF:
2393 case SND_SOC_DAIFMT_IB_IF:
2394 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2396 case SND_SOC_DAIFMT_IB_NF:
2397 aif1 |= WM8994_AIF1_BCLK_INV;
2399 case SND_SOC_DAIFMT_NB_IF:
2400 aif1 |= WM8994_AIF1_LRCLK_INV;
2410 /* The AIF2 format configuration needs to be mirrored to AIF3
2411 * on WM8958 if it's in use so just do it all the time. */
2412 switch (control->type) {
2416 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2417 WM8994_AIF1_LRCLK_INV |
2418 WM8958_AIF3_FMT_MASK, aif1);
2425 snd_soc_update_bits(codec, aif1_reg,
2426 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2427 WM8994_AIF1_FMT_MASK,
2429 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2451 static int fs_ratios[] = {
2452 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2455 static int bclk_divs[] = {
2456 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2457 640, 880, 960, 1280, 1760, 1920
2460 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2461 struct snd_pcm_hw_params *params,
2462 struct snd_soc_dai *dai)
2464 struct snd_soc_codec *codec = dai->codec;
2465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2476 int id = dai->id - 1;
2478 int i, cur_val, best_val, bclk_rate, best;
2482 aif1_reg = WM8994_AIF1_CONTROL_1;
2483 aif2_reg = WM8994_AIF1_CONTROL_2;
2484 bclk_reg = WM8994_AIF1_BCLK;
2485 rate_reg = WM8994_AIF1_RATE;
2486 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2487 wm8994->lrclk_shared[0]) {
2488 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2490 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2491 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2495 aif1_reg = WM8994_AIF2_CONTROL_1;
2496 aif2_reg = WM8994_AIF2_CONTROL_2;
2497 bclk_reg = WM8994_AIF2_BCLK;
2498 rate_reg = WM8994_AIF2_RATE;
2499 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2500 wm8994->lrclk_shared[1]) {
2501 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2503 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2504 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2511 bclk_rate = params_rate(params) * 2;
2512 switch (params_format(params)) {
2513 case SNDRV_PCM_FORMAT_S16_LE:
2516 case SNDRV_PCM_FORMAT_S20_3LE:
2520 case SNDRV_PCM_FORMAT_S24_LE:
2524 case SNDRV_PCM_FORMAT_S32_LE:
2532 /* Try to find an appropriate sample rate; look for an exact match. */
2533 for (i = 0; i < ARRAY_SIZE(srs); i++)
2534 if (srs[i].rate == params_rate(params))
2536 if (i == ARRAY_SIZE(srs))
2538 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2540 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2541 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2542 dai->id, wm8994->aifclk[id], bclk_rate);
2544 if (params_channels(params) == 1 &&
2545 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2546 aif2 |= WM8994_AIF1_MONO;
2548 if (wm8994->aifclk[id] == 0) {
2549 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2553 /* AIFCLK/fs ratio; look for a close match in either direction */
2555 best_val = abs((fs_ratios[0] * params_rate(params))
2556 - wm8994->aifclk[id]);
2557 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2558 cur_val = abs((fs_ratios[i] * params_rate(params))
2559 - wm8994->aifclk[id]);
2560 if (cur_val >= best_val)
2565 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2566 dai->id, fs_ratios[best]);
2569 /* We may not get quite the right frequency if using
2570 * approximate clocks so look for the closest match that is
2571 * higher than the target (we need to ensure that there enough
2572 * BCLKs to clock out the samples).
2575 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2576 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2577 if (cur_val < 0) /* BCLK table is sorted */
2581 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2582 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2583 bclk_divs[best], bclk_rate);
2584 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2586 lrclk = bclk_rate / params_rate(params);
2588 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2592 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2593 lrclk, bclk_rate / lrclk);
2595 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2596 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2597 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2598 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2600 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2601 WM8994_AIF1CLK_RATE_MASK, rate_val);
2603 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2606 wm8994->dac_rates[0] = params_rate(params);
2607 wm8994_set_retune_mobile(codec, 0);
2608 wm8994_set_retune_mobile(codec, 1);
2611 wm8994->dac_rates[1] = params_rate(params);
2612 wm8994_set_retune_mobile(codec, 2);
2620 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2621 struct snd_pcm_hw_params *params,
2622 struct snd_soc_dai *dai)
2624 struct snd_soc_codec *codec = dai->codec;
2625 struct wm8994 *control = codec->control_data;
2631 switch (control->type) {
2634 aif1_reg = WM8958_AIF3_CONTROL_1;
2643 switch (params_format(params)) {
2644 case SNDRV_PCM_FORMAT_S16_LE:
2646 case SNDRV_PCM_FORMAT_S20_3LE:
2649 case SNDRV_PCM_FORMAT_S24_LE:
2652 case SNDRV_PCM_FORMAT_S32_LE:
2659 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2662 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2663 struct snd_soc_dai *dai)
2665 struct snd_soc_codec *codec = dai->codec;
2670 rate_reg = WM8994_AIF1_RATE;
2673 rate_reg = WM8994_AIF2_RATE;
2679 /* If the DAI is idle then configure the divider tree for the
2680 * lowest output rate to save a little power if the clock is
2681 * still active (eg, because it is system clock).
2683 if (rate_reg && !dai->playback_active && !dai->capture_active)
2684 snd_soc_update_bits(codec, rate_reg,
2685 WM8994_AIF1_SR_MASK |
2686 WM8994_AIF1CLK_RATE_MASK, 0x9);
2689 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2691 struct snd_soc_codec *codec = codec_dai->codec;
2695 switch (codec_dai->id) {
2697 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2700 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2707 reg = WM8994_AIF1DAC1_MUTE;
2711 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2716 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2718 struct snd_soc_codec *codec = codec_dai->codec;
2721 switch (codec_dai->id) {
2723 reg = WM8994_AIF1_MASTER_SLAVE;
2724 mask = WM8994_AIF1_TRI;
2727 reg = WM8994_AIF2_MASTER_SLAVE;
2728 mask = WM8994_AIF2_TRI;
2731 reg = WM8994_POWER_MANAGEMENT_6;
2732 mask = WM8994_AIF3_TRI;
2743 return snd_soc_update_bits(codec, reg, mask, val);
2746 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2748 struct snd_soc_codec *codec = dai->codec;
2750 /* Disable the pulls on the AIF if we're using it to save power. */
2751 snd_soc_update_bits(codec, WM8994_GPIO_3,
2752 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2753 snd_soc_update_bits(codec, WM8994_GPIO_4,
2754 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2755 snd_soc_update_bits(codec, WM8994_GPIO_5,
2756 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2761 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2763 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2764 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2766 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2767 .set_sysclk = wm8994_set_dai_sysclk,
2768 .set_fmt = wm8994_set_dai_fmt,
2769 .hw_params = wm8994_hw_params,
2770 .shutdown = wm8994_aif_shutdown,
2771 .digital_mute = wm8994_aif_mute,
2772 .set_pll = wm8994_set_fll,
2773 .set_tristate = wm8994_set_tristate,
2776 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2777 .set_sysclk = wm8994_set_dai_sysclk,
2778 .set_fmt = wm8994_set_dai_fmt,
2779 .hw_params = wm8994_hw_params,
2780 .shutdown = wm8994_aif_shutdown,
2781 .digital_mute = wm8994_aif_mute,
2782 .set_pll = wm8994_set_fll,
2783 .set_tristate = wm8994_set_tristate,
2786 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2787 .hw_params = wm8994_aif3_hw_params,
2788 .set_tristate = wm8994_set_tristate,
2791 static struct snd_soc_dai_driver wm8994_dai[] = {
2793 .name = "wm8994-aif1",
2796 .stream_name = "AIF1 Playback",
2799 .rates = WM8994_RATES,
2800 .formats = WM8994_FORMATS,
2803 .stream_name = "AIF1 Capture",
2806 .rates = WM8994_RATES,
2807 .formats = WM8994_FORMATS,
2809 .ops = &wm8994_aif1_dai_ops,
2812 .name = "wm8994-aif2",
2815 .stream_name = "AIF2 Playback",
2818 .rates = WM8994_RATES,
2819 .formats = WM8994_FORMATS,
2822 .stream_name = "AIF2 Capture",
2825 .rates = WM8994_RATES,
2826 .formats = WM8994_FORMATS,
2828 .probe = wm8994_aif2_probe,
2829 .ops = &wm8994_aif2_dai_ops,
2832 .name = "wm8994-aif3",
2835 .stream_name = "AIF3 Playback",
2838 .rates = WM8994_RATES,
2839 .formats = WM8994_FORMATS,
2842 .stream_name = "AIF3 Capture",
2845 .rates = WM8994_RATES,
2846 .formats = WM8994_FORMATS,
2848 .ops = &wm8994_aif3_dai_ops,
2853 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2855 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2856 struct wm8994 *control = codec->control_data;
2859 switch (control->type) {
2861 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2865 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2866 WM8958_MICD_ENA, 0);
2870 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2871 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2872 sizeof(struct wm8994_fll_config));
2873 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2875 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2879 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2884 static int wm8994_resume(struct snd_soc_codec *codec)
2886 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2887 struct wm8994 *control = codec->control_data;
2889 unsigned int val, mask;
2891 if (wm8994->revision < 4) {
2892 /* force a HW read */
2893 val = wm8994_reg_read(codec->control_data,
2894 WM8994_POWER_MANAGEMENT_5);
2896 /* modify the cache only */
2897 codec->cache_only = 1;
2898 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2899 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2901 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2903 codec->cache_only = 0;
2906 /* Restore the registers */
2907 ret = snd_soc_cache_sync(codec);
2909 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2911 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2913 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2914 if (!wm8994->fll_suspend[i].out)
2917 ret = _wm8994_set_fll(codec, i + 1,
2918 wm8994->fll_suspend[i].src,
2919 wm8994->fll_suspend[i].in,
2920 wm8994->fll_suspend[i].out);
2922 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2926 switch (control->type) {
2928 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2929 snd_soc_update_bits(codec, WM8994_MICBIAS,
2930 WM8994_MICD_ENA, WM8994_MICD_ENA);
2934 if (wm8994->jack_cb)
2935 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2936 WM8958_MICD_ENA, WM8958_MICD_ENA);
2943 #define wm8994_suspend NULL
2944 #define wm8994_resume NULL
2947 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2949 struct snd_soc_codec *codec = wm8994->codec;
2950 struct wm8994_pdata *pdata = wm8994->pdata;
2951 struct snd_kcontrol_new controls[] = {
2952 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2953 wm8994->retune_mobile_enum,
2954 wm8994_get_retune_mobile_enum,
2955 wm8994_put_retune_mobile_enum),
2956 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2957 wm8994->retune_mobile_enum,
2958 wm8994_get_retune_mobile_enum,
2959 wm8994_put_retune_mobile_enum),
2960 SOC_ENUM_EXT("AIF2 EQ Mode",
2961 wm8994->retune_mobile_enum,
2962 wm8994_get_retune_mobile_enum,
2963 wm8994_put_retune_mobile_enum),
2968 /* We need an array of texts for the enum API but the number
2969 * of texts is likely to be less than the number of
2970 * configurations due to the sample rate dependency of the
2971 * configurations. */
2972 wm8994->num_retune_mobile_texts = 0;
2973 wm8994->retune_mobile_texts = NULL;
2974 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2975 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2976 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2977 wm8994->retune_mobile_texts[j]) == 0)
2981 if (j != wm8994->num_retune_mobile_texts)
2984 /* Expand the array... */
2985 t = krealloc(wm8994->retune_mobile_texts,
2987 (wm8994->num_retune_mobile_texts + 1),
2992 /* ...store the new entry... */
2993 t[wm8994->num_retune_mobile_texts] =
2994 pdata->retune_mobile_cfgs[i].name;
2996 /* ...and remember the new version. */
2997 wm8994->num_retune_mobile_texts++;
2998 wm8994->retune_mobile_texts = t;
3001 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3002 wm8994->num_retune_mobile_texts);
3004 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3005 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3007 ret = snd_soc_add_controls(wm8994->codec, controls,
3008 ARRAY_SIZE(controls));
3010 dev_err(wm8994->codec->dev,
3011 "Failed to add ReTune Mobile controls: %d\n", ret);
3014 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3016 struct snd_soc_codec *codec = wm8994->codec;
3017 struct wm8994_pdata *pdata = wm8994->pdata;
3023 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3024 pdata->lineout2_diff,
3029 pdata->micbias1_lvl,
3030 pdata->micbias2_lvl);
3032 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3034 if (pdata->num_drc_cfgs) {
3035 struct snd_kcontrol_new controls[] = {
3036 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3037 wm8994_get_drc_enum, wm8994_put_drc_enum),
3038 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3039 wm8994_get_drc_enum, wm8994_put_drc_enum),
3040 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3041 wm8994_get_drc_enum, wm8994_put_drc_enum),
3044 /* We need an array of texts for the enum API */
3045 wm8994->drc_texts = kmalloc(sizeof(char *)
3046 * pdata->num_drc_cfgs, GFP_KERNEL);
3047 if (!wm8994->drc_texts) {
3048 dev_err(wm8994->codec->dev,
3049 "Failed to allocate %d DRC config texts\n",
3050 pdata->num_drc_cfgs);
3054 for (i = 0; i < pdata->num_drc_cfgs; i++)
3055 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3057 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3058 wm8994->drc_enum.texts = wm8994->drc_texts;
3060 ret = snd_soc_add_controls(wm8994->codec, controls,
3061 ARRAY_SIZE(controls));
3063 dev_err(wm8994->codec->dev,
3064 "Failed to add DRC mode controls: %d\n", ret);
3066 for (i = 0; i < WM8994_NUM_DRC; i++)
3067 wm8994_set_drc(codec, i);
3070 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3071 pdata->num_retune_mobile_cfgs);
3073 if (pdata->num_retune_mobile_cfgs)
3074 wm8994_handle_retune_mobile_pdata(wm8994);
3076 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
3077 ARRAY_SIZE(wm8994_eq_controls));
3079 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3080 if (pdata->micbias[i]) {
3081 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3082 pdata->micbias[i] & 0xffff);
3088 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3090 * @codec: WM8994 codec
3091 * @jack: jack to report detection events on
3092 * @micbias: microphone bias to detect on
3093 * @det: value to report for presence detection
3094 * @shrt: value to report for short detection
3096 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3097 * being used to bring out signals to the processor then only platform
3098 * data configuration is needed for WM8994 and processor GPIOs should
3099 * be configured using snd_soc_jack_add_gpios() instead.
3101 * Configuration of detection levels is available via the micbias1_lvl
3102 * and micbias2_lvl platform data members.
3104 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3105 int micbias, int det, int shrt)
3107 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3108 struct wm8994_micdet *micdet;
3109 struct wm8994 *control = codec->control_data;
3112 if (control->type != WM8994)
3117 micdet = &wm8994->micdet[0];
3120 micdet = &wm8994->micdet[1];
3126 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
3127 micbias, det, shrt);
3129 /* Store the configuration */
3130 micdet->jack = jack;
3132 micdet->shrt = shrt;
3134 /* If either of the jacks is set up then enable detection */
3135 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3136 reg = WM8994_MICD_ENA;
3140 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3144 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3146 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3148 struct wm8994_priv *priv = data;
3149 struct snd_soc_codec *codec = priv->codec;
3153 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3154 trace_snd_soc_jack_irq(dev_name(codec->dev));
3157 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3159 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3164 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3167 if (reg & WM8994_MIC1_DET_STS)
3168 report |= priv->micdet[0].det;
3169 if (reg & WM8994_MIC1_SHRT_STS)
3170 report |= priv->micdet[0].shrt;
3171 snd_soc_jack_report(priv->micdet[0].jack, report,
3172 priv->micdet[0].det | priv->micdet[0].shrt);
3175 if (reg & WM8994_MIC2_DET_STS)
3176 report |= priv->micdet[1].det;
3177 if (reg & WM8994_MIC2_SHRT_STS)
3178 report |= priv->micdet[1].shrt;
3179 snd_soc_jack_report(priv->micdet[1].jack, report,
3180 priv->micdet[1].det | priv->micdet[1].shrt);
3185 /* Default microphone detection handler for WM8958 - the user can
3186 * override this if they wish.
3188 static void wm8958_default_micdet(u16 status, void *data)
3190 struct snd_soc_codec *codec = data;
3191 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3194 /* If nothing present then clear our statuses */
3195 if (!(status & WM8958_MICD_STS))
3198 report = SND_JACK_MICROPHONE;
3200 /* Everything else is buttons; just assign slots */
3202 report |= SND_JACK_BTN_0;
3205 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3206 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
3210 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3212 * @codec: WM8958 codec
3213 * @jack: jack to report detection events on
3215 * Enable microphone detection functionality for the WM8958. By
3216 * default simple detection which supports the detection of up to 6
3217 * buttons plus video and microphone functionality is supported.
3219 * The WM8958 has an advanced jack detection facility which is able to
3220 * support complex accessory detection, especially when used in
3221 * conjunction with external circuitry. In order to provide maximum
3222 * flexiblity a callback is provided which allows a completely custom
3223 * detection algorithm.
3225 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3226 wm8958_micdet_cb cb, void *cb_data)
3228 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3229 struct wm8994 *control = codec->control_data;
3231 switch (control->type) {
3241 dev_dbg(codec->dev, "Using default micdet callback\n");
3242 cb = wm8958_default_micdet;
3246 wm8994->micdet[0].jack = jack;
3247 wm8994->jack_cb = cb;
3248 wm8994->jack_cb_data = cb_data;
3250 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3251 WM8958_MICD_ENA, WM8958_MICD_ENA);
3253 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3254 WM8958_MICD_ENA, 0);
3259 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3261 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3263 struct wm8994_priv *wm8994 = data;
3264 struct snd_soc_codec *codec = wm8994->codec;
3267 /* We may occasionally read a detection without an impedence
3268 * range being provided - if that happens loop again.
3272 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3275 "Failed to read mic detect status: %d\n",
3280 if (!(reg & WM8958_MICD_VALID)) {
3281 dev_dbg(codec->dev, "Mic detect data not valid\n");
3285 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3292 dev_warn(codec->dev, "No impedence range reported for jack\n");
3294 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3295 trace_snd_soc_jack_irq(dev_name(codec->dev));
3298 if (wm8994->jack_cb)
3299 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3301 dev_warn(codec->dev, "Accessory detection with no callback\n");
3307 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3309 struct snd_soc_codec *codec = data;
3311 dev_err(codec->dev, "FIFO error\n");
3316 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3318 struct snd_soc_codec *codec = data;
3320 dev_err(codec->dev, "Thermal warning\n");
3325 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3327 struct snd_soc_codec *codec = data;
3329 dev_crit(codec->dev, "Thermal shutdown\n");
3334 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3336 struct wm8994 *control;
3337 struct wm8994_priv *wm8994;
3338 struct snd_soc_dapm_context *dapm = &codec->dapm;
3341 codec->control_data = dev_get_drvdata(codec->dev->parent);
3342 control = codec->control_data;
3344 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3347 snd_soc_codec_set_drvdata(codec, wm8994);
3349 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3350 wm8994->codec = codec;
3352 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3353 init_completion(&wm8994->fll_locked[i]);
3355 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3356 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3357 else if (wm8994->pdata && wm8994->pdata->irq_base)
3358 wm8994->micdet_irq = wm8994->pdata->irq_base +
3359 WM8994_IRQ_MIC1_DET;
3361 pm_runtime_enable(codec->dev);
3362 pm_runtime_resume(codec->dev);
3364 /* Read our current status back from the chip - we don't want to
3365 * reset as this may interfere with the GPIO or LDO operation. */
3366 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3367 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3370 ret = wm8994_reg_read(codec->control_data, i);
3374 ret = snd_soc_cache_write(codec, i, ret);
3377 "Failed to initialise cache for 0x%x: %d\n",
3383 /* Set revision-specific configuration */
3384 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3385 switch (control->type) {
3387 switch (wm8994->revision) {
3390 wm8994->hubs.dcs_codes_l = -5;
3391 wm8994->hubs.dcs_codes_r = -5;
3392 wm8994->hubs.hp_startup_mode = 1;
3393 wm8994->hubs.dcs_readback_mode = 1;
3394 wm8994->hubs.series_startup = 1;
3397 wm8994->hubs.dcs_readback_mode = 2;
3403 wm8994->hubs.dcs_readback_mode = 1;
3407 wm8994->hubs.dcs_readback_mode = 2;
3408 wm8994->hubs.no_series_update = 1;
3410 switch (wm8994->revision) {
3415 wm8994->hubs.dcs_codes_l = -9;
3416 wm8994->hubs.dcs_codes_r = -7;
3422 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3423 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3430 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3431 wm8994_fifo_error, "FIFO error", codec);
3432 wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_WARN,
3433 wm8994_temp_warn, "Thermal warning", codec);
3434 wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT,
3435 wm8994_temp_shut, "Thermal shutdown", codec);
3437 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3438 wm_hubs_dcs_done, "DC servo done",
3441 wm8994->hubs.dcs_done_irq = true;
3443 switch (control->type) {
3445 if (wm8994->micdet_irq) {
3446 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3448 IRQF_TRIGGER_RISING,
3452 dev_warn(codec->dev,
3453 "Failed to request Mic1 detect IRQ: %d\n",
3457 ret = wm8994_request_irq(codec->control_data,
3458 WM8994_IRQ_MIC1_SHRT,
3459 wm8994_mic_irq, "Mic 1 short",
3462 dev_warn(codec->dev,
3463 "Failed to request Mic1 short IRQ: %d\n",
3466 ret = wm8994_request_irq(codec->control_data,
3467 WM8994_IRQ_MIC2_DET,
3468 wm8994_mic_irq, "Mic 2 detect",
3471 dev_warn(codec->dev,
3472 "Failed to request Mic2 detect IRQ: %d\n",
3475 ret = wm8994_request_irq(codec->control_data,
3476 WM8994_IRQ_MIC2_SHRT,
3477 wm8994_mic_irq, "Mic 2 short",
3480 dev_warn(codec->dev,
3481 "Failed to request Mic2 short IRQ: %d\n",
3487 if (wm8994->micdet_irq) {
3488 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3490 IRQF_TRIGGER_RISING,
3494 dev_warn(codec->dev,
3495 "Failed to request Mic detect IRQ: %d\n",
3500 wm8994->fll_locked_irq = true;
3501 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3502 ret = wm8994_request_irq(codec->control_data,
3503 WM8994_IRQ_FLL1_LOCK + i,
3504 wm8994_fll_locked_irq, "FLL lock",
3505 &wm8994->fll_locked[i]);
3507 wm8994->fll_locked_irq = false;
3510 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3511 * configured on init - if a system wants to do this dynamically
3512 * at runtime we can deal with that then.
3514 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3516 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3519 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3520 wm8994->lrclk_shared[0] = 1;
3521 wm8994_dai[0].symmetric_rates = 1;
3523 wm8994->lrclk_shared[0] = 0;
3526 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3528 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3531 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3532 wm8994->lrclk_shared[1] = 1;
3533 wm8994_dai[1].symmetric_rates = 1;
3535 wm8994->lrclk_shared[1] = 0;
3538 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3540 /* Latch volume update bits */
3541 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3542 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3543 wm8994_vu_bits[i].mask,
3544 wm8994_vu_bits[i].mask);
3546 /* Set the low bit of the 3D stereo depth so TLV matches */
3547 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3548 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3549 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3550 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3551 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3552 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3553 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3554 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3555 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3557 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3558 * use this; it only affects behaviour on idle TDM clock
3560 switch (control->type) {
3563 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3564 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3570 wm8994_update_class_w(codec);
3572 wm8994_handle_pdata(wm8994);
3574 wm_hubs_add_analogue_controls(codec);
3575 snd_soc_add_controls(codec, wm8994_snd_controls,
3576 ARRAY_SIZE(wm8994_snd_controls));
3577 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3578 ARRAY_SIZE(wm8994_dapm_widgets));
3580 switch (control->type) {
3582 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3583 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3584 if (wm8994->revision < 4) {
3585 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3586 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3587 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3588 ARRAY_SIZE(wm8994_adc_revd_widgets));
3589 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3590 ARRAY_SIZE(wm8994_dac_revd_widgets));
3592 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3593 ARRAY_SIZE(wm8994_lateclk_widgets));
3594 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3595 ARRAY_SIZE(wm8994_adc_widgets));
3596 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3597 ARRAY_SIZE(wm8994_dac_widgets));
3601 snd_soc_add_controls(codec, wm8958_snd_controls,
3602 ARRAY_SIZE(wm8958_snd_controls));
3603 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3604 ARRAY_SIZE(wm8958_dapm_widgets));
3605 if (wm8994->revision < 1) {
3606 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3607 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3608 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3609 ARRAY_SIZE(wm8994_adc_revd_widgets));
3610 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3611 ARRAY_SIZE(wm8994_dac_revd_widgets));
3613 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3614 ARRAY_SIZE(wm8994_lateclk_widgets));
3615 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3616 ARRAY_SIZE(wm8994_adc_widgets));
3617 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3618 ARRAY_SIZE(wm8994_dac_widgets));
3623 snd_soc_add_controls(codec, wm8958_snd_controls,
3624 ARRAY_SIZE(wm8958_snd_controls));
3625 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3626 ARRAY_SIZE(wm8958_dapm_widgets));
3627 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3628 ARRAY_SIZE(wm8994_lateclk_widgets));
3629 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3630 ARRAY_SIZE(wm8994_adc_widgets));
3631 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3632 ARRAY_SIZE(wm8994_dac_widgets));
3637 wm_hubs_add_analogue_routes(codec, 0, 0);
3638 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3640 switch (control->type) {
3642 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3643 ARRAY_SIZE(wm8994_intercon));
3645 if (wm8994->revision < 4) {
3646 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3647 ARRAY_SIZE(wm8994_revd_intercon));
3648 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3649 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3651 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3652 ARRAY_SIZE(wm8994_lateclk_intercon));
3656 if (wm8994->revision < 1) {
3657 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3658 ARRAY_SIZE(wm8994_revd_intercon));
3659 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3660 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3662 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3663 ARRAY_SIZE(wm8994_lateclk_intercon));
3664 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3665 ARRAY_SIZE(wm8958_intercon));
3668 wm8958_dsp2_init(codec);
3671 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3672 ARRAY_SIZE(wm8994_lateclk_intercon));
3673 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3674 ARRAY_SIZE(wm8958_intercon));
3681 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3682 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3683 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3684 if (wm8994->micdet_irq)
3685 free_irq(wm8994->micdet_irq, wm8994);
3686 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3687 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3688 &wm8994->fll_locked[i]);
3689 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3691 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3692 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3693 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3699 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3702 struct wm8994 *control = codec->control_data;
3705 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3707 pm_runtime_disable(codec->dev);
3709 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3710 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3711 &wm8994->fll_locked[i]);
3713 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3715 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3716 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3717 wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3719 switch (control->type) {
3721 if (wm8994->micdet_irq)
3722 free_irq(wm8994->micdet_irq, wm8994);
3723 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3725 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3727 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3733 if (wm8994->micdet_irq)
3734 free_irq(wm8994->micdet_irq, wm8994);
3738 release_firmware(wm8994->mbc);
3739 if (wm8994->mbc_vss)
3740 release_firmware(wm8994->mbc_vss);
3742 release_firmware(wm8994->enh_eq);
3743 kfree(wm8994->retune_mobile_texts);
3744 kfree(wm8994->drc_texts);
3750 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3751 .probe = wm8994_codec_probe,
3752 .remove = wm8994_codec_remove,
3753 .suspend = wm8994_suspend,
3754 .resume = wm8994_resume,
3755 .read = wm8994_read,
3756 .write = wm8994_write,
3757 .readable_register = wm8994_readable,
3758 .volatile_register = wm8994_volatile,
3759 .set_bias_level = wm8994_set_bias_level,
3761 .reg_cache_size = WM8994_CACHE_SIZE,
3762 .reg_cache_default = wm8994_reg_defaults,
3764 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3767 static int __devinit wm8994_probe(struct platform_device *pdev)
3769 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3770 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3773 static int __devexit wm8994_remove(struct platform_device *pdev)
3775 snd_soc_unregister_codec(&pdev->dev);
3779 static struct platform_driver wm8994_codec_driver = {
3781 .name = "wm8994-codec",
3782 .owner = THIS_MODULE,
3784 .probe = wm8994_probe,
3785 .remove = __devexit_p(wm8994_remove),
3788 static __init int wm8994_init(void)
3790 return platform_driver_register(&wm8994_codec_driver);
3792 module_init(wm8994_init);
3794 static __exit void wm8994_exit(void)
3796 platform_driver_unregister(&wm8994_codec_driver);
3798 module_exit(wm8994_exit);
3801 MODULE_DESCRIPTION("ASoC WM8994 driver");
3802 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3803 MODULE_LICENSE("GPL");
3804 MODULE_ALIAS("platform:wm8994-codec");