sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 struct fll_config {
  42         int src;
  43         int in;
  44         int out;
  45 };
  46
  47 #define WM8994_NUM_DRC 3
  48 #define WM8994_NUM_EQ  3
  49
  50 static int wm8994_drc_base[] = {
  51         WM8994_AIF1_DRC1_1,
  52         WM8994_AIF1_DRC2_1,
  53         WM8994_AIF2_DRC_1,
  54 };
  55
  56 static int wm8994_retune_mobile_base[] = {
  57         WM8994_AIF1_DAC1_EQ_GAINS_1,
  58         WM8994_AIF1_DAC2_EQ_GAINS_1,
  59         WM8994_AIF2_EQ_GAINS_1,
  60 };
  61
  62 struct wm8994_micdet {
  63         struct snd_soc_jack *jack;
  64         int det;
  65         int shrt;
  66 };
  67
  68 /* codec private data */
  69 struct wm8994_priv {
  70         struct wm_hubs_data hubs;
  71         enum snd_soc_control_type control_type;
  72         void *control_data;
  73         struct snd_soc_codec *codec;
  74         int sysclk[2];
  75         int sysclk_rate[2];
  76         int mclk[2];
  77         int aifclk[2];
  78         struct fll_config fll[2], fll_suspend[2];
  79
  80         int dac_rates[2];
  81         int lrclk_shared[2];
  82
  83         int mbc_ena[3];
  84
  85         /* Platform dependant DRC configuration */
  86         const char **drc_texts;
  87         int drc_cfg[WM8994_NUM_DRC];
  88         struct soc_enum drc_enum;
  89
  90         /* Platform dependant ReTune mobile configuration */
  91         int num_retune_mobile_texts;
  92         const char **retune_mobile_texts;
  93         int retune_mobile_cfg[WM8994_NUM_EQ];
  94         struct soc_enum retune_mobile_enum;
  95
  96         /* Platform dependant MBC configuration */
  97         int mbc_cfg;
  98         const char **mbc_texts;
  99         struct soc_enum mbc_enum;
 100
 101         struct wm8994_micdet micdet[2];
 102
 103         wm8958_micdet_cb jack_cb;
 104         void *jack_cb_data;
 105         bool jack_is_mic;
 106         bool jack_is_video;
 107
 108         int revision;
 109         struct wm8994_pdata *pdata;
 110
 111         unsigned int aif1clk_enable:1;
 112         unsigned int aif2clk_enable:1;
 113 };
 114
 115 static int wm8994_readable(unsigned int reg)
 116 {
 117         switch (reg) {
 118         case WM8994_GPIO_1:
 119         case WM8994_GPIO_2:
 120         case WM8994_GPIO_3:
 121         case WM8994_GPIO_4:
 122         case WM8994_GPIO_5:
 123         case WM8994_GPIO_6:
 124         case WM8994_GPIO_7:
 125         case WM8994_GPIO_8:
 126         case WM8994_GPIO_9:
 127         case WM8994_GPIO_10:
 128         case WM8994_GPIO_11:
 129         case WM8994_INTERRUPT_STATUS_1:
 130         case WM8994_INTERRUPT_STATUS_2:
 131         case WM8994_INTERRUPT_RAW_STATUS_2:
 132                 return 1;
 133         default:
 134                 break;
 135         }
 136
 137         if (reg >= WM8994_CACHE_SIZE)
 138                 return 0;
 139         return wm8994_access_masks[reg].readable != 0;
 140 }
 141
 142 static int wm8994_volatile(unsigned int reg)
 143 {
 144         if (reg >= WM8994_CACHE_SIZE)
 145                 return 1;
 146
 147         switch (reg) {
 148         case WM8994_SOFTWARE_RESET:
 149         case WM8994_CHIP_REVISION:
 150         case WM8994_DC_SERVO_1:
 151         case WM8994_DC_SERVO_READBACK:
 152         case WM8994_RATE_STATUS:
 153         case WM8994_LDO_1:
 154         case WM8994_LDO_2:
 155         case WM8958_DSP2_EXECCONTROL:
 156         case WM8958_MIC_DETECT_3:
 157                 return 1;
 158         default:
 159                 return 0;
 160         }
 161 }
 162
 163 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 164         unsigned int value)
 165 {
 166         int ret;
 167
 168         BUG_ON(reg > WM8994_MAX_REGISTER);
 169
 170         if (!wm8994_volatile(reg)) {
 171                 ret = snd_soc_cache_write(codec, reg, value);
 172                 if (ret != 0)
 173                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 174                                 reg, ret);
 175         }
 176
 177         return wm8994_reg_write(codec->control_data, reg, value);
 178 }
 179
 180 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 181                                 unsigned int reg)
 182 {
 183         unsigned int val;
 184         int ret;
 185
 186         BUG_ON(reg > WM8994_MAX_REGISTER);
 187
 188         if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
 189             reg < codec->driver->reg_cache_size) {
 190                 ret = snd_soc_cache_read(codec, reg, &val);
 191                 if (ret >= 0)
 192                         return val;
 193                 else
 194                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 195                                 reg, ret);
 196         }
 197
 198         return wm8994_reg_read(codec->control_data, reg);
 199 }
 200
 201 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 202 {
 203         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 204         int rate;
 205         int reg1 = 0;
 206         int offset;
 207
 208         if (aif)
 209                 offset = 4;
 210         else
 211                 offset = 0;
 212
 213         switch (wm8994->sysclk[aif]) {
 214         case WM8994_SYSCLK_MCLK1:
 215                 rate = wm8994->mclk[0];
 216                 break;
 217
 218         case WM8994_SYSCLK_MCLK2:
 219                 reg1 |= 0x8;
 220                 rate = wm8994->mclk[1];
 221                 break;
 222
 223         case WM8994_SYSCLK_FLL1:
 224                 reg1 |= 0x10;
 225                 rate = wm8994->fll[0].out;
 226                 break;
 227
 228         case WM8994_SYSCLK_FLL2:
 229                 reg1 |= 0x18;
 230                 rate = wm8994->fll[1].out;
 231                 break;
 232
 233         default:
 234                 return -EINVAL;
 235         }
 236
 237         if (rate >= 13500000) {
 238                 rate /= 2;
 239                 reg1 |= WM8994_AIF1CLK_DIV;
 240
 241                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 242                         aif + 1, rate);
 243         }
 244
 245         if (rate && rate < 3000000)
 246                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 247                          aif + 1, rate);
 248
 249         wm8994->aifclk[aif] = rate;
 250
 251         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 252                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 253                             reg1);
 254
 255         return 0;
 256 }
 257
 258 static int configure_clock(struct snd_soc_codec *codec)
 259 {
 260         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 261         int old, new;
 262
 263         /* Bring up the AIF clocks first */
 264         configure_aif_clock(codec, 0);
 265         configure_aif_clock(codec, 1);
 266
 267         /* Then switch CLK_SYS over to the higher of them; a change
 268          * can only happen as a result of a clocking change which can
 269          * only be made outside of DAPM so we can safely redo the
 270          * clocking.
 271          */
 272
 273         /* If they're equal it doesn't matter which is used */
 274         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 275                 return 0;
 276
 277         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 278                 new = WM8994_SYSCLK_SRC;
 279         else
 280                 new = 0;
 281
 282         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 283
 284         /* If there's no change then we're done. */
 285         if (old == new)
 286                 return 0;
 287
 288         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 289
 290         snd_soc_dapm_sync(&codec->dapm);
 291
 292         return 0;
 293 }
 294
 295 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 296                          struct snd_soc_dapm_widget *sink)
 297 {
 298         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 299         const char *clk;
 300
 301         /* Check what we're currently using for CLK_SYS */
 302         if (reg & WM8994_SYSCLK_SRC)
 303                 clk = "AIF2CLK";
 304         else
 305                 clk = "AIF1CLK";
 306
 307         return strcmp(source->name, clk) == 0;
 308 }
 309
 310 static const char *sidetone_hpf_text[] = {
 311         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 312 };
 313
 314 static const struct soc_enum sidetone_hpf =
 315         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 316
 317 static const char *adc_hpf_text[] = {
 318         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 319 };
 320
 321 static const struct soc_enum aif1adc1_hpf =
 322         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 323
 324 static const struct soc_enum aif1adc2_hpf =
 325         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 326
 327 static const struct soc_enum aif2adc_hpf =
 328         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 329
 330 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 331 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 332 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 333 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 334 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 335
 336 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 337 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 338         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 339         .put = wm8994_put_drc_sw, \
 340         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 341
 342 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 343                              struct snd_ctl_elem_value *ucontrol)
 344 {
 345         struct soc_mixer_control *mc =
 346                 (struct soc_mixer_control *)kcontrol->private_value;
 347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 348         int mask, ret;
 349
 350         /* Can't enable both ADC and DAC paths simultaneously */
 351         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 352                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 353                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 354         else
 355                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 356
 357         ret = snd_soc_read(codec, mc->reg);
 358         if (ret < 0)
 359                 return ret;
 360         if (ret & mask)
 361                 return -EINVAL;
 362
 363         return snd_soc_put_volsw(kcontrol, ucontrol);
 364 }
 365
 366 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 367 {
 368         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 369         struct wm8994_pdata *pdata = wm8994->pdata;
 370         int base = wm8994_drc_base[drc];
 371         int cfg = wm8994->drc_cfg[drc];
 372         int save, i;
 373
 374         /* Save any enables; the configuration should clear them. */
 375         save = snd_soc_read(codec, base);
 376         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 377                 WM8994_AIF1ADC1R_DRC_ENA;
 378
 379         for (i = 0; i < WM8994_DRC_REGS; i++)
 380                 snd_soc_update_bits(codec, base + i, 0xffff,
 381                                     pdata->drc_cfgs[cfg].regs[i]);
 382
 383         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 384                              WM8994_AIF1ADC1L_DRC_ENA |
 385                              WM8994_AIF1ADC1R_DRC_ENA, save);
 386 }
 387
 388 /* Icky as hell but saves code duplication */
 389 static int wm8994_get_drc(const char *name)
 390 {
 391         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 392                 return 0;
 393         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 394                 return 1;
 395         if (strcmp(name, "AIF2DRC Mode") == 0)
 396                 return 2;
 397         return -EINVAL;
 398 }
 399
 400 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 401                                struct snd_ctl_elem_value *ucontrol)
 402 {
 403         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 404         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 405         struct wm8994_pdata *pdata = wm8994->pdata;
 406         int drc = wm8994_get_drc(kcontrol->id.name);
 407         int value = ucontrol->value.integer.value[0];
 408
 409         if (drc < 0)
 410                 return drc;
 411
 412         if (value >= pdata->num_drc_cfgs)
 413                 return -EINVAL;
 414
 415         wm8994->drc_cfg[drc] = value;
 416
 417         wm8994_set_drc(codec, drc);
 418
 419         return 0;
 420 }
 421
 422 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 423                                struct snd_ctl_elem_value *ucontrol)
 424 {
 425         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 426         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 427         int drc = wm8994_get_drc(kcontrol->id.name);
 428
 429         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 430
 431         return 0;
 432 }
 433
 434 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 435 {
 436         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 437         struct wm8994_pdata *pdata = wm8994->pdata;
 438         int base = wm8994_retune_mobile_base[block];
 439         int iface, best, best_val, save, i, cfg;
 440
 441         if (!pdata || !wm8994->num_retune_mobile_texts)
 442                 return;
 443
 444         switch (block) {
 445         case 0:
 446         case 1:
 447                 iface = 0;
 448                 break;
 449         case 2:
 450                 iface = 1;
 451                 break;
 452         default:
 453                 return;
 454         }
 455
 456         /* Find the version of the currently selected configuration
 457          * with the nearest sample rate. */
 458         cfg = wm8994->retune_mobile_cfg[block];
 459         best = 0;
 460         best_val = INT_MAX;
 461         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 462                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 463                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 464                     abs(pdata->retune_mobile_cfgs[i].rate
 465                         - wm8994->dac_rates[iface]) < best_val) {
 466                         best = i;
 467                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 468                                        - wm8994->dac_rates[iface]);
 469                 }
 470         }
 471
 472         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 473                 block,
 474                 pdata->retune_mobile_cfgs[best].name,
 475                 pdata->retune_mobile_cfgs[best].rate,
 476                 wm8994->dac_rates[iface]);
 477
 478         /* The EQ will be disabled while reconfiguring it, remember the
 479          * current configuration.
 480          */
 481         save = snd_soc_read(codec, base);
 482         save &= WM8994_AIF1DAC1_EQ_ENA;
 483
 484         for (i = 0; i < WM8994_EQ_REGS; i++)
 485                 snd_soc_update_bits(codec, base + i, 0xffff,
 486                                 pdata->retune_mobile_cfgs[best].regs[i]);
 487
 488         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 489 }
 490
 491 /* Icky as hell but saves code duplication */
 492 static int wm8994_get_retune_mobile_block(const char *name)
 493 {
 494         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 495                 return 0;
 496         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 497                 return 1;
 498         if (strcmp(name, "AIF2 EQ Mode") == 0)
 499                 return 2;
 500         return -EINVAL;
 501 }
 502
 503 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 504                                          struct snd_ctl_elem_value *ucontrol)
 505 {
 506         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 507         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 508         struct wm8994_pdata *pdata = wm8994->pdata;
 509         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 510         int value = ucontrol->value.integer.value[0];
 511
 512         if (block < 0)
 513                 return block;
 514
 515         if (value >= pdata->num_retune_mobile_cfgs)
 516                 return -EINVAL;
 517
 518         wm8994->retune_mobile_cfg[block] = value;
 519
 520         wm8994_set_retune_mobile(codec, block);
 521
 522         return 0;
 523 }
 524
 525 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 526                                          struct snd_ctl_elem_value *ucontrol)
 527 {
 528         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 529         struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
 530         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 531
 532         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 533
 534         return 0;
 535 }
 536
 537 static const char *aif_chan_src_text[] = {
 538         "Left", "Right"
 539 };
 540
 541 static const struct soc_enum aif1adcl_src =
 542         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 543
 544 static const struct soc_enum aif1adcr_src =
 545         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 546
 547 static const struct soc_enum aif2adcl_src =
 548         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 549
 550 static const struct soc_enum aif2adcr_src =
 551         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 552
 553 static const struct soc_enum aif1dacl_src =
 554         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 555
 556 static const struct soc_enum aif1dacr_src =
 557         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 558
 559 static const struct soc_enum aif2dacl_src =
 560         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 561
 562 static const struct soc_enum aif2dacr_src =
 563         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 564
 565 static const char *osr_text[] = {
 566         "Low Power", "High Performance",
 567 };
 568
 569 static const struct soc_enum dac_osr =
 570         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 571
 572 static const struct soc_enum adc_osr =
 573         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 574
 575 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
 576 {
 577         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 578         struct wm8994_pdata *pdata = wm8994->pdata;
 579         int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
 580         int ena, reg, aif, i;
 581
 582         switch (mbc) {
 583         case 0:
 584                 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
 585                 aif = 0;
 586                 break;
 587         case 1:
 588                 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
 589                 aif = 0;
 590                 break;
 591         case 2:
 592                 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
 593                 aif = 1;
 594                 break;
 595         default:
 596                 BUG();
 597                 return;
 598         }
 599
 600         /* We can only enable the MBC if the AIF is enabled and we
 601          * want it to be enabled. */
 602         ena = pwr_reg && wm8994->mbc_ena[mbc];
 603
 604         reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
 605
 606         dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
 607                 mbc, start, pwr_reg, reg);
 608
 609         if (start && ena) {
 610                 /* If the DSP is already running then noop */
 611                 if (reg & WM8958_DSP2_ENA)
 612                         return;
 613
 614                 /* Switch the clock over to the appropriate AIF */
 615                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 616                                     WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
 617                                     aif << WM8958_DSP2CLK_SRC_SHIFT |
 618                                     WM8958_DSP2CLK_ENA);
 619
 620                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 621                                     WM8958_DSP2_ENA, WM8958_DSP2_ENA);
 622
 623                 /* If we've got user supplied MBC settings use them */
 624                 if (pdata && pdata->num_mbc_cfgs) {
 625                         struct wm8958_mbc_cfg *cfg
 626                                 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
 627
 628                         for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
 629                                 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
 630                                               cfg->coeff_regs[i]);
 631
 632                         for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
 633                                 snd_soc_write(codec,
 634                                               i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
 635                                               cfg->cutoff_regs[i]);
 636                 }
 637
 638                 /* Run the DSP */
 639                 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
 640                               WM8958_DSP2_RUNR);
 641
 642                 /* And we're off! */
 643                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 644                                     WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
 645                                     mbc << WM8958_MBC_SEL_SHIFT |
 646                                     WM8958_MBC_ENA);
 647         } else {
 648                 /* If the DSP is already stopped then noop */
 649                 if (!(reg & WM8958_DSP2_ENA))
 650                         return;
 651
 652                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 653                                     WM8958_MBC_ENA, 0);
 654                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 655                                     WM8958_DSP2_ENA, 0);
 656                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 657                                     WM8958_DSP2CLK_ENA, 0);
 658         }
 659 }
 660
 661 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
 662                     struct snd_kcontrol *kcontrol, int event)
 663 {
 664         struct snd_soc_codec *codec = w->codec;
 665         int mbc;
 666
 667         switch (w->shift) {
 668         case 13:
 669         case 12:
 670                 mbc = 2;
 671                 break;
 672         case 11:
 673         case 10:
 674                 mbc = 1;
 675                 break;
 676         case 9:
 677         case 8:
 678                 mbc = 0;
 679                 break;
 680         default:
 681                 BUG();
 682                 return -EINVAL;
 683         }
 684
 685         switch (event) {
 686         case SND_SOC_DAPM_POST_PMU:
 687                 wm8958_mbc_apply(codec, mbc, 1);
 688                 break;
 689         case SND_SOC_DAPM_POST_PMD:
 690                 wm8958_mbc_apply(codec, mbc, 0);
 691                 break;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
 698                                struct snd_ctl_elem_value *ucontrol)
 699 {
 700         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 701         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 702         struct wm8994_pdata *pdata = wm8994->pdata;
 703         int value = ucontrol->value.integer.value[0];
 704         int reg;
 705
 706         /* Don't allow on the fly reconfiguration */
 707         reg = snd_soc_read(codec, WM8994_CLOCKING_1);
 708         if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
 709                 return -EBUSY;
 710
 711         if (value >= pdata->num_mbc_cfgs)
 712                 return -EINVAL;
 713
 714         wm8994->mbc_cfg = value;
 715
 716         return 0;
 717 }
 718
 719 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
 720                                struct snd_ctl_elem_value *ucontrol)
 721 {
 722         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 723         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 724
 725         ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
 726
 727         return 0;
 728 }
 729
 730 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
 731                            struct snd_ctl_elem_info *uinfo)
 732 {
 733         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 734         uinfo->count = 1;
 735         uinfo->value.integer.min = 0;
 736         uinfo->value.integer.max = 1;
 737         return 0;
 738 }
 739
 740 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
 741                           struct snd_ctl_elem_value *ucontrol)
 742 {
 743         int mbc = kcontrol->private_value;
 744         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 745         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 746
 747         ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
 748
 749         return 0;
 750 }
 751
 752 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
 753                           struct snd_ctl_elem_value *ucontrol)
 754 {
 755         int mbc = kcontrol->private_value;
 756         int i;
 757         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 758         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 759
 760         if (ucontrol->value.integer.value[0] > 1)
 761                 return -EINVAL;
 762
 763         for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
 764                 if (mbc != i && wm8994->mbc_ena[i]) {
 765                         dev_dbg(codec->dev, "MBC %d active already\n", mbc);
 766                         return -EBUSY;
 767                 }
 768         }
 769
 770         wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
 771
 772         wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
 773
 774         return 0;
 775 }
 776
 777 #define WM8958_MBC_SWITCH(xname, xval) {\
 778         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 779         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 780         .info = wm8958_mbc_info, \
 781         .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
 782         .private_value = xval }
 783
 784 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 785 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 786                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 787                  1, 119, 0, digital_tlv),
 788 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 789                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 790                  1, 119, 0, digital_tlv),
 791 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 792                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 793                  1, 119, 0, digital_tlv),
 794
 795 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 796 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 797 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 798 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 799
 800 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 801 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 802 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 803 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 804
 805 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 806                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 807 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 808                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 809 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 810                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 811
 812 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 813 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 814
 815 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 816 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 817 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 818
 819 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 820 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 821 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 822
 823 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 824 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 825 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 826
 827 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 828 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 829 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 830
 831 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 832                5, 12, 0, st_tlv),
 833 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 834                0, 12, 0, st_tlv),
 835 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 836                5, 12, 0, st_tlv),
 837 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 838                0, 12, 0, st_tlv),
 839 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 840 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 841
 842 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 843 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 844
 845 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 846 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 847
 848 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 849 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 850
 851 SOC_ENUM("ADC OSR", adc_osr),
 852 SOC_ENUM("DAC OSR", dac_osr),
 853
 854 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 855                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 856 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 857              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 858
 859 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 860                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 861 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 862              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 863
 864 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 865                6, 1, 1, wm_hubs_spkmix_tlv),
 866 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 867                2, 1, 1, wm_hubs_spkmix_tlv),
 868
 869 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 870                6, 1, 1, wm_hubs_spkmix_tlv),
 871 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 872                2, 1, 1, wm_hubs_spkmix_tlv),
 873
 874 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 875                10, 15, 0, wm8994_3d_tlv),
 876 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 877            8, 1, 0),
 878 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 879                10, 15, 0, wm8994_3d_tlv),
 880 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 881            8, 1, 0),
 882 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 883                10, 15, 0, wm8994_3d_tlv),
 884 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 885            8, 1, 0),
 886 };
 887
 888 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 889 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 890                eq_tlv),
 891 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 892                eq_tlv),
 893 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 894                eq_tlv),
 895 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 896                eq_tlv),
 897 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 898                eq_tlv),
 899
 900 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 901                eq_tlv),
 902 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 903                eq_tlv),
 904 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 905                eq_tlv),
 906 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 907                eq_tlv),
 908 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 909                eq_tlv),
 910
 911 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 912                eq_tlv),
 913 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 914                eq_tlv),
 915 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 916                eq_tlv),
 917 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 918                eq_tlv),
 919 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 920                eq_tlv),
 921 };
 922
 923 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 924 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 925 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
 926 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
 927 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
 928 };
 929
 930 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 931                          struct snd_kcontrol *kcontrol, int event)
 932 {
 933         struct snd_soc_codec *codec = w->codec;
 934
 935         switch (event) {
 936         case SND_SOC_DAPM_PRE_PMU:
 937                 return configure_clock(codec);
 938
 939         case SND_SOC_DAPM_POST_PMD:
 940                 configure_clock(codec);
 941                 break;
 942         }
 943
 944         return 0;
 945 }
 946
 947 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 948 {
 949         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 950         int enable = 1;
 951         int source = 0;  /* GCC flow analysis can't track enable */
 952         int reg, reg_r;
 953
 954         /* Only support direct DAC->headphone paths */
 955         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 956         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 957                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 958                 enable = 0;
 959         }
 960
 961         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 962         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 963                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 964                 enable = 0;
 965         }
 966
 967         /* We also need the same setting for L/R and only one path */
 968         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 969         switch (reg) {
 970         case WM8994_AIF2DACL_TO_DAC1L:
 971                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 972                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 973                 break;
 974         case WM8994_AIF1DAC2L_TO_DAC1L:
 975                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 976                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 977                 break;
 978         case WM8994_AIF1DAC1L_TO_DAC1L:
 979                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 980                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 981                 break;
 982         default:
 983                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 984                 enable = 0;
 985                 break;
 986         }
 987
 988         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 989         if (reg_r != reg) {
 990                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 991                 enable = 0;
 992         }
 993
 994         if (enable) {
 995                 dev_dbg(codec->dev, "Class W enabled\n");
 996                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 997                                     WM8994_CP_DYN_PWR |
 998                                     WM8994_CP_DYN_SRC_SEL_MASK,
 999                                     source | WM8994_CP_DYN_PWR);
1000                 wm8994->hubs.class_w = true;
1001
1002         } else {
1003                 dev_dbg(codec->dev, "Class W disabled\n");
1004                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1005                                     WM8994_CP_DYN_PWR, 0);
1006                 wm8994->hubs.class_w = false;
1007         }
1008 }
1009
1010 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1011                           struct snd_kcontrol *kcontrol, int event)
1012 {
1013         struct snd_soc_codec *codec = w->codec;
1014         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1015
1016         switch (event) {
1017         case SND_SOC_DAPM_PRE_PMU:
1018                 if (wm8994->aif1clk_enable)
1019                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1020                                             WM8994_AIF1CLK_ENA_MASK,
1021                                             WM8994_AIF1CLK_ENA);
1022                 if (wm8994->aif2clk_enable)
1023                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1024                                             WM8994_AIF2CLK_ENA_MASK,
1025                                             WM8994_AIF2CLK_ENA);
1026                 break;
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1033                            struct snd_kcontrol *kcontrol, int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037
1038         switch (event) {
1039         case SND_SOC_DAPM_POST_PMD:
1040                 if (wm8994->aif1clk_enable) {
1041                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1042                                             WM8994_AIF1CLK_ENA_MASK, 0);
1043                         wm8994->aif1clk_enable = 0;
1044                 }
1045                 if (wm8994->aif2clk_enable) {
1046                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1047                                             WM8994_AIF2CLK_ENA_MASK, 0);
1048                         wm8994->aif2clk_enable = 0;
1049                 }
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1057                       struct snd_kcontrol *kcontrol, int event)
1058 {
1059         struct snd_soc_codec *codec = w->codec;
1060         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1061
1062         switch (event) {
1063         case SND_SOC_DAPM_PRE_PMU:
1064                 wm8994->aif1clk_enable = 1;
1065                 break;
1066         }
1067
1068         return 0;
1069 }
1070
1071 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1072                       struct snd_kcontrol *kcontrol, int event)
1073 {
1074         struct snd_soc_codec *codec = w->codec;
1075         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1076
1077         switch (event) {
1078         case SND_SOC_DAPM_PRE_PMU:
1079                 wm8994->aif2clk_enable = 1;
1080                 break;
1081         }
1082
1083         return 0;
1084 }
1085
1086 static int dac_ev(struct snd_soc_dapm_widget *w,
1087                   struct snd_kcontrol *kcontrol, int event)
1088 {
1089         struct snd_soc_codec *codec = w->codec;
1090         unsigned int mask = 1 << w->shift;
1091
1092         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1093                             mask, mask);
1094         return 0;
1095 }
1096
1097 static const char *hp_mux_text[] = {
1098         "Mixer",
1099         "DAC",
1100 };
1101
1102 #define WM8994_HP_ENUM(xname, xenum) \
1103 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1104         .info = snd_soc_info_enum_double, \
1105         .get = snd_soc_dapm_get_enum_double, \
1106         .put = wm8994_put_hp_enum, \
1107         .private_value = (unsigned long)&xenum }
1108
1109 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1110                               struct snd_ctl_elem_value *ucontrol)
1111 {
1112         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1113         struct snd_soc_codec *codec = w->codec;
1114         int ret;
1115
1116         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1117
1118         wm8994_update_class_w(codec);
1119
1120         return ret;
1121 }
1122
1123 static const struct soc_enum hpl_enum =
1124         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1125
1126 static const struct snd_kcontrol_new hpl_mux =
1127         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1128
1129 static const struct soc_enum hpr_enum =
1130         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1131
1132 static const struct snd_kcontrol_new hpr_mux =
1133         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1134
1135 static const char *adc_mux_text[] = {
1136         "ADC",
1137         "DMIC",
1138 };
1139
1140 static const struct soc_enum adc_enum =
1141         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1142
1143 static const struct snd_kcontrol_new adcl_mux =
1144         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1145
1146 static const struct snd_kcontrol_new adcr_mux =
1147         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1148
1149 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1150 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1151 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1152 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1153 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1154 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1155 };
1156
1157 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1158 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1159 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1160 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1161 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1162 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1163 };
1164
1165 /* Debugging; dump chip status after DAPM transitions */
1166 static int post_ev(struct snd_soc_dapm_widget *w,
1167             struct snd_kcontrol *kcontrol, int event)
1168 {
1169         struct snd_soc_codec *codec = w->codec;
1170         dev_dbg(codec->dev, "SRC status: %x\n",
1171                 snd_soc_read(codec,
1172                              WM8994_RATE_STATUS));
1173         return 0;
1174 }
1175
1176 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1177 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1178                 1, 1, 0),
1179 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1180                 0, 1, 0),
1181 };
1182
1183 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1184 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1185                 1, 1, 0),
1186 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1187                 0, 1, 0),
1188 };
1189
1190 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1191 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1192                 1, 1, 0),
1193 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1194                 0, 1, 0),
1195 };
1196
1197 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1198 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1199                 1, 1, 0),
1200 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1201                 0, 1, 0),
1202 };
1203
1204 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1205 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1206                 5, 1, 0),
1207 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1208                 4, 1, 0),
1209 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1210                 2, 1, 0),
1211 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1212                 1, 1, 0),
1213 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1214                 0, 1, 0),
1215 };
1216
1217 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1218 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1219                 5, 1, 0),
1220 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1221                 4, 1, 0),
1222 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1223                 2, 1, 0),
1224 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1225                 1, 1, 0),
1226 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1227                 0, 1, 0),
1228 };
1229
1230 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1231 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1232         .info = snd_soc_info_volsw, \
1233         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1234         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1235
1236 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1237                               struct snd_ctl_elem_value *ucontrol)
1238 {
1239         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1240         struct snd_soc_codec *codec = w->codec;
1241         int ret;
1242
1243         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1244
1245         wm8994_update_class_w(codec);
1246
1247         return ret;
1248 }
1249
1250 static const struct snd_kcontrol_new dac1l_mix[] = {
1251 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1252                       5, 1, 0),
1253 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1254                       4, 1, 0),
1255 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1256                       2, 1, 0),
1257 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1258                       1, 1, 0),
1259 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1260                       0, 1, 0),
1261 };
1262
1263 static const struct snd_kcontrol_new dac1r_mix[] = {
1264 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1265                       5, 1, 0),
1266 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1267                       4, 1, 0),
1268 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1269                       2, 1, 0),
1270 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1271                       1, 1, 0),
1272 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1273                       0, 1, 0),
1274 };
1275
1276 static const char *sidetone_text[] = {
1277         "ADC/DMIC1", "DMIC2",
1278 };
1279
1280 static const struct soc_enum sidetone1_enum =
1281         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1282
1283 static const struct snd_kcontrol_new sidetone1_mux =
1284         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1285
1286 static const struct soc_enum sidetone2_enum =
1287         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1288
1289 static const struct snd_kcontrol_new sidetone2_mux =
1290         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1291
1292 static const char *aif1dac_text[] = {
1293         "AIF1DACDAT", "AIF3DACDAT",
1294 };
1295
1296 static const struct soc_enum aif1dac_enum =
1297         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1298
1299 static const struct snd_kcontrol_new aif1dac_mux =
1300         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1301
1302 static const char *aif2dac_text[] = {
1303         "AIF2DACDAT", "AIF3DACDAT",
1304 };
1305
1306 static const struct soc_enum aif2dac_enum =
1307         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1308
1309 static const struct snd_kcontrol_new aif2dac_mux =
1310         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1311
1312 static const char *aif2adc_text[] = {
1313         "AIF2ADCDAT", "AIF3DACDAT",
1314 };
1315
1316 static const struct soc_enum aif2adc_enum =
1317         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1318
1319 static const struct snd_kcontrol_new aif2adc_mux =
1320         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1321
1322 static const char *aif3adc_text[] = {
1323         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1324 };
1325
1326 static const struct soc_enum wm8994_aif3adc_enum =
1327         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1328
1329 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1330         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1331
1332 static const struct soc_enum wm8958_aif3adc_enum =
1333         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1334
1335 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1336         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1337
1338 static const char *mono_pcm_out_text[] = {
1339         "None", "AIF2ADCL", "AIF2ADCR",
1340 };
1341
1342 static const struct soc_enum mono_pcm_out_enum =
1343         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1344
1345 static const struct snd_kcontrol_new mono_pcm_out_mux =
1346         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1347
1348 static const char *aif2dac_src_text[] = {
1349         "AIF2", "AIF3",
1350 };
1351
1352 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1353 static const struct soc_enum aif2dacl_src_enum =
1354         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1355
1356 static const struct snd_kcontrol_new aif2dacl_src_mux =
1357         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1358
1359 static const struct soc_enum aif2dacr_src_enum =
1360         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1361
1362 static const struct snd_kcontrol_new aif2dacr_src_mux =
1363         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1364
1365 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1366 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1367         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1368 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1369         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1370
1371 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1372         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1373 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1374         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1375 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1376         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1377 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1378         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1379
1380 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1381 };
1382
1383 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1384 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1385 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1386 };
1387
1388 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1389 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1390         dac_ev, SND_SOC_DAPM_PRE_PMU),
1391 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1392         dac_ev, SND_SOC_DAPM_PRE_PMU),
1393 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1394         dac_ev, SND_SOC_DAPM_PRE_PMU),
1395 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1396         dac_ev, SND_SOC_DAPM_PRE_PMU),
1397 };
1398
1399 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1400 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1401 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1402 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1403 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1404 };
1405
1406 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1407 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1408 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1409 SND_SOC_DAPM_INPUT("Clock"),
1410
1411 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1412                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1413
1414 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1415 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1416 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1417
1418 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1419                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1420 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1421                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1422 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1423                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1424                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1425 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1426                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1427                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1428
1429 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1430                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1431 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1432                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1433 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1434                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1435                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1436 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1437                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1438                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1439
1440 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1441                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1442 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1443                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1444
1445 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1446                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1447 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1448                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1449
1450 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1451                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1452 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1453                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1454
1455 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1456 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1457
1458 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1459                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1460 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1461                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1462
1463 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1464                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1465 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1466                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1467 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1468                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1469                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1470 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1471                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1472                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1473
1474 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1475 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1476 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1477 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1478
1479 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1480 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1481 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1482
1483 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1484 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1485
1486 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1487
1488 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1489 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1490 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1491 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1492
1493 /* Power is done with the muxes since the ADC power also controls the
1494  * downsampling chain, the chip will automatically manage the analogue
1495  * specific portions.
1496  */
1497 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1498 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1499
1500 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1501 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1502
1503 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1504 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1505
1506 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1507                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1508 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1509                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1510
1511 SND_SOC_DAPM_POST("Debug log", post_ev),
1512 };
1513
1514 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1515 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1516 };
1517
1518 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1519 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1520 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1521 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1522 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1523 };
1524
1525 static const struct snd_soc_dapm_route intercon[] = {
1526         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1527         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1528
1529         { "DSP1CLK", NULL, "CLK_SYS" },
1530         { "DSP2CLK", NULL, "CLK_SYS" },
1531         { "DSPINTCLK", NULL, "CLK_SYS" },
1532
1533         { "AIF1ADC1L", NULL, "AIF1CLK" },
1534         { "AIF1ADC1L", NULL, "DSP1CLK" },
1535         { "AIF1ADC1R", NULL, "AIF1CLK" },
1536         { "AIF1ADC1R", NULL, "DSP1CLK" },
1537         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1538
1539         { "AIF1DAC1L", NULL, "AIF1CLK" },
1540         { "AIF1DAC1L", NULL, "DSP1CLK" },
1541         { "AIF1DAC1R", NULL, "AIF1CLK" },
1542         { "AIF1DAC1R", NULL, "DSP1CLK" },
1543         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1544
1545         { "AIF1ADC2L", NULL, "AIF1CLK" },
1546         { "AIF1ADC2L", NULL, "DSP1CLK" },
1547         { "AIF1ADC2R", NULL, "AIF1CLK" },
1548         { "AIF1ADC2R", NULL, "DSP1CLK" },
1549         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1550
1551         { "AIF1DAC2L", NULL, "AIF1CLK" },
1552         { "AIF1DAC2L", NULL, "DSP1CLK" },
1553         { "AIF1DAC2R", NULL, "AIF1CLK" },
1554         { "AIF1DAC2R", NULL, "DSP1CLK" },
1555         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1556
1557         { "AIF2ADCL", NULL, "AIF2CLK" },
1558         { "AIF2ADCL", NULL, "DSP2CLK" },
1559         { "AIF2ADCR", NULL, "AIF2CLK" },
1560         { "AIF2ADCR", NULL, "DSP2CLK" },
1561         { "AIF2ADCR", NULL, "DSPINTCLK" },
1562
1563         { "AIF2DACL", NULL, "AIF2CLK" },
1564         { "AIF2DACL", NULL, "DSP2CLK" },
1565         { "AIF2DACR", NULL, "AIF2CLK" },
1566         { "AIF2DACR", NULL, "DSP2CLK" },
1567         { "AIF2DACR", NULL, "DSPINTCLK" },
1568
1569         { "DMIC1L", NULL, "DMIC1DAT" },
1570         { "DMIC1L", NULL, "CLK_SYS" },
1571         { "DMIC1R", NULL, "DMIC1DAT" },
1572         { "DMIC1R", NULL, "CLK_SYS" },
1573         { "DMIC2L", NULL, "DMIC2DAT" },
1574         { "DMIC2L", NULL, "CLK_SYS" },
1575         { "DMIC2R", NULL, "DMIC2DAT" },
1576         { "DMIC2R", NULL, "CLK_SYS" },
1577
1578         { "ADCL", NULL, "AIF1CLK" },
1579         { "ADCL", NULL, "DSP1CLK" },
1580         { "ADCL", NULL, "DSPINTCLK" },
1581
1582         { "ADCR", NULL, "AIF1CLK" },
1583         { "ADCR", NULL, "DSP1CLK" },
1584         { "ADCR", NULL, "DSPINTCLK" },
1585
1586         { "ADCL Mux", "ADC", "ADCL" },
1587         { "ADCL Mux", "DMIC", "DMIC1L" },
1588         { "ADCR Mux", "ADC", "ADCR" },
1589         { "ADCR Mux", "DMIC", "DMIC1R" },
1590
1591         { "DAC1L", NULL, "AIF1CLK" },
1592         { "DAC1L", NULL, "DSP1CLK" },
1593         { "DAC1L", NULL, "DSPINTCLK" },
1594
1595         { "DAC1R", NULL, "AIF1CLK" },
1596         { "DAC1R", NULL, "DSP1CLK" },
1597         { "DAC1R", NULL, "DSPINTCLK" },
1598
1599         { "DAC2L", NULL, "AIF2CLK" },
1600         { "DAC2L", NULL, "DSP2CLK" },
1601         { "DAC2L", NULL, "DSPINTCLK" },
1602
1603         { "DAC2R", NULL, "AIF2DACR" },
1604         { "DAC2R", NULL, "AIF2CLK" },
1605         { "DAC2R", NULL, "DSP2CLK" },
1606         { "DAC2R", NULL, "DSPINTCLK" },
1607
1608         { "TOCLK", NULL, "CLK_SYS" },
1609
1610         /* AIF1 outputs */
1611         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1612         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1613         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1614
1615         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1616         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1617         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1618
1619         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1620         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1621         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1622
1623         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1624         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1625         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1626
1627         /* Pin level routing for AIF3 */
1628         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1629         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1630         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1631         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1632
1633         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1634         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1635         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1636         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1637         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1638         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1639         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1640
1641         /* DAC1 inputs */
1642         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1643         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1644         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1645         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1646         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1647
1648         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1649         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1650         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1651         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1652         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1653
1654         /* DAC2/AIF2 outputs  */
1655         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1656         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1657         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1658         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1659         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1660         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1661
1662         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1663         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1664         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1665         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1666         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1667         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1668
1669         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1670         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1671         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1672         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1673
1674         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1675
1676         /* AIF3 output */
1677         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1678         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1679         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1680         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1681         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1682         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1683         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1684         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1685
1686         /* Sidetone */
1687         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1688         { "Left Sidetone", "DMIC2", "DMIC2L" },
1689         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1690         { "Right Sidetone", "DMIC2", "DMIC2R" },
1691
1692         /* Output stages */
1693         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1694         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1695
1696         { "SPKL", "DAC1 Switch", "DAC1L" },
1697         { "SPKL", "DAC2 Switch", "DAC2L" },
1698
1699         { "SPKR", "DAC1 Switch", "DAC1R" },
1700         { "SPKR", "DAC2 Switch", "DAC2R" },
1701
1702         { "Left Headphone Mux", "DAC", "DAC1L" },
1703         { "Right Headphone Mux", "DAC", "DAC1R" },
1704 };
1705
1706 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1707         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1708         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1709         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1710         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1711         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1712         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1713         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1714         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1715 };
1716
1717 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1718         { "DAC1L", NULL, "DAC1L Mixer" },
1719         { "DAC1R", NULL, "DAC1R Mixer" },
1720         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1721         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1722 };
1723
1724 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1725         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1726         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1727         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1728         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1729 };
1730
1731 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1732         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1733         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1734 };
1735
1736 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1737         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1738         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1739
1740         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1741         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1742         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1743         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1744
1745         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1746         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1747
1748         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1749 };
1750
1751 /* The size in bits of the FLL divide multiplied by 10
1752  * to allow rounding later */
1753 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1754
1755 struct fll_div {
1756         u16 outdiv;
1757         u16 n;
1758         u16 k;
1759         u16 clk_ref_div;
1760         u16 fll_fratio;
1761 };
1762
1763 static int wm8994_get_fll_config(struct fll_div *fll,
1764                                  int freq_in, int freq_out)
1765 {
1766         u64 Kpart;
1767         unsigned int K, Ndiv, Nmod;
1768
1769         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1770
1771         /* Scale the input frequency down to <= 13.5MHz */
1772         fll->clk_ref_div = 0;
1773         while (freq_in > 13500000) {
1774                 fll->clk_ref_div++;
1775                 freq_in /= 2;
1776
1777                 if (fll->clk_ref_div > 3)
1778                         return -EINVAL;
1779         }
1780         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1781
1782         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1783         fll->outdiv = 3;
1784         while (freq_out * (fll->outdiv + 1) < 90000000) {
1785                 fll->outdiv++;
1786                 if (fll->outdiv > 63)
1787                         return -EINVAL;
1788         }
1789         freq_out *= fll->outdiv + 1;
1790         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1791
1792         if (freq_in > 1000000) {
1793                 fll->fll_fratio = 0;
1794         } else if (freq_in > 256000) {
1795                 fll->fll_fratio = 1;
1796                 freq_in *= 2;
1797         } else if (freq_in > 128000) {
1798                 fll->fll_fratio = 2;
1799                 freq_in *= 4;
1800         } else if (freq_in > 64000) {
1801                 fll->fll_fratio = 3;
1802                 freq_in *= 8;
1803         } else {
1804                 fll->fll_fratio = 4;
1805                 freq_in *= 16;
1806         }
1807         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1808
1809         /* Now, calculate N.K */
1810         Ndiv = freq_out / freq_in;
1811
1812         fll->n = Ndiv;
1813         Nmod = freq_out % freq_in;
1814         pr_debug("Nmod=%d\n", Nmod);
1815
1816         /* Calculate fractional part - scale up so we can round. */
1817         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1818
1819         do_div(Kpart, freq_in);
1820
1821         K = Kpart & 0xFFFFFFFF;
1822
1823         if ((K % 10) >= 5)
1824                 K += 5;
1825
1826         /* Move down to proper range now rounding is done */
1827         fll->k = K / 10;
1828
1829         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1830
1831         return 0;
1832 }
1833
1834 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1835                           unsigned int freq_in, unsigned int freq_out)
1836 {
1837         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1838         int reg_offset, ret;
1839         struct fll_div fll;
1840         u16 reg, aif1, aif2;
1841
1842         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1843                 & WM8994_AIF1CLK_ENA;
1844
1845         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1846                 & WM8994_AIF2CLK_ENA;
1847
1848         switch (id) {
1849         case WM8994_FLL1:
1850                 reg_offset = 0;
1851                 id = 0;
1852                 break;
1853         case WM8994_FLL2:
1854                 reg_offset = 0x20;
1855                 id = 1;
1856                 break;
1857         default:
1858                 return -EINVAL;
1859         }
1860
1861         switch (src) {
1862         case 0:
1863                 /* Allow no source specification when stopping */
1864                 if (freq_out)
1865                         return -EINVAL;
1866                 src = wm8994->fll[id].src;
1867                 break;
1868         case WM8994_FLL_SRC_MCLK1:
1869         case WM8994_FLL_SRC_MCLK2:
1870         case WM8994_FLL_SRC_LRCLK:
1871         case WM8994_FLL_SRC_BCLK:
1872                 break;
1873         default:
1874                 return -EINVAL;
1875         }
1876
1877         /* Are we changing anything? */
1878         if (wm8994->fll[id].src == src &&
1879             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1880                 return 0;
1881
1882         /* If we're stopping the FLL redo the old config - no
1883          * registers will actually be written but we avoid GCC flow
1884          * analysis bugs spewing warnings.
1885          */
1886         if (freq_out)
1887                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1888         else
1889                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1890                                             wm8994->fll[id].out);
1891         if (ret < 0)
1892                 return ret;
1893
1894         /* Gate the AIF clocks while we reclock */
1895         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1896                             WM8994_AIF1CLK_ENA, 0);
1897         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1898                             WM8994_AIF2CLK_ENA, 0);
1899
1900         /* We always need to disable the FLL while reconfiguring */
1901         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1902                             WM8994_FLL1_ENA, 0);
1903
1904         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1905                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1906         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1907                             WM8994_FLL1_OUTDIV_MASK |
1908                             WM8994_FLL1_FRATIO_MASK, reg);
1909
1910         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1911
1912         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1913                             WM8994_FLL1_N_MASK,
1914                                     fll.n << WM8994_FLL1_N_SHIFT);
1915
1916         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1917                             WM8994_FLL1_REFCLK_DIV_MASK |
1918                             WM8994_FLL1_REFCLK_SRC_MASK,
1919                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1920                             (src - 1));
1921
1922         /* Enable (with fractional mode if required) */
1923         if (freq_out) {
1924                 if (fll.k)
1925                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1926                 else
1927                         reg = WM8994_FLL1_ENA;
1928                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1929                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1930                                     reg);
1931         }
1932
1933         wm8994->fll[id].in = freq_in;
1934         wm8994->fll[id].out = freq_out;
1935         wm8994->fll[id].src = src;
1936
1937         /* Enable any gated AIF clocks */
1938         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1939                             WM8994_AIF1CLK_ENA, aif1);
1940         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1941                             WM8994_AIF2CLK_ENA, aif2);
1942
1943         configure_clock(codec);
1944
1945         return 0;
1946 }
1947
1948
1949 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1950
1951 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1952                           unsigned int freq_in, unsigned int freq_out)
1953 {
1954         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1955 }
1956
1957 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1958                 int clk_id, unsigned int freq, int dir)
1959 {
1960         struct snd_soc_codec *codec = dai->codec;
1961         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1962         int i;
1963
1964         switch (dai->id) {
1965         case 1:
1966         case 2:
1967                 break;
1968
1969         default:
1970                 /* AIF3 shares clocking with AIF1/2 */
1971                 return -EINVAL;
1972         }
1973
1974         switch (clk_id) {
1975         case WM8994_SYSCLK_MCLK1:
1976                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1977                 wm8994->mclk[0] = freq;
1978                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1979                         dai->id, freq);
1980                 break;
1981
1982         case WM8994_SYSCLK_MCLK2:
1983                 /* TODO: Set GPIO AF */
1984                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1985                 wm8994->mclk[1] = freq;
1986                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1987                         dai->id, freq);
1988                 break;
1989
1990         case WM8994_SYSCLK_FLL1:
1991                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1992                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1993                 break;
1994
1995         case WM8994_SYSCLK_FLL2:
1996                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1997                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1998                 break;
1999
2000         case WM8994_SYSCLK_OPCLK:
2001                 /* Special case - a division (times 10) is given and
2002                  * no effect on main clocking.
2003                  */
2004                 if (freq) {
2005                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2006                                 if (opclk_divs[i] == freq)
2007                                         break;
2008                         if (i == ARRAY_SIZE(opclk_divs))
2009                                 return -EINVAL;
2010                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2011                                             WM8994_OPCLK_DIV_MASK, i);
2012                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2013                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2014                 } else {
2015                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2016                                             WM8994_OPCLK_ENA, 0);
2017                 }
2018
2019         default:
2020                 return -EINVAL;
2021         }
2022
2023         configure_clock(codec);
2024
2025         return 0;
2026 }
2027
2028 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2029                                  enum snd_soc_bias_level level)
2030 {
2031         struct wm8994 *control = codec->control_data;
2032         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2033
2034         switch (level) {
2035         case SND_SOC_BIAS_ON:
2036                 break;
2037
2038         case SND_SOC_BIAS_PREPARE:
2039                 /* VMID=2x40k */
2040                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2041                                     WM8994_VMID_SEL_MASK, 0x2);
2042                 break;
2043
2044         case SND_SOC_BIAS_STANDBY:
2045                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2046                         pm_runtime_get_sync(codec->dev);
2047
2048                         switch (control->type) {
2049                         case WM8994:
2050                                 if (wm8994->revision < 4) {
2051                                         /* Tweak DC servo and DSP
2052                                          * configuration for improved
2053                                          * performance. */
2054                                         snd_soc_write(codec, 0x102, 0x3);
2055                                         snd_soc_write(codec, 0x56, 0x3);
2056                                         snd_soc_write(codec, 0x817, 0);
2057                                         snd_soc_write(codec, 0x102, 0);
2058                                 }
2059                                 break;
2060
2061                         case WM8958:
2062                                 if (wm8994->revision == 0) {
2063                                         /* Optimise performance for rev A */
2064                                         snd_soc_write(codec, 0x102, 0x3);
2065                                         snd_soc_write(codec, 0xcb, 0x81);
2066                                         snd_soc_write(codec, 0x817, 0);
2067                                         snd_soc_write(codec, 0x102, 0);
2068
2069                                         snd_soc_update_bits(codec,
2070                                                             WM8958_CHARGE_PUMP_2,
2071                                                             WM8958_CP_DISCH,
2072                                                             WM8958_CP_DISCH);
2073                                 }
2074                                 break;
2075                         }
2076
2077                         /* Discharge LINEOUT1 & 2 */
2078                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2079                                             WM8994_LINEOUT1_DISCH |
2080                                             WM8994_LINEOUT2_DISCH,
2081                                             WM8994_LINEOUT1_DISCH |
2082                                             WM8994_LINEOUT2_DISCH);
2083
2084                         /* Startup bias, VMID ramp & buffer */
2085                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2086                                             WM8994_STARTUP_BIAS_ENA |
2087                                             WM8994_VMID_BUF_ENA |
2088                                             WM8994_VMID_RAMP_MASK,
2089                                             WM8994_STARTUP_BIAS_ENA |
2090                                             WM8994_VMID_BUF_ENA |
2091                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
2092
2093                         /* Main bias enable, VMID=2x40k */
2094                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2095                                             WM8994_BIAS_ENA |
2096                                             WM8994_VMID_SEL_MASK,
2097                                             WM8994_BIAS_ENA | 0x2);
2098
2099                         msleep(20);
2100                 }
2101
2102                 /* VMID=2x500k */
2103                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2104                                     WM8994_VMID_SEL_MASK, 0x4);
2105
2106                 break;
2107
2108         case SND_SOC_BIAS_OFF:
2109                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2110                         /* Switch over to startup biases */
2111                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2112                                             WM8994_BIAS_SRC |
2113                                             WM8994_STARTUP_BIAS_ENA |
2114                                             WM8994_VMID_BUF_ENA |
2115                                             WM8994_VMID_RAMP_MASK,
2116                                             WM8994_BIAS_SRC |
2117                                             WM8994_STARTUP_BIAS_ENA |
2118                                             WM8994_VMID_BUF_ENA |
2119                                             (1 << WM8994_VMID_RAMP_SHIFT));
2120
2121                         /* Disable main biases */
2122                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2123                                             WM8994_BIAS_ENA |
2124                                             WM8994_VMID_SEL_MASK, 0);
2125
2126                         /* Discharge line */
2127                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2128                                             WM8994_LINEOUT1_DISCH |
2129                                             WM8994_LINEOUT2_DISCH,
2130                                             WM8994_LINEOUT1_DISCH |
2131                                             WM8994_LINEOUT2_DISCH);
2132
2133                         msleep(5);
2134
2135                         /* Switch off startup biases */
2136                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2137                                             WM8994_BIAS_SRC |
2138                                             WM8994_STARTUP_BIAS_ENA |
2139                                             WM8994_VMID_BUF_ENA |
2140                                             WM8994_VMID_RAMP_MASK, 0);
2141
2142                         pm_runtime_put(codec->dev);
2143                 }
2144                 break;
2145         }
2146         codec->dapm.bias_level = level;
2147         return 0;
2148 }
2149
2150 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2151 {
2152         struct snd_soc_codec *codec = dai->codec;
2153         struct wm8994 *control = codec->control_data;
2154         int ms_reg;
2155         int aif1_reg;
2156         int ms = 0;
2157         int aif1 = 0;
2158
2159         switch (dai->id) {
2160         case 1:
2161                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2162                 aif1_reg = WM8994_AIF1_CONTROL_1;
2163                 break;
2164         case 2:
2165                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2166                 aif1_reg = WM8994_AIF2_CONTROL_1;
2167                 break;
2168         default:
2169                 return -EINVAL;
2170         }
2171
2172         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2173         case SND_SOC_DAIFMT_CBS_CFS:
2174                 break;
2175         case SND_SOC_DAIFMT_CBM_CFM:
2176                 ms = WM8994_AIF1_MSTR;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2183         case SND_SOC_DAIFMT_DSP_B:
2184                 aif1 |= WM8994_AIF1_LRCLK_INV;
2185         case SND_SOC_DAIFMT_DSP_A:
2186                 aif1 |= 0x18;
2187                 break;
2188         case SND_SOC_DAIFMT_I2S:
2189                 aif1 |= 0x10;
2190                 break;
2191         case SND_SOC_DAIFMT_RIGHT_J:
2192                 break;
2193         case SND_SOC_DAIFMT_LEFT_J:
2194                 aif1 |= 0x8;
2195                 break;
2196         default:
2197                 return -EINVAL;
2198         }
2199
2200         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2201         case SND_SOC_DAIFMT_DSP_A:
2202         case SND_SOC_DAIFMT_DSP_B:
2203                 /* frame inversion not valid for DSP modes */
2204                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2205                 case SND_SOC_DAIFMT_NB_NF:
2206                         break;
2207                 case SND_SOC_DAIFMT_IB_NF:
2208                         aif1 |= WM8994_AIF1_BCLK_INV;
2209                         break;
2210                 default:
2211                         return -EINVAL;
2212                 }
2213                 break;
2214
2215         case SND_SOC_DAIFMT_I2S:
2216         case SND_SOC_DAIFMT_RIGHT_J:
2217         case SND_SOC_DAIFMT_LEFT_J:
2218                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2219                 case SND_SOC_DAIFMT_NB_NF:
2220                         break;
2221                 case SND_SOC_DAIFMT_IB_IF:
2222                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2223                         break;
2224                 case SND_SOC_DAIFMT_IB_NF:
2225                         aif1 |= WM8994_AIF1_BCLK_INV;
2226                         break;
2227                 case SND_SOC_DAIFMT_NB_IF:
2228                         aif1 |= WM8994_AIF1_LRCLK_INV;
2229                         break;
2230                 default:
2231                         return -EINVAL;
2232                 }
2233                 break;
2234         default:
2235                 return -EINVAL;
2236         }
2237
2238         /* The AIF2 format configuration needs to be mirrored to AIF3
2239          * on WM8958 if it's in use so just do it all the time. */
2240         if (control->type == WM8958 && dai->id == 2)
2241                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2242                                     WM8994_AIF1_LRCLK_INV |
2243                                     WM8958_AIF3_FMT_MASK, aif1);
2244
2245         snd_soc_update_bits(codec, aif1_reg,
2246                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2247                             WM8994_AIF1_FMT_MASK,
2248                             aif1);
2249         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2250                             ms);
2251
2252         return 0;
2253 }
2254
2255 static struct {
2256         int val, rate;
2257 } srs[] = {
2258         { 0,   8000 },
2259         { 1,  11025 },
2260         { 2,  12000 },
2261         { 3,  16000 },
2262         { 4,  22050 },
2263         { 5,  24000 },
2264         { 6,  32000 },
2265         { 7,  44100 },
2266         { 8,  48000 },
2267         { 9,  88200 },
2268         { 10, 96000 },
2269 };
2270
2271 static int fs_ratios[] = {
2272         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2273 };
2274
2275 static int bclk_divs[] = {
2276         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2277         640, 880, 960, 1280, 1760, 1920
2278 };
2279
2280 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2281                             struct snd_pcm_hw_params *params,
2282                             struct snd_soc_dai *dai)
2283 {
2284         struct snd_soc_codec *codec = dai->codec;
2285         struct wm8994 *control = codec->control_data;
2286         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2287         int aif1_reg;
2288         int aif2_reg;
2289         int bclk_reg;
2290         int lrclk_reg;
2291         int rate_reg;
2292         int aif1 = 0;
2293         int aif2 = 0;
2294         int bclk = 0;
2295         int lrclk = 0;
2296         int rate_val = 0;
2297         int id = dai->id - 1;
2298
2299         int i, cur_val, best_val, bclk_rate, best;
2300
2301         switch (dai->id) {
2302         case 1:
2303                 aif1_reg = WM8994_AIF1_CONTROL_1;
2304                 aif2_reg = WM8994_AIF1_CONTROL_2;
2305                 bclk_reg = WM8994_AIF1_BCLK;
2306                 rate_reg = WM8994_AIF1_RATE;
2307                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2308                     wm8994->lrclk_shared[0]) {
2309                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2310                 } else {
2311                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2312                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2313                 }
2314                 break;
2315         case 2:
2316                 aif1_reg = WM8994_AIF2_CONTROL_1;
2317                 aif2_reg = WM8994_AIF2_CONTROL_2;
2318                 bclk_reg = WM8994_AIF2_BCLK;
2319                 rate_reg = WM8994_AIF2_RATE;
2320                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2321                     wm8994->lrclk_shared[1]) {
2322                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2323                 } else {
2324                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2325                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2326                 }
2327                 break;
2328         case 3:
2329                 switch (control->type) {
2330                 case WM8958:
2331                         aif1_reg = WM8958_AIF3_CONTROL_1;
2332                         break;
2333                 default:
2334                         return 0;
2335                 }
2336         default:
2337                 return -EINVAL;
2338         }
2339
2340         bclk_rate = params_rate(params) * 2;
2341         switch (params_format(params)) {
2342         case SNDRV_PCM_FORMAT_S16_LE:
2343                 bclk_rate *= 16;
2344                 break;
2345         case SNDRV_PCM_FORMAT_S20_3LE:
2346                 bclk_rate *= 20;
2347                 aif1 |= 0x20;
2348                 break;
2349         case SNDRV_PCM_FORMAT_S24_LE:
2350                 bclk_rate *= 24;
2351                 aif1 |= 0x40;
2352                 break;
2353         case SNDRV_PCM_FORMAT_S32_LE:
2354                 bclk_rate *= 32;
2355                 aif1 |= 0x60;
2356                 break;
2357         default:
2358                 return -EINVAL;
2359         }
2360
2361         /* Try to find an appropriate sample rate; look for an exact match. */
2362         for (i = 0; i < ARRAY_SIZE(srs); i++)
2363                 if (srs[i].rate == params_rate(params))
2364                         break;
2365         if (i == ARRAY_SIZE(srs))
2366                 return -EINVAL;
2367         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2368
2369         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2370         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2371                 dai->id, wm8994->aifclk[id], bclk_rate);
2372
2373         if (params_channels(params) == 1 &&
2374             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2375                 aif2 |= WM8994_AIF1_MONO;
2376
2377         if (wm8994->aifclk[id] == 0) {
2378                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2379                 return -EINVAL;
2380         }
2381
2382         /* AIFCLK/fs ratio; look for a close match in either direction */
2383         best = 0;
2384         best_val = abs((fs_ratios[0] * params_rate(params))
2385                        - wm8994->aifclk[id]);
2386         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2387                 cur_val = abs((fs_ratios[i] * params_rate(params))
2388                               - wm8994->aifclk[id]);
2389                 if (cur_val >= best_val)
2390                         continue;
2391                 best = i;
2392                 best_val = cur_val;
2393         }
2394         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2395                 dai->id, fs_ratios[best]);
2396         rate_val |= best;
2397
2398         /* We may not get quite the right frequency if using
2399          * approximate clocks so look for the closest match that is
2400          * higher than the target (we need to ensure that there enough
2401          * BCLKs to clock out the samples).
2402          */
2403         best = 0;
2404         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2405                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2406                 if (cur_val < 0) /* BCLK table is sorted */
2407                         break;
2408                 best = i;
2409         }
2410         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2411         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2412                 bclk_divs[best], bclk_rate);
2413         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2414
2415         lrclk = bclk_rate / params_rate(params);
2416         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2417                 lrclk, bclk_rate / lrclk);
2418
2419         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2420         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2421         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2422         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2423                             lrclk);
2424         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2425                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2426
2427         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2428                 switch (dai->id) {
2429                 case 1:
2430                         wm8994->dac_rates[0] = params_rate(params);
2431                         wm8994_set_retune_mobile(codec, 0);
2432                         wm8994_set_retune_mobile(codec, 1);
2433                         break;
2434                 case 2:
2435                         wm8994->dac_rates[1] = params_rate(params);
2436                         wm8994_set_retune_mobile(codec, 2);
2437                         break;
2438                 }
2439         }
2440
2441         return 0;
2442 }
2443
2444 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2445                                  struct snd_pcm_hw_params *params,
2446                                  struct snd_soc_dai *dai)
2447 {
2448         struct snd_soc_codec *codec = dai->codec;
2449         struct wm8994 *control = codec->control_data;
2450         int aif1_reg;
2451         int aif1 = 0;
2452
2453         switch (dai->id) {
2454         case 3:
2455                 switch (control->type) {
2456                 case WM8958:
2457                         aif1_reg = WM8958_AIF3_CONTROL_1;
2458                         break;
2459                 default:
2460                         return 0;
2461                 }
2462         default:
2463                 return 0;
2464         }
2465
2466         switch (params_format(params)) {
2467         case SNDRV_PCM_FORMAT_S16_LE:
2468                 break;
2469         case SNDRV_PCM_FORMAT_S20_3LE:
2470                 aif1 |= 0x20;
2471                 break;
2472         case SNDRV_PCM_FORMAT_S24_LE:
2473                 aif1 |= 0x40;
2474                 break;
2475         case SNDRV_PCM_FORMAT_S32_LE:
2476                 aif1 |= 0x60;
2477                 break;
2478         default:
2479                 return -EINVAL;
2480         }
2481
2482         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2483 }
2484
2485 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2486 {
2487         struct snd_soc_codec *codec = codec_dai->codec;
2488         int mute_reg;
2489         int reg;
2490
2491         switch (codec_dai->id) {
2492         case 1:
2493                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2494                 break;
2495         case 2:
2496                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2497                 break;
2498         default:
2499                 return -EINVAL;
2500         }
2501
2502         if (mute)
2503                 reg = WM8994_AIF1DAC1_MUTE;
2504         else
2505                 reg = 0;
2506
2507         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2508
2509         return 0;
2510 }
2511
2512 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2513 {
2514         struct snd_soc_codec *codec = codec_dai->codec;
2515         int reg, val, mask;
2516
2517         switch (codec_dai->id) {
2518         case 1:
2519                 reg = WM8994_AIF1_MASTER_SLAVE;
2520                 mask = WM8994_AIF1_TRI;
2521                 break;
2522         case 2:
2523                 reg = WM8994_AIF2_MASTER_SLAVE;
2524                 mask = WM8994_AIF2_TRI;
2525                 break;
2526         case 3:
2527                 reg = WM8994_POWER_MANAGEMENT_6;
2528                 mask = WM8994_AIF3_TRI;
2529                 break;
2530         default:
2531                 return -EINVAL;
2532         }
2533
2534         if (tristate)
2535                 val = mask;
2536         else
2537                 val = 0;
2538
2539         return snd_soc_update_bits(codec, reg, mask, val);
2540 }
2541
2542 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2543
2544 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2545                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2546
2547 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2548         .set_sysclk     = wm8994_set_dai_sysclk,
2549         .set_fmt        = wm8994_set_dai_fmt,
2550         .hw_params      = wm8994_hw_params,
2551         .digital_mute   = wm8994_aif_mute,
2552         .set_pll        = wm8994_set_fll,
2553         .set_tristate   = wm8994_set_tristate,
2554 };
2555
2556 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2557         .set_sysclk     = wm8994_set_dai_sysclk,
2558         .set_fmt        = wm8994_set_dai_fmt,
2559         .hw_params      = wm8994_hw_params,
2560         .digital_mute   = wm8994_aif_mute,
2561         .set_pll        = wm8994_set_fll,
2562         .set_tristate   = wm8994_set_tristate,
2563 };
2564
2565 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2566         .hw_params      = wm8994_aif3_hw_params,
2567         .set_tristate   = wm8994_set_tristate,
2568 };
2569
2570 static struct snd_soc_dai_driver wm8994_dai[] = {
2571         {
2572                 .name = "wm8994-aif1",
2573                 .id = 1,
2574                 .playback = {
2575                         .stream_name = "AIF1 Playback",
2576                         .channels_min = 1,
2577                         .channels_max = 2,
2578                         .rates = WM8994_RATES,
2579                         .formats = WM8994_FORMATS,
2580                 },
2581                 .capture = {
2582                         .stream_name = "AIF1 Capture",
2583                         .channels_min = 1,
2584                         .channels_max = 2,
2585                         .rates = WM8994_RATES,
2586                         .formats = WM8994_FORMATS,
2587                  },
2588                 .ops = &wm8994_aif1_dai_ops,
2589         },
2590         {
2591                 .name = "wm8994-aif2",
2592                 .id = 2,
2593                 .playback = {
2594                         .stream_name = "AIF2 Playback",
2595                         .channels_min = 1,
2596                         .channels_max = 2,
2597                         .rates = WM8994_RATES,
2598                         .formats = WM8994_FORMATS,
2599                 },
2600                 .capture = {
2601                         .stream_name = "AIF2 Capture",
2602                         .channels_min = 1,
2603                         .channels_max = 2,
2604                         .rates = WM8994_RATES,
2605                         .formats = WM8994_FORMATS,
2606                 },
2607                 .ops = &wm8994_aif2_dai_ops,
2608         },
2609         {
2610                 .name = "wm8994-aif3",
2611                 .id = 3,
2612                 .playback = {
2613                         .stream_name = "AIF3 Playback",
2614                         .channels_min = 1,
2615                         .channels_max = 2,
2616                         .rates = WM8994_RATES,
2617                         .formats = WM8994_FORMATS,
2618                 },
2619                 .capture = {
2620                         .stream_name = "AIF3 Capture",
2621                         .channels_min = 1,
2622                         .channels_max = 2,
2623                         .rates = WM8994_RATES,
2624                         .formats = WM8994_FORMATS,
2625                 },
2626                 .ops = &wm8994_aif3_dai_ops,
2627         }
2628 };
2629
2630 #ifdef CONFIG_PM
2631 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2632 {
2633         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2634         int i, ret;
2635
2636         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2637                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2638                        sizeof(struct fll_config));
2639                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2640                 if (ret < 0)
2641                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2642                                  i + 1, ret);
2643         }
2644
2645         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2646
2647         return 0;
2648 }
2649
2650 static int wm8994_resume(struct snd_soc_codec *codec)
2651 {
2652         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2653         int i, ret;
2654         unsigned int val, mask;
2655
2656         if (wm8994->revision < 4) {
2657                 /* force a HW read */
2658                 val = wm8994_reg_read(codec->control_data,
2659                                       WM8994_POWER_MANAGEMENT_5);
2660
2661                 /* modify the cache only */
2662                 codec->cache_only = 1;
2663                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2664                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2665                 val &= mask;
2666                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2667                                     mask, val);
2668                 codec->cache_only = 0;
2669         }
2670
2671         /* Restore the registers */
2672         ret = snd_soc_cache_sync(codec);
2673         if (ret != 0)
2674                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2675
2676         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2677
2678         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2679                 if (!wm8994->fll_suspend[i].out)
2680                         continue;
2681
2682                 ret = _wm8994_set_fll(codec, i + 1,
2683                                      wm8994->fll_suspend[i].src,
2684                                      wm8994->fll_suspend[i].in,
2685                                      wm8994->fll_suspend[i].out);
2686                 if (ret < 0)
2687                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2688                                  i + 1, ret);
2689         }
2690
2691         return 0;
2692 }
2693 #else
2694 #define wm8994_suspend NULL
2695 #define wm8994_resume NULL
2696 #endif
2697
2698 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2699 {
2700         struct snd_soc_codec *codec = wm8994->codec;
2701         struct wm8994_pdata *pdata = wm8994->pdata;
2702         struct snd_kcontrol_new controls[] = {
2703                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2704                              wm8994->retune_mobile_enum,
2705                              wm8994_get_retune_mobile_enum,
2706                              wm8994_put_retune_mobile_enum),
2707                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2708                              wm8994->retune_mobile_enum,
2709                              wm8994_get_retune_mobile_enum,
2710                              wm8994_put_retune_mobile_enum),
2711                 SOC_ENUM_EXT("AIF2 EQ Mode",
2712                              wm8994->retune_mobile_enum,
2713                              wm8994_get_retune_mobile_enum,
2714                              wm8994_put_retune_mobile_enum),
2715         };
2716         int ret, i, j;
2717         const char **t;
2718
2719         /* We need an array of texts for the enum API but the number
2720          * of texts is likely to be less than the number of
2721          * configurations due to the sample rate dependency of the
2722          * configurations. */
2723         wm8994->num_retune_mobile_texts = 0;
2724         wm8994->retune_mobile_texts = NULL;
2725         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2726                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2727                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2728                                    wm8994->retune_mobile_texts[j]) == 0)
2729                                 break;
2730                 }
2731
2732                 if (j != wm8994->num_retune_mobile_texts)
2733                         continue;
2734
2735                 /* Expand the array... */
2736                 t = krealloc(wm8994->retune_mobile_texts,
2737                              sizeof(char *) *
2738                              (wm8994->num_retune_mobile_texts + 1),
2739                              GFP_KERNEL);
2740                 if (t == NULL)
2741                         continue;
2742
2743                 /* ...store the new entry... */
2744                 t[wm8994->num_retune_mobile_texts] =
2745                         pdata->retune_mobile_cfgs[i].name;
2746
2747                 /* ...and remember the new version. */
2748                 wm8994->num_retune_mobile_texts++;
2749                 wm8994->retune_mobile_texts = t;
2750         }
2751
2752         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2753                 wm8994->num_retune_mobile_texts);
2754
2755         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2756         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2757
2758         ret = snd_soc_add_controls(wm8994->codec, controls,
2759                                    ARRAY_SIZE(controls));
2760         if (ret != 0)
2761                 dev_err(wm8994->codec->dev,
2762                         "Failed to add ReTune Mobile controls: %d\n", ret);
2763 }
2764
2765 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2766 {
2767         struct snd_soc_codec *codec = wm8994->codec;
2768         struct wm8994_pdata *pdata = wm8994->pdata;
2769         int ret, i;
2770
2771         if (!pdata)
2772                 return;
2773
2774         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2775                                       pdata->lineout2_diff,
2776                                       pdata->lineout1fb,
2777                                       pdata->lineout2fb,
2778                                       pdata->jd_scthr,
2779                                       pdata->jd_thr,
2780                                       pdata->micbias1_lvl,
2781                                       pdata->micbias2_lvl);
2782
2783         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2784
2785         if (pdata->num_drc_cfgs) {
2786                 struct snd_kcontrol_new controls[] = {
2787                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2788                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2789                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2790                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2791                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2792                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2793                 };
2794
2795                 /* We need an array of texts for the enum API */
2796                 wm8994->drc_texts = kmalloc(sizeof(char *)
2797                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2798                 if (!wm8994->drc_texts) {
2799                         dev_err(wm8994->codec->dev,
2800                                 "Failed to allocate %d DRC config texts\n",
2801                                 pdata->num_drc_cfgs);
2802                         return;
2803                 }
2804
2805                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2806                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2807
2808                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2809                 wm8994->drc_enum.texts = wm8994->drc_texts;
2810
2811                 ret = snd_soc_add_controls(wm8994->codec, controls,
2812                                            ARRAY_SIZE(controls));
2813                 if (ret != 0)
2814                         dev_err(wm8994->codec->dev,
2815                                 "Failed to add DRC mode controls: %d\n", ret);
2816
2817                 for (i = 0; i < WM8994_NUM_DRC; i++)
2818                         wm8994_set_drc(codec, i);
2819         }
2820
2821         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2822                 pdata->num_retune_mobile_cfgs);
2823
2824         if (pdata->num_mbc_cfgs) {
2825                 struct snd_kcontrol_new control[] = {
2826                         SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2827                                      wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2828                 };
2829
2830                 /* We need an array of texts for the enum API */
2831                 wm8994->mbc_texts = kmalloc(sizeof(char *)
2832                                             * pdata->num_mbc_cfgs, GFP_KERNEL);
2833                 if (!wm8994->mbc_texts) {
2834                         dev_err(wm8994->codec->dev,
2835                                 "Failed to allocate %d MBC config texts\n",
2836                                 pdata->num_mbc_cfgs);
2837                         return;
2838                 }
2839
2840                 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2841                         wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2842
2843                 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2844                 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2845
2846                 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2847                 if (ret != 0)
2848                         dev_err(wm8994->codec->dev,
2849                                 "Failed to add MBC mode controls: %d\n", ret);
2850         }
2851
2852         if (pdata->num_retune_mobile_cfgs)
2853                 wm8994_handle_retune_mobile_pdata(wm8994);
2854         else
2855                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2856                                      ARRAY_SIZE(wm8994_eq_controls));
2857 }
2858
2859 /**
2860  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2861  *
2862  * @codec:   WM8994 codec
2863  * @jack:    jack to report detection events on
2864  * @micbias: microphone bias to detect on
2865  * @det:     value to report for presence detection
2866  * @shrt:    value to report for short detection
2867  *
2868  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2869  * being used to bring out signals to the processor then only platform
2870  * data configuration is needed for WM8994 and processor GPIOs should
2871  * be configured using snd_soc_jack_add_gpios() instead.
2872  *
2873  * Configuration of detection levels is available via the micbias1_lvl
2874  * and micbias2_lvl platform data members.
2875  */
2876 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2877                       int micbias, int det, int shrt)
2878 {
2879         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2880         struct wm8994_micdet *micdet;
2881         struct wm8994 *control = codec->control_data;
2882         int reg;
2883
2884         if (control->type != WM8994)
2885                 return -EINVAL;
2886
2887         switch (micbias) {
2888         case 1:
2889                 micdet = &wm8994->micdet[0];
2890                 break;
2891         case 2:
2892                 micdet = &wm8994->micdet[1];
2893                 break;
2894         default:
2895                 return -EINVAL;
2896         }
2897
2898         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2899                 micbias, det, shrt);
2900
2901         /* Store the configuration */
2902         micdet->jack = jack;
2903         micdet->det = det;
2904         micdet->shrt = shrt;
2905
2906         /* If either of the jacks is set up then enable detection */
2907         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2908                 reg = WM8994_MICD_ENA;
2909         else
2910                 reg = 0;
2911
2912         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2913
2914         return 0;
2915 }
2916 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2917
2918 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2919 {
2920         struct wm8994_priv *priv = data;
2921         struct snd_soc_codec *codec = priv->codec;
2922         int reg;
2923         int report;
2924
2925 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2926         trace_snd_soc_jack_irq(dev_name(codec->dev));
2927 #endif
2928
2929         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2930         if (reg < 0) {
2931                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2932                         reg);
2933                 return IRQ_HANDLED;
2934         }
2935
2936         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2937
2938         report = 0;
2939         if (reg & WM8994_MIC1_DET_STS)
2940                 report |= priv->micdet[0].det;
2941         if (reg & WM8994_MIC1_SHRT_STS)
2942                 report |= priv->micdet[0].shrt;
2943         snd_soc_jack_report(priv->micdet[0].jack, report,
2944                             priv->micdet[0].det | priv->micdet[0].shrt);
2945
2946         report = 0;
2947         if (reg & WM8994_MIC2_DET_STS)
2948                 report |= priv->micdet[1].det;
2949         if (reg & WM8994_MIC2_SHRT_STS)
2950                 report |= priv->micdet[1].shrt;
2951         snd_soc_jack_report(priv->micdet[1].jack, report,
2952                             priv->micdet[1].det | priv->micdet[1].shrt);
2953
2954         return IRQ_HANDLED;
2955 }
2956
2957 /* Default microphone detection handler for WM8958 - the user can
2958  * override this if they wish.
2959  */
2960 static void wm8958_default_micdet(u16 status, void *data)
2961 {
2962         struct snd_soc_codec *codec = data;
2963         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2964         int report = 0;
2965
2966         /* If nothing present then clear our statuses */
2967         if (!(status & WM8958_MICD_STS)) {
2968                 wm8994->jack_is_video = false;
2969                 wm8994->jack_is_mic = false;
2970                 goto done;
2971         }
2972
2973         /* Assume anything over 475 ohms is a microphone and remember
2974          * that we've seen one (since buttons override it) */
2975         if (status & 0x600)
2976                 wm8994->jack_is_mic = true;
2977         if (wm8994->jack_is_mic)
2978                 report |= SND_JACK_MICROPHONE;
2979
2980         /* Video has an impedence of approximately 75 ohms; assume
2981          * this isn't used as a button and remember it since buttons
2982          * override it. */
2983         if (status & 0x40)
2984                 wm8994->jack_is_video = true;
2985         if (wm8994->jack_is_video)
2986                 report |= SND_JACK_VIDEOOUT;
2987
2988         /* Everything else is buttons; just assign slots */
2989         if (status & 0x4)
2990                 report |= SND_JACK_BTN_0;
2991         if (status & 0x8)
2992                 report |= SND_JACK_BTN_1;
2993         if (status & 0x10)
2994                 report |= SND_JACK_BTN_2;
2995         if (status & 0x20)
2996                 report |= SND_JACK_BTN_3;
2997         if (status & 0x80)
2998                 report |= SND_JACK_BTN_4;
2999         if (status & 0x100)
3000                 report |= SND_JACK_BTN_5;
3001
3002 done:
3003         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3004                             SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
3005                             SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
3006                             SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT);
3007 }
3008
3009 /**
3010  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3011  *
3012  * @codec:   WM8958 codec
3013  * @jack:    jack to report detection events on
3014  *
3015  * Enable microphone detection functionality for the WM8958.  By
3016  * default simple detection which supports the detection of up to 6
3017  * buttons plus video and microphone functionality is supported.
3018  *
3019  * The WM8958 has an advanced jack detection facility which is able to
3020  * support complex accessory detection, especially when used in
3021  * conjunction with external circuitry.  In order to provide maximum
3022  * flexiblity a callback is provided which allows a completely custom
3023  * detection algorithm.
3024  */
3025 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3026                       wm8958_micdet_cb cb, void *cb_data)
3027 {
3028         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3029         struct wm8994 *control = codec->control_data;
3030
3031         if (control->type != WM8958)
3032                 return -EINVAL;
3033
3034         if (jack) {
3035                 if (!cb) {
3036                         dev_dbg(codec->dev, "Using default micdet callback\n");
3037                         cb = wm8958_default_micdet;
3038                         cb_data = codec;
3039                 }
3040
3041                 wm8994->micdet[0].jack = jack;
3042                 wm8994->jack_cb = cb;
3043                 wm8994->jack_cb_data = cb_data;
3044
3045                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3046                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3047         } else {
3048                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3049                                     WM8958_MICD_ENA, 0);
3050         }
3051
3052         return 0;
3053 }
3054 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3055
3056 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3057 {
3058         struct wm8994_priv *wm8994 = data;
3059         struct snd_soc_codec *codec = wm8994->codec;
3060         int reg;
3061
3062         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3063         if (reg < 0) {
3064                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3065                         reg);
3066                 return IRQ_NONE;
3067         }
3068
3069         if (!(reg & WM8958_MICD_VALID)) {
3070                 dev_dbg(codec->dev, "Mic detect data not valid\n");
3071                 goto out;
3072         }
3073
3074 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3075         trace_snd_soc_jack_irq(dev_name(codec->dev));
3076 #endif
3077
3078         if (wm8994->jack_cb)
3079                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3080         else
3081                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3082
3083 out:
3084         return IRQ_HANDLED;
3085 }
3086
3087 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3088 {
3089         struct wm8994 *control;
3090         struct wm8994_priv *wm8994;
3091         struct snd_soc_dapm_context *dapm = &codec->dapm;
3092         int ret, i;
3093
3094         codec->control_data = dev_get_drvdata(codec->dev->parent);
3095         control = codec->control_data;
3096
3097         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3098         if (wm8994 == NULL)
3099                 return -ENOMEM;
3100         snd_soc_codec_set_drvdata(codec, wm8994);
3101
3102         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3103         wm8994->codec = codec;
3104
3105         pm_runtime_enable(codec->dev);
3106         pm_runtime_resume(codec->dev);
3107
3108         /* Read our current status back from the chip - we don't want to
3109          * reset as this may interfere with the GPIO or LDO operation. */
3110         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3111                 if (!wm8994_readable(i) || wm8994_volatile(i))
3112                         continue;
3113
3114                 ret = wm8994_reg_read(codec->control_data, i);
3115                 if (ret <= 0)
3116                         continue;
3117
3118                 ret = snd_soc_cache_write(codec, i, ret);
3119                 if (ret != 0) {
3120                         dev_err(codec->dev,
3121                                 "Failed to initialise cache for 0x%x: %d\n",
3122                                 i, ret);
3123                         goto err;
3124                 }
3125         }
3126
3127         /* Set revision-specific configuration */
3128         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3129         switch (control->type) {
3130         case WM8994:
3131                 switch (wm8994->revision) {
3132                 case 2:
3133                 case 3:
3134                         wm8994->hubs.dcs_codes = -5;
3135                         wm8994->hubs.hp_startup_mode = 1;
3136                         wm8994->hubs.dcs_readback_mode = 1;
3137                         break;
3138                 default:
3139                         wm8994->hubs.dcs_readback_mode = 1;
3140                         break;
3141                 }
3142
3143         case WM8958:
3144                 wm8994->hubs.dcs_readback_mode = 1;
3145                 break;
3146
3147         default:
3148                 break;
3149         }
3150
3151         switch (control->type) {
3152         case WM8994:
3153                 ret = wm8994_request_irq(codec->control_data,
3154                                          WM8994_IRQ_MIC1_DET,
3155                                          wm8994_mic_irq, "Mic 1 detect",
3156                                          wm8994);
3157                 if (ret != 0)
3158                         dev_warn(codec->dev,
3159                                  "Failed to request Mic1 detect IRQ: %d\n",
3160                                  ret);
3161
3162                 ret = wm8994_request_irq(codec->control_data,
3163                                          WM8994_IRQ_MIC1_SHRT,
3164                                          wm8994_mic_irq, "Mic 1 short",
3165                                          wm8994);
3166                 if (ret != 0)
3167                         dev_warn(codec->dev,
3168                                  "Failed to request Mic1 short IRQ: %d\n",
3169                                  ret);
3170
3171                 ret = wm8994_request_irq(codec->control_data,
3172                                          WM8994_IRQ_MIC2_DET,
3173                                          wm8994_mic_irq, "Mic 2 detect",
3174                                          wm8994);
3175                 if (ret != 0)
3176                         dev_warn(codec->dev,
3177                                  "Failed to request Mic2 detect IRQ: %d\n",
3178                                  ret);
3179
3180                 ret = wm8994_request_irq(codec->control_data,
3181                                          WM8994_IRQ_MIC2_SHRT,
3182                                          wm8994_mic_irq, "Mic 2 short",
3183                                          wm8994);
3184                 if (ret != 0)
3185                         dev_warn(codec->dev,
3186                                  "Failed to request Mic2 short IRQ: %d\n",
3187                                  ret);
3188                 break;
3189
3190         case WM8958:
3191                 ret = wm8994_request_irq(codec->control_data,
3192                                          WM8994_IRQ_MIC1_DET,
3193                                          wm8958_mic_irq, "Mic detect",
3194                                          wm8994);
3195                 if (ret != 0)
3196                         dev_warn(codec->dev,
3197                                  "Failed to request Mic detect IRQ: %d\n",
3198                                  ret);
3199                 break;
3200         }
3201
3202         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3203          * configured on init - if a system wants to do this dynamically
3204          * at runtime we can deal with that then.
3205          */
3206         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3207         if (ret < 0) {
3208                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3209                 goto err_irq;
3210         }
3211         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3212                 wm8994->lrclk_shared[0] = 1;
3213                 wm8994_dai[0].symmetric_rates = 1;
3214         } else {
3215                 wm8994->lrclk_shared[0] = 0;
3216         }
3217
3218         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3219         if (ret < 0) {
3220                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3221                 goto err_irq;
3222         }
3223         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3224                 wm8994->lrclk_shared[1] = 1;
3225                 wm8994_dai[1].symmetric_rates = 1;
3226         } else {
3227                 wm8994->lrclk_shared[1] = 0;
3228         }
3229
3230         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3231
3232         /* Latch volume updates (right only; we always do left then right). */
3233         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3234                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3235         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3236                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3237         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3238                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3239         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3240                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3241         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3242                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3243         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3244                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3245         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3246                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3247         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3248                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3249
3250         /* Set the low bit of the 3D stereo depth so TLV matches */
3251         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3252                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3253                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3254         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3255                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3256                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3257         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3258                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3259                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3260
3261         /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3262          * behaviour on idle TDM clock cycles. */
3263         snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3264                             WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3265
3266         wm8994_update_class_w(codec);
3267
3268         wm8994_handle_pdata(wm8994);
3269
3270         wm_hubs_add_analogue_controls(codec);
3271         snd_soc_add_controls(codec, wm8994_snd_controls,
3272                              ARRAY_SIZE(wm8994_snd_controls));
3273         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3274                                   ARRAY_SIZE(wm8994_dapm_widgets));
3275
3276         switch (control->type) {
3277         case WM8994:
3278                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3279                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3280                 if (wm8994->revision < 4) {
3281                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3282                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3283                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3284                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3285                 } else {
3286                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3287                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3288                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3289                                                   ARRAY_SIZE(wm8994_dac_widgets));
3290                 }
3291                 break;
3292         case WM8958:
3293                 snd_soc_add_controls(codec, wm8958_snd_controls,
3294                                      ARRAY_SIZE(wm8958_snd_controls));
3295                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3296                                           ARRAY_SIZE(wm8958_dapm_widgets));
3297                 break;
3298         }
3299
3300
3301         wm_hubs_add_analogue_routes(codec, 0, 0);
3302         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3303
3304         switch (control->type) {
3305         case WM8994:
3306                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3307                                         ARRAY_SIZE(wm8994_intercon));
3308
3309                 if (wm8994->revision < 4) {
3310                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3311                                                 ARRAY_SIZE(wm8994_revd_intercon));
3312                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3313                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3314                 } else {
3315                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3316                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3317                 }
3318                 break;
3319         case WM8958:
3320                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3321                                         ARRAY_SIZE(wm8958_intercon));
3322                 break;
3323         }
3324
3325         return 0;
3326
3327 err_irq:
3328         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3329         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3330         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3331         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
3332 err:
3333         kfree(wm8994);
3334         return ret;
3335 }
3336
3337 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3338 {
3339         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3340         struct wm8994 *control = codec->control_data;
3341
3342         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3343
3344         pm_runtime_disable(codec->dev);
3345
3346         switch (control->type) {
3347         case WM8994:
3348                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3349                                 wm8994);
3350                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3351                                 wm8994);
3352                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3353                                 wm8994);
3354                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3355                                 wm8994);
3356                 break;
3357
3358         case WM8958:
3359                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3360                                 wm8994);
3361                 break;
3362         }
3363         kfree(wm8994->retune_mobile_texts);
3364         kfree(wm8994->drc_texts);
3365         kfree(wm8994);
3366
3367         return 0;
3368 }
3369
3370 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3371         .probe =        wm8994_codec_probe,
3372         .remove =       wm8994_codec_remove,
3373         .suspend =      wm8994_suspend,
3374         .resume =       wm8994_resume,
3375         .read =         wm8994_read,
3376         .write =        wm8994_write,
3377         .readable_register = wm8994_readable,
3378         .volatile_register = wm8994_volatile,
3379         .set_bias_level = wm8994_set_bias_level,
3380
3381         .reg_cache_size = WM8994_CACHE_SIZE,
3382         .reg_cache_default = wm8994_reg_defaults,
3383         .reg_word_size = 2,
3384         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3385 };
3386
3387 static int __devinit wm8994_probe(struct platform_device *pdev)
3388 {
3389         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3390                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3391 }
3392
3393 static int __devexit wm8994_remove(struct platform_device *pdev)
3394 {
3395         snd_soc_unregister_codec(&pdev->dev);
3396         return 0;
3397 }
3398
3399 static struct platform_driver wm8994_codec_driver = {
3400         .driver = {
3401                    .name = "wm8994-codec",
3402                    .owner = THIS_MODULE,
3403                    },
3404         .probe = wm8994_probe,
3405         .remove = __devexit_p(wm8994_remove),
3406 };
3407
3408 static __init int wm8994_init(void)
3409 {
3410         return platform_driver_register(&wm8994_codec_driver);
3411 }
3412 module_init(wm8994_init);
3413
3414 static __exit void wm8994_exit(void)
3415 {
3416         platform_driver_unregister(&wm8994_codec_driver);
3417 }
3418 module_exit(wm8994_exit);
3419
3420
3421 MODULE_DESCRIPTION("ASoC WM8994 driver");
3422 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3423 MODULE_LICENSE("GPL");
3424 MODULE_ALIAS("platform:wm8994-codec");