sound/soc/codecs/wm8961.c

   1 /*
   2  * wm8961.c  --  WM8961 ALSA SoC Audio driver
   3  *
   4  * Author: Mark Brown
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Currently unimplemented features:
  11  *  - ALC
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29
  30 #include "wm8961.h"
  31
  32 #define WM8961_MAX_REGISTER                     0xFC
  33
  34 static u16 wm8961_reg_defaults[] = {
  35         0x009F,     /* R0   - Left Input volume */
  36         0x009F,     /* R1   - Right Input volume */
  37         0x0000,     /* R2   - LOUT1 volume */
  38         0x0000,     /* R3   - ROUT1 volume */
  39         0x0020,     /* R4   - Clocking1 */
  40         0x0008,     /* R5   - ADC & DAC Control 1 */
  41         0x0000,     /* R6   - ADC & DAC Control 2 */
  42         0x000A,     /* R7   - Audio Interface 0 */
  43         0x01F4,     /* R8   - Clocking2 */
  44         0x0000,     /* R9   - Audio Interface 1 */
  45         0x00FF,     /* R10  - Left DAC volume */
  46         0x00FF,     /* R11  - Right DAC volume */
  47         0x0000,     /* R12 */
  48         0x0000,     /* R13 */
  49         0x0040,     /* R14  - Audio Interface 2 */
  50         0x0000,     /* R15  - Software Reset */
  51         0x0000,     /* R16 */
  52         0x007B,     /* R17  - ALC1 */
  53         0x0000,     /* R18  - ALC2 */
  54         0x0032,     /* R19  - ALC3 */
  55         0x0000,     /* R20  - Noise Gate */
  56         0x00C0,     /* R21  - Left ADC volume */
  57         0x00C0,     /* R22  - Right ADC volume */
  58         0x0120,     /* R23  - Additional control(1) */
  59         0x0000,     /* R24  - Additional control(2) */
  60         0x0000,     /* R25  - Pwr Mgmt (1) */
  61         0x0000,     /* R26  - Pwr Mgmt (2) */
  62         0x0000,     /* R27  - Additional Control (3) */
  63         0x0000,     /* R28  - Anti-pop */
  64         0x0000,     /* R29 */
  65         0x005F,     /* R30  - Clocking 3 */
  66         0x0000,     /* R31 */
  67         0x0000,     /* R32  - ADCL signal path */
  68         0x0000,     /* R33  - ADCR signal path */
  69         0x0000,     /* R34 */
  70         0x0000,     /* R35 */
  71         0x0000,     /* R36 */
  72         0x0000,     /* R37 */
  73         0x0000,     /* R38 */
  74         0x0000,     /* R39 */
  75         0x0000,     /* R40  - LOUT2 volume */
  76         0x0000,     /* R41  - ROUT2 volume */
  77         0x0000,     /* R42 */
  78         0x0000,     /* R43 */
  79         0x0000,     /* R44 */
  80         0x0000,     /* R45 */
  81         0x0000,     /* R46 */
  82         0x0000,     /* R47  - Pwr Mgmt (3) */
  83         0x0023,     /* R48  - Additional Control (4) */
  84         0x0000,     /* R49  - Class D Control 1 */
  85         0x0000,     /* R50 */
  86         0x0003,     /* R51  - Class D Control 2 */
  87         0x0000,     /* R52 */
  88         0x0000,     /* R53 */
  89         0x0000,     /* R54 */
  90         0x0000,     /* R55 */
  91         0x0106,     /* R56  - Clocking 4 */
  92         0x0000,     /* R57  - DSP Sidetone 0 */
  93         0x0000,     /* R58  - DSP Sidetone 1 */
  94         0x0000,     /* R59 */
  95         0x0000,     /* R60  - DC Servo 0 */
  96         0x0000,     /* R61  - DC Servo 1 */
  97         0x0000,     /* R62 */
  98         0x015E,     /* R63  - DC Servo 3 */
  99         0x0010,     /* R64 */
 100         0x0010,     /* R65  - DC Servo 5 */
 101         0x0000,     /* R66 */
 102         0x0001,     /* R67 */
 103         0x0003,     /* R68  - Analogue PGA Bias */
 104         0x0000,     /* R69  - Analogue HP 0 */
 105         0x0060,     /* R70 */
 106         0x01FB,     /* R71  - Analogue HP 2 */
 107         0x0000,     /* R72  - Charge Pump 1 */
 108         0x0065,     /* R73 */
 109         0x005F,     /* R74 */
 110         0x0059,     /* R75 */
 111         0x006B,     /* R76 */
 112         0x0038,     /* R77 */
 113         0x000C,     /* R78 */
 114         0x000A,     /* R79 */
 115         0x006B,     /* R80 */
 116         0x0000,     /* R81 */
 117         0x0000,     /* R82  - Charge Pump B */
 118         0x0087,     /* R83 */
 119         0x0000,     /* R84 */
 120         0x005C,     /* R85 */
 121         0x0000,     /* R86 */
 122         0x0000,     /* R87  - Write Sequencer 1 */
 123         0x0000,     /* R88  - Write Sequencer 2 */
 124         0x0000,     /* R89  - Write Sequencer 3 */
 125         0x0000,     /* R90  - Write Sequencer 4 */
 126         0x0000,     /* R91  - Write Sequencer 5 */
 127         0x0000,     /* R92  - Write Sequencer 6 */
 128         0x0000,     /* R93  - Write Sequencer 7 */
 129         0x0000,     /* R94 */
 130         0x0000,     /* R95 */
 131         0x0000,     /* R96 */
 132         0x0000,     /* R97 */
 133         0x0000,     /* R98 */
 134         0x0000,     /* R99 */
 135         0x0000,     /* R100 */
 136         0x0000,     /* R101 */
 137         0x0000,     /* R102 */
 138         0x0000,     /* R103 */
 139         0x0000,     /* R104 */
 140         0x0000,     /* R105 */
 141         0x0000,     /* R106 */
 142         0x0000,     /* R107 */
 143         0x0000,     /* R108 */
 144         0x0000,     /* R109 */
 145         0x0000,     /* R110 */
 146         0x0000,     /* R111 */
 147         0x0000,     /* R112 */
 148         0x0000,     /* R113 */
 149         0x0000,     /* R114 */
 150         0x0000,     /* R115 */
 151         0x0000,     /* R116 */
 152         0x0000,     /* R117 */
 153         0x0000,     /* R118 */
 154         0x0000,     /* R119 */
 155         0x0000,     /* R120 */
 156         0x0000,     /* R121 */
 157         0x0000,     /* R122 */
 158         0x0000,     /* R123 */
 159         0x0000,     /* R124 */
 160         0x0000,     /* R125 */
 161         0x0000,     /* R126 */
 162         0x0000,     /* R127 */
 163         0x0000,     /* R128 */
 164         0x0000,     /* R129 */
 165         0x0000,     /* R130 */
 166         0x0000,     /* R131 */
 167         0x0000,     /* R132 */
 168         0x0000,     /* R133 */
 169         0x0000,     /* R134 */
 170         0x0000,     /* R135 */
 171         0x0000,     /* R136 */
 172         0x0000,     /* R137 */
 173         0x0000,     /* R138 */
 174         0x0000,     /* R139 */
 175         0x0000,     /* R140 */
 176         0x0000,     /* R141 */
 177         0x0000,     /* R142 */
 178         0x0000,     /* R143 */
 179         0x0000,     /* R144 */
 180         0x0000,     /* R145 */
 181         0x0000,     /* R146 */
 182         0x0000,     /* R147 */
 183         0x0000,     /* R148 */
 184         0x0000,     /* R149 */
 185         0x0000,     /* R150 */
 186         0x0000,     /* R151 */
 187         0x0000,     /* R152 */
 188         0x0000,     /* R153 */
 189         0x0000,     /* R154 */
 190         0x0000,     /* R155 */
 191         0x0000,     /* R156 */
 192         0x0000,     /* R157 */
 193         0x0000,     /* R158 */
 194         0x0000,     /* R159 */
 195         0x0000,     /* R160 */
 196         0x0000,     /* R161 */
 197         0x0000,     /* R162 */
 198         0x0000,     /* R163 */
 199         0x0000,     /* R164 */
 200         0x0000,     /* R165 */
 201         0x0000,     /* R166 */
 202         0x0000,     /* R167 */
 203         0x0000,     /* R168 */
 204         0x0000,     /* R169 */
 205         0x0000,     /* R170 */
 206         0x0000,     /* R171 */
 207         0x0000,     /* R172 */
 208         0x0000,     /* R173 */
 209         0x0000,     /* R174 */
 210         0x0000,     /* R175 */
 211         0x0000,     /* R176 */
 212         0x0000,     /* R177 */
 213         0x0000,     /* R178 */
 214         0x0000,     /* R179 */
 215         0x0000,     /* R180 */
 216         0x0000,     /* R181 */
 217         0x0000,     /* R182 */
 218         0x0000,     /* R183 */
 219         0x0000,     /* R184 */
 220         0x0000,     /* R185 */
 221         0x0000,     /* R186 */
 222         0x0000,     /* R187 */
 223         0x0000,     /* R188 */
 224         0x0000,     /* R189 */
 225         0x0000,     /* R190 */
 226         0x0000,     /* R191 */
 227         0x0000,     /* R192 */
 228         0x0000,     /* R193 */
 229         0x0000,     /* R194 */
 230         0x0000,     /* R195 */
 231         0x0030,     /* R196 */
 232         0x0006,     /* R197 */
 233         0x0000,     /* R198 */
 234         0x0060,     /* R199 */
 235         0x0000,     /* R200 */
 236         0x003F,     /* R201 */
 237         0x0000,     /* R202 */
 238         0x0000,     /* R203 */
 239         0x0000,     /* R204 */
 240         0x0001,     /* R205 */
 241         0x0000,     /* R206 */
 242         0x0181,     /* R207 */
 243         0x0005,     /* R208 */
 244         0x0008,     /* R209 */
 245         0x0008,     /* R210 */
 246         0x0000,     /* R211 */
 247         0x013B,     /* R212 */
 248         0x0000,     /* R213 */
 249         0x0000,     /* R214 */
 250         0x0000,     /* R215 */
 251         0x0000,     /* R216 */
 252         0x0070,     /* R217 */
 253         0x0000,     /* R218 */
 254         0x0000,     /* R219 */
 255         0x0000,     /* R220 */
 256         0x0000,     /* R221 */
 257         0x0000,     /* R222 */
 258         0x0003,     /* R223 */
 259         0x0000,     /* R224 */
 260         0x0000,     /* R225 */
 261         0x0001,     /* R226 */
 262         0x0008,     /* R227 */
 263         0x0000,     /* R228 */
 264         0x0000,     /* R229 */
 265         0x0000,     /* R230 */
 266         0x0000,     /* R231 */
 267         0x0004,     /* R232 */
 268         0x0000,     /* R233 */
 269         0x0000,     /* R234 */
 270         0x0000,     /* R235 */
 271         0x0000,     /* R236 */
 272         0x0000,     /* R237 */
 273         0x0080,     /* R238 */
 274         0x0000,     /* R239 */
 275         0x0000,     /* R240 */
 276         0x0000,     /* R241 */
 277         0x0000,     /* R242 */
 278         0x0000,     /* R243 */
 279         0x0000,     /* R244 */
 280         0x0052,     /* R245 */
 281         0x0110,     /* R246 */
 282         0x0040,     /* R247 */
 283         0x0000,     /* R248 */
 284         0x0030,     /* R249 */
 285         0x0000,     /* R250 */
 286         0x0000,     /* R251 */
 287         0x0001,     /* R252 - General test 1 */
 288 };
 289
 290 struct wm8961_priv {
 291         enum snd_soc_control_type control_type;
 292         int sysclk;
 293         u16 reg_cache[WM8961_MAX_REGISTER];
 294 };
 295
 296 static int wm8961_volatile_register(unsigned int reg)
 297 {
 298         switch (reg) {
 299         case WM8961_SOFTWARE_RESET:
 300         case WM8961_WRITE_SEQUENCER_7:
 301         case WM8961_DC_SERVO_1:
 302                 return 1;
 303
 304         default:
 305                 return 0;
 306         }
 307 }
 308
 309 static int wm8961_reset(struct snd_soc_codec *codec)
 310 {
 311         return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
 312 }
 313
 314 /*
 315  * The headphone output supports special anti-pop sequences giving
 316  * silent power up and power down.
 317  */
 318 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
 319                            struct snd_kcontrol *kcontrol, int event)
 320 {
 321         struct snd_soc_codec *codec = w->codec;
 322         u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
 323         u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
 324         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 325         u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 326         int timeout = 500;
 327
 328         if (event & SND_SOC_DAPM_POST_PMU) {
 329                 /* Make sure the output is shorted */
 330                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 331                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 332
 333                 /* Enable the charge pump */
 334                 cp_reg |= WM8961_CP_ENA;
 335                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
 336                 mdelay(5);
 337
 338                 /* Enable the PGA */
 339                 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
 340                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 341
 342                 /* Enable the amplifier */
 343                 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
 344                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 345
 346                 /* Second stage enable */
 347                 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
 348                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 349
 350                 /* Enable the DC servo & trigger startup */
 351                 dcs_reg |=
 352                         WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
 353                         WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
 354                 dev_dbg(codec->dev, "Enabling DC servo\n");
 355
 356                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 357                 do {
 358                         msleep(1);
 359                         dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 360                 } while (--timeout &&
 361                          dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 362                                 WM8961_DCS_TRIG_STARTUP_HPL));
 363                 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 364                                WM8961_DCS_TRIG_STARTUP_HPL))
 365                         dev_err(codec->dev, "DC servo timed out\n");
 366                 else
 367                         dev_dbg(codec->dev, "DC servo startup complete\n");
 368
 369                 /* Enable the output stage */
 370                 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
 371                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 372
 373                 /* Remove the short on the output stage */
 374                 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
 375                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 376         }
 377
 378         if (event & SND_SOC_DAPM_PRE_PMD) {
 379                 /* Short the output */
 380                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 381                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 382
 383                 /* Disable the output stage */
 384                 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
 385                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 386
 387                 /* Disable DC offset cancellation */
 388                 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
 389                              WM8961_DCS_ENA_CHAN_HPL);
 390                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 391
 392                 /* Finish up */
 393                 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
 394                             WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
 395                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 396
 397                 /* Disable the PGA */
 398                 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
 399                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 400
 401                 /* Disable the charge pump */
 402                 dev_dbg(codec->dev, "Disabling charge pump\n");
 403                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
 404                              cp_reg & ~WM8961_CP_ENA);
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
 411                             struct snd_kcontrol *kcontrol, int event)
 412 {
 413         struct snd_soc_codec *codec = w->codec;
 414         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 415         u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
 416
 417         if (event & SND_SOC_DAPM_POST_PMU) {
 418                 /* Enable the PGA */
 419                 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
 420                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 421
 422                 /* Enable the amplifier */
 423                 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
 424                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 425         }
 426
 427         if (event & SND_SOC_DAPM_PRE_PMD) {
 428                 /* Enable the amplifier */
 429                 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
 430                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 431
 432                 /* Enable the PGA */
 433                 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
 434                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 435         }
 436
 437         return 0;
 438 }
 439
 440 static const char *adc_hpf_text[] = {
 441         "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
 442 };
 443
 444 static const struct soc_enum adc_hpf =
 445         SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
 446
 447 static const char *dac_deemph_text[] = {
 448         "None", "32kHz", "44.1kHz", "48kHz",
 449 };
 450
 451 static const struct soc_enum dac_deemph =
 452         SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
 453
 454 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
 455 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
 456 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
 457 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 458 static unsigned int boost_tlv[] = {
 459         TLV_DB_RANGE_HEAD(4),
 460         0, 0, TLV_DB_SCALE_ITEM(0,  0, 0),
 461         1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
 462         2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
 463         3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
 464 };
 465 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
 466
 467 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
 468 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 469                  0, 127, 0, out_tlv),
 470 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
 471                6, 3, 7, 0, hp_sec_tlv),
 472 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 473              7, 1, 0),
 474
 475 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 476                  0, 127, 0, out_tlv),
 477 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 478            7, 1, 0),
 479 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
 480
 481 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
 482 SOC_ENUM("DAC Deemphasis", dac_deemph),
 483 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
 484
 485 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
 486                  WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
 487
 488 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
 489 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
 490
 491 SOC_DOUBLE_R_TLV("Capture Volume",
 492                  WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
 493                  1, 119, 0, adc_tlv),
 494 SOC_DOUBLE_R_TLV("Capture Boost Volume",
 495                  WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
 496                  4, 3, 0, boost_tlv),
 497 SOC_DOUBLE_R_TLV("Capture PGA Volume",
 498                  WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 499                  0, 62, 0, pga_tlv),
 500 SOC_DOUBLE_R("Capture PGA ZC Switch",
 501              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 502              6, 1, 1),
 503 SOC_DOUBLE_R("Capture PGA Switch",
 504              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 505              7, 1, 1),
 506 };
 507
 508 static const char *sidetone_text[] = {
 509         "None", "Left", "Right"
 510 };
 511
 512 static const struct soc_enum dacl_sidetone =
 513         SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
 514
 515 static const struct soc_enum dacr_sidetone =
 516         SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
 517
 518 static const struct snd_kcontrol_new dacl_mux =
 519         SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
 520
 521 static const struct snd_kcontrol_new dacr_mux =
 522         SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
 523
 524 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
 525 SND_SOC_DAPM_INPUT("LINPUT"),
 526 SND_SOC_DAPM_INPUT("RINPUT"),
 527
 528 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
 529
 530 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
 531 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
 532
 533 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
 534 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
 535
 536 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0),
 537
 538 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
 539 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
 540
 541 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
 542 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
 543
 544 /* Handle as a mono path for DCS */
 545 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
 546                    4, 0, NULL, 0, wm8961_hp_event,
 547                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 548 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
 549                    4, 0, NULL, 0, wm8961_spk_event,
 550                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 551
 552 SND_SOC_DAPM_OUTPUT("HP_L"),
 553 SND_SOC_DAPM_OUTPUT("HP_R"),
 554 SND_SOC_DAPM_OUTPUT("SPK_LN"),
 555 SND_SOC_DAPM_OUTPUT("SPK_LP"),
 556 SND_SOC_DAPM_OUTPUT("SPK_RN"),
 557 SND_SOC_DAPM_OUTPUT("SPK_RP"),
 558 };
 559
 560
 561 static const struct snd_soc_dapm_route audio_paths[] = {
 562         { "DACL", NULL, "CLK_DSP" },
 563         { "DACL", NULL, "DACL Sidetone" },
 564         { "DACR", NULL, "CLK_DSP" },
 565         { "DACR", NULL, "DACR Sidetone" },
 566
 567         { "DACL Sidetone", "Left", "ADCL" },
 568         { "DACL Sidetone", "Right", "ADCR" },
 569
 570         { "DACR Sidetone", "Left", "ADCL" },
 571         { "DACR Sidetone", "Right", "ADCR" },
 572
 573         { "HP_L", NULL, "Headphone Output" },
 574         { "HP_R", NULL, "Headphone Output" },
 575         { "Headphone Output", NULL, "DACL" },
 576         { "Headphone Output", NULL, "DACR" },
 577
 578         { "SPK_LN", NULL, "Speaker Output" },
 579         { "SPK_LP", NULL, "Speaker Output" },
 580         { "SPK_RN", NULL, "Speaker Output" },
 581         { "SPK_RP", NULL, "Speaker Output" },
 582
 583         { "Speaker Output", NULL, "DACL" },
 584         { "Speaker Output", NULL, "DACR" },
 585
 586         { "ADCL", NULL, "Left Input" },
 587         { "ADCL", NULL, "CLK_DSP" },
 588         { "ADCR", NULL, "Right Input" },
 589         { "ADCR", NULL, "CLK_DSP" },
 590
 591         { "Left Input", NULL, "LINPUT" },
 592         { "Right Input", NULL, "RINPUT" },
 593
 594 };
 595
 596 /* Values for CLK_SYS_RATE */
 597 static struct {
 598         int ratio;
 599         u16 val;
 600 } wm8961_clk_sys_ratio[] = {
 601         {  64,  0 },
 602         {  128, 1 },
 603         {  192, 2 },
 604         {  256, 3 },
 605         {  384, 4 },
 606         {  512, 5 },
 607         {  768, 6 },
 608         { 1024, 7 },
 609         { 1408, 8 },
 610         { 1536, 9 },
 611 };
 612
 613 /* Values for SAMPLE_RATE */
 614 static struct {
 615         int rate;
 616         u16 val;
 617 } wm8961_srate[] = {
 618         { 48000, 0 },
 619         { 44100, 0 },
 620         { 32000, 1 },
 621         { 22050, 2 },
 622         { 24000, 2 },
 623         { 16000, 3 },
 624         { 11250, 4 },
 625         { 12000, 4 },
 626         {  8000, 5 },
 627 };
 628
 629 static int wm8961_hw_params(struct snd_pcm_substream *substream,
 630                             struct snd_pcm_hw_params *params,
 631                             struct snd_soc_dai *dai)
 632 {
 633         struct snd_soc_codec *codec = dai->codec;
 634         struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
 635         int i, best, target, fs;
 636         u16 reg;
 637
 638         fs = params_rate(params);
 639
 640         if (!wm8961->sysclk) {
 641                 dev_err(codec->dev, "MCLK has not been specified\n");
 642                 return -EINVAL;
 643         }
 644
 645         /* Find the closest sample rate for the filters */
 646         best = 0;
 647         for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
 648                 if (abs(wm8961_srate[i].rate - fs) <
 649                     abs(wm8961_srate[best].rate - fs))
 650                         best = i;
 651         }
 652         reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
 653         reg &= ~WM8961_SAMPLE_RATE_MASK;
 654         reg |= wm8961_srate[best].val;
 655         snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
 656         dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
 657                 wm8961_srate[best].rate, fs);
 658
 659         /* Select a CLK_SYS/fs ratio equal to or higher than required */
 660         target = wm8961->sysclk / fs;
 661
 662         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
 663                 dev_err(codec->dev,
 664                         "SYSCLK must be at least 64*fs for DAC\n");
 665                 return -EINVAL;
 666         }
 667         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
 668                 dev_err(codec->dev,
 669                         "SYSCLK must be at least 256*fs for ADC\n");
 670                 return -EINVAL;
 671         }
 672
 673         for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
 674                 if (wm8961_clk_sys_ratio[i].ratio >= target)
 675                         break;
 676         }
 677         if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
 678                 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
 679                 return -EINVAL;
 680         }
 681         dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
 682                 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
 683                 wm8961->sysclk / fs);
 684
 685         reg = snd_soc_read(codec, WM8961_CLOCKING_4);
 686         reg &= ~WM8961_CLK_SYS_RATE_MASK;
 687         reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
 688         snd_soc_write(codec, WM8961_CLOCKING_4, reg);
 689
 690         reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 691         reg &= ~WM8961_WL_MASK;
 692         switch (params_format(params)) {
 693         case SNDRV_PCM_FORMAT_S16_LE:
 694                 break;
 695         case SNDRV_PCM_FORMAT_S20_3LE:
 696                 reg |= 1 << WM8961_WL_SHIFT;
 697                 break;
 698         case SNDRV_PCM_FORMAT_S24_LE:
 699                 reg |= 2 << WM8961_WL_SHIFT;
 700                 break;
 701         case SNDRV_PCM_FORMAT_S32_LE:
 702                 reg |= 3 << WM8961_WL_SHIFT;
 703                 break;
 704         default:
 705                 return -EINVAL;
 706         }
 707         snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
 708
 709         /* Sloping stop-band filter is recommended for <= 24kHz */
 710         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
 711         if (fs <= 24000)
 712                 reg |= WM8961_DACSLOPE;
 713         else
 714                 reg &= ~WM8961_DACSLOPE;
 715         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
 716
 717         return 0;
 718 }
 719
 720 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 721                              unsigned int freq,
 722                              int dir)
 723 {
 724         struct snd_soc_codec *codec = dai->codec;
 725         struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
 726         u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
 727
 728         if (freq > 33000000) {
 729                 dev_err(codec->dev, "MCLK must be <33MHz\n");
 730                 return -EINVAL;
 731         }
 732
 733         if (freq > 16500000) {
 734                 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
 735                 reg |= WM8961_MCLKDIV;
 736                 freq /= 2;
 737         } else {
 738                 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
 739                 reg &= ~WM8961_MCLKDIV;
 740         }
 741
 742         snd_soc_write(codec, WM8961_CLOCKING1, reg);
 743
 744         wm8961->sysclk = freq;
 745
 746         return 0;
 747 }
 748
 749 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 750 {
 751         struct snd_soc_codec *codec = dai->codec;
 752         u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 753
 754         aif &= ~(WM8961_BCLKINV | WM8961_LRP |
 755                  WM8961_MS | WM8961_FORMAT_MASK);
 756
 757         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 758         case SND_SOC_DAIFMT_CBM_CFM:
 759                 aif |= WM8961_MS;
 760                 break;
 761         case SND_SOC_DAIFMT_CBS_CFS:
 762                 break;
 763         default:
 764                 return -EINVAL;
 765         }
 766
 767         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 768         case SND_SOC_DAIFMT_RIGHT_J:
 769                 break;
 770
 771         case SND_SOC_DAIFMT_LEFT_J:
 772                 aif |= 1;
 773                 break;
 774
 775         case SND_SOC_DAIFMT_I2S:
 776                 aif |= 2;
 777                 break;
 778
 779         case SND_SOC_DAIFMT_DSP_B:
 780                 aif |= WM8961_LRP;
 781         case SND_SOC_DAIFMT_DSP_A:
 782                 aif |= 3;
 783                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 784                 case SND_SOC_DAIFMT_NB_NF:
 785                 case SND_SOC_DAIFMT_IB_NF:
 786                         break;
 787                 default:
 788                         return -EINVAL;
 789                 }
 790                 break;
 791
 792         default:
 793                 return -EINVAL;
 794         }
 795
 796         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 797         case SND_SOC_DAIFMT_NB_NF:
 798                 break;
 799         case SND_SOC_DAIFMT_NB_IF:
 800                 aif |= WM8961_LRP;
 801                 break;
 802         case SND_SOC_DAIFMT_IB_NF:
 803                 aif |= WM8961_BCLKINV;
 804                 break;
 805         case SND_SOC_DAIFMT_IB_IF:
 806                 aif |= WM8961_BCLKINV | WM8961_LRP;
 807                 break;
 808         default:
 809                 return -EINVAL;
 810         }
 811
 812         return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
 813 }
 814
 815 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
 816 {
 817         struct snd_soc_codec *codec = dai->codec;
 818         u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
 819
 820         if (tristate)
 821                 reg |= WM8961_TRIS;
 822         else
 823                 reg &= ~WM8961_TRIS;
 824
 825         return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
 826 }
 827
 828 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
 829 {
 830         struct snd_soc_codec *codec = dai->codec;
 831         u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
 832
 833         if (mute)
 834                 reg |= WM8961_DACMU;
 835         else
 836                 reg &= ~WM8961_DACMU;
 837
 838         msleep(17);
 839
 840         return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
 841 }
 842
 843 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
 844 {
 845         struct snd_soc_codec *codec = dai->codec;
 846         u16 reg;
 847
 848         switch (div_id) {
 849         case WM8961_BCLK:
 850                 reg = snd_soc_read(codec, WM8961_CLOCKING2);
 851                 reg &= ~WM8961_BCLKDIV_MASK;
 852                 reg |= div;
 853                 snd_soc_write(codec, WM8961_CLOCKING2, reg);
 854                 break;
 855
 856         case WM8961_LRCLK:
 857                 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
 858                 reg &= ~WM8961_LRCLK_RATE_MASK;
 859                 reg |= div;
 860                 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
 861                 break;
 862
 863         default:
 864                 return -EINVAL;
 865         }
 866
 867         return 0;
 868 }
 869
 870 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
 871                                  enum snd_soc_bias_level level)
 872 {
 873         u16 reg;
 874
 875         /* This is all slightly unusual since we have no bypass paths
 876          * and the output amplifier structure means we can just slam
 877          * the biases straight up rather than having to ramp them
 878          * slowly.
 879          */
 880         switch (level) {
 881         case SND_SOC_BIAS_ON:
 882                 break;
 883
 884         case SND_SOC_BIAS_PREPARE:
 885                 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
 886                         /* Enable bias generation */
 887                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 888                         reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
 889                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 890
 891                         /* VMID=2*50k, VREF */
 892                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 893                         reg &= ~WM8961_VMIDSEL_MASK;
 894                         reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
 895                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 896                 }
 897                 break;
 898
 899         case SND_SOC_BIAS_STANDBY:
 900                 if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
 901                         /* VREF off */
 902                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 903                         reg &= ~WM8961_VREF;
 904                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 905
 906                         /* Bias generation off */
 907                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 908                         reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
 909                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 910
 911                         /* VMID off */
 912                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 913                         reg &= ~WM8961_VMIDSEL_MASK;
 914                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 915                 }
 916                 break;
 917
 918         case SND_SOC_BIAS_OFF:
 919                 break;
 920         }
 921
 922         codec->bias_level = level;
 923
 924         return 0;
 925 }
 926
 927
 928 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
 929
 930 #define WM8961_FORMATS \
 931         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 932         SNDRV_PCM_FMTBIT_S24_LE)
 933
 934 static struct snd_soc_dai_ops wm8961_dai_ops = {
 935         .hw_params = wm8961_hw_params,
 936         .set_sysclk = wm8961_set_sysclk,
 937         .set_fmt = wm8961_set_fmt,
 938         .digital_mute = wm8961_digital_mute,
 939         .set_tristate = wm8961_set_tristate,
 940         .set_clkdiv = wm8961_set_clkdiv,
 941 };
 942
 943 static struct snd_soc_dai_driver wm8961_dai = {
 944         .name = "wm8961-hifi",
 945         .playback = {
 946                 .stream_name = "HiFi Playback",
 947                 .channels_min = 1,
 948                 .channels_max = 2,
 949                 .rates = WM8961_RATES,
 950                 .formats = WM8961_FORMATS,},
 951         .capture = {
 952                 .stream_name = "HiFi Capture",
 953                 .channels_min = 1,
 954                 .channels_max = 2,
 955                 .rates = WM8961_RATES,
 956                 .formats = WM8961_FORMATS,},
 957         .ops = &wm8961_dai_ops,
 958 };
 959
 960 static int wm8961_probe(struct snd_soc_codec *codec)
 961 {
 962         int ret = 0;
 963         u16 reg;
 964
 965         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
 966         if (ret != 0) {
 967                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 968                 return ret;
 969         }
 970
 971         reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
 972         if (reg != 0x1801) {
 973                 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
 974                 return -EINVAL;
 975         }
 976
 977         /* This isn't volatile - readback doesn't correspond to write */
 978         reg = codec->hw_read(codec, WM8961_RIGHT_INPUT_VOLUME);
 979         dev_info(codec->dev, "WM8961 family %d revision %c\n",
 980                  (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
 981                  ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
 982                  + 'A');
 983
 984         ret = wm8961_reset(codec);
 985         if (ret < 0) {
 986                 dev_err(codec->dev, "Failed to issue reset\n");
 987                 return ret;
 988         }
 989
 990         /* Enable class W */
 991         reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
 992         reg |= WM8961_CP_DYN_PWR_MASK;
 993         snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
 994
 995         /* Latch volume update bits (right channel only, we always
 996          * write both out) and default ZC on. */
 997         reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
 998         snd_soc_write(codec, WM8961_ROUT1_VOLUME,
 999                      reg | WM8961_LO1ZC | WM8961_OUT1VU);
1000         snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1001         reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1002         snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1003                      reg | WM8961_SPKRZC | WM8961_SPKVU);
1004         snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1005
1006         reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1007         snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1008         reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1009         snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1010
1011         /* Use soft mute by default */
1012         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1013         reg |= WM8961_DACSMM;
1014         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1015
1016         /* Use automatic clocking mode by default; for now this is all
1017          * we support.
1018          */
1019         reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1020         reg &= ~WM8961_MANUAL_MODE;
1021         snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1022
1023         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1024
1025         snd_soc_add_controls(codec, wm8961_snd_controls,
1026                                 ARRAY_SIZE(wm8961_snd_controls));
1027         snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets,
1028                                   ARRAY_SIZE(wm8961_dapm_widgets));
1029         snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1030
1031         return 0;
1032 }
1033
1034 static int wm8961_remove(struct snd_soc_codec *codec)
1035 {
1036         wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1037         return 0;
1038 }
1039
1040 #ifdef CONFIG_PM
1041 static int wm8961_suspend(struct snd_soc_codec *codec, pm_message_t state)
1042 {
1043         wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1044
1045         return 0;
1046 }
1047
1048 static int wm8961_resume(struct snd_soc_codec *codec)
1049 {
1050         u16 *reg_cache = codec->reg_cache;
1051         int i;
1052
1053         for (i = 0; i < codec->driver->reg_cache_size; i++) {
1054                 if (reg_cache[i] == wm8961_reg_defaults[i])
1055                         continue;
1056
1057                 if (i == WM8961_SOFTWARE_RESET)
1058                         continue;
1059
1060                 snd_soc_write(codec, i, reg_cache[i]);
1061         }
1062
1063         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1064
1065         return 0;
1066 }
1067 #else
1068 #define wm8961_suspend NULL
1069 #define wm8961_resume NULL
1070 #endif
1071
1072 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
1073         .probe =        wm8961_probe,
1074         .remove =       wm8961_remove,
1075         .suspend =      wm8961_suspend,
1076         .resume =       wm8961_resume,
1077         .set_bias_level = wm8961_set_bias_level,
1078         .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults),
1079         .reg_word_size = sizeof(u16),
1080         .reg_cache_default = wm8961_reg_defaults,
1081         .volatile_register = wm8961_volatile_register,
1082 };
1083
1084 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1085 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1086                                       const struct i2c_device_id *id)
1087 {
1088         struct wm8961_priv *wm8961;
1089         int ret;
1090
1091         wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
1092         if (wm8961 == NULL)
1093                 return -ENOMEM;
1094
1095         i2c_set_clientdata(i2c, wm8961);
1096
1097         ret = snd_soc_register_codec(&i2c->dev,
1098                         &soc_codec_dev_wm8961, &wm8961_dai, 1);
1099         if (ret < 0)
1100                 kfree(wm8961);
1101         return ret;
1102 }
1103
1104 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1105 {
1106         snd_soc_unregister_codec(&client->dev);
1107         kfree(i2c_get_clientdata(client));
1108         return 0;
1109 }
1110
1111 static const struct i2c_device_id wm8961_i2c_id[] = {
1112         { "wm8961", 0 },
1113         { }
1114 };
1115 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1116
1117 static struct i2c_driver wm8961_i2c_driver = {
1118         .driver = {
1119                 .name = "wm8961-codec",
1120                 .owner = THIS_MODULE,
1121         },
1122         .probe =    wm8961_i2c_probe,
1123         .remove =   __devexit_p(wm8961_i2c_remove),
1124         .id_table = wm8961_i2c_id,
1125 };
1126 #endif
1127
1128 static int __init wm8961_modinit(void)
1129 {
1130         int ret = 0;
1131 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1132         ret = i2c_add_driver(&wm8961_i2c_driver);
1133         if (ret != 0) {
1134                 printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
1135                        ret);
1136         }
1137 #endif
1138         return ret;
1139 }
1140 module_init(wm8961_modinit);
1141
1142 static void __exit wm8961_exit(void)
1143 {
1144 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1145         i2c_del_driver(&wm8961_i2c_driver);
1146 #endif
1147 }
1148 module_exit(wm8961_exit);
1149
1150 MODULE_DESCRIPTION("ASoC WM8961 driver");
1151 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1152 MODULE_LICENSE("GPL");