sound/soc/codecs/wm5100.c

   1 /*
   2  * wm5100.c  --  WM5100 ALSA SoC Audio driver
   3  *
   4  * Copyright 2011 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/gcd.h>
  19 #include <linux/gpio.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/regulator/fixed.h>
  24 #include <linux/slab.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/jack.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32 #include <sound/wm5100.h>
  33
  34 #include "wm5100.h"
  35
  36 #define WM5100_NUM_CORE_SUPPLIES 2
  37 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
  38         "DBVDD1",
  39         "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
  40 };
  41
  42 #define WM5100_AIFS     3
  43 #define WM5100_SYNC_SRS 3
  44
  45 struct wm5100_fll {
  46         int fref;
  47         int fout;
  48         int src;
  49         struct completion lock;
  50 };
  51
  52 /* codec private data */
  53 struct wm5100_priv {
  54         struct snd_soc_codec *codec;
  55
  56         struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
  57         struct regulator *cpvdd;
  58         struct regulator *dbvdd2;
  59         struct regulator *dbvdd3;
  60
  61         int rev;
  62
  63         int sysclk;
  64         int asyncclk;
  65
  66         bool aif_async[WM5100_AIFS];
  67         bool aif_symmetric[WM5100_AIFS];
  68         int sr_ref[WM5100_SYNC_SRS];
  69
  70         bool out_ena[2];
  71
  72         struct snd_soc_jack *jack;
  73         bool jack_detecting;
  74         bool jack_mic;
  75         int jack_mode;
  76
  77         struct wm5100_fll fll[2];
  78
  79         struct wm5100_pdata pdata;
  80
  81 #ifdef CONFIG_GPIOLIB
  82         struct gpio_chip gpio_chip;
  83 #endif
  84 };
  85
  86 static int wm5100_sr_code[] = {
  87         0,
  88         12000,
  89         24000,
  90         48000,
  91         96000,
  92         192000,
  93         384000,
  94         768000,
  95         0,
  96         11025,
  97         22050,
  98         44100,
  99         88200,
 100         176400,
 101         352800,
 102         705600,
 103         4000,
 104         8000,
 105         16000,
 106         32000,
 107         64000,
 108         128000,
 109         256000,
 110         512000,
 111 };
 112
 113 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
 114         WM5100_CLOCKING_4,
 115         WM5100_CLOCKING_5,
 116         WM5100_CLOCKING_6,
 117 };
 118
 119 static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
 120 {
 121         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
 122         int sr_code, sr_free, i;
 123
 124         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
 125                 if (wm5100_sr_code[i] == rate)
 126                         break;
 127         if (i == ARRAY_SIZE(wm5100_sr_code)) {
 128                 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
 129                 return -EINVAL;
 130         }
 131         sr_code = i;
 132
 133         if ((wm5100->sysclk % rate) == 0) {
 134                 /* Is this rate already in use? */
 135                 sr_free = -1;
 136                 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
 137                         if (!wm5100->sr_ref[i] && sr_free == -1) {
 138                                 sr_free = i;
 139                                 continue;
 140                         }
 141                         if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
 142                              WM5100_SAMPLE_RATE_1_MASK) == sr_code)
 143                                 break;
 144                 }
 145
 146                 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
 147                         wm5100->sr_ref[i]++;
 148                         dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
 149                                 rate, i, wm5100->sr_ref[i]);
 150                         return i;
 151                 }
 152
 153                 if (sr_free == -1) {
 154                         dev_err(codec->dev, "All SR slots already in use\n");
 155                         return -EBUSY;
 156                 }
 157
 158                 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
 159                         sr_free, rate);
 160                 wm5100->sr_ref[sr_free]++;
 161                 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
 162                                     WM5100_SAMPLE_RATE_1_MASK,
 163                                     sr_code);
 164
 165                 return sr_free;
 166
 167         } else {
 168                 dev_err(codec->dev,
 169                         "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
 170                         rate, wm5100->sysclk, wm5100->asyncclk);
 171                 return -EINVAL;
 172         }
 173 }
 174
 175 static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
 176 {
 177         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
 178         int i, sr_code;
 179
 180         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
 181                 if (wm5100_sr_code[i] == rate)
 182                         break;
 183         if (i == ARRAY_SIZE(wm5100_sr_code)) {
 184                 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
 185                 return;
 186         }
 187         sr_code = wm5100_sr_code[i];
 188
 189         for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
 190                 if (!wm5100->sr_ref[i])
 191                         continue;
 192
 193                 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
 194                      WM5100_SAMPLE_RATE_1_MASK) == sr_code)
 195                         break;
 196         }
 197         if (i < ARRAY_SIZE(wm5100_sr_regs)) {
 198                 wm5100->sr_ref[i]--;
 199                 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
 200                         rate, wm5100->sr_ref[i]);
 201         } else {
 202                 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
 203                          rate);
 204         }
 205 }
 206
 207 static int wm5100_reset(struct snd_soc_codec *codec)
 208 {
 209         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
 210
 211         if (wm5100->pdata.reset) {
 212                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
 213                 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
 214
 215                 return 0;
 216         } else {
 217                 return snd_soc_write(codec, WM5100_SOFTWARE_RESET, 0);
 218         }
 219 }
 220
 221 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
 222 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 223 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
 224 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
 225 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
 226
 227 static const char *wm5100_mixer_texts[] = {
 228         "None",
 229         "Tone Generator 1",
 230         "Tone Generator 2",
 231         "AEC loopback",
 232         "IN1L",
 233         "IN1R",
 234         "IN2L",
 235         "IN2R",
 236         "IN3L",
 237         "IN3R",
 238         "IN4L",
 239         "IN4R",
 240         "AIF1RX1",
 241         "AIF1RX2",
 242         "AIF1RX3",
 243         "AIF1RX4",
 244         "AIF1RX5",
 245         "AIF1RX6",
 246         "AIF1RX7",
 247         "AIF1RX8",
 248         "AIF2RX1",
 249         "AIF2RX2",
 250         "AIF3RX1",
 251         "AIF3RX2",
 252         "EQ1",
 253         "EQ2",
 254         "EQ3",
 255         "EQ4",
 256         "DRC1L",
 257         "DRC1R",
 258         "LHPF1",
 259         "LHPF2",
 260         "LHPF3",
 261         "LHPF4",
 262         "DSP1.1",
 263         "DSP1.2",
 264         "DSP1.3",
 265         "DSP1.4",
 266         "DSP1.5",
 267         "DSP1.6",
 268         "DSP2.1",
 269         "DSP2.2",
 270         "DSP2.3",
 271         "DSP2.4",
 272         "DSP2.5",
 273         "DSP2.6",
 274         "DSP3.1",
 275         "DSP3.2",
 276         "DSP3.3",
 277         "DSP3.4",
 278         "DSP3.5",
 279         "DSP3.6",
 280         "ASRC1L",
 281         "ASRC1R",
 282         "ASRC2L",
 283         "ASRC2R",
 284         "ISRC1INT1",
 285         "ISRC1INT2",
 286         "ISRC1INT3",
 287         "ISRC1INT4",
 288         "ISRC2INT1",
 289         "ISRC2INT2",
 290         "ISRC2INT3",
 291         "ISRC2INT4",
 292         "ISRC1DEC1",
 293         "ISRC1DEC2",
 294         "ISRC1DEC3",
 295         "ISRC1DEC4",
 296         "ISRC2DEC1",
 297         "ISRC2DEC2",
 298         "ISRC2DEC3",
 299         "ISRC2DEC4",
 300 };
 301
 302 static int wm5100_mixer_values[] = {
 303         0x00,
 304         0x04,   /* Tone */
 305         0x05,
 306         0x08,   /* AEC */
 307         0x10,   /* Input */
 308         0x11,
 309         0x12,
 310         0x13,
 311         0x14,
 312         0x15,
 313         0x16,
 314         0x17,
 315         0x20,   /* AIF */
 316         0x21,
 317         0x22,
 318         0x23,
 319         0x24,
 320         0x25,
 321         0x26,
 322         0x27,
 323         0x28,
 324         0x29,
 325         0x30,   /* AIF3 - check */
 326         0x31,
 327         0x50,   /* EQ */
 328         0x51,
 329         0x52,
 330         0x53,
 331         0x54,
 332         0x58,   /* DRC */
 333         0x59,
 334         0x60,   /* LHPF1 */
 335         0x61,   /* LHPF2 */
 336         0x62,   /* LHPF3 */
 337         0x63,   /* LHPF4 */
 338         0x68,   /* DSP1 */
 339         0x69,
 340         0x6a,
 341         0x6b,
 342         0x6c,
 343         0x6d,
 344         0x70,   /* DSP2 */
 345         0x71,
 346         0x72,
 347         0x73,
 348         0x74,
 349         0x75,
 350         0x78,   /* DSP3 */
 351         0x79,
 352         0x7a,
 353         0x7b,
 354         0x7c,
 355         0x7d,
 356         0x90,   /* ASRC1 */
 357         0x91,
 358         0x92,   /* ASRC2 */
 359         0x93,
 360         0xa0,   /* ISRC1DEC1 */
 361         0xa1,
 362         0xa2,
 363         0xa3,
 364         0xa4,   /* ISRC1INT1 */
 365         0xa5,
 366         0xa6,
 367         0xa7,
 368         0xa8,   /* ISRC2DEC1 */
 369         0xa9,
 370         0xaa,
 371         0xab,
 372         0xac,   /* ISRC2INT1 */
 373         0xad,
 374         0xae,
 375         0xaf,
 376 };
 377
 378 #define WM5100_MIXER_CONTROLS(name, base) \
 379         SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
 380                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
 381         SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
 382                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
 383         SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
 384                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
 385         SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
 386                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
 387
 388 #define WM5100_MUX_ENUM_DECL(name, reg) \
 389         SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff,                  \
 390                                    wm5100_mixer_texts, wm5100_mixer_values)
 391
 392 #define WM5100_MUX_CTL_DECL(name) \
 393         const struct snd_kcontrol_new name##_mux =      \
 394                 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
 395
 396 #define WM5100_MIXER_ENUMS(name, base_reg) \
 397         static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg);      \
 398         static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2);  \
 399         static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4);  \
 400         static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6);  \
 401         static WM5100_MUX_CTL_DECL(name##_in1); \
 402         static WM5100_MUX_CTL_DECL(name##_in2); \
 403         static WM5100_MUX_CTL_DECL(name##_in3); \
 404         static WM5100_MUX_CTL_DECL(name##_in4)
 405
 406 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
 407 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
 408 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
 409 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
 410 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
 411 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
 412
 413 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
 414 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
 415 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
 416 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
 417 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
 418 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
 419
 420 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
 421 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
 422
 423 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
 424 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
 425 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
 426 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
 427 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
 428 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
 429 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
 430 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
 431
 432 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
 433 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
 434
 435 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
 436 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
 437
 438 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
 439 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
 440 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
 441 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
 442
 443 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
 444 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
 445
 446 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
 447 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
 448 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
 449 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
 450
 451 #define WM5100_MUX(name, ctrl) \
 452         SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
 453
 454 #define WM5100_MIXER_WIDGETS(name, name_str)    \
 455         WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
 456         WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
 457         WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
 458         WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
 459         SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
 460
 461 #define WM5100_MIXER_INPUT_ROUTES(name) \
 462         { name, "Tone Generator 1", "Tone Generator 1" }, \
 463         { name, "Tone Generator 2", "Tone Generator 2" }, \
 464         { name, "IN1L", "IN1L PGA" }, \
 465         { name, "IN1R", "IN1R PGA" }, \
 466         { name, "IN2L", "IN2L PGA" }, \
 467         { name, "IN2R", "IN2R PGA" }, \
 468         { name, "IN3L", "IN3L PGA" }, \
 469         { name, "IN3R", "IN3R PGA" }, \
 470         { name, "IN4L", "IN4L PGA" }, \
 471         { name, "IN4R", "IN4R PGA" }, \
 472         { name, "AIF1RX1", "AIF1RX1" }, \
 473         { name, "AIF1RX2", "AIF1RX2" }, \
 474         { name, "AIF1RX3", "AIF1RX3" }, \
 475         { name, "AIF1RX4", "AIF1RX4" }, \
 476         { name, "AIF1RX5", "AIF1RX5" }, \
 477         { name, "AIF1RX6", "AIF1RX6" }, \
 478         { name, "AIF1RX7", "AIF1RX7" }, \
 479         { name, "AIF1RX8", "AIF1RX8" }, \
 480         { name, "AIF2RX1", "AIF2RX1" }, \
 481         { name, "AIF2RX2", "AIF2RX2" }, \
 482         { name, "AIF3RX1", "AIF3RX1" }, \
 483         { name, "AIF3RX2", "AIF3RX2" }, \
 484         { name, "EQ1", "EQ1" }, \
 485         { name, "EQ2", "EQ2" }, \
 486         { name, "EQ3", "EQ3" }, \
 487         { name, "EQ4", "EQ4" }, \
 488         { name, "DRC1L", "DRC1L" }, \
 489         { name, "DRC1R", "DRC1R" }, \
 490         { name, "LHPF1", "LHPF1" }, \
 491         { name, "LHPF2", "LHPF2" }, \
 492         { name, "LHPF3", "LHPF3" }, \
 493         { name, "LHPF4", "LHPF4" }
 494
 495 #define WM5100_MIXER_ROUTES(widget, name) \
 496         { widget, NULL, name " Mixer" },         \
 497         { name " Mixer", NULL, name " Input 1" }, \
 498         { name " Mixer", NULL, name " Input 2" }, \
 499         { name " Mixer", NULL, name " Input 3" }, \
 500         { name " Mixer", NULL, name " Input 4" }, \
 501         WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
 502         WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
 503         WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
 504         WM5100_MIXER_INPUT_ROUTES(name " Input 4")
 505
 506 static const char *wm5100_lhpf_mode_text[] = {
 507         "Low-pass", "High-pass"
 508 };
 509
 510 static const struct soc_enum wm5100_lhpf1_mode =
 511         SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
 512                         wm5100_lhpf_mode_text);
 513
 514 static const struct soc_enum wm5100_lhpf2_mode =
 515         SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
 516                         wm5100_lhpf_mode_text);
 517
 518 static const struct soc_enum wm5100_lhpf3_mode =
 519         SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
 520                         wm5100_lhpf_mode_text);
 521
 522 static const struct soc_enum wm5100_lhpf4_mode =
 523         SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
 524                         wm5100_lhpf_mode_text);
 525
 526 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
 527 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
 528            WM5100_IN1_OSR_SHIFT, 1, 0),
 529 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
 530            WM5100_IN2_OSR_SHIFT, 1, 0),
 531 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
 532            WM5100_IN3_OSR_SHIFT, 1, 0),
 533 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
 534            WM5100_IN4_OSR_SHIFT, 1, 0),
 535
 536 /* Only applicable for analogue inputs */
 537 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
 538                  WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
 539 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
 540                  WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
 541 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
 542                  WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
 543 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
 544                  WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
 545
 546 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
 547                  WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
 548                  0, digital_tlv),
 549 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
 550                  WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
 551                  0, digital_tlv),
 552 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
 553                  WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
 554                  0, digital_tlv),
 555 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
 556                  WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
 557                  0, digital_tlv),
 558
 559 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
 560              WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
 561 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
 562              WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
 563 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
 564              WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
 565 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
 566              WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
 567
 568 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
 569            WM5100_OUT1_OSR_SHIFT, 1, 0),
 570 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
 571            WM5100_OUT2_OSR_SHIFT, 1, 0),
 572 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
 573            WM5100_OUT3_OSR_SHIFT, 1, 0),
 574 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
 575            WM5100_OUT4_OSR_SHIFT, 1, 0),
 576 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
 577            WM5100_OUT5_OSR_SHIFT, 1, 0),
 578 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
 579            WM5100_OUT6_OSR_SHIFT, 1, 0),
 580
 581 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
 582                  WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
 583                  digital_tlv),
 584 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
 585                  WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
 586                  digital_tlv),
 587 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
 588                  WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
 589                  digital_tlv),
 590 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
 591                  WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
 592                  digital_tlv),
 593 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
 594                  WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
 595                  digital_tlv),
 596 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
 597                  WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
 598                  digital_tlv),
 599
 600 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
 601              WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
 602 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
 603              WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
 604 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
 605              WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
 606 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
 607              WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
 608 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
 609              WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
 610 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
 611              WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
 612
 613 /* FIXME: Only valid from -12dB to 0dB (52-64) */
 614 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
 615                  WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
 616 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
 617                  WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
 618 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
 619                  WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
 620
 621 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
 622            WM5100_SPK1R_MUTE_SHIFT, 1, 1),
 623 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
 624            WM5100_SPK2R_MUTE_SHIFT, 1, 1),
 625
 626 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
 627                24, 0, eq_tlv),
 628 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
 629                24, 0, eq_tlv),
 630 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
 631                24, 0, eq_tlv),
 632 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
 633                24, 0, eq_tlv),
 634 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
 635                24, 0, eq_tlv),
 636
 637 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
 638                24, 0, eq_tlv),
 639 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
 640                24, 0, eq_tlv),
 641 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
 642                24, 0, eq_tlv),
 643 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
 644                24, 0, eq_tlv),
 645 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
 646                24, 0, eq_tlv),
 647
 648 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
 649                24, 0, eq_tlv),
 650 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
 651                24, 0, eq_tlv),
 652 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
 653                24, 0, eq_tlv),
 654 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
 655                24, 0, eq_tlv),
 656 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
 657                24, 0, eq_tlv),
 658
 659 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
 660                24, 0, eq_tlv),
 661 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
 662                24, 0, eq_tlv),
 663 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
 664                24, 0, eq_tlv),
 665 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
 666                24, 0, eq_tlv),
 667 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
 668                24, 0, eq_tlv),
 669
 670 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
 671 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
 672 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
 673 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
 674
 675 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
 676 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
 677 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
 678 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
 679 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
 680 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
 681
 682 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
 683 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
 684 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
 685 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
 686 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
 687 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
 688
 689 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
 690 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
 691
 692 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
 693 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
 694 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
 695 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
 696 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
 697 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
 698 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
 699 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
 700
 701 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
 702 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
 703
 704 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
 705 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
 706
 707 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
 708 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
 709 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
 710 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
 711
 712 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
 713 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
 714
 715 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
 716 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
 717 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
 718 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
 719 };
 720
 721 static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
 722                                 enum snd_soc_dapm_type event, int subseq)
 723 {
 724         struct snd_soc_codec *codec = container_of(dapm,
 725                                                    struct snd_soc_codec, dapm);
 726         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
 727         u16 val, expect, i;
 728
 729         /* Wait for the outputs to flag themselves as enabled */
 730         if (wm5100->out_ena[0]) {
 731                 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
 732                 for (i = 0; i < 200; i++) {
 733                         val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
 734                         if (val == expect) {
 735                                 wm5100->out_ena[0] = false;
 736                                 break;
 737                         }
 738                 }
 739                 if (i == 200) {
 740                         dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
 741                                 expect);
 742                 }
 743         }
 744
 745         if (wm5100->out_ena[1]) {
 746                 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
 747                 for (i = 0; i < 200; i++) {
 748                         val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
 749                         if (val == expect) {
 750                                 wm5100->out_ena[1] = false;
 751                                 break;
 752                         }
 753                 }
 754                 if (i == 200) {
 755                         dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
 756                                 expect);
 757                 }
 758         }
 759 }
 760
 761 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
 762                          struct snd_kcontrol *kcontrol,
 763                          int event)
 764 {
 765         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
 766
 767         switch (w->reg) {
 768         case WM5100_CHANNEL_ENABLES_1:
 769                 wm5100->out_ena[0] = true;
 770                 break;
 771         case WM5100_OUTPUT_ENABLES_2:
 772                 wm5100->out_ena[0] = true;
 773                 break;
 774         default:
 775                 break;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int wm5100_cp_ev(struct snd_soc_dapm_widget *w,
 782                         struct snd_kcontrol *kcontrol,
 783                         int event)
 784 {
 785         struct snd_soc_codec *codec = w->codec;
 786         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
 787         int ret;
 788
 789         switch (event) {
 790         case SND_SOC_DAPM_PRE_PMU:
 791                 ret = regulator_enable(wm5100->cpvdd);
 792                 if (ret != 0) {
 793                         dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
 794                                 ret);
 795                         return ret;
 796                 }
 797                 return ret;
 798
 799         case SND_SOC_DAPM_POST_PMD:
 800                 ret = regulator_disable_deferred(wm5100->cpvdd, 20);
 801                 if (ret != 0) {
 802                         dev_err(codec->dev, "Failed to disable CPVDD: %d\n",
 803                                 ret);
 804                         return ret;
 805                 }
 806                 return ret;
 807
 808         default:
 809                 BUG();
 810                 return 0;
 811         }
 812 }
 813
 814 static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget *w,
 815                            struct snd_kcontrol *kcontrol,
 816                            int event)
 817 {
 818         struct snd_soc_codec *codec = w->codec;
 819         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
 820         struct regulator *regulator;
 821         int ret;
 822
 823         switch (w->shift) {
 824         case 2:
 825                 regulator = wm5100->dbvdd2;
 826                 break;
 827         case 3:
 828                 regulator = wm5100->dbvdd3;
 829                 break;
 830         default:
 831                 BUG();
 832                 return 0;
 833         }
 834
 835         switch (event) {
 836         case SND_SOC_DAPM_PRE_PMU:
 837                 ret = regulator_enable(regulator);
 838                 if (ret != 0) {
 839                         dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
 840                                 w->shift, ret);
 841                         return ret;
 842                 }
 843                 return ret;
 844
 845         case SND_SOC_DAPM_POST_PMD:
 846                 ret = regulator_disable(regulator);
 847                 if (ret != 0) {
 848                         dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
 849                                 w->shift, ret);
 850                         return ret;
 851                 }
 852                 return ret;
 853
 854         default:
 855                 BUG();
 856                 return 0;
 857         }
 858 }
 859
 860 static void wm5100_log_status3(struct snd_soc_codec *codec, int val)
 861 {
 862         if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
 863                 dev_crit(codec->dev, "Speaker shutdown warning\n");
 864         if (val & WM5100_SPK_SHUTDOWN_EINT)
 865                 dev_crit(codec->dev, "Speaker shutdown\n");
 866         if (val & WM5100_CLKGEN_ERR_EINT)
 867                 dev_crit(codec->dev, "SYSCLK underclocked\n");
 868         if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
 869                 dev_crit(codec->dev, "ASYNCCLK underclocked\n");
 870 }
 871
 872 static void wm5100_log_status4(struct snd_soc_codec *codec, int val)
 873 {
 874         if (val & WM5100_AIF3_ERR_EINT)
 875                 dev_err(codec->dev, "AIF3 configuration error\n");
 876         if (val & WM5100_AIF2_ERR_EINT)
 877                 dev_err(codec->dev, "AIF2 configuration error\n");
 878         if (val & WM5100_AIF1_ERR_EINT)
 879                 dev_err(codec->dev, "AIF1 configuration error\n");
 880         if (val & WM5100_CTRLIF_ERR_EINT)
 881                 dev_err(codec->dev, "Control interface error\n");
 882         if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
 883                 dev_err(codec->dev, "ISRC2 underclocked\n");
 884         if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
 885                 dev_err(codec->dev, "ISRC1 underclocked\n");
 886         if (val & WM5100_FX_UNDERCLOCKED_EINT)
 887                 dev_err(codec->dev, "FX underclocked\n");
 888         if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
 889                 dev_err(codec->dev, "AIF3 underclocked\n");
 890         if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
 891                 dev_err(codec->dev, "AIF2 underclocked\n");
 892         if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
 893                 dev_err(codec->dev, "AIF1 underclocked\n");
 894         if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
 895                 dev_err(codec->dev, "ASRC underclocked\n");
 896         if (val & WM5100_DAC_UNDERCLOCKED_EINT)
 897                 dev_err(codec->dev, "DAC underclocked\n");
 898         if (val & WM5100_ADC_UNDERCLOCKED_EINT)
 899                 dev_err(codec->dev, "ADC underclocked\n");
 900         if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
 901                 dev_err(codec->dev, "Mixer underclocked\n");
 902 }
 903
 904 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
 905                           struct snd_kcontrol *kcontrol,
 906                           int event)
 907 {
 908         struct snd_soc_codec *codec = w->codec;
 909         int ret;
 910
 911         ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
 912         ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
 913                 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
 914                 WM5100_CLKGEN_ERR_ASYNC_STS;
 915         wm5100_log_status3(codec, ret);
 916
 917         ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
 918         wm5100_log_status4(codec, ret);
 919
 920         return 0;
 921 }
 922
 923 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
 924 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
 925                     NULL, 0),
 926 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
 927                     0, NULL, 0),
 928
 929 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
 930                     wm5100_cp_ev,
 931                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 932 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
 933                     NULL, 0),
 934 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
 935                     WM5100_CP2_BYPASS_SHIFT, 1, wm5100_cp_ev,
 936                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 937 SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM, 2, 0, wm5100_dbvdd_ev,
 938                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 939 SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM, 3, 0, wm5100_dbvdd_ev,
 940                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 941
 942 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
 943                     0, NULL, 0),
 944 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
 945                     0, NULL, 0),
 946 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
 947                     0, NULL, 0),
 948
 949 SND_SOC_DAPM_INPUT("IN1L"),
 950 SND_SOC_DAPM_INPUT("IN1R"),
 951 SND_SOC_DAPM_INPUT("IN2L"),
 952 SND_SOC_DAPM_INPUT("IN2R"),
 953 SND_SOC_DAPM_INPUT("IN3L"),
 954 SND_SOC_DAPM_INPUT("IN3R"),
 955 SND_SOC_DAPM_INPUT("IN4L"),
 956 SND_SOC_DAPM_INPUT("IN4R"),
 957 SND_SOC_DAPM_INPUT("TONE"),
 958
 959 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
 960                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 961 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
 962                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 963 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
 964                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 965 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
 966                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 967 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
 968                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 969 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
 970                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 971 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
 972                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 973 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
 974                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
 975
 976 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
 977                  WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
 978 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
 979                  WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
 980
 981 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
 982                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
 983 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
 984                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
 985 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
 986                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
 987 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
 988                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
 989 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
 990                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
 991 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
 992                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
 993 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
 994                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
 995 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
 996                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
 997
 998 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
 999                     WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
1000 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
1001                     WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
1002
1003 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1004                     WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
1005 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1006                     WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
1007
1008 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1009                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
1010 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1011                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1013                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
1014 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1015                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
1016 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1017                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
1018 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1019                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
1020 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1021                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
1022 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1023                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
1024
1025 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1026                     WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
1027 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1028                     WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
1029
1030 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1031                     WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
1032 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1033                     WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
1034
1035 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
1036                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1037 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
1038                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1039 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
1040                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1041 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
1042                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1043 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
1044                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1045 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
1046                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1047 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
1048                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1049 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
1050                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1051 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
1052                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1053 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
1054                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1055 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
1056                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1057 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
1058                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1059 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
1060                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1061 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
1062                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1063
1064 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1065 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1066 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1067 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1068
1069 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1070                  NULL, 0),
1071 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1072                  NULL, 0),
1073
1074 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1075                  NULL, 0),
1076 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1077                  NULL, 0),
1078 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1079                  NULL, 0),
1080 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1081                  NULL, 0),
1082
1083 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1084 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1085 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1086 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1087
1088 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1089 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1090
1091 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1092 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1093 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1094 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1095
1096 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1097 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1098 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1099 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1100 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1101 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1102 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1103 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1104
1105 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1106 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1107
1108 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1109 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1110
1111 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1112 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1113 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1114 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1115 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1116 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1117
1118 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1119 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1120 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1121 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1122 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1123 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1124
1125 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1126 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1127
1128 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1129 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1130 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1131 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1132 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1133 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1134 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1135 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1136 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1137 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1138 SND_SOC_DAPM_OUTPUT("PWM1"),
1139 SND_SOC_DAPM_OUTPUT("PWM2"),
1140 };
1141
1142 /* We register a _POST event if we don't have IRQ support so we can
1143  * look at the error status from the CODEC - if we've got the IRQ
1144  * hooked up then we will get prompted to look by an interrupt.
1145  */
1146 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1147 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1148 };
1149
1150 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1151         { "IN1L", NULL, "SYSCLK" },
1152         { "IN1R", NULL, "SYSCLK" },
1153         { "IN2L", NULL, "SYSCLK" },
1154         { "IN2R", NULL, "SYSCLK" },
1155         { "IN3L", NULL, "SYSCLK" },
1156         { "IN3R", NULL, "SYSCLK" },
1157         { "IN4L", NULL, "SYSCLK" },
1158         { "IN4R", NULL, "SYSCLK" },
1159
1160         { "OUT1L", NULL, "SYSCLK" },
1161         { "OUT1R", NULL, "SYSCLK" },
1162         { "OUT2L", NULL, "SYSCLK" },
1163         { "OUT2R", NULL, "SYSCLK" },
1164         { "OUT3L", NULL, "SYSCLK" },
1165         { "OUT3R", NULL, "SYSCLK" },
1166         { "OUT4L", NULL, "SYSCLK" },
1167         { "OUT4R", NULL, "SYSCLK" },
1168         { "OUT5L", NULL, "SYSCLK" },
1169         { "OUT5R", NULL, "SYSCLK" },
1170         { "OUT6L", NULL, "SYSCLK" },
1171         { "OUT6R", NULL, "SYSCLK" },
1172
1173         { "AIF1RX1", NULL, "SYSCLK" },
1174         { "AIF1RX2", NULL, "SYSCLK" },
1175         { "AIF1RX3", NULL, "SYSCLK" },
1176         { "AIF1RX4", NULL, "SYSCLK" },
1177         { "AIF1RX5", NULL, "SYSCLK" },
1178         { "AIF1RX6", NULL, "SYSCLK" },
1179         { "AIF1RX7", NULL, "SYSCLK" },
1180         { "AIF1RX8", NULL, "SYSCLK" },
1181
1182         { "AIF2RX1", NULL, "SYSCLK" },
1183         { "AIF2RX1", NULL, "DBVDD2" },
1184         { "AIF2RX2", NULL, "SYSCLK" },
1185         { "AIF2RX2", NULL, "DBVDD2" },
1186
1187         { "AIF3RX1", NULL, "SYSCLK" },
1188         { "AIF3RX1", NULL, "DBVDD3" },
1189         { "AIF3RX2", NULL, "SYSCLK" },
1190         { "AIF3RX2", NULL, "DBVDD3" },
1191
1192         { "AIF1TX1", NULL, "SYSCLK" },
1193         { "AIF1TX2", NULL, "SYSCLK" },
1194         { "AIF1TX3", NULL, "SYSCLK" },
1195         { "AIF1TX4", NULL, "SYSCLK" },
1196         { "AIF1TX5", NULL, "SYSCLK" },
1197         { "AIF1TX6", NULL, "SYSCLK" },
1198         { "AIF1TX7", NULL, "SYSCLK" },
1199         { "AIF1TX8", NULL, "SYSCLK" },
1200
1201         { "AIF2TX1", NULL, "SYSCLK" },
1202         { "AIF2TX1", NULL, "DBVDD2" },
1203         { "AIF2TX2", NULL, "SYSCLK" },
1204         { "AIF2TX2", NULL, "DBVDD2" },
1205
1206         { "AIF3TX1", NULL, "SYSCLK" },
1207         { "AIF3TX1", NULL, "DBVDD3" },
1208         { "AIF3TX2", NULL, "SYSCLK" },
1209         { "AIF3TX2", NULL, "DBVDD3" },
1210
1211         { "MICBIAS1", NULL, "CP2" },
1212         { "MICBIAS2", NULL, "CP2" },
1213         { "MICBIAS3", NULL, "CP2" },
1214
1215         { "IN1L PGA", NULL, "CP2" },
1216         { "IN1R PGA", NULL, "CP2" },
1217         { "IN2L PGA", NULL, "CP2" },
1218         { "IN2R PGA", NULL, "CP2" },
1219         { "IN3L PGA", NULL, "CP2" },
1220         { "IN3R PGA", NULL, "CP2" },
1221         { "IN4L PGA", NULL, "CP2" },
1222         { "IN4R PGA", NULL, "CP2" },
1223
1224         { "IN1L PGA", NULL, "CP2 Active" },
1225         { "IN1R PGA", NULL, "CP2 Active" },
1226         { "IN2L PGA", NULL, "CP2 Active" },
1227         { "IN2R PGA", NULL, "CP2 Active" },
1228         { "IN3L PGA", NULL, "CP2 Active" },
1229         { "IN3R PGA", NULL, "CP2 Active" },
1230         { "IN4L PGA", NULL, "CP2 Active" },
1231         { "IN4R PGA", NULL, "CP2 Active" },
1232
1233         { "OUT1L", NULL, "CP1" },
1234         { "OUT1R", NULL, "CP1" },
1235         { "OUT2L", NULL, "CP1" },
1236         { "OUT2R", NULL, "CP1" },
1237         { "OUT3L", NULL, "CP1" },
1238         { "OUT3R", NULL, "CP1" },
1239
1240         { "Tone Generator 1", NULL, "TONE" },
1241         { "Tone Generator 2", NULL, "TONE" },
1242
1243         { "IN1L PGA", NULL, "IN1L" },
1244         { "IN1R PGA", NULL, "IN1R" },
1245         { "IN2L PGA", NULL, "IN2L" },
1246         { "IN2R PGA", NULL, "IN2R" },
1247         { "IN3L PGA", NULL, "IN3L" },
1248         { "IN3R PGA", NULL, "IN3R" },
1249         { "IN4L PGA", NULL, "IN4L" },
1250         { "IN4R PGA", NULL, "IN4R" },
1251
1252         WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1253         WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1254         WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1255         WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1256         WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1257         WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1258
1259         WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1260         WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1261         WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1262         WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1263         WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1264         WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1265
1266         WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1267         WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1268
1269         WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1270         WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1271         WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1272         WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1273         WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1274         WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1275         WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1276         WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1277
1278         WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1279         WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1280
1281         WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1282         WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1283
1284         WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1285         WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1286         WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1287         WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1288
1289         WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1290         WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1291
1292         WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1293         WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1294         WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1295         WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1296
1297         { "HPOUT1L", NULL, "OUT1L" },
1298         { "HPOUT1R", NULL, "OUT1R" },
1299         { "HPOUT2L", NULL, "OUT2L" },
1300         { "HPOUT2R", NULL, "OUT2R" },
1301         { "HPOUT3L", NULL, "OUT3L" },
1302         { "HPOUT3R", NULL, "OUT3R" },
1303         { "SPKOUTL", NULL, "OUT4L" },
1304         { "SPKOUTR", NULL, "OUT4R" },
1305         { "SPKDAT1", NULL, "OUT5L" },
1306         { "SPKDAT1", NULL, "OUT5R" },
1307         { "SPKDAT2", NULL, "OUT6L" },
1308         { "SPKDAT2", NULL, "OUT6R" },
1309         { "PWM1", NULL, "PWM1 Driver" },
1310         { "PWM2", NULL, "PWM2 Driver" },
1311 };
1312
1313 static struct {
1314         int reg;
1315         int val;
1316 } wm5100_reva_patches[] = {
1317         { WM5100_AUDIO_IF_1_10, 0 },
1318         { WM5100_AUDIO_IF_1_11, 1 },
1319         { WM5100_AUDIO_IF_1_12, 2 },
1320         { WM5100_AUDIO_IF_1_13, 3 },
1321         { WM5100_AUDIO_IF_1_14, 4 },
1322         { WM5100_AUDIO_IF_1_15, 5 },
1323         { WM5100_AUDIO_IF_1_16, 6 },
1324         { WM5100_AUDIO_IF_1_17, 7 },
1325
1326         { WM5100_AUDIO_IF_1_18, 0 },
1327         { WM5100_AUDIO_IF_1_19, 1 },
1328         { WM5100_AUDIO_IF_1_20, 2 },
1329         { WM5100_AUDIO_IF_1_21, 3 },
1330         { WM5100_AUDIO_IF_1_22, 4 },
1331         { WM5100_AUDIO_IF_1_23, 5 },
1332         { WM5100_AUDIO_IF_1_24, 6 },
1333         { WM5100_AUDIO_IF_1_25, 7 },
1334
1335         { WM5100_AUDIO_IF_2_10, 0 },
1336         { WM5100_AUDIO_IF_2_11, 1 },
1337
1338         { WM5100_AUDIO_IF_2_18, 0 },
1339         { WM5100_AUDIO_IF_2_19, 1 },
1340
1341         { WM5100_AUDIO_IF_3_10, 0 },
1342         { WM5100_AUDIO_IF_3_11, 1 },
1343
1344         { WM5100_AUDIO_IF_3_18, 0 },
1345         { WM5100_AUDIO_IF_3_19, 1 },
1346 };
1347
1348 static int wm5100_set_bias_level(struct snd_soc_codec *codec,
1349                                  enum snd_soc_bias_level level)
1350 {
1351         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1352         int ret, i;
1353
1354         switch (level) {
1355         case SND_SOC_BIAS_ON:
1356                 break;
1357
1358         case SND_SOC_BIAS_PREPARE:
1359                 break;
1360
1361         case SND_SOC_BIAS_STANDBY:
1362                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1363                         ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
1364                                                     wm5100->core_supplies);
1365                         if (ret != 0) {
1366                                 dev_err(codec->dev,
1367                                         "Failed to enable supplies: %d\n",
1368                                         ret);
1369                                 return ret;
1370                         }
1371
1372                         if (wm5100->pdata.ldo_ena) {
1373                                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena,
1374                                                         1);
1375                                 msleep(2);
1376                         }
1377
1378                         codec->cache_only = false;
1379
1380                         switch (wm5100->rev) {
1381                         case 0:
1382                                 snd_soc_write(codec, 0x11, 0x3);
1383                                 snd_soc_write(codec, 0x203, 0xc);
1384                                 snd_soc_write(codec, 0x206, 0);
1385                                 snd_soc_write(codec, 0x207, 0xf0);
1386                                 snd_soc_write(codec, 0x208, 0x3c);
1387                                 snd_soc_write(codec, 0x209, 0);
1388                                 snd_soc_write(codec, 0x211, 0x20d8);
1389                                 snd_soc_write(codec, 0x11, 0);
1390
1391                                 for (i = 0;
1392                                      i < ARRAY_SIZE(wm5100_reva_patches);
1393                                      i++)
1394                                         snd_soc_write(codec,
1395                                                       wm5100_reva_patches[i].reg,
1396                                                       wm5100_reva_patches[i].val);
1397                                 break;
1398                         default:
1399                                 break;
1400                         }
1401
1402                         snd_soc_cache_sync(codec);
1403                 }
1404                 break;
1405
1406         case SND_SOC_BIAS_OFF:
1407                 if (wm5100->pdata.ldo_ena)
1408                         gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
1409                 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
1410                                        wm5100->core_supplies);
1411                 break;
1412         }
1413         codec->dapm.bias_level = level;
1414
1415         return 0;
1416 }
1417
1418 static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1419 {
1420         switch (dai->id) {
1421         case 0:
1422                 return WM5100_AUDIO_IF_1_1 - 1;
1423         case 1:
1424                 return WM5100_AUDIO_IF_2_1 - 1;
1425         case 2:
1426                 return WM5100_AUDIO_IF_3_1 - 1;
1427         default:
1428                 BUG();
1429                 return -EINVAL;
1430         }
1431 }
1432
1433 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1434 {
1435         struct snd_soc_codec *codec = dai->codec;
1436         int lrclk, bclk, mask, base;
1437
1438         base = wm5100_dai_to_base(dai);
1439         if (base < 0)
1440                 return base;
1441
1442         lrclk = 0;
1443         bclk = 0;
1444
1445         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1446         case SND_SOC_DAIFMT_DSP_A:
1447                 mask = 0;
1448                 break;
1449         case SND_SOC_DAIFMT_I2S:
1450                 mask = 2;
1451                 break;
1452         default:
1453                 dev_err(codec->dev, "Unsupported DAI format %d\n",
1454                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1455                 return -EINVAL;
1456         }
1457
1458         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1459         case SND_SOC_DAIFMT_CBS_CFS:
1460                 break;
1461         case SND_SOC_DAIFMT_CBS_CFM:
1462                 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1463                 break;
1464         case SND_SOC_DAIFMT_CBM_CFS:
1465                 bclk |= WM5100_AIF1_BCLK_MSTR;
1466                 break;
1467         case SND_SOC_DAIFMT_CBM_CFM:
1468                 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1469                 bclk |= WM5100_AIF1_BCLK_MSTR;
1470                 break;
1471         default:
1472                 dev_err(codec->dev, "Unsupported master mode %d\n",
1473                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
1474                 return -EINVAL;
1475         }
1476
1477         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1478         case SND_SOC_DAIFMT_NB_NF:
1479                 break;
1480         case SND_SOC_DAIFMT_IB_IF:
1481                 bclk |= WM5100_AIF1_BCLK_INV;
1482                 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1483                 break;
1484         case SND_SOC_DAIFMT_IB_NF:
1485                 bclk |= WM5100_AIF1_BCLK_INV;
1486                 break;
1487         case SND_SOC_DAIFMT_NB_IF:
1488                 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1489                 break;
1490         default:
1491                 return -EINVAL;
1492         }
1493
1494         snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1495                             WM5100_AIF1_BCLK_INV, bclk);
1496         snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1497                             WM5100_AIF1TX_LRCLK_INV, lrclk);
1498         snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1499                             WM5100_AIF1TX_LRCLK_INV, lrclk);
1500         snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1501
1502         return 0;
1503 }
1504
1505 #define WM5100_NUM_BCLK_RATES 19
1506
1507 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1508         32000,
1509         48000,
1510         64000,
1511         96000,
1512         128000,
1513         192000,
1514         256000,
1515         384000,
1516         512000,
1517         768000,
1518         1024000,
1519         1536000,
1520         2048000,
1521         3072000,
1522         4096000,
1523         6144000,
1524         8192000,
1525         12288000,
1526         24576000,
1527 };
1528
1529 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1530         29400,
1531         44100,
1532         58800,
1533         88200,
1534         117600,
1535         176400,
1536         235200,
1537         352800,
1538         470400,
1539         705600,
1540         940800,
1541         1411200,
1542         1881600,
1543         2882400,
1544         3763200,
1545         5644800,
1546         7526400,
1547         11289600,
1548         22579600,
1549 };
1550
1551 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1552                             struct snd_pcm_hw_params *params,
1553                             struct snd_soc_dai *dai)
1554 {
1555         struct snd_soc_codec *codec = dai->codec;
1556         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1557         bool async = wm5100->aif_async[dai->id];
1558         int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1559         int *bclk_rates;
1560
1561         base = wm5100_dai_to_base(dai);
1562         if (base < 0)
1563                 return base;
1564
1565         /* Data sizes if not using TDM */
1566         wl = snd_pcm_format_width(params_format(params));
1567         if (wl < 0)
1568                 return wl;
1569         fl = snd_soc_params_to_frame_size(params);
1570         if (fl < 0)
1571                 return fl;
1572
1573         dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1574                 wl, fl);
1575
1576         /* Target BCLK rate */
1577         bclk = snd_soc_params_to_bclk(params);
1578         if (bclk < 0)
1579                 return bclk;
1580
1581         /* Root for BCLK depends on SYS/ASYNCCLK */
1582         if (!async) {
1583                 aif_rate = wm5100->sysclk;
1584                 sr = wm5100_alloc_sr(codec, params_rate(params));
1585                 if (sr < 0)
1586                         return sr;
1587         } else {
1588                 /* If we're in ASYNCCLK set the ASYNC sample rate */
1589                 aif_rate = wm5100->asyncclk;
1590                 sr = 3;
1591
1592                 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1593                         if (params_rate(params) == wm5100_sr_code[i])
1594                                 break;
1595                 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1596                         dev_err(codec->dev, "Invalid rate %dHzn",
1597                                 params_rate(params));
1598                         return -EINVAL;
1599                 }
1600
1601                 /* TODO: We should really check for symmetry */
1602                 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1603                                     WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1604         }
1605
1606         if (!aif_rate) {
1607                 dev_err(codec->dev, "%s has no rate set\n",
1608                         async ? "ASYNCCLK" : "SYSCLK");
1609                 return -EINVAL;
1610         }
1611
1612         dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1613                 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1614
1615         if (aif_rate % 4000)
1616                 bclk_rates = wm5100_bclk_rates_cd;
1617         else
1618                 bclk_rates = wm5100_bclk_rates_dat;
1619
1620         for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1621                 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1622                         break;
1623         if (i == WM5100_NUM_BCLK_RATES) {
1624                 dev_err(codec->dev,
1625                         "No valid BCLK for %dHz found from %dHz %s\n",
1626                         bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1627                 return -EINVAL;
1628         }
1629
1630         bclk = i;
1631         dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1632         snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1633
1634         lrclk = bclk_rates[bclk] / params_rate(params);
1635         dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1636         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1637             wm5100->aif_symmetric[dai->id])
1638                 snd_soc_update_bits(codec, base + 7,
1639                                     WM5100_AIF1RX_BCPF_MASK, lrclk);
1640         else
1641                 snd_soc_update_bits(codec, base + 6,
1642                                     WM5100_AIF1TX_BCPF_MASK, lrclk);
1643
1644         i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1645         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1646                 snd_soc_update_bits(codec, base + 9,
1647                                     WM5100_AIF1RX_WL_MASK |
1648                                     WM5100_AIF1RX_SLOT_LEN_MASK, i);
1649         else
1650                 snd_soc_update_bits(codec, base + 8,
1651                                     WM5100_AIF1TX_WL_MASK |
1652                                     WM5100_AIF1TX_SLOT_LEN_MASK, i);
1653
1654         snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1655
1656         return 0;
1657 }
1658
1659 static struct snd_soc_dai_ops wm5100_dai_ops = {
1660         .set_fmt = wm5100_set_fmt,
1661         .hw_params = wm5100_hw_params,
1662 };
1663
1664 static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1665                              int source, unsigned int freq, int dir)
1666 {
1667         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1668         int *rate_store;
1669         int fval, audio_rate, ret, reg;
1670
1671         switch (clk_id) {
1672         case WM5100_CLK_SYSCLK:
1673                 reg = WM5100_CLOCKING_3;
1674                 rate_store = &wm5100->sysclk;
1675                 break;
1676         case WM5100_CLK_ASYNCCLK:
1677                 reg = WM5100_CLOCKING_7;
1678                 rate_store = &wm5100->asyncclk;
1679                 break;
1680         case WM5100_CLK_32KHZ:
1681                 /* The 32kHz clock is slightly different to the others */
1682                 switch (source) {
1683                 case WM5100_CLKSRC_MCLK1:
1684                 case WM5100_CLKSRC_MCLK2:
1685                 case WM5100_CLKSRC_SYSCLK:
1686                         snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1687                                             WM5100_CLK_32K_SRC_MASK,
1688                                             source);
1689                         break;
1690                 default:
1691                         return -EINVAL;
1692                 }
1693                 return 0;
1694
1695         case WM5100_CLK_AIF1:
1696         case WM5100_CLK_AIF2:
1697         case WM5100_CLK_AIF3:
1698                 /* Not real clocks, record which clock domain they're in */
1699                 switch (source) {
1700                 case WM5100_CLKSRC_SYSCLK:
1701                         wm5100->aif_async[clk_id - 1] = false;
1702                         break;
1703                 case WM5100_CLKSRC_ASYNCCLK:
1704                         wm5100->aif_async[clk_id - 1] = true;
1705                         break;
1706                 default:
1707                         dev_err(codec->dev, "Invalid source %d\n", source);
1708                         return -EINVAL;
1709                 }
1710                 return 0;
1711
1712         case WM5100_CLK_OPCLK:
1713                 switch (freq) {
1714                 case 5644800:
1715                 case 6144000:
1716                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1717                                             WM5100_OPCLK_SEL_MASK, 0);
1718                         break;
1719                 case 11289600:
1720                 case 12288000:
1721                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1722                                             WM5100_OPCLK_SEL_MASK, 0);
1723                         break;
1724                 case 22579200:
1725                 case 24576000:
1726                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1727                                             WM5100_OPCLK_SEL_MASK, 0);
1728                         break;
1729                 default:
1730                         dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1731                                 freq);
1732                         return -EINVAL;
1733                 }
1734                 return 0;
1735
1736         default:
1737                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1738                 return -EINVAL;
1739         }
1740
1741         switch (source) {
1742         case WM5100_CLKSRC_SYSCLK:
1743         case WM5100_CLKSRC_ASYNCCLK:
1744                 dev_err(codec->dev, "Invalid source %d\n", source);
1745                 return -EINVAL;
1746         }
1747
1748         switch (freq) {
1749         case 5644800:
1750         case 6144000:
1751                 fval = 0;
1752                 break;
1753         case 11289600:
1754         case 12288000:
1755                 fval = 1;
1756                 break;
1757         case 22579200:
1758         case 24576000:
1759                 fval = 2;
1760                 break;
1761         default:
1762                 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1763                 return -EINVAL;
1764         }
1765
1766         switch (freq) {
1767         case 5644800:
1768         case 11289600:
1769         case 22579200:
1770                 audio_rate = 44100;
1771                 break;
1772
1773         case 6144000:
1774         case 12288000:
1775         case 24576000:
1776                 audio_rate = 48000;
1777                 break;
1778
1779         default:
1780                 BUG();
1781                 audio_rate = 0;
1782                 break;
1783         }
1784
1785         /* TODO: Check if MCLKs are in use and enable/disable pulls to
1786          * match.
1787          */
1788
1789         snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1790                             WM5100_SYSCLK_SRC_MASK,
1791                             fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1792
1793         /* If this is SYSCLK then configure the clock rate for the
1794          * internal audio functions to the natural sample rate for
1795          * this clock rate.
1796          */
1797         if (clk_id == WM5100_CLK_SYSCLK) {
1798                 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1799                         audio_rate);
1800                 if (0 && *rate_store)
1801                         wm5100_free_sr(codec, audio_rate);
1802                 ret = wm5100_alloc_sr(codec, audio_rate);
1803                 if (ret != 0)
1804                         dev_warn(codec->dev, "Primary audio slot is %d\n",
1805                                  ret);
1806         }
1807
1808         *rate_store = freq;
1809
1810         return 0;
1811 }
1812
1813 struct _fll_div {
1814         u16 fll_fratio;
1815         u16 fll_outdiv;
1816         u16 fll_refclk_div;
1817         u16 n;
1818         u16 theta;
1819         u16 lambda;
1820 };
1821
1822 static struct {
1823         unsigned int min;
1824         unsigned int max;
1825         u16 fll_fratio;
1826         int ratio;
1827 } fll_fratios[] = {
1828         {       0,    64000, 4, 16 },
1829         {   64000,   128000, 3,  8 },
1830         {  128000,   256000, 2,  4 },
1831         {  256000,  1000000, 1,  2 },
1832         { 1000000, 13500000, 0,  1 },
1833 };
1834
1835 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1836                        unsigned int Fout)
1837 {
1838         unsigned int target;
1839         unsigned int div;
1840         unsigned int fratio, gcd_fll;
1841         int i;
1842
1843         /* Fref must be <=13.5MHz */
1844         div = 1;
1845         fll_div->fll_refclk_div = 0;
1846         while ((Fref / div) > 13500000) {
1847                 div *= 2;
1848                 fll_div->fll_refclk_div++;
1849
1850                 if (div > 8) {
1851                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1852                                Fref);
1853                         return -EINVAL;
1854                 }
1855         }
1856
1857         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1858
1859         /* Apply the division for our remaining calculations */
1860         Fref /= div;
1861
1862         /* Fvco should be 90-100MHz; don't check the upper bound */
1863         div = 2;
1864         while (Fout * div < 90000000) {
1865                 div++;
1866                 if (div > 64) {
1867                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1868                                Fout);
1869                         return -EINVAL;
1870                 }
1871         }
1872         target = Fout * div;
1873         fll_div->fll_outdiv = div - 1;
1874
1875         pr_debug("FLL Fvco=%dHz\n", target);
1876
1877         /* Find an appropraite FLL_FRATIO and factor it out of the target */
1878         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1879                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1880                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1881                         fratio = fll_fratios[i].ratio;
1882                         break;
1883                 }
1884         }
1885         if (i == ARRAY_SIZE(fll_fratios)) {
1886                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1887                 return -EINVAL;
1888         }
1889
1890         fll_div->n = target / (fratio * Fref);
1891
1892         if (target % Fref == 0) {
1893                 fll_div->theta = 0;
1894                 fll_div->lambda = 0;
1895         } else {
1896                 gcd_fll = gcd(target, fratio * Fref);
1897
1898                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1899                         / gcd_fll;
1900                 fll_div->lambda = (fratio * Fref) / gcd_fll;
1901         }
1902
1903         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1904                  fll_div->n, fll_div->theta, fll_div->lambda);
1905         pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1906                  fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1907                  fll_div->fll_refclk_div);
1908
1909         return 0;
1910 }
1911
1912 static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1913                           unsigned int Fref, unsigned int Fout)
1914 {
1915         struct i2c_client *i2c = to_i2c_client(codec->dev);
1916         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1917         struct _fll_div factors;
1918         struct wm5100_fll *fll;
1919         int ret, base, lock, i, timeout;
1920
1921         switch (fll_id) {
1922         case WM5100_FLL1:
1923                 fll = &wm5100->fll[0];
1924                 base = WM5100_FLL1_CONTROL_1 - 1;
1925                 lock = WM5100_FLL1_LOCK_STS;
1926                 break;
1927         case WM5100_FLL2:
1928                 fll = &wm5100->fll[1];
1929                 base = WM5100_FLL2_CONTROL_2 - 1;
1930                 lock = WM5100_FLL2_LOCK_STS;
1931                 break;
1932         default:
1933                 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1934                 return -EINVAL;
1935         }
1936
1937         if (!Fout) {
1938                 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1939                 fll->fout = 0;
1940                 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1941                 return 0;
1942         }
1943
1944         switch (source) {
1945         case WM5100_FLL_SRC_MCLK1:
1946         case WM5100_FLL_SRC_MCLK2:
1947         case WM5100_FLL_SRC_FLL1:
1948         case WM5100_FLL_SRC_FLL2:
1949         case WM5100_FLL_SRC_AIF1BCLK:
1950         case WM5100_FLL_SRC_AIF2BCLK:
1951         case WM5100_FLL_SRC_AIF3BCLK:
1952                 break;
1953         default:
1954                 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1955                 return -EINVAL;
1956         }
1957
1958         ret = fll_factors(&factors, Fref, Fout);
1959         if (ret < 0)
1960                 return ret;
1961
1962         /* Disable the FLL while we reconfigure */
1963         snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1964
1965         snd_soc_update_bits(codec, base + 2,
1966                             WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1967                             (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1968                             factors.fll_fratio);
1969         snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1970                             factors.theta);
1971         snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1972         snd_soc_update_bits(codec, base + 6,
1973                             WM5100_FLL1_REFCLK_DIV_MASK |
1974                             WM5100_FLL1_REFCLK_SRC_MASK,
1975                             (factors.fll_refclk_div
1976                              << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1977         snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1978                             factors.lambda);
1979
1980         /* Clear any pending completions */
1981         try_wait_for_completion(&fll->lock);
1982
1983         snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1984
1985         if (i2c->irq)
1986                 timeout = 2;
1987         else
1988                 timeout = 50;
1989
1990         /* Poll for the lock; will use interrupt when we can test */
1991         for (i = 0; i < timeout; i++) {
1992                 if (i2c->irq) {
1993                         ret = wait_for_completion_timeout(&fll->lock,
1994                                                           msecs_to_jiffies(25));
1995                         if (ret > 0)
1996                                 break;
1997                 } else {
1998                         msleep(1);
1999                 }
2000
2001                 ret = snd_soc_read(codec,
2002                                    WM5100_INTERRUPT_RAW_STATUS_3);
2003                 if (ret < 0) {
2004                         dev_err(codec->dev,
2005                                 "Failed to read FLL status: %d\n",
2006                                 ret);
2007                         continue;
2008                 }
2009                 if (ret & lock)
2010                         break;
2011         }
2012         if (i == timeout) {
2013                 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
2014                 return -ETIMEDOUT;
2015         }
2016
2017         fll->src = source;
2018         fll->fref = Fref;
2019         fll->fout = Fout;
2020
2021         dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
2022                 Fref, Fout);
2023
2024         return 0;
2025 }
2026
2027 /* Actually go much higher */
2028 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2029
2030 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2031                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2032
2033 static struct snd_soc_dai_driver wm5100_dai[] = {
2034         {
2035                 .name = "wm5100-aif1",
2036                 .playback = {
2037                         .stream_name = "AIF1 Playback",
2038                         .channels_min = 2,
2039                         .channels_max = 2,
2040                         .rates = WM5100_RATES,
2041                         .formats = WM5100_FORMATS,
2042                 },
2043                 .capture = {
2044                          .stream_name = "AIF1 Capture",
2045                          .channels_min = 2,
2046                          .channels_max = 2,
2047                          .rates = WM5100_RATES,
2048                          .formats = WM5100_FORMATS,
2049                  },
2050                 .ops = &wm5100_dai_ops,
2051         },
2052         {
2053                 .name = "wm5100-aif2",
2054                 .id = 1,
2055                 .playback = {
2056                         .stream_name = "AIF2 Playback",
2057                         .channels_min = 2,
2058                         .channels_max = 2,
2059                         .rates = WM5100_RATES,
2060                         .formats = WM5100_FORMATS,
2061                 },
2062                 .capture = {
2063                          .stream_name = "AIF2 Capture",
2064                          .channels_min = 2,
2065                          .channels_max = 2,
2066                          .rates = WM5100_RATES,
2067                          .formats = WM5100_FORMATS,
2068                  },
2069                 .ops = &wm5100_dai_ops,
2070         },
2071         {
2072                 .name = "wm5100-aif3",
2073                 .id = 2,
2074                 .playback = {
2075                         .stream_name = "AIF3 Playback",
2076                         .channels_min = 2,
2077                         .channels_max = 2,
2078                         .rates = WM5100_RATES,
2079                         .formats = WM5100_FORMATS,
2080                 },
2081                 .capture = {
2082                          .stream_name = "AIF3 Capture",
2083                          .channels_min = 2,
2084                          .channels_max = 2,
2085                          .rates = WM5100_RATES,
2086                          .formats = WM5100_FORMATS,
2087                  },
2088                 .ops = &wm5100_dai_ops,
2089         },
2090 };
2091
2092 static int wm5100_dig_vu[] = {
2093         WM5100_ADC_DIGITAL_VOLUME_1L,
2094         WM5100_ADC_DIGITAL_VOLUME_1R,
2095         WM5100_ADC_DIGITAL_VOLUME_2L,
2096         WM5100_ADC_DIGITAL_VOLUME_2R,
2097         WM5100_ADC_DIGITAL_VOLUME_3L,
2098         WM5100_ADC_DIGITAL_VOLUME_3R,
2099         WM5100_ADC_DIGITAL_VOLUME_4L,
2100         WM5100_ADC_DIGITAL_VOLUME_4R,
2101
2102         WM5100_DAC_DIGITAL_VOLUME_1L,
2103         WM5100_DAC_DIGITAL_VOLUME_1R,
2104         WM5100_DAC_DIGITAL_VOLUME_2L,
2105         WM5100_DAC_DIGITAL_VOLUME_2R,
2106         WM5100_DAC_DIGITAL_VOLUME_3L,
2107         WM5100_DAC_DIGITAL_VOLUME_3R,
2108         WM5100_DAC_DIGITAL_VOLUME_4L,
2109         WM5100_DAC_DIGITAL_VOLUME_4R,
2110         WM5100_DAC_DIGITAL_VOLUME_5L,
2111         WM5100_DAC_DIGITAL_VOLUME_5R,
2112         WM5100_DAC_DIGITAL_VOLUME_6L,
2113         WM5100_DAC_DIGITAL_VOLUME_6R,
2114 };
2115
2116 static void wm5100_set_detect_mode(struct snd_soc_codec *codec, int the_mode)
2117 {
2118         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2119         struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
2120
2121         BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
2122
2123         gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
2124         snd_soc_update_bits(codec, WM5100_ACCESSORY_DETECT_MODE_1,
2125                             WM5100_ACCDET_BIAS_SRC_MASK |
2126                             WM5100_ACCDET_SRC,
2127                             (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
2128                             mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
2129         snd_soc_update_bits(codec, WM5100_MISC_CONTROL,
2130                             WM5100_HPCOM_SRC,
2131                             mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
2132
2133         wm5100->jack_mode = the_mode;
2134
2135         dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2136                 wm5100->jack_mode);
2137 }
2138
2139 static void wm5100_micd_irq(struct snd_soc_codec *codec)
2140 {
2141         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2142         int val;
2143
2144         val = snd_soc_read(codec, WM5100_MIC_DETECT_3);
2145
2146         dev_dbg(codec->dev, "Microphone event: %x\n", val);
2147
2148         if (!(val & WM5100_ACCDET_VALID)) {
2149                 dev_warn(codec->dev, "Microphone detection state invalid\n");
2150                 return;
2151         }
2152
2153         /* No accessory, reset everything and report removal */
2154         if (!(val & WM5100_ACCDET_STS)) {
2155                 dev_dbg(codec->dev, "Jack removal detected\n");
2156                 wm5100->jack_mic = false;
2157                 wm5100->jack_detecting = true;
2158                 snd_soc_jack_report(wm5100->jack, 0,
2159                                     SND_JACK_LINEOUT | SND_JACK_HEADSET |
2160                                     SND_JACK_BTN_0);
2161
2162                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2163                                     WM5100_ACCDET_RATE_MASK,
2164                                     WM5100_ACCDET_RATE_MASK);
2165                 return;
2166         }
2167
2168         /* If the measurement is very high we've got a microphone,
2169          * either we just detected one or if we already reported then
2170          * we've got a button release event.
2171          */
2172         if (val & 0x400) {
2173                 if (wm5100->jack_detecting) {
2174                         dev_dbg(codec->dev, "Microphone detected\n");
2175                         wm5100->jack_mic = true;
2176                         snd_soc_jack_report(wm5100->jack,
2177                                             SND_JACK_HEADSET,
2178                                             SND_JACK_HEADSET | SND_JACK_BTN_0);
2179
2180                         /* Increase poll rate to give better responsiveness
2181                          * for buttons */
2182                         snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2183                                             WM5100_ACCDET_RATE_MASK,
2184                                             5 << WM5100_ACCDET_RATE_SHIFT);
2185                 } else {
2186                         dev_dbg(codec->dev, "Mic button up\n");
2187                         snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2188                 }
2189
2190                 return;
2191         }
2192
2193         /* If we detected a lower impedence during initial startup
2194          * then we probably have the wrong polarity, flip it.  Don't
2195          * do this for the lowest impedences to speed up detection of
2196          * plain headphones.
2197          */
2198         if (wm5100->jack_detecting && (val & 0x3f8)) {
2199                 wm5100_set_detect_mode(codec, !wm5100->jack_mode);
2200
2201                 return;
2202         }
2203
2204         /* Don't distinguish between buttons, just report any low
2205          * impedence as BTN_0.
2206          */
2207         if (val & 0x3fc) {
2208                 if (wm5100->jack_mic) {
2209                         dev_dbg(codec->dev, "Mic button detected\n");
2210                         snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2211                                             SND_JACK_BTN_0);
2212                 } else if (wm5100->jack_detecting) {
2213                         dev_dbg(codec->dev, "Headphone detected\n");
2214                         snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2215                                             SND_JACK_HEADPHONE);
2216
2217                         /* Increase the detection rate a bit for
2218                          * responsiveness.
2219                          */
2220                         snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2221                                             WM5100_ACCDET_RATE_MASK,
2222                                             7 << WM5100_ACCDET_RATE_SHIFT);
2223                 }
2224         }
2225 }
2226
2227 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2228 {
2229         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2230
2231         if (jack) {
2232                 wm5100->jack = jack;
2233                 wm5100->jack_detecting = true;
2234
2235                 wm5100_set_detect_mode(codec, 0);
2236
2237                 /* Slowest detection rate, gives debounce for initial
2238                  * detection */
2239                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2240                                     WM5100_ACCDET_BIAS_STARTTIME_MASK |
2241                                     WM5100_ACCDET_RATE_MASK,
2242                                     (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2243                                     WM5100_ACCDET_RATE_MASK);
2244
2245                 /* We need the charge pump to power MICBIAS */
2246                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2247                 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2248                 snd_soc_dapm_sync(&codec->dapm);
2249
2250                 /* We start off just enabling microphone detection - even a
2251                  * plain headphone will trigger detection.
2252                  */
2253                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2254                                     WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2255
2256                 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2257                                     WM5100_IM_ACCDET_EINT, 0);
2258         } else {
2259                 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2260                                     WM5100_IM_HPDET_EINT |
2261                                     WM5100_IM_ACCDET_EINT,
2262                                     WM5100_IM_HPDET_EINT |
2263                                     WM5100_IM_ACCDET_EINT);
2264                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2265                                     WM5100_ACCDET_ENA, 0);
2266                 wm5100->jack = NULL;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static irqreturn_t wm5100_irq(int irq, void *data)
2273 {
2274         struct snd_soc_codec *codec = data;
2275         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2276         irqreturn_t status = IRQ_NONE;
2277         int irq_val;
2278
2279         irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3);
2280         if (irq_val < 0) {
2281                 dev_err(codec->dev, "Failed to read IRQ status 3: %d\n",
2282                         irq_val);
2283                 irq_val = 0;
2284         }
2285         irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3_MASK);
2286
2287         snd_soc_write(codec, WM5100_INTERRUPT_STATUS_3, irq_val);
2288
2289         if (irq_val)
2290                 status = IRQ_HANDLED;
2291
2292         wm5100_log_status3(codec, irq_val);
2293
2294         if (irq_val & WM5100_FLL1_LOCK_EINT) {
2295                 dev_dbg(codec->dev, "FLL1 locked\n");
2296                 complete(&wm5100->fll[0].lock);
2297         }
2298         if (irq_val & WM5100_FLL2_LOCK_EINT) {
2299                 dev_dbg(codec->dev, "FLL2 locked\n");
2300                 complete(&wm5100->fll[1].lock);
2301         }
2302
2303         if (irq_val & WM5100_ACCDET_EINT)
2304                 wm5100_micd_irq(codec);
2305
2306         irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4);
2307         if (irq_val < 0) {
2308                 dev_err(codec->dev, "Failed to read IRQ status 4: %d\n",
2309                         irq_val);
2310                 irq_val = 0;
2311         }
2312         irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4_MASK);
2313
2314         if (irq_val)
2315                 status = IRQ_HANDLED;
2316
2317         snd_soc_write(codec, WM5100_INTERRUPT_STATUS_4, irq_val);
2318
2319         wm5100_log_status4(codec, irq_val);
2320
2321         return status;
2322 }
2323
2324 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2325 {
2326         irqreturn_t ret = IRQ_NONE;
2327         irqreturn_t val;
2328
2329         do {
2330                 val = wm5100_irq(irq, data);
2331                 if (val != IRQ_NONE)
2332                         ret = val;
2333         } while (val != IRQ_NONE);
2334
2335         return ret;
2336 }
2337
2338 #ifdef CONFIG_GPIOLIB
2339 static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2340 {
2341         return container_of(chip, struct wm5100_priv, gpio_chip);
2342 }
2343
2344 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2345 {
2346         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2347         struct snd_soc_codec *codec = wm5100->codec;
2348
2349         snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2350                             WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2351 }
2352
2353 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2354                                      unsigned offset, int value)
2355 {
2356         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2357         struct snd_soc_codec *codec = wm5100->codec;
2358         int val, ret;
2359
2360         val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2361
2362         ret = snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2363                                   WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2364                                   WM5100_GP1_LVL, val);
2365         if (ret < 0)
2366                 return ret;
2367         else
2368                 return 0;
2369 }
2370
2371 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2372 {
2373         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2374         struct snd_soc_codec *codec = wm5100->codec;
2375         int ret;
2376
2377         ret = snd_soc_read(codec, WM5100_GPIO_CTRL_1 + offset);
2378         if (ret < 0)
2379                 return ret;
2380
2381         return (ret & WM5100_GP1_LVL) != 0;
2382 }
2383
2384 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2385 {
2386         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2387         struct snd_soc_codec *codec = wm5100->codec;
2388
2389         return snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2390                                    WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2391                                    (1 << WM5100_GP1_FN_SHIFT) |
2392                                    (1 << WM5100_GP1_DIR_SHIFT));
2393 }
2394
2395 static struct gpio_chip wm5100_template_chip = {
2396         .label                  = "wm5100",
2397         .owner                  = THIS_MODULE,
2398         .direction_output       = wm5100_gpio_direction_out,
2399         .set                    = wm5100_gpio_set,
2400         .direction_input        = wm5100_gpio_direction_in,
2401         .get                    = wm5100_gpio_get,
2402         .can_sleep              = 1,
2403 };
2404
2405 static void wm5100_init_gpio(struct snd_soc_codec *codec)
2406 {
2407         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2408         int ret;
2409
2410         wm5100->gpio_chip = wm5100_template_chip;
2411         wm5100->gpio_chip.ngpio = 6;
2412         wm5100->gpio_chip.dev = codec->dev;
2413
2414         if (wm5100->pdata.gpio_base)
2415                 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2416         else
2417                 wm5100->gpio_chip.base = -1;
2418
2419         ret = gpiochip_add(&wm5100->gpio_chip);
2420         if (ret != 0)
2421                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2422 }
2423
2424 static void wm5100_free_gpio(struct snd_soc_codec *codec)
2425 {
2426         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2427         int ret;
2428
2429         ret = gpiochip_remove(&wm5100->gpio_chip);
2430         if (ret != 0)
2431                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2432 }
2433 #else
2434 static void wm5100_init_gpio(struct snd_soc_codec *codec)
2435 {
2436 }
2437
2438 static void wm5100_free_gpio(struct snd_soc_codec *codec)
2439 {
2440 }
2441 #endif
2442
2443 static int wm5100_probe(struct snd_soc_codec *codec)
2444 {
2445         struct i2c_client *i2c = to_i2c_client(codec->dev);
2446         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2447         int ret, i, irq_flags;
2448
2449         wm5100->codec = codec;
2450
2451         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2452         if (ret != 0) {
2453                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2454                 return ret;
2455         }
2456
2457         for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2458                 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2459
2460         ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm5100->core_supplies),
2461                                  wm5100->core_supplies);
2462         if (ret != 0) {
2463                 dev_err(codec->dev, "Failed to request core supplies: %d\n",
2464                         ret);
2465                 return ret;
2466         }
2467
2468         wm5100->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2469         if (IS_ERR(wm5100->cpvdd)) {
2470                 ret = PTR_ERR(wm5100->cpvdd);
2471                 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2472                 goto err_core;
2473         }
2474
2475         wm5100->dbvdd2 = regulator_get(&i2c->dev, "DBVDD2");
2476         if (IS_ERR(wm5100->dbvdd2)) {
2477                 ret = PTR_ERR(wm5100->dbvdd2);
2478                 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2479                 goto err_cpvdd;
2480         }
2481
2482         wm5100->dbvdd3 = regulator_get(&i2c->dev, "DBVDD3");
2483         if (IS_ERR(wm5100->dbvdd3)) {
2484                 ret = PTR_ERR(wm5100->dbvdd3);
2485                 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2486                 goto err_dbvdd2;
2487         }
2488
2489         ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2490                                     wm5100->core_supplies);
2491         if (ret != 0) {
2492                 dev_err(codec->dev, "Failed to enable core supplies: %d\n",
2493                         ret);
2494                 goto err_dbvdd3;
2495         }
2496
2497         if (wm5100->pdata.ldo_ena) {
2498                 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2499                                        GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2500                 if (ret < 0) {
2501                         dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2502                                 wm5100->pdata.ldo_ena, ret);
2503                         goto err_enable;
2504                 }
2505                 msleep(2);
2506         }
2507
2508         if (wm5100->pdata.reset) {
2509                 ret = gpio_request_one(wm5100->pdata.reset,
2510                                        GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2511                 if (ret < 0) {
2512                         dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2513                                 wm5100->pdata.reset, ret);
2514                         goto err_ldo;
2515                 }
2516         }
2517
2518         ret = snd_soc_read(codec, WM5100_SOFTWARE_RESET);
2519         if (ret < 0) {
2520                 dev_err(codec->dev, "Failed to read ID register\n");
2521                 goto err_reset;
2522         }
2523         switch (ret) {
2524         case 0x8997:
2525         case 0x5100:
2526                 break;
2527
2528         default:
2529                 dev_err(codec->dev, "Device is not a WM5100, ID is %x\n", ret);
2530                 ret = -EINVAL;
2531                 goto err_reset;
2532         }
2533
2534         ret = snd_soc_read(codec, WM5100_DEVICE_REVISION);
2535         if (ret < 0) {
2536                 dev_err(codec->dev, "Failed to read revision register\n");
2537                 goto err_reset;
2538         }
2539         wm5100->rev = ret & WM5100_DEVICE_REVISION_MASK;
2540
2541         dev_info(codec->dev, "revision %c\n", wm5100->rev + 'A');
2542
2543         ret = wm5100_reset(codec);
2544         if (ret < 0) {
2545                 dev_err(codec->dev, "Failed to issue reset\n");
2546                 goto err_reset;
2547         }
2548
2549         codec->cache_only = true;
2550
2551         wm5100_init_gpio(codec);
2552
2553         for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2554                 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2555                                     WM5100_OUT_VU);
2556
2557         for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2558                 snd_soc_update_bits(codec, WM5100_IN1L_CONTROL,
2559                                     WM5100_IN1_MODE_MASK |
2560                                     WM5100_IN1_DMIC_SUP_MASK,
2561                                     (wm5100->pdata.in_mode[i] <<
2562                                      WM5100_IN1_MODE_SHIFT) |
2563                                     (wm5100->pdata.dmic_sup[i] <<
2564                                      WM5100_IN1_DMIC_SUP_SHIFT));
2565         }
2566
2567         for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2568                 if (!wm5100->pdata.gpio_defaults[i])
2569                         continue;
2570
2571                 snd_soc_write(codec, WM5100_GPIO_CTRL_1 + i,
2572                               wm5100->pdata.gpio_defaults[i]);
2573         }
2574
2575         /* Don't debounce interrupts to support use of SYSCLK only */
2576         snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2577         snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2578
2579         /* TODO: check if we're symmetric */
2580
2581         if (i2c->irq) {
2582                 if (wm5100->pdata.irq_flags)
2583                         irq_flags = wm5100->pdata.irq_flags;
2584                 else
2585                         irq_flags = IRQF_TRIGGER_LOW;
2586
2587                 irq_flags |= IRQF_ONESHOT;
2588
2589                 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2590                         ret = request_threaded_irq(i2c->irq, NULL,
2591                                                    wm5100_edge_irq,
2592                                                    irq_flags, "wm5100", codec);
2593                 else
2594                         ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2595                                                    irq_flags, "wm5100", codec);
2596
2597                 if (ret != 0) {
2598                         dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
2599                                 i2c->irq, ret);
2600                 } else {
2601                         /* Enable default interrupts */
2602                         snd_soc_update_bits(codec,
2603                                             WM5100_INTERRUPT_STATUS_3_MASK,
2604                                             WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2605                                             WM5100_IM_SPK_SHUTDOWN_EINT |
2606                                             WM5100_IM_ASRC2_LOCK_EINT |
2607                                             WM5100_IM_ASRC1_LOCK_EINT |
2608                                             WM5100_IM_FLL2_LOCK_EINT |
2609                                             WM5100_IM_FLL1_LOCK_EINT |
2610                                             WM5100_CLKGEN_ERR_EINT |
2611                                             WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2612
2613                         snd_soc_update_bits(codec,
2614                                             WM5100_INTERRUPT_STATUS_4_MASK,
2615                                             WM5100_AIF3_ERR_EINT |
2616                                             WM5100_AIF2_ERR_EINT |
2617                                             WM5100_AIF1_ERR_EINT |
2618                                             WM5100_CTRLIF_ERR_EINT |
2619                                             WM5100_ISRC2_UNDERCLOCKED_EINT |
2620                                             WM5100_ISRC1_UNDERCLOCKED_EINT |
2621                                             WM5100_FX_UNDERCLOCKED_EINT |
2622                                             WM5100_AIF3_UNDERCLOCKED_EINT |
2623                                             WM5100_AIF2_UNDERCLOCKED_EINT |
2624                                             WM5100_AIF1_UNDERCLOCKED_EINT |
2625                                             WM5100_ASRC_UNDERCLOCKED_EINT |
2626                                             WM5100_DAC_UNDERCLOCKED_EINT |
2627                                             WM5100_ADC_UNDERCLOCKED_EINT |
2628                                             WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2629                 }
2630         } else {
2631                 snd_soc_dapm_new_controls(&codec->dapm,
2632                                           wm5100_dapm_widgets_noirq,
2633                                           ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2634         }
2635
2636         if (wm5100->pdata.hp_pol) {
2637                 ret = gpio_request_one(wm5100->pdata.hp_pol,
2638                                        GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2639                 if (ret < 0) {
2640                         dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2641                                 wm5100->pdata.hp_pol, ret);
2642                         goto err_gpio;
2643                 }
2644         }
2645
2646         /* We'll get woken up again when the system has something useful
2647          * for us to do.
2648          */
2649         if (wm5100->pdata.ldo_ena)
2650                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2651         regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2652                                wm5100->core_supplies);
2653
2654         return 0;
2655
2656 err_gpio:
2657         if (i2c->irq)
2658                 free_irq(i2c->irq, codec);
2659         wm5100_free_gpio(codec);
2660 err_reset:
2661         if (wm5100->pdata.reset) {
2662                 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2663                 gpio_free(wm5100->pdata.reset);
2664         }
2665 err_ldo:
2666         if (wm5100->pdata.ldo_ena) {
2667                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2668                 gpio_free(wm5100->pdata.ldo_ena);
2669         }
2670 err_enable:
2671         regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2672                                wm5100->core_supplies);
2673 err_dbvdd3:
2674         regulator_put(wm5100->dbvdd3);
2675 err_dbvdd2:
2676         regulator_put(wm5100->dbvdd2);
2677 err_cpvdd:
2678         regulator_put(wm5100->cpvdd);
2679 err_core:
2680         regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2681                             wm5100->core_supplies);
2682
2683         return ret;
2684 }
2685
2686 static int wm5100_remove(struct snd_soc_codec *codec)
2687 {
2688         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2689         struct i2c_client *i2c = to_i2c_client(codec->dev);
2690
2691         wm5100_set_bias_level(codec, SND_SOC_BIAS_OFF);
2692         if (wm5100->pdata.hp_pol) {
2693                 gpio_free(wm5100->pdata.hp_pol);
2694         }
2695         if (i2c->irq)
2696                 free_irq(i2c->irq, codec);
2697         wm5100_free_gpio(codec);
2698         if (wm5100->pdata.reset) {
2699                 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2700                 gpio_free(wm5100->pdata.reset);
2701         }
2702         if (wm5100->pdata.ldo_ena) {
2703                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2704                 gpio_free(wm5100->pdata.ldo_ena);
2705         }
2706         regulator_put(wm5100->dbvdd3);
2707         regulator_put(wm5100->dbvdd2);
2708         regulator_put(wm5100->cpvdd);
2709         regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2710                             wm5100->core_supplies);
2711         return 0;
2712 }
2713
2714 static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2715         .probe =        wm5100_probe,
2716         .remove =       wm5100_remove,
2717
2718         .set_sysclk = wm5100_set_sysclk,
2719         .set_pll = wm5100_set_fll,
2720         .set_bias_level = wm5100_set_bias_level,
2721         .idle_bias_off = 1,
2722
2723         .seq_notifier = wm5100_seq_notifier,
2724         .controls = wm5100_snd_controls,
2725         .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2726         .dapm_widgets = wm5100_dapm_widgets,
2727         .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2728         .dapm_routes = wm5100_dapm_routes,
2729         .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2730
2731         .reg_cache_size = ARRAY_SIZE(wm5100_reg_defaults),
2732         .reg_word_size = sizeof(u16),
2733         .compress_type = SND_SOC_RBTREE_COMPRESSION,
2734         .reg_cache_default = wm5100_reg_defaults,
2735
2736         .volatile_register = wm5100_volatile_register,
2737         .readable_register = wm5100_readable_register,
2738 };
2739
2740 static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2741                                       const struct i2c_device_id *id)
2742 {
2743         struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2744         struct wm5100_priv *wm5100;
2745         int ret, i;
2746
2747         wm5100 = kzalloc(sizeof(struct wm5100_priv), GFP_KERNEL);
2748         if (wm5100 == NULL)
2749                 return -ENOMEM;
2750
2751         for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2752                 init_completion(&wm5100->fll[i].lock);
2753
2754         if (pdata)
2755                 wm5100->pdata = *pdata;
2756
2757         i2c_set_clientdata(i2c, wm5100);
2758
2759         ret = snd_soc_register_codec(&i2c->dev,
2760                                      &soc_codec_dev_wm5100, wm5100_dai,
2761                                      ARRAY_SIZE(wm5100_dai));
2762         if (ret < 0) {
2763                 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2764                 kfree(wm5100);
2765         }
2766
2767         return ret;
2768 }
2769
2770 static __devexit int wm5100_i2c_remove(struct i2c_client *client)
2771 {
2772         snd_soc_unregister_codec(&client->dev);
2773         kfree(i2c_get_clientdata(client));
2774         return 0;
2775 }
2776
2777 static const struct i2c_device_id wm5100_i2c_id[] = {
2778         { "wm5100", 0 },
2779         { }
2780 };
2781 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2782
2783 static struct i2c_driver wm5100_i2c_driver = {
2784         .driver = {
2785                 .name = "wm5100",
2786                 .owner = THIS_MODULE,
2787         },
2788         .probe =    wm5100_i2c_probe,
2789         .remove =   __devexit_p(wm5100_i2c_remove),
2790         .id_table = wm5100_i2c_id,
2791 };
2792
2793 static int __init wm5100_modinit(void)
2794 {
2795         return i2c_add_driver(&wm5100_i2c_driver);
2796 }
2797 module_init(wm5100_modinit);
2798
2799 static void __exit wm5100_exit(void)
2800 {
2801         i2c_del_driver(&wm5100_i2c_driver);
2802 }
2803 module_exit(wm5100_exit);
2804
2805 MODULE_DESCRIPTION("ASoC WM5100 driver");
2806 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2807 MODULE_LICENSE("GPL");