sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/soc-dapm.h>
  40 #include <sound/initval.h>
  41 #include <sound/tlv.h>
  42
  43 #include <sound/tlv320dac33-plat.h>
  44 #include "tlv320dac33.h"
  45
  46 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  47                                                  * 6144 stereo */
  48 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  49
  50 #define NSAMPLE_MAX             5700
  51
  52 #define MODE7_LTHR              10
  53 #define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / ((rate * 1000) / samples))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         (rate / (1000000 / (us < 1000000 ? us : 1000000)))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 enum dac33_state {
  70         DAC33_IDLE = 0,
  71         DAC33_PREFILL,
  72         DAC33_PLAYBACK,
  73         DAC33_FLUSH,
  74 };
  75
  76 enum dac33_fifo_modes {
  77         DAC33_FIFO_BYPASS = 0,
  78         DAC33_FIFO_MODE1,
  79         DAC33_FIFO_MODE7,
  80         DAC33_FIFO_LAST_MODE,
  81 };
  82
  83 #define DAC33_NUM_SUPPLIES 3
  84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  85         "AVDD",
  86         "DVDD",
  87         "IOVDD",
  88 };
  89
  90 struct tlv320dac33_priv {
  91         struct mutex mutex;
  92         struct workqueue_struct *dac33_wq;
  93         struct work_struct work;
  94         struct snd_soc_codec *codec;
  95         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  96         struct snd_pcm_substream *substream;
  97         int power_gpio;
  98         int chip_power;
  99         int irq;
 100         unsigned int refclk;
 101
 102         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 103         unsigned int nsample_min;       /* nsample should not be lower than
 104                                          * this */
 105         unsigned int nsample_max;       /* nsample should not be higher than
 106                                          * this */
 107         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 108         unsigned int nsample;           /* burst read amount from host */
 109         int mode1_latency;              /* latency caused by the i2c writes in
 110                                          * us */
 111         int auto_fifo_config;           /* Configure the FIFO based on the
 112                                          * period size */
 113         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 114         unsigned int burst_rate;        /* Interface speed in Burst modes */
 115
 116         int keep_bclk;                  /* Keep the BCLK continuously running
 117                                          * in FIFO modes */
 118         spinlock_t lock;
 119         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 120         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 121
 122         unsigned int mode1_us_burst;    /* Time to burst read n number of
 123                                          * samples */
 124         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 125
 126         unsigned int uthr;
 127
 128         enum dac33_state state;
 129         enum snd_soc_control_type control_type;
 130         void *control_data;
 131 };
 132
 133 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 148 0x00, 0x00,             /* 0x38 - 0x39 */
 149 /* Registers 0x3a - 0x3f are reserved  */
 150             0x00, 0x00, /* 0x3a - 0x3b */
 151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 152
 153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 154 0x00, 0x80,             /* 0x44 - 0x45 */
 155 /* Registers 0x46 - 0x47 are reserved  */
 156             0x80, 0x80, /* 0x46 - 0x47 */
 157
 158 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 159 /* Registers 0x4b - 0x7c are reserved  */
 160                   0x00, /* 0x4b        */
 161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 173 0x00,                   /* 0x7c        */
 174
 175       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 176 };
 177
 178 /* Register read and write */
 179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 180                                                 unsigned reg)
 181 {
 182         u8 *cache = codec->reg_cache;
 183         if (reg >= DAC33_CACHEREGNUM)
 184                 return 0;
 185
 186         return cache[reg];
 187 }
 188
 189 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 190                                          u8 reg, u8 value)
 191 {
 192         u8 *cache = codec->reg_cache;
 193         if (reg >= DAC33_CACHEREGNUM)
 194                 return;
 195
 196         cache[reg] = value;
 197 }
 198
 199 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 200                       u8 *value)
 201 {
 202         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 203         int val, ret = 0;
 204
 205         *value = reg & 0xff;
 206
 207         /* If powered off, return the cached value */
 208         if (dac33->chip_power) {
 209                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 210                 if (val < 0) {
 211                         dev_err(codec->dev, "Read failed (%d)\n", val);
 212                         value[0] = dac33_read_reg_cache(codec, reg);
 213                         ret = val;
 214                 } else {
 215                         value[0] = val;
 216                         dac33_write_reg_cache(codec, reg, val);
 217                 }
 218         } else {
 219                 value[0] = dac33_read_reg_cache(codec, reg);
 220         }
 221
 222         return ret;
 223 }
 224
 225 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 226                        unsigned int value)
 227 {
 228         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 229         u8 data[2];
 230         int ret = 0;
 231
 232         /*
 233          * data is
 234          *   D15..D8 dac33 register offset
 235          *   D7...D0 register data
 236          */
 237         data[0] = reg & 0xff;
 238         data[1] = value & 0xff;
 239
 240         dac33_write_reg_cache(codec, data[0], data[1]);
 241         if (dac33->chip_power) {
 242                 ret = codec->hw_write(codec->control_data, data, 2);
 243                 if (ret != 2)
 244                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 245                 else
 246                         ret = 0;
 247         }
 248
 249         return ret;
 250 }
 251
 252 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 253                        unsigned int value)
 254 {
 255         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 256         int ret;
 257
 258         mutex_lock(&dac33->mutex);
 259         ret = dac33_write(codec, reg, value);
 260         mutex_unlock(&dac33->mutex);
 261
 262         return ret;
 263 }
 264
 265 #define DAC33_I2C_ADDR_AUTOINC  0x80
 266 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 267                        unsigned int value)
 268 {
 269         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 270         u8 data[3];
 271         int ret = 0;
 272
 273         /*
 274          * data is
 275          *   D23..D16 dac33 register offset
 276          *   D15..D8  register data MSB
 277          *   D7...D0  register data LSB
 278          */
 279         data[0] = reg & 0xff;
 280         data[1] = (value >> 8) & 0xff;
 281         data[2] = value & 0xff;
 282
 283         dac33_write_reg_cache(codec, data[0], data[1]);
 284         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 285
 286         if (dac33->chip_power) {
 287                 /* We need to set autoincrement mode for 16 bit writes */
 288                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 289                 ret = codec->hw_write(codec->control_data, data, 3);
 290                 if (ret != 3)
 291                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 292                 else
 293                         ret = 0;
 294         }
 295
 296         return ret;
 297 }
 298
 299 static void dac33_init_chip(struct snd_soc_codec *codec)
 300 {
 301         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 302
 303         if (unlikely(!dac33->chip_power))
 304                 return;
 305
 306         /* 44-46: DAC Control Registers */
 307         /* A : DAC sample rate Fsref/1.5 */
 308         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 309         /* B : DAC src=normal, not muted */
 310         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 311                                              DAC33_DACSRCL_LEFT);
 312         /* C : (defaults) */
 313         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 314
 315         /* 73 : volume soft stepping control,
 316          clock source = internal osc (?) */
 317         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 318
 319         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
 320
 321         /* Restore only selected registers (gains mostly) */
 322         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 323                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 324         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 325                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 326
 327         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 328                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 329         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 330                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 331 }
 332
 333 static inline int dac33_read_id(struct snd_soc_codec *codec)
 334 {
 335         int i, ret = 0;
 336         u8 reg;
 337
 338         for (i = 0; i < 3; i++) {
 339                 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
 340                 if (ret < 0)
 341                         break;
 342         }
 343
 344         return ret;
 345 }
 346
 347 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 348 {
 349         u8 reg;
 350
 351         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 352         if (power)
 353                 reg |= DAC33_PDNALLB;
 354         else
 355                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 356                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 357         dac33_write(codec, DAC33_PWR_CTRL, reg);
 358 }
 359
 360 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 361 {
 362         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 363         int ret = 0;
 364
 365         mutex_lock(&dac33->mutex);
 366
 367         /* Safety check */
 368         if (unlikely(power == dac33->chip_power)) {
 369                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 370                         power ? "ON" : "OFF");
 371                 goto exit;
 372         }
 373
 374         if (power) {
 375                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 376                                           dac33->supplies);
 377                 if (ret != 0) {
 378                         dev_err(codec->dev,
 379                                 "Failed to enable supplies: %d\n", ret);
 380                                 goto exit;
 381                 }
 382
 383                 if (dac33->power_gpio >= 0)
 384                         gpio_set_value(dac33->power_gpio, 1);
 385
 386                 dac33->chip_power = 1;
 387         } else {
 388                 dac33_soft_power(codec, 0);
 389                 if (dac33->power_gpio >= 0)
 390                         gpio_set_value(dac33->power_gpio, 0);
 391
 392                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 393                                              dac33->supplies);
 394                 if (ret != 0) {
 395                         dev_err(codec->dev,
 396                                 "Failed to disable supplies: %d\n", ret);
 397                         goto exit;
 398                 }
 399
 400                 dac33->chip_power = 0;
 401         }
 402
 403 exit:
 404         mutex_unlock(&dac33->mutex);
 405         return ret;
 406 }
 407
 408 static int playback_event(struct snd_soc_dapm_widget *w,
 409                 struct snd_kcontrol *kcontrol, int event)
 410 {
 411         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 412
 413         switch (event) {
 414         case SND_SOC_DAPM_PRE_PMU:
 415                 if (likely(dac33->substream)) {
 416                         dac33_calculate_times(dac33->substream);
 417                         dac33_prepare_chip(dac33->substream);
 418                 }
 419                 break;
 420         }
 421         return 0;
 422 }
 423
 424 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 425                          struct snd_ctl_elem_value *ucontrol)
 426 {
 427         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 428         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 429
 430         ucontrol->value.integer.value[0] = dac33->nsample;
 431
 432         return 0;
 433 }
 434
 435 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 436                          struct snd_ctl_elem_value *ucontrol)
 437 {
 438         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 439         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 440         int ret = 0;
 441
 442         if (dac33->nsample == ucontrol->value.integer.value[0])
 443                 return 0;
 444
 445         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 446             ucontrol->value.integer.value[0] > dac33->nsample_max) {
 447                 ret = -EINVAL;
 448         } else {
 449                 dac33->nsample = ucontrol->value.integer.value[0];
 450                 /* Re calculate the burst time */
 451                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
 452                                                       dac33->nsample);
 453         }
 454
 455         return ret;
 456 }
 457
 458 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
 459                          struct snd_ctl_elem_value *ucontrol)
 460 {
 461         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 462         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 463
 464         ucontrol->value.integer.value[0] = dac33->uthr;
 465
 466         return 0;
 467 }
 468
 469 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
 470                          struct snd_ctl_elem_value *ucontrol)
 471 {
 472         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 473         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 474         int ret = 0;
 475
 476         if (dac33->substream)
 477                 return -EBUSY;
 478
 479         if (dac33->uthr == ucontrol->value.integer.value[0])
 480                 return 0;
 481
 482         if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
 483             ucontrol->value.integer.value[0] > MODE7_UTHR)
 484                 ret = -EINVAL;
 485         else
 486                 dac33->uthr = ucontrol->value.integer.value[0];
 487
 488         return ret;
 489 }
 490
 491 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 492                          struct snd_ctl_elem_value *ucontrol)
 493 {
 494         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 495         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 496
 497         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 498
 499         return 0;
 500 }
 501
 502 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 503                          struct snd_ctl_elem_value *ucontrol)
 504 {
 505         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 506         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 507         int ret = 0;
 508
 509         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 510                 return 0;
 511         /* Do not allow changes while stream is running*/
 512         if (codec->active)
 513                 return -EPERM;
 514
 515         if (ucontrol->value.integer.value[0] < 0 ||
 516             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 517                 ret = -EINVAL;
 518         else
 519                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 520
 521         return ret;
 522 }
 523
 524 /* Codec operation modes */
 525 static const char *dac33_fifo_mode_texts[] = {
 526         "Bypass", "Mode 1", "Mode 7"
 527 };
 528
 529 static const struct soc_enum dac33_fifo_mode_enum =
 530         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 531                             dac33_fifo_mode_texts);
 532
 533 /* L/R Line Output Gain */
 534 static const char *lr_lineout_gain_texts[] = {
 535         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 536         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 537 };
 538
 539 static const struct soc_enum l_lineout_gain_enum =
 540         SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
 541                         ARRAY_SIZE(lr_lineout_gain_texts),
 542                         lr_lineout_gain_texts);
 543
 544 static const struct soc_enum r_lineout_gain_enum =
 545         SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
 546                         ARRAY_SIZE(lr_lineout_gain_texts),
 547                         lr_lineout_gain_texts);
 548
 549 /*
 550  * DACL/R digital volume control:
 551  * from 0 dB to -63.5 in 0.5 dB steps
 552  * Need to be inverted later on:
 553  * 0x00 == 0 dB
 554  * 0x7f == -63.5 dB
 555  */
 556 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 557
 558 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 559         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 560                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 561                 0, 0x7f, 1, dac_digivol_tlv),
 562         SOC_DOUBLE_R("DAC Digital Playback Switch",
 563                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 564         SOC_DOUBLE_R("Line to Line Out Volume",
 565                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 566         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 567         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 568 };
 569
 570 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 571         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 572                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 573 };
 574
 575 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
 576         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 577                 dac33_get_nsample, dac33_set_nsample),
 578         SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
 579                  dac33_get_uthr, dac33_set_uthr),
 580 };
 581
 582 /* Analog bypass */
 583 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 584         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 585
 586 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 587         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 588
 589 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 590         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 591         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 592
 593         SND_SOC_DAPM_INPUT("LINEL"),
 594         SND_SOC_DAPM_INPUT("LINER"),
 595
 596         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
 597         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
 598
 599         /* Analog bypass */
 600         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 601                                 &dac33_dapm_abypassl_control),
 602         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 603                                 &dac33_dapm_abypassr_control),
 604
 605         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
 606                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 607         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
 608                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 609
 610         SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
 611 };
 612
 613 static const struct snd_soc_dapm_route audio_map[] = {
 614         /* Analog bypass */
 615         {"Analog Left Bypass", "Switch", "LINEL"},
 616         {"Analog Right Bypass", "Switch", "LINER"},
 617
 618         {"Output Left Amp Power", NULL, "DACL"},
 619         {"Output Right Amp Power", NULL, "DACR"},
 620
 621         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
 622         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
 623
 624         /* output */
 625         {"LEFT_LO", NULL, "Output Left Amp Power"},
 626         {"RIGHT_LO", NULL, "Output Right Amp Power"},
 627 };
 628
 629 static int dac33_add_widgets(struct snd_soc_codec *codec)
 630 {
 631         struct snd_soc_dapm_context *dapm = &codec->dapm;
 632
 633         snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
 634                                   ARRAY_SIZE(dac33_dapm_widgets));
 635         /* set up audio path interconnects */
 636         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 637
 638         return 0;
 639 }
 640
 641 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 642                                 enum snd_soc_bias_level level)
 643 {
 644         int ret;
 645
 646         switch (level) {
 647         case SND_SOC_BIAS_ON:
 648                 dac33_soft_power(codec, 1);
 649                 break;
 650         case SND_SOC_BIAS_PREPARE:
 651                 break;
 652         case SND_SOC_BIAS_STANDBY:
 653                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 654                         /* Coming from OFF, switch on the codec */
 655                         ret = dac33_hard_power(codec, 1);
 656                         if (ret != 0)
 657                                 return ret;
 658
 659                         dac33_init_chip(codec);
 660                 }
 661                 break;
 662         case SND_SOC_BIAS_OFF:
 663                 /* Do not power off, when the codec is already off */
 664                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
 665                         return 0;
 666                 ret = dac33_hard_power(codec, 0);
 667                 if (ret != 0)
 668                         return ret;
 669                 break;
 670         }
 671         codec->dapm.bias_level = level;
 672
 673         return 0;
 674 }
 675
 676 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 677 {
 678         struct snd_soc_codec *codec = dac33->codec;
 679         unsigned int delay;
 680
 681         switch (dac33->fifo_mode) {
 682         case DAC33_FIFO_MODE1:
 683                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 684                         DAC33_THRREG(dac33->nsample));
 685
 686                 /* Take the timestamps */
 687                 spin_lock_irq(&dac33->lock);
 688                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 689                 dac33->t_stamp1 = dac33->t_stamp2;
 690                 spin_unlock_irq(&dac33->lock);
 691
 692                 dac33_write16(codec, DAC33_PREFILL_MSB,
 693                                 DAC33_THRREG(dac33->alarm_threshold));
 694                 /* Enable Alarm Threshold IRQ with a delay */
 695                 delay = SAMPLES_TO_US(dac33->burst_rate,
 696                                      dac33->alarm_threshold) + 1000;
 697                 usleep_range(delay, delay + 500);
 698                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 699                 break;
 700         case DAC33_FIFO_MODE7:
 701                 /* Take the timestamp */
 702                 spin_lock_irq(&dac33->lock);
 703                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 704                 /* Move back the timestamp with drain time */
 705                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 706                 spin_unlock_irq(&dac33->lock);
 707
 708                 dac33_write16(codec, DAC33_PREFILL_MSB,
 709                                 DAC33_THRREG(MODE7_LTHR));
 710
 711                 /* Enable Upper Threshold IRQ */
 712                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 713                 break;
 714         default:
 715                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 716                                                         dac33->fifo_mode);
 717                 break;
 718         }
 719 }
 720
 721 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 722 {
 723         struct snd_soc_codec *codec = dac33->codec;
 724
 725         switch (dac33->fifo_mode) {
 726         case DAC33_FIFO_MODE1:
 727                 /* Take the timestamp */
 728                 spin_lock_irq(&dac33->lock);
 729                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 730                 spin_unlock_irq(&dac33->lock);
 731
 732                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 733                                 DAC33_THRREG(dac33->nsample));
 734                 break;
 735         case DAC33_FIFO_MODE7:
 736                 /* At the moment we are not using interrupts in mode7 */
 737                 break;
 738         default:
 739                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 740                                                         dac33->fifo_mode);
 741                 break;
 742         }
 743 }
 744
 745 static void dac33_work(struct work_struct *work)
 746 {
 747         struct snd_soc_codec *codec;
 748         struct tlv320dac33_priv *dac33;
 749         u8 reg;
 750
 751         dac33 = container_of(work, struct tlv320dac33_priv, work);
 752         codec = dac33->codec;
 753
 754         mutex_lock(&dac33->mutex);
 755         switch (dac33->state) {
 756         case DAC33_PREFILL:
 757                 dac33->state = DAC33_PLAYBACK;
 758                 dac33_prefill_handler(dac33);
 759                 break;
 760         case DAC33_PLAYBACK:
 761                 dac33_playback_handler(dac33);
 762                 break;
 763         case DAC33_IDLE:
 764                 break;
 765         case DAC33_FLUSH:
 766                 dac33->state = DAC33_IDLE;
 767                 /* Mask all interrupts from dac33 */
 768                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 769
 770                 /* flush fifo */
 771                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 772                 reg |= DAC33_FIFOFLUSH;
 773                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 774                 break;
 775         }
 776         mutex_unlock(&dac33->mutex);
 777 }
 778
 779 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 780 {
 781         struct snd_soc_codec *codec = dev;
 782         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 783
 784         spin_lock(&dac33->lock);
 785         dac33->t_stamp1 = ktime_to_us(ktime_get());
 786         spin_unlock(&dac33->lock);
 787
 788         /* Do not schedule the workqueue in Mode7 */
 789         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 790                 queue_work(dac33->dac33_wq, &dac33->work);
 791
 792         return IRQ_HANDLED;
 793 }
 794
 795 static void dac33_oscwait(struct snd_soc_codec *codec)
 796 {
 797         int timeout = 60;
 798         u8 reg;
 799
 800         do {
 801                 usleep_range(1000, 2000);
 802                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 803         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 804         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 805                 dev_err(codec->dev,
 806                         "internal oscillator calibration failed\n");
 807 }
 808
 809 static int dac33_startup(struct snd_pcm_substream *substream,
 810                            struct snd_soc_dai *dai)
 811 {
 812         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 813         struct snd_soc_codec *codec = rtd->codec;
 814         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 815
 816         /* Stream started, save the substream pointer */
 817         dac33->substream = substream;
 818
 819         return 0;
 820 }
 821
 822 static void dac33_shutdown(struct snd_pcm_substream *substream,
 823                              struct snd_soc_dai *dai)
 824 {
 825         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 826         struct snd_soc_codec *codec = rtd->codec;
 827         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 828
 829         dac33->substream = NULL;
 830
 831         /* Reset the nSample restrictions */
 832         dac33->nsample_min = 0;
 833         dac33->nsample_max = NSAMPLE_MAX;
 834 }
 835
 836 static int dac33_hw_params(struct snd_pcm_substream *substream,
 837                            struct snd_pcm_hw_params *params,
 838                            struct snd_soc_dai *dai)
 839 {
 840         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 841         struct snd_soc_codec *codec = rtd->codec;
 842
 843         /* Check parameters for validity */
 844         switch (params_rate(params)) {
 845         case 44100:
 846         case 48000:
 847                 break;
 848         default:
 849                 dev_err(codec->dev, "unsupported rate %d\n",
 850                         params_rate(params));
 851                 return -EINVAL;
 852         }
 853
 854         switch (params_format(params)) {
 855         case SNDRV_PCM_FORMAT_S16_LE:
 856                 break;
 857         default:
 858                 dev_err(codec->dev, "unsupported format %d\n",
 859                         params_format(params));
 860                 return -EINVAL;
 861         }
 862
 863         return 0;
 864 }
 865
 866 #define CALC_OSCSET(rate, refclk) ( \
 867         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 868 #define CALC_RATIOSET(rate, refclk) ( \
 869         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 870
 871 /*
 872  * tlv320dac33 is strict on the sequence of the register writes, if the register
 873  * writes happens in different order, than dac33 might end up in unknown state.
 874  * Use the known, working sequence of register writes to initialize the dac33.
 875  */
 876 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 877 {
 878         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 879         struct snd_soc_codec *codec = rtd->codec;
 880         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 881         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 882         u8 aictrl_a, aictrl_b, fifoctrl_a;
 883
 884         switch (substream->runtime->rate) {
 885         case 44100:
 886         case 48000:
 887                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 888                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 889                                          dac33->refclk);
 890                 break;
 891         default:
 892                 dev_err(codec->dev, "unsupported rate %d\n",
 893                         substream->runtime->rate);
 894                 return -EINVAL;
 895         }
 896
 897
 898         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 899         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 900         /* Read FIFO control A, and clear FIFO flush bit */
 901         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 902         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 903
 904         fifoctrl_a &= ~DAC33_WIDTH;
 905         switch (substream->runtime->format) {
 906         case SNDRV_PCM_FORMAT_S16_LE:
 907                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 908                 fifoctrl_a |= DAC33_WIDTH;
 909                 break;
 910         default:
 911                 dev_err(codec->dev, "unsupported format %d\n",
 912                         substream->runtime->format);
 913                 return -EINVAL;
 914         }
 915
 916         mutex_lock(&dac33->mutex);
 917
 918         if (!dac33->chip_power) {
 919                 /*
 920                  * Chip is not powered yet.
 921                  * Do the init in the dac33_set_bias_level later.
 922                  */
 923                 mutex_unlock(&dac33->mutex);
 924                 return 0;
 925         }
 926
 927         dac33_soft_power(codec, 0);
 928         dac33_soft_power(codec, 1);
 929
 930         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 931         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 932
 933         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 934         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 935
 936         /* calib time: 128 is a nice number ;) */
 937         dac33_write(codec, DAC33_CALIB_TIME, 128);
 938
 939         /* adjustment treshold & step */
 940         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 941                                                  DAC33_ADJSTEP(1));
 942
 943         /* div=4 / gain=1 / div */
 944         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 945
 946         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 947         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 948         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 949
 950         dac33_oscwait(codec);
 951
 952         if (dac33->fifo_mode) {
 953                 /* Generic for all FIFO modes */
 954                 /* 50-51 : ASRC Control registers */
 955                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 956                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 957
 958                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 959                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 960
 961                 /* Set interrupts to high active */
 962                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 963         } else {
 964                 /* FIFO bypass mode */
 965                 /* 50-51 : ASRC Control registers */
 966                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 967                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 968         }
 969
 970         /* Interrupt behaviour configuration */
 971         switch (dac33->fifo_mode) {
 972         case DAC33_FIFO_MODE1:
 973                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 974                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 975                 break;
 976         case DAC33_FIFO_MODE7:
 977                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 978                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 979                 break;
 980         default:
 981                 /* in FIFO bypass mode, the interrupts are not used */
 982                 break;
 983         }
 984
 985         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 986
 987         switch (dac33->fifo_mode) {
 988         case DAC33_FIFO_MODE1:
 989                 /*
 990                  * For mode1:
 991                  * Disable the FIFO bypass (Enable the use of FIFO)
 992                  * Select nSample mode
 993                  * BCLK is only running when data is needed by DAC33
 994                  */
 995                 fifoctrl_a &= ~DAC33_FBYPAS;
 996                 fifoctrl_a &= ~DAC33_FAUTO;
 997                 if (dac33->keep_bclk)
 998                         aictrl_b |= DAC33_BCLKON;
 999                 else
1000                         aictrl_b &= ~DAC33_BCLKON;
1001                 break;
1002         case DAC33_FIFO_MODE7:
1003                 /*
1004                  * For mode1:
1005                  * Disable the FIFO bypass (Enable the use of FIFO)
1006                  * Select Threshold mode
1007                  * BCLK is only running when data is needed by DAC33
1008                  */
1009                 fifoctrl_a &= ~DAC33_FBYPAS;
1010                 fifoctrl_a |= DAC33_FAUTO;
1011                 if (dac33->keep_bclk)
1012                         aictrl_b |= DAC33_BCLKON;
1013                 else
1014                         aictrl_b &= ~DAC33_BCLKON;
1015                 break;
1016         default:
1017                 /*
1018                  * For FIFO bypass mode:
1019                  * Enable the FIFO bypass (Disable the FIFO use)
1020                  * Set the BCLK as continous
1021                  */
1022                 fifoctrl_a |= DAC33_FBYPAS;
1023                 aictrl_b |= DAC33_BCLKON;
1024                 break;
1025         }
1026
1027         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1028         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1029         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1030
1031         /*
1032          * BCLK divide ratio
1033          * 0: 1.5
1034          * 1: 1
1035          * 2: 2
1036          * ...
1037          * 254: 254
1038          * 255: 255
1039          */
1040         if (dac33->fifo_mode)
1041                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1042                                                         dac33->burst_bclkdiv);
1043         else
1044                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1045
1046         switch (dac33->fifo_mode) {
1047         case DAC33_FIFO_MODE1:
1048                 dac33_write16(codec, DAC33_ATHR_MSB,
1049                               DAC33_THRREG(dac33->alarm_threshold));
1050                 break;
1051         case DAC33_FIFO_MODE7:
1052                 /*
1053                  * Configure the threshold levels, and leave 10 sample space
1054                  * at the bottom, and also at the top of the FIFO
1055                  */
1056                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1057                 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1058                 break;
1059         default:
1060                 break;
1061         }
1062
1063         mutex_unlock(&dac33->mutex);
1064
1065         return 0;
1066 }
1067
1068 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1069 {
1070         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1071         struct snd_soc_codec *codec = rtd->codec;
1072         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1073         unsigned int period_size = substream->runtime->period_size;
1074         unsigned int rate = substream->runtime->rate;
1075         unsigned int nsample_limit;
1076
1077         /* In bypass mode we don't need to calculate */
1078         if (!dac33->fifo_mode)
1079                 return;
1080
1081         switch (dac33->fifo_mode) {
1082         case DAC33_FIFO_MODE1:
1083                 /* Number of samples under i2c latency */
1084                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1085                                                 dac33->mode1_latency);
1086                 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1087                                 dac33->alarm_threshold;
1088
1089                 if (dac33->auto_fifo_config) {
1090                         if (period_size <= dac33->alarm_threshold)
1091                                 /*
1092                                  * Configure nSamaple to number of periods,
1093                                  * which covers the latency requironment.
1094                                  */
1095                                 dac33->nsample = period_size *
1096                                        ((dac33->alarm_threshold / period_size) +
1097                                        (dac33->alarm_threshold % period_size ?
1098                                        1 : 0));
1099                         else if (period_size > nsample_limit)
1100                                 dac33->nsample = nsample_limit;
1101                         else
1102                                 dac33->nsample = period_size;
1103                 } else {
1104                         /* nSample time shall not be shorter than i2c latency */
1105                         dac33->nsample_min = dac33->alarm_threshold;
1106                         /*
1107                          * nSample should not be bigger than alsa buffer minus
1108                          * size of one period to avoid overruns
1109                          */
1110                         dac33->nsample_max = substream->runtime->buffer_size -
1111                                                 period_size;
1112
1113                         if (dac33->nsample_max > nsample_limit)
1114                                 dac33->nsample_max = nsample_limit;
1115
1116                         /* Correct the nSample if it is outside of the ranges */
1117                         if (dac33->nsample < dac33->nsample_min)
1118                                 dac33->nsample = dac33->nsample_min;
1119                         if (dac33->nsample > dac33->nsample_max)
1120                                 dac33->nsample = dac33->nsample_max;
1121                 }
1122
1123                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1124                                                       dac33->nsample);
1125                 dac33->t_stamp1 = 0;
1126                 dac33->t_stamp2 = 0;
1127                 break;
1128         case DAC33_FIFO_MODE7:
1129                 if (dac33->auto_fifo_config) {
1130                         dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1131                                         period_size,
1132                                         rate,
1133                                         dac33->burst_rate) + 9;
1134                         if (dac33->uthr > MODE7_UTHR)
1135                                 dac33->uthr = MODE7_UTHR;
1136                         if (dac33->uthr < (MODE7_LTHR + 10))
1137                                 dac33->uthr = (MODE7_LTHR + 10);
1138                 }
1139                 dac33->mode7_us_to_lthr =
1140                                 SAMPLES_TO_US(substream->runtime->rate,
1141                                         dac33->uthr - MODE7_LTHR + 1);
1142                 dac33->t_stamp1 = 0;
1143                 break;
1144         default:
1145                 break;
1146         }
1147
1148 }
1149
1150 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1151                              struct snd_soc_dai *dai)
1152 {
1153         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1154         struct snd_soc_codec *codec = rtd->codec;
1155         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1156         int ret = 0;
1157
1158         switch (cmd) {
1159         case SNDRV_PCM_TRIGGER_START:
1160         case SNDRV_PCM_TRIGGER_RESUME:
1161         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1162                 if (dac33->fifo_mode) {
1163                         dac33->state = DAC33_PREFILL;
1164                         queue_work(dac33->dac33_wq, &dac33->work);
1165                 }
1166                 break;
1167         case SNDRV_PCM_TRIGGER_STOP:
1168         case SNDRV_PCM_TRIGGER_SUSPEND:
1169         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1170                 if (dac33->fifo_mode) {
1171                         dac33->state = DAC33_FLUSH;
1172                         queue_work(dac33->dac33_wq, &dac33->work);
1173                 }
1174                 break;
1175         default:
1176                 ret = -EINVAL;
1177         }
1178
1179         return ret;
1180 }
1181
1182 static snd_pcm_sframes_t dac33_dai_delay(
1183                         struct snd_pcm_substream *substream,
1184                         struct snd_soc_dai *dai)
1185 {
1186         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1187         struct snd_soc_codec *codec = rtd->codec;
1188         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1189         unsigned long long t0, t1, t_now;
1190         unsigned int time_delta, uthr;
1191         int samples_out, samples_in, samples;
1192         snd_pcm_sframes_t delay = 0;
1193
1194         switch (dac33->fifo_mode) {
1195         case DAC33_FIFO_BYPASS:
1196                 break;
1197         case DAC33_FIFO_MODE1:
1198                 spin_lock(&dac33->lock);
1199                 t0 = dac33->t_stamp1;
1200                 t1 = dac33->t_stamp2;
1201                 spin_unlock(&dac33->lock);
1202                 t_now = ktime_to_us(ktime_get());
1203
1204                 /* We have not started to fill the FIFO yet, delay is 0 */
1205                 if (!t1)
1206                         goto out;
1207
1208                 if (t0 > t1) {
1209                         /*
1210                          * Phase 1:
1211                          * After Alarm threshold, and before nSample write
1212                          */
1213                         time_delta = t_now - t0;
1214                         samples_out = time_delta ? US_TO_SAMPLES(
1215                                                 substream->runtime->rate,
1216                                                 time_delta) : 0;
1217
1218                         if (likely(dac33->alarm_threshold > samples_out))
1219                                 delay = dac33->alarm_threshold - samples_out;
1220                         else
1221                                 delay = 0;
1222                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1223                         /*
1224                          * Phase 2:
1225                          * After nSample write (during burst operation)
1226                          */
1227                         time_delta = t_now - t0;
1228                         samples_out = time_delta ? US_TO_SAMPLES(
1229                                                 substream->runtime->rate,
1230                                                 time_delta) : 0;
1231
1232                         time_delta = t_now - t1;
1233                         samples_in = time_delta ? US_TO_SAMPLES(
1234                                                 dac33->burst_rate,
1235                                                 time_delta) : 0;
1236
1237                         samples = dac33->alarm_threshold;
1238                         samples += (samples_in - samples_out);
1239
1240                         if (likely(samples > 0))
1241                                 delay = samples;
1242                         else
1243                                 delay = 0;
1244                 } else {
1245                         /*
1246                          * Phase 3:
1247                          * After burst operation, before next alarm threshold
1248                          */
1249                         time_delta = t_now - t0;
1250                         samples_out = time_delta ? US_TO_SAMPLES(
1251                                                 substream->runtime->rate,
1252                                                 time_delta) : 0;
1253
1254                         samples_in = dac33->nsample;
1255                         samples = dac33->alarm_threshold;
1256                         samples += (samples_in - samples_out);
1257
1258                         if (likely(samples > 0))
1259                                 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1260                                         DAC33_BUFFER_SIZE_SAMPLES : samples;
1261                         else
1262                                 delay = 0;
1263                 }
1264                 break;
1265         case DAC33_FIFO_MODE7:
1266                 spin_lock(&dac33->lock);
1267                 t0 = dac33->t_stamp1;
1268                 uthr = dac33->uthr;
1269                 spin_unlock(&dac33->lock);
1270                 t_now = ktime_to_us(ktime_get());
1271
1272                 /* We have not started to fill the FIFO yet, delay is 0 */
1273                 if (!t0)
1274                         goto out;
1275
1276                 if (t_now <= t0) {
1277                         /*
1278                          * Either the timestamps are messed or equal. Report
1279                          * maximum delay
1280                          */
1281                         delay = uthr;
1282                         goto out;
1283                 }
1284
1285                 time_delta = t_now - t0;
1286                 if (time_delta <= dac33->mode7_us_to_lthr) {
1287                         /*
1288                         * Phase 1:
1289                         * After burst (draining phase)
1290                         */
1291                         samples_out = US_TO_SAMPLES(
1292                                         substream->runtime->rate,
1293                                         time_delta);
1294
1295                         if (likely(uthr > samples_out))
1296                                 delay = uthr - samples_out;
1297                         else
1298                                 delay = 0;
1299                 } else {
1300                         /*
1301                         * Phase 2:
1302                         * During burst operation
1303                         */
1304                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1305
1306                         samples_out = US_TO_SAMPLES(
1307                                         substream->runtime->rate,
1308                                         time_delta);
1309                         samples_in = US_TO_SAMPLES(
1310                                         dac33->burst_rate,
1311                                         time_delta);
1312                         delay = MODE7_LTHR + samples_in - samples_out;
1313
1314                         if (unlikely(delay > uthr))
1315                                 delay = uthr;
1316                 }
1317                 break;
1318         default:
1319                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1320                                                         dac33->fifo_mode);
1321                 break;
1322         }
1323 out:
1324         return delay;
1325 }
1326
1327 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1328                 int clk_id, unsigned int freq, int dir)
1329 {
1330         struct snd_soc_codec *codec = codec_dai->codec;
1331         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1332         u8 ioc_reg, asrcb_reg;
1333
1334         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1335         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1336         switch (clk_id) {
1337         case TLV320DAC33_MCLK:
1338                 ioc_reg |= DAC33_REFSEL;
1339                 asrcb_reg |= DAC33_SRCREFSEL;
1340                 break;
1341         case TLV320DAC33_SLEEPCLK:
1342                 ioc_reg &= ~DAC33_REFSEL;
1343                 asrcb_reg &= ~DAC33_SRCREFSEL;
1344                 break;
1345         default:
1346                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1347                 break;
1348         }
1349         dac33->refclk = freq;
1350
1351         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1352         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1353
1354         return 0;
1355 }
1356
1357 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1358                              unsigned int fmt)
1359 {
1360         struct snd_soc_codec *codec = codec_dai->codec;
1361         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1362         u8 aictrl_a, aictrl_b;
1363
1364         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1365         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1366         /* set master/slave audio interface */
1367         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1368         case SND_SOC_DAIFMT_CBM_CFM:
1369                 /* Codec Master */
1370                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1371                 break;
1372         case SND_SOC_DAIFMT_CBS_CFS:
1373                 /* Codec Slave */
1374                 if (dac33->fifo_mode) {
1375                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1376                         return -EINVAL;
1377                 } else
1378                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1379                 break;
1380         default:
1381                 return -EINVAL;
1382         }
1383
1384         aictrl_a &= ~DAC33_AFMT_MASK;
1385         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1386         case SND_SOC_DAIFMT_I2S:
1387                 aictrl_a |= DAC33_AFMT_I2S;
1388                 break;
1389         case SND_SOC_DAIFMT_DSP_A:
1390                 aictrl_a |= DAC33_AFMT_DSP;
1391                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1392                 aictrl_b |= DAC33_DATA_DELAY(0);
1393                 break;
1394         case SND_SOC_DAIFMT_RIGHT_J:
1395                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1396                 break;
1397         case SND_SOC_DAIFMT_LEFT_J:
1398                 aictrl_a |= DAC33_AFMT_LEFT_J;
1399                 break;
1400         default:
1401                 dev_err(codec->dev, "Unsupported format (%u)\n",
1402                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1403                 return -EINVAL;
1404         }
1405
1406         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1407         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1408
1409         return 0;
1410 }
1411
1412 static int dac33_soc_probe(struct snd_soc_codec *codec)
1413 {
1414         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1415         int ret = 0;
1416
1417         codec->control_data = dac33->control_data;
1418         codec->hw_write = (hw_write_t) i2c_master_send;
1419         codec->dapm.idle_bias_off = 1;
1420         dac33->codec = codec;
1421
1422         /* Read the tlv320dac33 ID registers */
1423         ret = dac33_hard_power(codec, 1);
1424         if (ret != 0) {
1425                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1426                 goto err_power;
1427         }
1428         ret = dac33_read_id(codec);
1429         dac33_hard_power(codec, 0);
1430
1431         if (ret < 0) {
1432                 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1433                 ret = -ENODEV;
1434                 goto err_power;
1435         }
1436
1437         /* Check if the IRQ number is valid and request it */
1438         if (dac33->irq >= 0) {
1439                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1440                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1441                                   codec->name, codec);
1442                 if (ret < 0) {
1443                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1444                                                 dac33->irq, ret);
1445                         dac33->irq = -1;
1446                 }
1447                 if (dac33->irq != -1) {
1448                         /* Setup work queue */
1449                         dac33->dac33_wq =
1450                                 create_singlethread_workqueue("tlv320dac33");
1451                         if (dac33->dac33_wq == NULL) {
1452                                 free_irq(dac33->irq, codec);
1453                                 return -ENOMEM;
1454                         }
1455
1456                         INIT_WORK(&dac33->work, dac33_work);
1457                 }
1458         }
1459
1460         snd_soc_add_controls(codec, dac33_snd_controls,
1461                              ARRAY_SIZE(dac33_snd_controls));
1462         /* Only add the FIFO controls, if we have valid IRQ number */
1463         if (dac33->irq >= 0) {
1464                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1465                                      ARRAY_SIZE(dac33_mode_snd_controls));
1466                 /* FIFO usage controls only, if autoio config is not selected */
1467                 if (!dac33->auto_fifo_config)
1468                         snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1469                                         ARRAY_SIZE(dac33_fifo_snd_controls));
1470         }
1471         dac33_add_widgets(codec);
1472
1473 err_power:
1474         return ret;
1475 }
1476
1477 static int dac33_soc_remove(struct snd_soc_codec *codec)
1478 {
1479         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1480
1481         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1482
1483         if (dac33->irq >= 0) {
1484                 free_irq(dac33->irq, dac33->codec);
1485                 destroy_workqueue(dac33->dac33_wq);
1486         }
1487         return 0;
1488 }
1489
1490 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1491 {
1492         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1493
1494         return 0;
1495 }
1496
1497 static int dac33_soc_resume(struct snd_soc_codec *codec)
1498 {
1499         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1500
1501         return 0;
1502 }
1503
1504 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1505         .read = dac33_read_reg_cache,
1506         .write = dac33_write_locked,
1507         .set_bias_level = dac33_set_bias_level,
1508         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1509         .reg_word_size = sizeof(u8),
1510         .reg_cache_default = dac33_reg,
1511         .probe = dac33_soc_probe,
1512         .remove = dac33_soc_remove,
1513         .suspend = dac33_soc_suspend,
1514         .resume = dac33_soc_resume,
1515 };
1516
1517 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1518                          SNDRV_PCM_RATE_48000)
1519 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1520
1521 static struct snd_soc_dai_ops dac33_dai_ops = {
1522         .startup        = dac33_startup,
1523         .shutdown       = dac33_shutdown,
1524         .hw_params      = dac33_hw_params,
1525         .trigger        = dac33_pcm_trigger,
1526         .delay          = dac33_dai_delay,
1527         .set_sysclk     = dac33_set_dai_sysclk,
1528         .set_fmt        = dac33_set_dai_fmt,
1529 };
1530
1531 static struct snd_soc_dai_driver dac33_dai = {
1532         .name = "tlv320dac33-hifi",
1533         .playback = {
1534                 .stream_name = "Playback",
1535                 .channels_min = 2,
1536                 .channels_max = 2,
1537                 .rates = DAC33_RATES,
1538                 .formats = DAC33_FORMATS,},
1539         .ops = &dac33_dai_ops,
1540 };
1541
1542 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1543                                      const struct i2c_device_id *id)
1544 {
1545         struct tlv320dac33_platform_data *pdata;
1546         struct tlv320dac33_priv *dac33;
1547         int ret, i;
1548
1549         if (client->dev.platform_data == NULL) {
1550                 dev_err(&client->dev, "Platform data not set\n");
1551                 return -ENODEV;
1552         }
1553         pdata = client->dev.platform_data;
1554
1555         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1556         if (dac33 == NULL)
1557                 return -ENOMEM;
1558
1559         dac33->control_data = client;
1560         mutex_init(&dac33->mutex);
1561         spin_lock_init(&dac33->lock);
1562
1563         i2c_set_clientdata(client, dac33);
1564
1565         dac33->power_gpio = pdata->power_gpio;
1566         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1567         /* Pre calculate the burst rate */
1568         dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1569         dac33->keep_bclk = pdata->keep_bclk;
1570         dac33->auto_fifo_config = pdata->auto_fifo_config;
1571         dac33->mode1_latency = pdata->mode1_latency;
1572         if (!dac33->mode1_latency)
1573                 dac33->mode1_latency = 10000; /* 10ms */
1574         dac33->irq = client->irq;
1575         dac33->nsample = NSAMPLE_MAX;
1576         dac33->nsample_max = NSAMPLE_MAX;
1577         dac33->uthr = MODE7_UTHR;
1578         /* Disable FIFO use by default */
1579         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1580
1581         /* Check if the reset GPIO number is valid and request it */
1582         if (dac33->power_gpio >= 0) {
1583                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1584                 if (ret < 0) {
1585                         dev_err(&client->dev,
1586                                 "Failed to request reset GPIO (%d)\n",
1587                                 dac33->power_gpio);
1588                         goto err_gpio;
1589                 }
1590                 gpio_direction_output(dac33->power_gpio, 0);
1591         }
1592
1593         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1594                 dac33->supplies[i].supply = dac33_supply_names[i];
1595
1596         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1597                                  dac33->supplies);
1598
1599         if (ret != 0) {
1600                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1601                 goto err_get;
1602         }
1603
1604         ret = snd_soc_register_codec(&client->dev,
1605                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1606         if (ret < 0)
1607                 goto err_register;
1608
1609         return ret;
1610 err_register:
1611         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1612 err_get:
1613         if (dac33->power_gpio >= 0)
1614                 gpio_free(dac33->power_gpio);
1615 err_gpio:
1616         kfree(dac33);
1617         return ret;
1618 }
1619
1620 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1621 {
1622         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1623
1624         if (unlikely(dac33->chip_power))
1625                 dac33_hard_power(dac33->codec, 0);
1626
1627         if (dac33->power_gpio >= 0)
1628                 gpio_free(dac33->power_gpio);
1629
1630         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1631
1632         snd_soc_unregister_codec(&client->dev);
1633         kfree(dac33);
1634
1635         return 0;
1636 }
1637
1638 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1639         {
1640                 .name = "tlv320dac33",
1641                 .driver_data = 0,
1642         },
1643         { },
1644 };
1645
1646 static struct i2c_driver tlv320dac33_i2c_driver = {
1647         .driver = {
1648                 .name = "tlv320dac33-codec",
1649                 .owner = THIS_MODULE,
1650         },
1651         .probe          = dac33_i2c_probe,
1652         .remove         = __devexit_p(dac33_i2c_remove),
1653         .id_table       = tlv320dac33_i2c_id,
1654 };
1655
1656 static int __init dac33_module_init(void)
1657 {
1658         int r;
1659         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1660         if (r < 0) {
1661                 printk(KERN_ERR "DAC33: driver registration failed\n");
1662                 return r;
1663         }
1664         return 0;
1665 }
1666 module_init(dac33_module_init);
1667
1668 static void __exit dac33_module_exit(void)
1669 {
1670         i2c_del_driver(&tlv320dac33_i2c_driver);
1671 }
1672 module_exit(dac33_module_exit);
1673
1674
1675 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1676 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1677 MODULE_LICENSE("GPL");