sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/soc-dapm.h>
  40 #include <sound/initval.h>
  41 #include <sound/tlv.h>
  42
  43 #include <sound/tlv320dac33-plat.h>
  44 #include "tlv320dac33.h"
  45
  46 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  47                                                  * 6144 stereo */
  48 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  49
  50 #define NSAMPLE_MAX             5700
  51
  52 #define LATENCY_TIME_MS         20
  53
  54 #define MODE7_LTHR              10
  55 #define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
  56
  57 #define BURST_BASEFREQ_HZ       49152000
  58
  59 #define SAMPLES_TO_US(rate, samples) \
  60         (1000000000 / ((rate * 1000) / samples))
  61
  62 #define US_TO_SAMPLES(rate, us) \
  63         (rate / (1000000 / us))
  64
  65 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  66 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  67
  68 static struct snd_soc_codec *tlv320dac33_codec;
  69
  70 enum dac33_state {
  71         DAC33_IDLE = 0,
  72         DAC33_PREFILL,
  73         DAC33_PLAYBACK,
  74         DAC33_FLUSH,
  75 };
  76
  77 enum dac33_fifo_modes {
  78         DAC33_FIFO_BYPASS = 0,
  79         DAC33_FIFO_MODE1,
  80         DAC33_FIFO_MODE7,
  81         DAC33_FIFO_LAST_MODE,
  82 };
  83
  84 #define DAC33_NUM_SUPPLIES 3
  85 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  86         "AVDD",
  87         "DVDD",
  88         "IOVDD",
  89 };
  90
  91 struct tlv320dac33_priv {
  92         struct mutex mutex;
  93         struct workqueue_struct *dac33_wq;
  94         struct work_struct work;
  95         struct snd_soc_codec codec;
  96         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  97         struct snd_pcm_substream *substream;
  98         int power_gpio;
  99         int chip_power;
 100         int irq;
 101         unsigned int refclk;
 102
 103         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 104         unsigned int nsample_min;       /* nsample should not be lower than
 105                                          * this */
 106         unsigned int nsample_max;       /* nsample should not be higher than
 107                                          * this */
 108         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 109         unsigned int nsample;           /* burst read amount from host */
 110         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 111         unsigned int burst_rate;        /* Interface speed in Burst modes */
 112
 113         int keep_bclk;                  /* Keep the BCLK continuously running
 114                                          * in FIFO modes */
 115         spinlock_t lock;
 116         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 117         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 118
 119         unsigned int mode1_us_burst;    /* Time to burst read n number of
 120                                          * samples */
 121         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 122
 123         enum dac33_state state;
 124 };
 125
 126 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 127 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 128 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 129 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 130 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 131 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 132 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 133 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 134 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 135 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 136 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 137 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 138 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 139 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 140 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 141 0x00, 0x00,             /* 0x38 - 0x39 */
 142 /* Registers 0x3a - 0x3f are reserved  */
 143             0x00, 0x00, /* 0x3a - 0x3b */
 144 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 145
 146 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 147 0x00, 0x80,             /* 0x44 - 0x45 */
 148 /* Registers 0x46 - 0x47 are reserved  */
 149             0x80, 0x80, /* 0x46 - 0x47 */
 150
 151 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 152 /* Registers 0x4b - 0x7c are reserved  */
 153                   0x00, /* 0x4b        */
 154 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 155 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 156 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 157 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 158 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 159 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 160 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 161 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 162 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 163 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 164 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 165 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 166 0x00,                   /* 0x7c        */
 167
 168       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 169 };
 170
 171 /* Register read and write */
 172 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 173                                                 unsigned reg)
 174 {
 175         u8 *cache = codec->reg_cache;
 176         if (reg >= DAC33_CACHEREGNUM)
 177                 return 0;
 178
 179         return cache[reg];
 180 }
 181
 182 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 183                                          u8 reg, u8 value)
 184 {
 185         u8 *cache = codec->reg_cache;
 186         if (reg >= DAC33_CACHEREGNUM)
 187                 return;
 188
 189         cache[reg] = value;
 190 }
 191
 192 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 193                       u8 *value)
 194 {
 195         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 196         int val;
 197
 198         *value = reg & 0xff;
 199
 200         /* If powered off, return the cached value */
 201         if (dac33->chip_power) {
 202                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 203                 if (val < 0) {
 204                         dev_err(codec->dev, "Read failed (%d)\n", val);
 205                         value[0] = dac33_read_reg_cache(codec, reg);
 206                 } else {
 207                         value[0] = val;
 208                         dac33_write_reg_cache(codec, reg, val);
 209                 }
 210         } else {
 211                 value[0] = dac33_read_reg_cache(codec, reg);
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 218                        unsigned int value)
 219 {
 220         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 221         u8 data[2];
 222         int ret = 0;
 223
 224         /*
 225          * data is
 226          *   D15..D8 dac33 register offset
 227          *   D7...D0 register data
 228          */
 229         data[0] = reg & 0xff;
 230         data[1] = value & 0xff;
 231
 232         dac33_write_reg_cache(codec, data[0], data[1]);
 233         if (dac33->chip_power) {
 234                 ret = codec->hw_write(codec->control_data, data, 2);
 235                 if (ret != 2)
 236                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 237                 else
 238                         ret = 0;
 239         }
 240
 241         return ret;
 242 }
 243
 244 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 245                        unsigned int value)
 246 {
 247         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 248         int ret;
 249
 250         mutex_lock(&dac33->mutex);
 251         ret = dac33_write(codec, reg, value);
 252         mutex_unlock(&dac33->mutex);
 253
 254         return ret;
 255 }
 256
 257 #define DAC33_I2C_ADDR_AUTOINC  0x80
 258 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 259                        unsigned int value)
 260 {
 261         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 262         u8 data[3];
 263         int ret = 0;
 264
 265         /*
 266          * data is
 267          *   D23..D16 dac33 register offset
 268          *   D15..D8  register data MSB
 269          *   D7...D0  register data LSB
 270          */
 271         data[0] = reg & 0xff;
 272         data[1] = (value >> 8) & 0xff;
 273         data[2] = value & 0xff;
 274
 275         dac33_write_reg_cache(codec, data[0], data[1]);
 276         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 277
 278         if (dac33->chip_power) {
 279                 /* We need to set autoincrement mode for 16 bit writes */
 280                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 281                 ret = codec->hw_write(codec->control_data, data, 3);
 282                 if (ret != 3)
 283                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 284                 else
 285                         ret = 0;
 286         }
 287
 288         return ret;
 289 }
 290
 291 static void dac33_init_chip(struct snd_soc_codec *codec)
 292 {
 293         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 294
 295         if (unlikely(!dac33->chip_power))
 296                 return;
 297
 298         /* 44-46: DAC Control Registers */
 299         /* A : DAC sample rate Fsref/1.5 */
 300         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 301         /* B : DAC src=normal, not muted */
 302         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 303                                              DAC33_DACSRCL_LEFT);
 304         /* C : (defaults) */
 305         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 306
 307         /* 73 : volume soft stepping control,
 308          clock source = internal osc (?) */
 309         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 310
 311         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
 312
 313         /* Restore only selected registers (gains mostly) */
 314         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 315                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 316         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 317                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 318
 319         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 320                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 321         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 322                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 323 }
 324
 325 static inline void dac33_read_id(struct snd_soc_codec *codec)
 326 {
 327         u8 reg;
 328
 329         dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
 330         dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
 331         dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
 332 }
 333
 334 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 335 {
 336         u8 reg;
 337
 338         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 339         if (power)
 340                 reg |= DAC33_PDNALLB;
 341         else
 342                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 343                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 344         dac33_write(codec, DAC33_PWR_CTRL, reg);
 345 }
 346
 347 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 348 {
 349         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 350         int ret = 0;
 351
 352         mutex_lock(&dac33->mutex);
 353
 354         /* Safety check */
 355         if (unlikely(power == dac33->chip_power)) {
 356                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 357                         power ? "ON" : "OFF");
 358                 goto exit;
 359         }
 360
 361         if (power) {
 362                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 363                                           dac33->supplies);
 364                 if (ret != 0) {
 365                         dev_err(codec->dev,
 366                                 "Failed to enable supplies: %d\n", ret);
 367                                 goto exit;
 368                 }
 369
 370                 if (dac33->power_gpio >= 0)
 371                         gpio_set_value(dac33->power_gpio, 1);
 372
 373                 dac33->chip_power = 1;
 374         } else {
 375                 dac33_soft_power(codec, 0);
 376                 if (dac33->power_gpio >= 0)
 377                         gpio_set_value(dac33->power_gpio, 0);
 378
 379                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 380                                              dac33->supplies);
 381                 if (ret != 0) {
 382                         dev_err(codec->dev,
 383                                 "Failed to disable supplies: %d\n", ret);
 384                         goto exit;
 385                 }
 386
 387                 dac33->chip_power = 0;
 388         }
 389
 390 exit:
 391         mutex_unlock(&dac33->mutex);
 392         return ret;
 393 }
 394
 395 static int playback_event(struct snd_soc_dapm_widget *w,
 396                 struct snd_kcontrol *kcontrol, int event)
 397 {
 398         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 399
 400         switch (event) {
 401         case SND_SOC_DAPM_PRE_PMU:
 402                 if (likely(dac33->substream)) {
 403                         dac33_calculate_times(dac33->substream);
 404                         dac33_prepare_chip(dac33->substream);
 405                 }
 406                 break;
 407         }
 408         return 0;
 409 }
 410
 411 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 412                          struct snd_ctl_elem_value *ucontrol)
 413 {
 414         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 415         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 416
 417         ucontrol->value.integer.value[0] = dac33->nsample;
 418
 419         return 0;
 420 }
 421
 422 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 423                          struct snd_ctl_elem_value *ucontrol)
 424 {
 425         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 426         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 427         int ret = 0;
 428
 429         if (dac33->nsample == ucontrol->value.integer.value[0])
 430                 return 0;
 431
 432         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 433             ucontrol->value.integer.value[0] > dac33->nsample_max) {
 434                 ret = -EINVAL;
 435         } else {
 436                 dac33->nsample = ucontrol->value.integer.value[0];
 437                 /* Re calculate the burst time */
 438                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
 439                                                       dac33->nsample);
 440         }
 441
 442         return ret;
 443 }
 444
 445 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 446                          struct snd_ctl_elem_value *ucontrol)
 447 {
 448         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 449         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 450
 451         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 452
 453         return 0;
 454 }
 455
 456 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 457                          struct snd_ctl_elem_value *ucontrol)
 458 {
 459         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 460         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 461         int ret = 0;
 462
 463         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 464                 return 0;
 465         /* Do not allow changes while stream is running*/
 466         if (codec->active)
 467                 return -EPERM;
 468
 469         if (ucontrol->value.integer.value[0] < 0 ||
 470             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 471                 ret = -EINVAL;
 472         else
 473                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 474
 475         return ret;
 476 }
 477
 478 /* Codec operation modes */
 479 static const char *dac33_fifo_mode_texts[] = {
 480         "Bypass", "Mode 1", "Mode 7"
 481 };
 482
 483 static const struct soc_enum dac33_fifo_mode_enum =
 484         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 485                             dac33_fifo_mode_texts);
 486
 487 /*
 488  * DACL/R digital volume control:
 489  * from 0 dB to -63.5 in 0.5 dB steps
 490  * Need to be inverted later on:
 491  * 0x00 == 0 dB
 492  * 0x7f == -63.5 dB
 493  */
 494 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 495
 496 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 497         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 498                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 499                 0, 0x7f, 1, dac_digivol_tlv),
 500         SOC_DOUBLE_R("DAC Digital Playback Switch",
 501                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 502         SOC_DOUBLE_R("Line to Line Out Volume",
 503                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 504 };
 505
 506 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
 507         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 508                  dac33_get_nsample, dac33_set_nsample),
 509         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 510                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 511 };
 512
 513 /* Analog bypass */
 514 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 515         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 516
 517 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 518         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 519
 520 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 521         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 522         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 523
 524         SND_SOC_DAPM_INPUT("LINEL"),
 525         SND_SOC_DAPM_INPUT("LINER"),
 526
 527         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
 528         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
 529
 530         /* Analog bypass */
 531         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 532                                 &dac33_dapm_abypassl_control),
 533         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 534                                 &dac33_dapm_abypassr_control),
 535
 536         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
 537                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 538         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
 539                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 540
 541         SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
 542 };
 543
 544 static const struct snd_soc_dapm_route audio_map[] = {
 545         /* Analog bypass */
 546         {"Analog Left Bypass", "Switch", "LINEL"},
 547         {"Analog Right Bypass", "Switch", "LINER"},
 548
 549         {"Output Left Amp Power", NULL, "DACL"},
 550         {"Output Right Amp Power", NULL, "DACR"},
 551
 552         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
 553         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
 554
 555         /* output */
 556         {"LEFT_LO", NULL, "Output Left Amp Power"},
 557         {"RIGHT_LO", NULL, "Output Right Amp Power"},
 558 };
 559
 560 static int dac33_add_widgets(struct snd_soc_codec *codec)
 561 {
 562         snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
 563                                   ARRAY_SIZE(dac33_dapm_widgets));
 564
 565         /* set up audio path interconnects */
 566         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 567
 568         return 0;
 569 }
 570
 571 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 572                                 enum snd_soc_bias_level level)
 573 {
 574         int ret;
 575
 576         switch (level) {
 577         case SND_SOC_BIAS_ON:
 578                 dac33_soft_power(codec, 1);
 579                 break;
 580         case SND_SOC_BIAS_PREPARE:
 581                 break;
 582         case SND_SOC_BIAS_STANDBY:
 583                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 584                         /* Coming from OFF, switch on the codec */
 585                         ret = dac33_hard_power(codec, 1);
 586                         if (ret != 0)
 587                                 return ret;
 588
 589                         dac33_init_chip(codec);
 590                 }
 591                 break;
 592         case SND_SOC_BIAS_OFF:
 593                 /* Do not power off, when the codec is already off */
 594                 if (codec->bias_level == SND_SOC_BIAS_OFF)
 595                         return 0;
 596                 ret = dac33_hard_power(codec, 0);
 597                 if (ret != 0)
 598                         return ret;
 599                 break;
 600         }
 601         codec->bias_level = level;
 602
 603         return 0;
 604 }
 605
 606 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 607 {
 608         struct snd_soc_codec *codec;
 609
 610         codec = &dac33->codec;
 611
 612         switch (dac33->fifo_mode) {
 613         case DAC33_FIFO_MODE1:
 614                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 615                         DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
 616
 617                 /* Take the timestamps */
 618                 spin_lock_irq(&dac33->lock);
 619                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 620                 dac33->t_stamp1 = dac33->t_stamp2;
 621                 spin_unlock_irq(&dac33->lock);
 622
 623                 dac33_write16(codec, DAC33_PREFILL_MSB,
 624                                 DAC33_THRREG(dac33->alarm_threshold));
 625                 /* Enable Alarm Threshold IRQ with a delay */
 626                 udelay(SAMPLES_TO_US(dac33->burst_rate,
 627                                      dac33->alarm_threshold));
 628                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 629                 break;
 630         case DAC33_FIFO_MODE7:
 631                 /* Take the timestamp */
 632                 spin_lock_irq(&dac33->lock);
 633                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 634                 /* Move back the timestamp with drain time */
 635                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 636                 spin_unlock_irq(&dac33->lock);
 637
 638                 dac33_write16(codec, DAC33_PREFILL_MSB,
 639                                 DAC33_THRREG(MODE7_LTHR));
 640
 641                 /* Enable Upper Threshold IRQ */
 642                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 643                 break;
 644         default:
 645                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 646                                                         dac33->fifo_mode);
 647                 break;
 648         }
 649 }
 650
 651 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 652 {
 653         struct snd_soc_codec *codec;
 654
 655         codec = &dac33->codec;
 656
 657         switch (dac33->fifo_mode) {
 658         case DAC33_FIFO_MODE1:
 659                 /* Take the timestamp */
 660                 spin_lock_irq(&dac33->lock);
 661                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 662                 spin_unlock_irq(&dac33->lock);
 663
 664                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 665                                 DAC33_THRREG(dac33->nsample));
 666                 break;
 667         case DAC33_FIFO_MODE7:
 668                 /* At the moment we are not using interrupts in mode7 */
 669                 break;
 670         default:
 671                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 672                                                         dac33->fifo_mode);
 673                 break;
 674         }
 675 }
 676
 677 static void dac33_work(struct work_struct *work)
 678 {
 679         struct snd_soc_codec *codec;
 680         struct tlv320dac33_priv *dac33;
 681         u8 reg;
 682
 683         dac33 = container_of(work, struct tlv320dac33_priv, work);
 684         codec = &dac33->codec;
 685
 686         mutex_lock(&dac33->mutex);
 687         switch (dac33->state) {
 688         case DAC33_PREFILL:
 689                 dac33->state = DAC33_PLAYBACK;
 690                 dac33_prefill_handler(dac33);
 691                 break;
 692         case DAC33_PLAYBACK:
 693                 dac33_playback_handler(dac33);
 694                 break;
 695         case DAC33_IDLE:
 696                 break;
 697         case DAC33_FLUSH:
 698                 dac33->state = DAC33_IDLE;
 699                 /* Mask all interrupts from dac33 */
 700                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 701
 702                 /* flush fifo */
 703                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 704                 reg |= DAC33_FIFOFLUSH;
 705                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 706                 break;
 707         }
 708         mutex_unlock(&dac33->mutex);
 709 }
 710
 711 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 712 {
 713         struct snd_soc_codec *codec = dev;
 714         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 715
 716         spin_lock(&dac33->lock);
 717         dac33->t_stamp1 = ktime_to_us(ktime_get());
 718         spin_unlock(&dac33->lock);
 719
 720         /* Do not schedule the workqueue in Mode7 */
 721         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 722                 queue_work(dac33->dac33_wq, &dac33->work);
 723
 724         return IRQ_HANDLED;
 725 }
 726
 727 static void dac33_oscwait(struct snd_soc_codec *codec)
 728 {
 729         int timeout = 20;
 730         u8 reg;
 731
 732         do {
 733                 msleep(1);
 734                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 735         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 736         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 737                 dev_err(codec->dev,
 738                         "internal oscillator calibration failed\n");
 739 }
 740
 741 static int dac33_startup(struct snd_pcm_substream *substream,
 742                            struct snd_soc_dai *dai)
 743 {
 744         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 745         struct snd_soc_device *socdev = rtd->socdev;
 746         struct snd_soc_codec *codec = socdev->card->codec;
 747         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 748
 749         /* Stream started, save the substream pointer */
 750         dac33->substream = substream;
 751
 752         return 0;
 753 }
 754
 755 static void dac33_shutdown(struct snd_pcm_substream *substream,
 756                              struct snd_soc_dai *dai)
 757 {
 758         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 759         struct snd_soc_device *socdev = rtd->socdev;
 760         struct snd_soc_codec *codec = socdev->card->codec;
 761         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 762
 763         dac33->substream = NULL;
 764 }
 765
 766 static int dac33_hw_params(struct snd_pcm_substream *substream,
 767                            struct snd_pcm_hw_params *params,
 768                            struct snd_soc_dai *dai)
 769 {
 770         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 771         struct snd_soc_device *socdev = rtd->socdev;
 772         struct snd_soc_codec *codec = socdev->card->codec;
 773
 774         /* Check parameters for validity */
 775         switch (params_rate(params)) {
 776         case 44100:
 777         case 48000:
 778                 break;
 779         default:
 780                 dev_err(codec->dev, "unsupported rate %d\n",
 781                         params_rate(params));
 782                 return -EINVAL;
 783         }
 784
 785         switch (params_format(params)) {
 786         case SNDRV_PCM_FORMAT_S16_LE:
 787                 break;
 788         default:
 789                 dev_err(codec->dev, "unsupported format %d\n",
 790                         params_format(params));
 791                 return -EINVAL;
 792         }
 793
 794         return 0;
 795 }
 796
 797 #define CALC_OSCSET(rate, refclk) ( \
 798         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 799 #define CALC_RATIOSET(rate, refclk) ( \
 800         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 801
 802 /*
 803  * tlv320dac33 is strict on the sequence of the register writes, if the register
 804  * writes happens in different order, than dac33 might end up in unknown state.
 805  * Use the known, working sequence of register writes to initialize the dac33.
 806  */
 807 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 808 {
 809         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 810         struct snd_soc_device *socdev = rtd->socdev;
 811         struct snd_soc_codec *codec = socdev->card->codec;
 812         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 813         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 814         u8 aictrl_a, aictrl_b, fifoctrl_a;
 815
 816         switch (substream->runtime->rate) {
 817         case 44100:
 818         case 48000:
 819                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 820                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 821                                          dac33->refclk);
 822                 break;
 823         default:
 824                 dev_err(codec->dev, "unsupported rate %d\n",
 825                         substream->runtime->rate);
 826                 return -EINVAL;
 827         }
 828
 829
 830         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 831         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 832         /* Read FIFO control A, and clear FIFO flush bit */
 833         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 834         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 835
 836         fifoctrl_a &= ~DAC33_WIDTH;
 837         switch (substream->runtime->format) {
 838         case SNDRV_PCM_FORMAT_S16_LE:
 839                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 840                 fifoctrl_a |= DAC33_WIDTH;
 841                 break;
 842         default:
 843                 dev_err(codec->dev, "unsupported format %d\n",
 844                         substream->runtime->format);
 845                 return -EINVAL;
 846         }
 847
 848         mutex_lock(&dac33->mutex);
 849
 850         if (!dac33->chip_power) {
 851                 /*
 852                  * Chip is not powered yet.
 853                  * Do the init in the dac33_set_bias_level later.
 854                  */
 855                 mutex_unlock(&dac33->mutex);
 856                 return 0;
 857         }
 858
 859         dac33_soft_power(codec, 0);
 860         dac33_soft_power(codec, 1);
 861
 862         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 863         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 864
 865         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 866         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 867
 868         /* calib time: 128 is a nice number ;) */
 869         dac33_write(codec, DAC33_CALIB_TIME, 128);
 870
 871         /* adjustment treshold & step */
 872         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 873                                                  DAC33_ADJSTEP(1));
 874
 875         /* div=4 / gain=1 / div */
 876         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 877
 878         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 879         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 880         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 881
 882         dac33_oscwait(codec);
 883
 884         if (dac33->fifo_mode) {
 885                 /* Generic for all FIFO modes */
 886                 /* 50-51 : ASRC Control registers */
 887                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 888                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 889
 890                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 891                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 892
 893                 /* Set interrupts to high active */
 894                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 895         } else {
 896                 /* FIFO bypass mode */
 897                 /* 50-51 : ASRC Control registers */
 898                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 899                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 900         }
 901
 902         /* Interrupt behaviour configuration */
 903         switch (dac33->fifo_mode) {
 904         case DAC33_FIFO_MODE1:
 905                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 906                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 907                 break;
 908         case DAC33_FIFO_MODE7:
 909                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 910                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 911                 break;
 912         default:
 913                 /* in FIFO bypass mode, the interrupts are not used */
 914                 break;
 915         }
 916
 917         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 918
 919         switch (dac33->fifo_mode) {
 920         case DAC33_FIFO_MODE1:
 921                 /*
 922                  * For mode1:
 923                  * Disable the FIFO bypass (Enable the use of FIFO)
 924                  * Select nSample mode
 925                  * BCLK is only running when data is needed by DAC33
 926                  */
 927                 fifoctrl_a &= ~DAC33_FBYPAS;
 928                 fifoctrl_a &= ~DAC33_FAUTO;
 929                 if (dac33->keep_bclk)
 930                         aictrl_b |= DAC33_BCLKON;
 931                 else
 932                         aictrl_b &= ~DAC33_BCLKON;
 933                 break;
 934         case DAC33_FIFO_MODE7:
 935                 /*
 936                  * For mode1:
 937                  * Disable the FIFO bypass (Enable the use of FIFO)
 938                  * Select Threshold mode
 939                  * BCLK is only running when data is needed by DAC33
 940                  */
 941                 fifoctrl_a &= ~DAC33_FBYPAS;
 942                 fifoctrl_a |= DAC33_FAUTO;
 943                 if (dac33->keep_bclk)
 944                         aictrl_b |= DAC33_BCLKON;
 945                 else
 946                         aictrl_b &= ~DAC33_BCLKON;
 947                 break;
 948         default:
 949                 /*
 950                  * For FIFO bypass mode:
 951                  * Enable the FIFO bypass (Disable the FIFO use)
 952                  * Set the BCLK as continous
 953                  */
 954                 fifoctrl_a |= DAC33_FBYPAS;
 955                 aictrl_b |= DAC33_BCLKON;
 956                 break;
 957         }
 958
 959         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
 960         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
 961         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
 962
 963         /*
 964          * BCLK divide ratio
 965          * 0: 1.5
 966          * 1: 1
 967          * 2: 2
 968          * ...
 969          * 254: 254
 970          * 255: 255
 971          */
 972         if (dac33->fifo_mode)
 973                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
 974                                                         dac33->burst_bclkdiv);
 975         else
 976                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
 977
 978         switch (dac33->fifo_mode) {
 979         case DAC33_FIFO_MODE1:
 980                 dac33_write16(codec, DAC33_ATHR_MSB,
 981                               DAC33_THRREG(dac33->alarm_threshold));
 982                 break;
 983         case DAC33_FIFO_MODE7:
 984                 /*
 985                  * Configure the threshold levels, and leave 10 sample space
 986                  * at the bottom, and also at the top of the FIFO
 987                  */
 988                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
 989                 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
 990                 break;
 991         default:
 992                 break;
 993         }
 994
 995         mutex_unlock(&dac33->mutex);
 996
 997         return 0;
 998 }
 999
1000 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1001 {
1002         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1003         struct snd_soc_device *socdev = rtd->socdev;
1004         struct snd_soc_codec *codec = socdev->card->codec;
1005         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1006         unsigned int nsample_limit;
1007
1008         /* In bypass mode we don't need to calculate */
1009         if (!dac33->fifo_mode)
1010                 return;
1011
1012         /* Number of samples (16bit, stereo) in one period */
1013         dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
1014
1015         /* Number of samples (16bit, stereo) in ALSA buffer */
1016         dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
1017         /* Subtract one period from the total */
1018         dac33->nsample_max -= dac33->nsample_min;
1019
1020         /* Number of samples for LATENCY_TIME_MS / 2 */
1021         dac33->alarm_threshold = substream->runtime->rate /
1022                                  (1000 / (LATENCY_TIME_MS / 2));
1023
1024         /* Find and fix up the lowest nsmaple limit */
1025         nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
1026
1027         if (dac33->nsample_min < nsample_limit)
1028                 dac33->nsample_min = nsample_limit;
1029
1030         if (dac33->nsample < dac33->nsample_min)
1031                 dac33->nsample = dac33->nsample_min;
1032
1033         /*
1034          * Find and fix up the highest nsmaple limit
1035          * In order to not overflow the DAC33 buffer substract the
1036          * alarm_threshold value from the size of the DAC33 buffer
1037          */
1038         nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
1039
1040         if (dac33->nsample_max > nsample_limit)
1041                 dac33->nsample_max = nsample_limit;
1042
1043         if (dac33->nsample > dac33->nsample_max)
1044                 dac33->nsample = dac33->nsample_max;
1045
1046         switch (dac33->fifo_mode) {
1047         case DAC33_FIFO_MODE1:
1048                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1049                                                       dac33->nsample);
1050                 dac33->t_stamp1 = 0;
1051                 dac33->t_stamp2 = 0;
1052                 break;
1053         case DAC33_FIFO_MODE7:
1054                 dac33->mode7_us_to_lthr =
1055                                         SAMPLES_TO_US(substream->runtime->rate,
1056                                                 MODE7_UTHR - MODE7_LTHR + 1);
1057                 dac33->t_stamp1 = 0;
1058                 break;
1059         default:
1060                 break;
1061         }
1062
1063 }
1064
1065 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1066                              struct snd_soc_dai *dai)
1067 {
1068         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1069         struct snd_soc_device *socdev = rtd->socdev;
1070         struct snd_soc_codec *codec = socdev->card->codec;
1071         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1072         int ret = 0;
1073
1074         switch (cmd) {
1075         case SNDRV_PCM_TRIGGER_START:
1076         case SNDRV_PCM_TRIGGER_RESUME:
1077         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1078                 if (dac33->fifo_mode) {
1079                         dac33->state = DAC33_PREFILL;
1080                         queue_work(dac33->dac33_wq, &dac33->work);
1081                 }
1082                 break;
1083         case SNDRV_PCM_TRIGGER_STOP:
1084         case SNDRV_PCM_TRIGGER_SUSPEND:
1085         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1086                 if (dac33->fifo_mode) {
1087                         dac33->state = DAC33_FLUSH;
1088                         queue_work(dac33->dac33_wq, &dac33->work);
1089                 }
1090                 break;
1091         default:
1092                 ret = -EINVAL;
1093         }
1094
1095         return ret;
1096 }
1097
1098 static snd_pcm_sframes_t dac33_dai_delay(
1099                         struct snd_pcm_substream *substream,
1100                         struct snd_soc_dai *dai)
1101 {
1102         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1103         struct snd_soc_device *socdev = rtd->socdev;
1104         struct snd_soc_codec *codec = socdev->card->codec;
1105         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1106         unsigned long long t0, t1, t_now;
1107         unsigned int time_delta;
1108         int samples_out, samples_in, samples;
1109         snd_pcm_sframes_t delay = 0;
1110
1111         switch (dac33->fifo_mode) {
1112         case DAC33_FIFO_BYPASS:
1113                 break;
1114         case DAC33_FIFO_MODE1:
1115                 spin_lock(&dac33->lock);
1116                 t0 = dac33->t_stamp1;
1117                 t1 = dac33->t_stamp2;
1118                 spin_unlock(&dac33->lock);
1119                 t_now = ktime_to_us(ktime_get());
1120
1121                 /* We have not started to fill the FIFO yet, delay is 0 */
1122                 if (!t1)
1123                         goto out;
1124
1125                 if (t0 > t1) {
1126                         /*
1127                          * Phase 1:
1128                          * After Alarm threshold, and before nSample write
1129                          */
1130                         time_delta = t_now - t0;
1131                         samples_out = time_delta ? US_TO_SAMPLES(
1132                                                 substream->runtime->rate,
1133                                                 time_delta) : 0;
1134
1135                         if (likely(dac33->alarm_threshold > samples_out))
1136                                 delay = dac33->alarm_threshold - samples_out;
1137                         else
1138                                 delay = 0;
1139                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1140                         /*
1141                          * Phase 2:
1142                          * After nSample write (during burst operation)
1143                          */
1144                         time_delta = t_now - t0;
1145                         samples_out = time_delta ? US_TO_SAMPLES(
1146                                                 substream->runtime->rate,
1147                                                 time_delta) : 0;
1148
1149                         time_delta = t_now - t1;
1150                         samples_in = time_delta ? US_TO_SAMPLES(
1151                                                 dac33->burst_rate,
1152                                                 time_delta) : 0;
1153
1154                         samples = dac33->alarm_threshold;
1155                         samples += (samples_in - samples_out);
1156
1157                         if (likely(samples > 0))
1158                                 delay = samples;
1159                         else
1160                                 delay = 0;
1161                 } else {
1162                         /*
1163                          * Phase 3:
1164                          * After burst operation, before next alarm threshold
1165                          */
1166                         time_delta = t_now - t0;
1167                         samples_out = time_delta ? US_TO_SAMPLES(
1168                                                 substream->runtime->rate,
1169                                                 time_delta) : 0;
1170
1171                         samples_in = dac33->nsample;
1172                         samples = dac33->alarm_threshold;
1173                         samples += (samples_in - samples_out);
1174
1175                         if (likely(samples > 0))
1176                                 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1177                                         DAC33_BUFFER_SIZE_SAMPLES : samples;
1178                         else
1179                                 delay = 0;
1180                 }
1181                 break;
1182         case DAC33_FIFO_MODE7:
1183                 spin_lock(&dac33->lock);
1184                 t0 = dac33->t_stamp1;
1185                 spin_unlock(&dac33->lock);
1186                 t_now = ktime_to_us(ktime_get());
1187
1188                 /* We have not started to fill the FIFO yet, delay is 0 */
1189                 if (!t0)
1190                         goto out;
1191
1192                 if (t_now <= t0) {
1193                         /*
1194                          * Either the timestamps are messed or equal. Report
1195                          * maximum delay
1196                          */
1197                         delay = MODE7_UTHR;
1198                         goto out;
1199                 }
1200
1201                 time_delta = t_now - t0;
1202                 if (time_delta <= dac33->mode7_us_to_lthr) {
1203                         /*
1204                         * Phase 1:
1205                         * After burst (draining phase)
1206                         */
1207                         samples_out = US_TO_SAMPLES(
1208                                         substream->runtime->rate,
1209                                         time_delta);
1210
1211                         if (likely(MODE7_UTHR > samples_out))
1212                                 delay = MODE7_UTHR - samples_out;
1213                         else
1214                                 delay = 0;
1215                 } else {
1216                         /*
1217                         * Phase 2:
1218                         * During burst operation
1219                         */
1220                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1221
1222                         samples_out = US_TO_SAMPLES(
1223                                         substream->runtime->rate,
1224                                         time_delta);
1225                         samples_in = US_TO_SAMPLES(
1226                                         dac33->burst_rate,
1227                                         time_delta);
1228                         delay = MODE7_LTHR + samples_in - samples_out;
1229
1230                         if (unlikely(delay > MODE7_UTHR))
1231                                 delay = MODE7_UTHR;
1232                 }
1233                 break;
1234         default:
1235                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1236                                                         dac33->fifo_mode);
1237                 break;
1238         }
1239 out:
1240         return delay;
1241 }
1242
1243 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1244                 int clk_id, unsigned int freq, int dir)
1245 {
1246         struct snd_soc_codec *codec = codec_dai->codec;
1247         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1248         u8 ioc_reg, asrcb_reg;
1249
1250         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1251         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1252         switch (clk_id) {
1253         case TLV320DAC33_MCLK:
1254                 ioc_reg |= DAC33_REFSEL;
1255                 asrcb_reg |= DAC33_SRCREFSEL;
1256                 break;
1257         case TLV320DAC33_SLEEPCLK:
1258                 ioc_reg &= ~DAC33_REFSEL;
1259                 asrcb_reg &= ~DAC33_SRCREFSEL;
1260                 break;
1261         default:
1262                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1263                 break;
1264         }
1265         dac33->refclk = freq;
1266
1267         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1268         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1269
1270         return 0;
1271 }
1272
1273 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1274                              unsigned int fmt)
1275 {
1276         struct snd_soc_codec *codec = codec_dai->codec;
1277         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1278         u8 aictrl_a, aictrl_b;
1279
1280         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1281         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1282         /* set master/slave audio interface */
1283         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1284         case SND_SOC_DAIFMT_CBM_CFM:
1285                 /* Codec Master */
1286                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1287                 break;
1288         case SND_SOC_DAIFMT_CBS_CFS:
1289                 /* Codec Slave */
1290                 if (dac33->fifo_mode) {
1291                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1292                         return -EINVAL;
1293                 } else
1294                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1295                 break;
1296         default:
1297                 return -EINVAL;
1298         }
1299
1300         aictrl_a &= ~DAC33_AFMT_MASK;
1301         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1302         case SND_SOC_DAIFMT_I2S:
1303                 aictrl_a |= DAC33_AFMT_I2S;
1304                 break;
1305         case SND_SOC_DAIFMT_DSP_A:
1306                 aictrl_a |= DAC33_AFMT_DSP;
1307                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1308                 aictrl_b |= DAC33_DATA_DELAY(0);
1309                 break;
1310         case SND_SOC_DAIFMT_RIGHT_J:
1311                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1312                 break;
1313         case SND_SOC_DAIFMT_LEFT_J:
1314                 aictrl_a |= DAC33_AFMT_LEFT_J;
1315                 break;
1316         default:
1317                 dev_err(codec->dev, "Unsupported format (%u)\n",
1318                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1319                 return -EINVAL;
1320         }
1321
1322         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1323         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1324
1325         return 0;
1326 }
1327
1328 static int dac33_soc_probe(struct platform_device *pdev)
1329 {
1330         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1331         struct snd_soc_codec *codec;
1332         struct tlv320dac33_priv *dac33;
1333         int ret = 0;
1334
1335         BUG_ON(!tlv320dac33_codec);
1336
1337         codec = tlv320dac33_codec;
1338         socdev->card->codec = codec;
1339         dac33 = snd_soc_codec_get_drvdata(codec);
1340
1341         /* register pcms */
1342         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1343         if (ret < 0) {
1344                 dev_err(codec->dev, "failed to create pcms\n");
1345                 goto pcm_err;
1346         }
1347
1348         snd_soc_add_controls(codec, dac33_snd_controls,
1349                              ARRAY_SIZE(dac33_snd_controls));
1350         /* Only add the nSample controls, if we have valid IRQ number */
1351         if (dac33->irq >= 0)
1352                 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1353                                      ARRAY_SIZE(dac33_nsample_snd_controls));
1354
1355         dac33_add_widgets(codec);
1356
1357         return 0;
1358
1359 pcm_err:
1360         dac33_hard_power(codec, 0);
1361         return ret;
1362 }
1363
1364 static int dac33_soc_remove(struct platform_device *pdev)
1365 {
1366         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1367         struct snd_soc_codec *codec = socdev->card->codec;
1368
1369         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1370
1371         snd_soc_free_pcms(socdev);
1372         snd_soc_dapm_free(socdev);
1373
1374         return 0;
1375 }
1376
1377 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1378 {
1379         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1380         struct snd_soc_codec *codec = socdev->card->codec;
1381
1382         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1383
1384         return 0;
1385 }
1386
1387 static int dac33_soc_resume(struct platform_device *pdev)
1388 {
1389         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1390         struct snd_soc_codec *codec = socdev->card->codec;
1391
1392         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1393
1394         return 0;
1395 }
1396
1397 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1398         .probe = dac33_soc_probe,
1399         .remove = dac33_soc_remove,
1400         .suspend = dac33_soc_suspend,
1401         .resume = dac33_soc_resume,
1402 };
1403 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1404
1405 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1406                          SNDRV_PCM_RATE_48000)
1407 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1408
1409 static struct snd_soc_dai_ops dac33_dai_ops = {
1410         .startup        = dac33_startup,
1411         .shutdown       = dac33_shutdown,
1412         .hw_params      = dac33_hw_params,
1413         .trigger        = dac33_pcm_trigger,
1414         .delay          = dac33_dai_delay,
1415         .set_sysclk     = dac33_set_dai_sysclk,
1416         .set_fmt        = dac33_set_dai_fmt,
1417 };
1418
1419 struct snd_soc_dai dac33_dai = {
1420         .name = "tlv320dac33",
1421         .playback = {
1422                 .stream_name = "Playback",
1423                 .channels_min = 2,
1424                 .channels_max = 2,
1425                 .rates = DAC33_RATES,
1426                 .formats = DAC33_FORMATS,},
1427         .ops = &dac33_dai_ops,
1428 };
1429 EXPORT_SYMBOL_GPL(dac33_dai);
1430
1431 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1432                                      const struct i2c_device_id *id)
1433 {
1434         struct tlv320dac33_platform_data *pdata;
1435         struct tlv320dac33_priv *dac33;
1436         struct snd_soc_codec *codec;
1437         int ret, i;
1438
1439         if (client->dev.platform_data == NULL) {
1440                 dev_err(&client->dev, "Platform data not set\n");
1441                 return -ENODEV;
1442         }
1443         pdata = client->dev.platform_data;
1444
1445         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1446         if (dac33 == NULL)
1447                 return -ENOMEM;
1448
1449         codec = &dac33->codec;
1450         snd_soc_codec_set_drvdata(codec, dac33);
1451         codec->control_data = client;
1452
1453         mutex_init(&codec->mutex);
1454         mutex_init(&dac33->mutex);
1455         spin_lock_init(&dac33->lock);
1456         INIT_LIST_HEAD(&codec->dapm_widgets);
1457         INIT_LIST_HEAD(&codec->dapm_paths);
1458
1459         codec->name = "tlv320dac33";
1460         codec->owner = THIS_MODULE;
1461         codec->read = dac33_read_reg_cache;
1462         codec->write = dac33_write_locked;
1463         codec->hw_write = (hw_write_t) i2c_master_send;
1464         codec->bias_level = SND_SOC_BIAS_OFF;
1465         codec->set_bias_level = dac33_set_bias_level;
1466         codec->idle_bias_off = 1;
1467         codec->dai = &dac33_dai;
1468         codec->num_dai = 1;
1469         codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1470         codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1471                                    GFP_KERNEL);
1472         if (codec->reg_cache == NULL) {
1473                 ret = -ENOMEM;
1474                 goto error_reg;
1475         }
1476
1477         i2c_set_clientdata(client, dac33);
1478
1479         dac33->power_gpio = pdata->power_gpio;
1480         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1481         /* Pre calculate the burst rate */
1482         dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1483         dac33->keep_bclk = pdata->keep_bclk;
1484         dac33->irq = client->irq;
1485         dac33->nsample = NSAMPLE_MAX;
1486         dac33->nsample_max = NSAMPLE_MAX;
1487         /* Disable FIFO use by default */
1488         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1489
1490         tlv320dac33_codec = codec;
1491
1492         codec->dev = &client->dev;
1493         dac33_dai.dev = codec->dev;
1494
1495         /* Check if the reset GPIO number is valid and request it */
1496         if (dac33->power_gpio >= 0) {
1497                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1498                 if (ret < 0) {
1499                         dev_err(codec->dev,
1500                                 "Failed to request reset GPIO (%d)\n",
1501                                 dac33->power_gpio);
1502                         snd_soc_unregister_dai(&dac33_dai);
1503                         snd_soc_unregister_codec(codec);
1504                         goto error_gpio;
1505                 }
1506                 gpio_direction_output(dac33->power_gpio, 0);
1507         }
1508
1509         /* Check if the IRQ number is valid and request it */
1510         if (dac33->irq >= 0) {
1511                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1512                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1513                                   codec->name, codec);
1514                 if (ret < 0) {
1515                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1516                                                 dac33->irq, ret);
1517                         dac33->irq = -1;
1518                 }
1519                 if (dac33->irq != -1) {
1520                         /* Setup work queue */
1521                         dac33->dac33_wq =
1522                                 create_singlethread_workqueue("tlv320dac33");
1523                         if (dac33->dac33_wq == NULL) {
1524                                 free_irq(dac33->irq, &dac33->codec);
1525                                 ret = -ENOMEM;
1526                                 goto error_wq;
1527                         }
1528
1529                         INIT_WORK(&dac33->work, dac33_work);
1530                 }
1531         }
1532
1533         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1534                 dac33->supplies[i].supply = dac33_supply_names[i];
1535
1536         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1537                                  dac33->supplies);
1538
1539         if (ret != 0) {
1540                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1541                 goto err_get;
1542         }
1543
1544         /* Read the tlv320dac33 ID registers */
1545         ret = dac33_hard_power(codec, 1);
1546         if (ret != 0) {
1547                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1548                 goto error_codec;
1549         }
1550         dac33_read_id(codec);
1551         dac33_hard_power(codec, 0);
1552
1553         ret = snd_soc_register_codec(codec);
1554         if (ret != 0) {
1555                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1556                 goto error_codec;
1557         }
1558
1559         ret = snd_soc_register_dai(&dac33_dai);
1560         if (ret != 0) {
1561                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1562                 snd_soc_unregister_codec(codec);
1563                 goto error_codec;
1564         }
1565
1566         return ret;
1567
1568 error_codec:
1569         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1570 err_get:
1571         if (dac33->irq >= 0) {
1572                 free_irq(dac33->irq, &dac33->codec);
1573                 destroy_workqueue(dac33->dac33_wq);
1574         }
1575 error_wq:
1576         if (dac33->power_gpio >= 0)
1577                 gpio_free(dac33->power_gpio);
1578 error_gpio:
1579         kfree(codec->reg_cache);
1580 error_reg:
1581         tlv320dac33_codec = NULL;
1582         kfree(dac33);
1583
1584         return ret;
1585 }
1586
1587 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1588 {
1589         struct tlv320dac33_priv *dac33;
1590
1591         dac33 = i2c_get_clientdata(client);
1592
1593         if (unlikely(dac33->chip_power))
1594                 dac33_hard_power(&dac33->codec, 0);
1595
1596         if (dac33->power_gpio >= 0)
1597                 gpio_free(dac33->power_gpio);
1598         if (dac33->irq >= 0)
1599                 free_irq(dac33->irq, &dac33->codec);
1600
1601         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1602
1603         destroy_workqueue(dac33->dac33_wq);
1604         snd_soc_unregister_dai(&dac33_dai);
1605         snd_soc_unregister_codec(&dac33->codec);
1606         kfree(dac33->codec.reg_cache);
1607         kfree(dac33);
1608         tlv320dac33_codec = NULL;
1609
1610         return 0;
1611 }
1612
1613 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1614         {
1615                 .name = "tlv320dac33",
1616                 .driver_data = 0,
1617         },
1618         { },
1619 };
1620
1621 static struct i2c_driver tlv320dac33_i2c_driver = {
1622         .driver = {
1623                 .name = "tlv320dac33",
1624                 .owner = THIS_MODULE,
1625         },
1626         .probe          = dac33_i2c_probe,
1627         .remove         = __devexit_p(dac33_i2c_remove),
1628         .id_table       = tlv320dac33_i2c_id,
1629 };
1630
1631 static int __init dac33_module_init(void)
1632 {
1633         int r;
1634         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1635         if (r < 0) {
1636                 printk(KERN_ERR "DAC33: driver registration failed\n");
1637                 return r;
1638         }
1639         return 0;
1640 }
1641 module_init(dac33_module_init);
1642
1643 static void __exit dac33_module_exit(void)
1644 {
1645         i2c_del_driver(&tlv320dac33_i2c_driver);
1646 }
1647 module_exit(dac33_module_exit);
1648
1649
1650 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1651 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1652 MODULE_LICENSE("GPL");