2 * Common code for ADAU1X61 and ADAU1X81 codecs
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <sound/core.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/spi/spi.h>
22 #include <linux/regmap.h>
27 static const char * const adau17x1_capture_mixer_boost_text[] = {
28 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
31 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
32 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
34 static const char * const adau17x1_mic_bias_mode_text[] = {
35 "Normal operation", "High performance",
38 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
39 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
41 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
43 static const struct snd_kcontrol_new adau17x1_controls[] = {
44 SOC_DOUBLE_R_TLV("Digital Capture Volume",
45 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
46 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
47 0, 0xff, 1, adau17x1_digital_tlv),
48 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
49 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
51 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
53 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
56 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
58 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
61 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
62 struct snd_kcontrol *kcontrol, int event)
64 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
65 struct adau *adau = snd_soc_codec_get_drvdata(codec);
68 if (SND_SOC_DAPM_EVENT_ON(event)) {
69 adau->pll_regs[5] = 1;
71 adau->pll_regs[5] = 0;
72 /* Bypass the PLL when disabled, otherwise registers will become
74 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
75 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
78 /* The PLL register is 6 bytes long and can only be written at once. */
79 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
80 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
82 if (SND_SOC_DAPM_EVENT_ON(event)) {
84 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
85 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
86 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
92 static const char * const adau17x1_mono_stereo_text[] = {
94 "Mono Left Channel (L+R)",
95 "Mono Right Channel (L+R)",
99 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
100 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
102 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
103 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
105 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
106 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
107 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
109 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
111 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
113 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
115 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
118 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
119 &adau17x1_dac_mode_mux),
120 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
121 &adau17x1_dac_mode_mux),
123 SND_SOC_DAPM_ADC("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0),
124 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
125 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
126 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
129 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
130 { "Left Decimator", NULL, "SYSCLK" },
131 { "Right Decimator", NULL, "SYSCLK" },
132 { "Left DAC", NULL, "SYSCLK" },
133 { "Right DAC", NULL, "SYSCLK" },
134 { "Capture", NULL, "SYSCLK" },
135 { "Playback", NULL, "SYSCLK" },
137 { "Left DAC", NULL, "Left DAC Mode Mux" },
138 { "Right DAC", NULL, "Right DAC Mode Mux" },
140 { "Capture", NULL, "AIFCLK" },
141 { "Playback", NULL, "AIFCLK" },
144 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
145 "SYSCLK", NULL, "PLL",
149 * The MUX register for the Capture and Playback MUXs selects either DSP as
150 * source/destination or one of the TDM slots. The TDM slot is selected via
151 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
152 * directly to the DAI interface with this control.
154 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
155 struct snd_ctl_elem_value *ucontrol)
157 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
158 struct adau *adau = snd_soc_codec_get_drvdata(codec);
159 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
160 struct snd_soc_dapm_update update;
161 unsigned int stream = e->shift_l;
162 unsigned int val, change;
165 if (ucontrol->value.enumerated.item[0] >= e->items)
168 switch (ucontrol->value.enumerated.item[0]) {
171 adau->dsp_bypass[stream] = false;
174 val = (adau->tdm_slot[stream] * 2) + 1;
175 adau->dsp_bypass[stream] = true;
179 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
180 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
182 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
184 change = snd_soc_test_bits(codec, reg, 0xff, val);
186 update.kcontrol = kcontrol;
191 snd_soc_dapm_mux_update_power(&codec->dapm, kcontrol,
192 ucontrol->value.enumerated.item[0], e, &update);
198 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
201 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
202 struct adau *adau = snd_soc_codec_get_drvdata(codec);
203 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
204 unsigned int stream = e->shift_l;
205 unsigned int reg, val;
208 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
209 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
211 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
213 ret = regmap_read(adau->regmap, reg, &val);
219 ucontrol->value.enumerated.item[0] = val;
224 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
225 const struct snd_kcontrol_new _name = \
226 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
227 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
228 ARRAY_SIZE(_text), _text), \
229 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
231 static const char * const adau17x1_dac_mux_text[] = {
236 static const char * const adau17x1_capture_mux_text[] = {
241 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
242 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
244 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
245 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
247 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
248 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
249 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
251 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
253 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
254 &adau17x1_capture_mux),
257 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
258 { "DAC Playback Mux", "DSP", "DSP" },
259 { "DAC Playback Mux", "AIFIN", "Playback" },
261 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
262 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
263 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
264 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
265 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
266 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
268 { "Capture Mux", "DSP", "DSP" },
269 { "Capture Mux", "Decimator", "Left Decimator" },
270 { "Capture Mux", "Decimator", "Right Decimator" },
272 { "Capture", NULL, "Capture Mux" },
274 { "DSP", NULL, "DSP Siggen" },
276 { "DSP", NULL, "Left Decimator" },
277 { "DSP", NULL, "Right Decimator" },
280 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
281 { "Left DAC Mode Mux", "Stereo", "Playback" },
282 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
283 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
284 { "Right DAC Mode Mux", "Stereo", "Playback" },
285 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
286 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
287 { "Capture", NULL, "Left Decimator" },
288 { "Capture", NULL, "Right Decimator" },
291 bool adau17x1_has_dsp(struct adau *adau)
293 switch (adau->type) {
302 EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
304 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
305 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
307 struct snd_soc_codec *codec = dai->codec;
308 struct adau *adau = snd_soc_codec_get_drvdata(codec);
309 unsigned int val, div, dsp_div;
312 if (adau->clk_src == ADAU17X1_CLK_SRC_PLL)
313 freq = adau->pll_freq;
317 if (freq % params_rate(params) != 0)
320 switch (freq / params_rate(params)) {
325 case 6144: /* fs / 6 */
329 case 4096: /* fs / 4 */
333 case 3072: /* fs / 3 */
337 case 2048: /* fs / 2 */
341 case 1536: /* fs / 1.5 */
345 case 512: /* fs / 0.5 */
353 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
354 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
355 if (adau17x1_has_dsp(adau)) {
356 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
357 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
360 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
363 switch (params_width(params)) {
365 val = ADAU17X1_SERIAL_PORT1_DELAY16;
368 val = ADAU17X1_SERIAL_PORT1_DELAY8;
371 val = ADAU17X1_SERIAL_PORT1_DELAY0;
377 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
378 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
381 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
382 int source, unsigned int freq_in, unsigned int freq_out)
384 struct snd_soc_codec *codec = dai->codec;
385 struct adau *adau = snd_soc_codec_get_drvdata(codec);
386 unsigned int r, n, m, i, j;
390 if (freq_in < 8000000 || freq_in > 27000000)
399 if (freq_out % freq_in != 0) {
400 div = DIV_ROUND_UP(freq_in, 13500000);
402 r = freq_out / freq_in;
403 i = freq_out % freq_in;
409 r = freq_out / freq_in;
414 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
418 adau->pll_regs[0] = m >> 8;
419 adau->pll_regs[1] = m & 0xff;
420 adau->pll_regs[2] = n >> 8;
421 adau->pll_regs[3] = n & 0xff;
422 adau->pll_regs[4] = (r << 3) | (div << 1);
424 adau->pll_regs[4] |= 1; /* Fractional mode */
426 /* The PLL register is 6 bytes long and can only be written at once. */
427 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
428 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
432 adau->pll_freq = freq_out;
437 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
438 int clk_id, unsigned int freq, int dir)
440 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
441 struct snd_soc_dapm_context *dapm = &dai->codec->dapm;
444 case ADAU17X1_CLK_SRC_MCLK:
445 case ADAU17X1_CLK_SRC_PLL:
453 if (adau->clk_src != clk_id) {
454 if (clk_id == ADAU17X1_CLK_SRC_PLL) {
455 snd_soc_dapm_add_routes(dapm,
456 &adau17x1_dapm_pll_route, 1);
458 snd_soc_dapm_del_routes(dapm,
459 &adau17x1_dapm_pll_route, 1);
463 adau->clk_src = clk_id;
468 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
471 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
472 unsigned int ctrl0, ctrl1;
475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
476 case SND_SOC_DAIFMT_CBM_CFM:
477 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
480 case SND_SOC_DAIFMT_CBS_CFS:
482 adau->master = false;
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_I2S:
491 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
493 case SND_SOC_DAIFMT_LEFT_J:
494 case SND_SOC_DAIFMT_RIGHT_J:
496 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
498 case SND_SOC_DAIFMT_DSP_A:
500 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
501 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
503 case SND_SOC_DAIFMT_DSP_B:
505 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
506 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
512 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
513 case SND_SOC_DAIFMT_NB_NF:
515 case SND_SOC_DAIFMT_IB_NF:
516 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
518 case SND_SOC_DAIFMT_NB_IF:
519 lrclk_pol = !lrclk_pol;
521 case SND_SOC_DAIFMT_IB_IF:
522 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
523 lrclk_pol = !lrclk_pol;
530 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
532 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
533 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
535 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
540 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
541 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
543 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
544 unsigned int ser_ctrl0, ser_ctrl1;
545 unsigned int conv_ctrl0, conv_ctrl1;
557 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
560 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
563 if (adau->type == ADAU1361)
566 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
572 switch (slot_width * slots) {
574 if (adau->type == ADAU1761)
577 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
580 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
583 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
586 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
589 if (adau->type == ADAU1361)
592 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
600 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
601 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
604 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
605 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
608 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
609 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
612 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
613 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
621 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
622 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
625 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
626 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
629 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
630 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
633 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
634 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
640 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
641 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
642 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
643 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
644 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
645 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
646 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
647 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
649 if (!adau17x1_has_dsp(adau))
652 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
653 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
654 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
657 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
658 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
659 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
665 const struct snd_soc_dai_ops adau17x1_dai_ops = {
666 .hw_params = adau17x1_hw_params,
667 .set_sysclk = adau17x1_set_dai_sysclk,
668 .set_fmt = adau17x1_set_dai_fmt,
669 .set_pll = adau17x1_set_dai_pll,
670 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
672 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
674 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
675 enum adau17x1_micbias_voltage micbias)
677 struct adau *adau = snd_soc_codec_get_drvdata(codec);
680 case ADAU17X1_MICBIAS_0_90_AVDD:
681 case ADAU17X1_MICBIAS_0_65_AVDD:
687 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
689 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
691 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
694 case ADAU17X1_CLOCK_CONTROL:
695 case ADAU17X1_PLL_CONTROL:
696 case ADAU17X1_REC_POWER_MGMT:
697 case ADAU17X1_MICBIAS:
698 case ADAU17X1_SERIAL_PORT0:
699 case ADAU17X1_SERIAL_PORT1:
700 case ADAU17X1_CONVERTER0:
701 case ADAU17X1_CONVERTER1:
702 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
703 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
704 case ADAU17X1_ADC_CONTROL:
705 case ADAU17X1_PLAY_POWER_MGMT:
706 case ADAU17X1_DAC_CONTROL0:
707 case ADAU17X1_DAC_CONTROL1:
708 case ADAU17X1_DAC_CONTROL2:
709 case ADAU17X1_SERIAL_PORT_PAD:
710 case ADAU17X1_CONTROL_PORT_PAD0:
711 case ADAU17X1_CONTROL_PORT_PAD1:
712 case ADAU17X1_DSP_SAMPLING_RATE:
713 case ADAU17X1_SERIAL_INPUT_ROUTE:
714 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
715 case ADAU17X1_DSP_ENABLE:
716 case ADAU17X1_DSP_RUN:
717 case ADAU17X1_SERIAL_SAMPLING_RATE:
724 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
726 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
728 /* SigmaDSP parameter and program memory */
733 /* The PLL register is 6 bytes long */
734 case ADAU17X1_PLL_CONTROL:
735 case ADAU17X1_PLL_CONTROL + 1:
736 case ADAU17X1_PLL_CONTROL + 2:
737 case ADAU17X1_PLL_CONTROL + 3:
738 case ADAU17X1_PLL_CONTROL + 4:
739 case ADAU17X1_PLL_CONTROL + 5:
747 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
749 int adau17x1_load_firmware(struct adau *adau, struct device *dev,
750 const char *firmware)
755 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
759 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
760 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
762 ret = process_sigma_firmware_regmap(dev, adau->regmap, firmware);
764 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
767 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
771 EXPORT_SYMBOL_GPL(adau17x1_load_firmware);
773 int adau17x1_add_widgets(struct snd_soc_codec *codec)
775 struct adau *adau = snd_soc_codec_get_drvdata(codec);
778 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
779 ARRAY_SIZE(adau17x1_controls));
782 ret = snd_soc_dapm_new_controls(&codec->dapm, adau17x1_dapm_widgets,
783 ARRAY_SIZE(adau17x1_dapm_widgets));
787 if (adau17x1_has_dsp(adau)) {
788 ret = snd_soc_dapm_new_controls(&codec->dapm,
789 adau17x1_dsp_dapm_widgets,
790 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
794 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
796 int adau17x1_add_routes(struct snd_soc_codec *codec)
798 struct adau *adau = snd_soc_codec_get_drvdata(codec);
801 ret = snd_soc_dapm_add_routes(&codec->dapm, adau17x1_dapm_routes,
802 ARRAY_SIZE(adau17x1_dapm_routes));
806 if (adau17x1_has_dsp(adau)) {
807 ret = snd_soc_dapm_add_routes(&codec->dapm,
808 adau17x1_dsp_dapm_routes,
809 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
811 ret = snd_soc_dapm_add_routes(&codec->dapm,
812 adau17x1_no_dsp_dapm_routes,
813 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
817 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
819 int adau17x1_resume(struct snd_soc_codec *codec)
821 struct adau *adau = snd_soc_codec_get_drvdata(codec);
823 if (adau->switch_mode)
824 adau->switch_mode(codec->dev);
826 regcache_sync(adau->regmap);
830 EXPORT_SYMBOL_GPL(adau17x1_resume);
832 int adau17x1_probe(struct device *dev, struct regmap *regmap,
833 enum adau17x1_type type, void (*switch_mode)(struct device *dev))
838 return PTR_ERR(regmap);
840 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
844 adau->regmap = regmap;
845 adau->switch_mode = switch_mode;
848 dev_set_drvdata(dev, adau);
855 EXPORT_SYMBOL_GPL(adau17x1_probe);
857 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
858 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
859 MODULE_LICENSE("GPL");