sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41 #include <linux/init.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/math64.h>
  48 #include <asm/io.h>
  49
  50 #include <sound/core.h>
  51 #include <sound/control.h>
  52 #include <sound/pcm.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/info.h>
  55 #include <sound/asoundef.h>
  56 #include <sound/rawmidi.h>
  57 #include <sound/hwdep.h>
  58 #include <sound/initval.h>
  59
  60 #include <sound/hdspm.h>
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  68
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  71
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  74
  75
  76 MODULE_AUTHOR
  77 (
  78         "Winfried Ritsch <ritsch_AT_iem.at>, "
  79         "Paul Davis <paul@linuxaudiosystems.com>, "
  80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  81         "Remy Bruno <remy.bruno@trinnov.com>, "
  82         "Florian Faber <faberman@linuxproaudio.org>, "
  83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
  84 );
  85 MODULE_DESCRIPTION("RME HDSPM");
  86 MODULE_LICENSE("GPL");
  87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  88
  89 /* --- Write registers. ---
  90   These are defined as byte-offsets from the iobase value.  */
  91
  92 #define HDSPM_WR_SETTINGS             0
  93 #define HDSPM_outputBufferAddress    32
  94 #define HDSPM_inputBufferAddress     36
  95 #define HDSPM_controlRegister        64
  96 #define HDSPM_interruptConfirmation  96
  97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  98 #define HDSPM_freqReg                256  /* for AES32 */
  99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 100 #define HDSPM_midiDataOut1           356
 101 #define HDSPM_eeprom_wr              384  /* for AES32 */
 102
 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
 104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 106
 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 109 #define HDSPM_pageAddressBufferOut       8192
 110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 111
 112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 113
 114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 115
 116 /* --- Read registers. ---
 117    These are defined as byte-offsets from the iobase value */
 118 #define HDSPM_statusRegister    0
 119 /*#define HDSPM_statusRegister2  96 */
 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 121  * offset 192, for AES32 *and* MADI
 122  * => need to check that offset 192 is working on MADI */
 123 #define HDSPM_statusRegister2  192
 124 #define HDSPM_timecodeRegister 128
 125
 126 /* AIO, RayDAT */
 127 #define HDSPM_RD_STATUS_0 0
 128 #define HDSPM_RD_STATUS_1 64
 129 #define HDSPM_RD_STATUS_2 128
 130 #define HDSPM_RD_STATUS_3 192
 131
 132 #define HDSPM_RD_TCO           256
 133 #define HDSPM_RD_PLL_FREQ      512
 134 #define HDSPM_WR_TCO           128
 135
 136 #define HDSPM_TCO1_TCO_lock                     0x00000001
 137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 143
 144 #define HDSPM_TCO1_set_TC                       0x00000100
 145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 148
 149 #define HDSPM_TCO2_TC_run                       0x00010000
 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 155 #define HDSPM_TCO2_set_flywheel                 0x00400000
 156
 157 #define HDSPM_TCO2_set_01_4                     0x01000000
 158 #define HDSPM_TCO2_set_pull_down                0x02000000
 159 #define HDSPM_TCO2_set_pull_up                  0x04000000
 160 #define HDSPM_TCO2_set_freq                     0x08000000
 161 #define HDSPM_TCO2_set_term_75R                 0x10000000
 162 #define HDSPM_TCO2_set_input_LSB                0x20000000
 163 #define HDSPM_TCO2_set_input_MSB                0x40000000
 164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 165
 166
 167 #define HDSPM_midiDataOut0    352
 168 #define HDSPM_midiDataOut1    356
 169 #define HDSPM_midiDataOut2    368
 170
 171 #define HDSPM_midiDataIn0     360
 172 #define HDSPM_midiDataIn1     364
 173 #define HDSPM_midiDataIn2     372
 174 #define HDSPM_midiDataIn3     376
 175
 176 /* status is data bytes in MIDI-FIFO (0-128) */
 177 #define HDSPM_midiStatusOut0  384
 178 #define HDSPM_midiStatusOut1  388
 179 #define HDSPM_midiStatusOut2  400
 180
 181 #define HDSPM_midiStatusIn0   392
 182 #define HDSPM_midiStatusIn1   396
 183 #define HDSPM_midiStatusIn2   404
 184 #define HDSPM_midiStatusIn3   408
 185
 186
 187 /* the meters are regular i/o-mapped registers, but offset
 188    considerably from the rest. the peak registers are reset
 189    when read; the least-significant 4 bits are full-scale counters;
 190    the actual peak value is in the most-significant 24 bits.
 191 */
 192
 193 #define HDSPM_MADI_INPUT_PEAK           4096
 194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 195 #define HDSPM_MADI_OUTPUT_PEAK          4608
 196
 197 #define HDSPM_MADI_INPUT_RMS_L          6144
 198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 200
 201 #define HDSPM_MADI_INPUT_RMS_H          7168
 202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 204
 205 /* --- Control Register bits --------- */
 206 #define HDSPM_Start                (1<<0) /* start engine */
 207
 208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 211
 212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 214                                           register [RayDAT, AIO] */
 215
 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 217
 218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 222
 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 225                                      56channelMODE=0 */ /* MADI ONLY*/
 226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 227
 228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 229                                      0=off, 1=on  */ /* MADI ONLY */
 230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 231
 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 233                                     * -- MADI ONLY
 234                                     */
 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 236
 237 #define HDSPM_SyncRef2     (1<<13)
 238 #define HDSPM_SyncRef3     (1<<25)
 239
 240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 242                                       AES additional bits in
 243                                       lower 5 Audiodatabits ??? */
 244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 246
 247 #define HDSPM_Midi0InterruptEnable 0x0400000
 248 #define HDSPM_Midi1InterruptEnable 0x0800000
 249 #define HDSPM_Midi2InterruptEnable 0x0200000
 250 #define HDSPM_Midi3InterruptEnable 0x4000000
 251
 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 253 #define HDSPe_FLOAT_FORMAT         0x2000000
 254
 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 258
 259 #define HDSPM_wclk_sel (1<<30)
 260
 261 /* --- bit helper defines */
 262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 266 #define HDSPM_InputOptical   0
 267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 270
 271 #define HDSPM_c0_SyncRef0      0x2
 272 #define HDSPM_c0_SyncRef1      0x4
 273 #define HDSPM_c0_SyncRef2      0x8
 274 #define HDSPM_c0_SyncRef3      0x10
 275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 277
 278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 280 #define HDSPM_SYNC_FROM_TCO     2
 281 #define HDSPM_SYNC_FROM_SYNC_IN 3
 282
 283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 289                                 HDSPM_Frequency0)
 290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 293                                  HDSPM_Frequency0)
 294
 295
 296 /* Synccheck Status */
 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 298 #define HDSPM_SYNC_CHECK_LOCK    1
 299 #define HDSPM_SYNC_CHECK_SYNC    2
 300
 301 /* AutoSync References - used by "autosync_ref" control switch */
 302 #define HDSPM_AUTOSYNC_FROM_WORD      0
 303 #define HDSPM_AUTOSYNC_FROM_MADI      1
 304 #define HDSPM_AUTOSYNC_FROM_TCO       2
 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 306 #define HDSPM_AUTOSYNC_FROM_NONE      4
 307
 308 /* Possible sources of MADI input */
 309 #define HDSPM_OPTICAL 0         /* optical   */
 310 #define HDSPM_COAXIAL 1         /* BNC */
 311
 312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 314
 315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 317
 318 /* --- control2 register bits --- */
 319 #define HDSPM_TMS             (1<<0)
 320 #define HDSPM_TCK             (1<<1)
 321 #define HDSPM_TDI             (1<<2)
 322 #define HDSPM_JTAG            (1<<3)
 323 #define HDSPM_PWDN            (1<<4)
 324 #define HDSPM_PROGRAM         (1<<5)
 325 #define HDSPM_CONFIG_MODE_0   (1<<6)
 326 #define HDSPM_CONFIG_MODE_1   (1<<7)
 327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 329 #define HDSPM_RD_MULTIPLE     (1<<10)
 330
 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 332      that do not conflict with specific bits for AES32 seem to be valid also
 333      for the AES32
 334  */
 335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 338                                          * (like inp0)
 339                                          */
 340
 341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 343
 344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
 345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
 346
 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
 349
 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 351                         /* since 64byte accurate, last 6 bits are not used */
 352
 353
 354
 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 356
 357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 361
 362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 363                                          * Interrupt
 364                                          */
 365 #define HDSPM_tco_detect         0x08000000
 366 #define HDSPM_tco_lock           0x20000000
 367
 368 #define HDSPM_s2_tco_detect      0x00000040
 369 #define HDSPM_s2_AEBO_D          0x00000080
 370 #define HDSPM_s2_AEBI_D          0x00000100
 371
 372
 373 #define HDSPM_midi0IRQPending    0x40000000
 374 #define HDSPM_midi1IRQPending    0x80000000
 375 #define HDSPM_midi2IRQPending    0x20000000
 376 #define HDSPM_midi2IRQPendingAES 0x00000020
 377 #define HDSPM_midi3IRQPending    0x00200000
 378
 379 /* --- status bit helpers */
 380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 391
 392 /* Status2 Register bits */ /* MADI ONLY */
 393
 394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 396 #define HDSPM_version2 (1<<2)
 397
 398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 400
 401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
 404 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
 405
 406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 407 #define HDSPM_SyncRef1 0x20000
 408
 409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 412
 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 414
 415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 416 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 417 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 418 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 419 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 420 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 421 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 422
 423 #define HDSPM_status1_F_0 0x0400000
 424 #define HDSPM_status1_F_1 0x0800000
 425 #define HDSPM_status1_F_2 0x1000000
 426 #define HDSPM_status1_F_3 0x2000000
 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 428
 429
 430 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 431                                     HDSPM_SelSyncRef2)
 432 #define HDSPM_SelSyncRef_WORD      0
 433 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 434 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 435 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 436 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 437                                     HDSPM_SelSyncRef2)
 438
 439 /*
 440    For AES32, bits for status, status2 and timecode are different
 441 */
 442 /* status */
 443 #define HDSPM_AES32_wcLock      0x0200000
 444 #define HDSPM_AES32_wcFreq_bit  22
 445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 446   HDSPM_bit2freq */
 447 #define HDSPM_AES32_syncref_bit  16
 448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 449
 450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
 460
 461 /*  status2 */
 462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 463 #define HDSPM_LockAES   0x80
 464 #define HDSPM_LockAES1  0x80
 465 #define HDSPM_LockAES2  0x40
 466 #define HDSPM_LockAES3  0x20
 467 #define HDSPM_LockAES4  0x10
 468 #define HDSPM_LockAES5  0x8
 469 #define HDSPM_LockAES6  0x4
 470 #define HDSPM_LockAES7  0x2
 471 #define HDSPM_LockAES8  0x1
 472 /*
 473    Timecode
 474    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 475    AES i+1
 476  bits 3210
 477       0001  32kHz
 478       0010  44.1kHz
 479       0011  48kHz
 480       0100  64kHz
 481       0101  88.2kHz
 482       0110  96kHz
 483       0111  128kHz
 484       1000  176.4kHz
 485       1001  192kHz
 486   NB: Timecode register doesn't seem to work on AES32 card revision 230
 487 */
 488
 489 /* Mixer Values */
 490 #define UNITY_GAIN          32768       /* = 65536/2 */
 491 #define MINUS_INFINITY_GAIN 0
 492
 493 /* Number of channels for different Speed Modes */
 494 #define MADI_SS_CHANNELS       64
 495 #define MADI_DS_CHANNELS       32
 496 #define MADI_QS_CHANNELS       16
 497
 498 #define RAYDAT_SS_CHANNELS     36
 499 #define RAYDAT_DS_CHANNELS     20
 500 #define RAYDAT_QS_CHANNELS     12
 501
 502 #define AIO_IN_SS_CHANNELS        14
 503 #define AIO_IN_DS_CHANNELS        10
 504 #define AIO_IN_QS_CHANNELS        8
 505 #define AIO_OUT_SS_CHANNELS        16
 506 #define AIO_OUT_DS_CHANNELS        12
 507 #define AIO_OUT_QS_CHANNELS        10
 508
 509 #define AES32_CHANNELS          16
 510
 511 /* the size of a substream (1 mono data stream) */
 512 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 513 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 514
 515 /* the size of the area we need to allocate for DMA transfers. the
 516    size is the same regardless of the number of channels, and
 517    also the latency to use.
 518    for one direction !!!
 519 */
 520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 522
 523 /* revisions >= 230 indicate AES32 card */
 524 #define HDSPM_MADI_REV          210
 525 #define HDSPM_RAYDAT_REV        211
 526 #define HDSPM_AIO_REV           212
 527 #define HDSPM_MADIFACE_REV      213
 528 #define HDSPM_AES_REV           240
 529 #define HDSPM_AES32_REV         234
 530 #define HDSPM_AES32_OLD_REV     233
 531
 532 /* speed factor modes */
 533 #define HDSPM_SPEED_SINGLE 0
 534 #define HDSPM_SPEED_DOUBLE 1
 535 #define HDSPM_SPEED_QUAD   2
 536
 537 /* names for speed modes */
 538 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 539
 540 static char *texts_autosync_aes_tco[] = { "Word Clock",
 541                                           "AES1", "AES2", "AES3", "AES4",
 542                                           "AES5", "AES6", "AES7", "AES8",
 543                                           "TCO" };
 544 static char *texts_autosync_aes[] = { "Word Clock",
 545                                       "AES1", "AES2", "AES3", "AES4",
 546                                       "AES5", "AES6", "AES7", "AES8" };
 547 static char *texts_autosync_madi_tco[] = { "Word Clock",
 548                                            "MADI", "TCO", "Sync In" };
 549 static char *texts_autosync_madi[] = { "Word Clock",
 550                                        "MADI", "Sync In" };
 551
 552 static char *texts_autosync_raydat_tco[] = {
 553         "Word Clock",
 554         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 555         "AES", "SPDIF", "TCO", "Sync In"
 556 };
 557 static char *texts_autosync_raydat[] = {
 558         "Word Clock",
 559         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 560         "AES", "SPDIF", "Sync In"
 561 };
 562 static char *texts_autosync_aio_tco[] = {
 563         "Word Clock",
 564         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 565 };
 566 static char *texts_autosync_aio[] = { "Word Clock",
 567                                       "ADAT", "AES", "SPDIF", "Sync In" };
 568
 569 static char *texts_freq[] = {
 570         "No Lock",
 571         "32 kHz",
 572         "44.1 kHz",
 573         "48 kHz",
 574         "64 kHz",
 575         "88.2 kHz",
 576         "96 kHz",
 577         "128 kHz",
 578         "176.4 kHz",
 579         "192 kHz"
 580 };
 581
 582 static char *texts_ports_madi[] = {
 583         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 584         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 585         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 586         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 587         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 588         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 589         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 590         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 591         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 592         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 593         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 594 };
 595
 596
 597 static char *texts_ports_raydat_ss[] = {
 598         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 599         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 600         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 601         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 602         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 603         "ADAT4.7", "ADAT4.8",
 604         "AES.L", "AES.R",
 605         "SPDIF.L", "SPDIF.R"
 606 };
 607
 608 static char *texts_ports_raydat_ds[] = {
 609         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 610         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 611         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 612         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 613         "AES.L", "AES.R",
 614         "SPDIF.L", "SPDIF.R"
 615 };
 616
 617 static char *texts_ports_raydat_qs[] = {
 618         "ADAT1.1", "ADAT1.2",
 619         "ADAT2.1", "ADAT2.2",
 620         "ADAT3.1", "ADAT3.2",
 621         "ADAT4.1", "ADAT4.2",
 622         "AES.L", "AES.R",
 623         "SPDIF.L", "SPDIF.R"
 624 };
 625
 626
 627 static char *texts_ports_aio_in_ss[] = {
 628         "Analogue.L", "Analogue.R",
 629         "AES.L", "AES.R",
 630         "SPDIF.L", "SPDIF.R",
 631         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 632         "ADAT.7", "ADAT.8"
 633 };
 634
 635 static char *texts_ports_aio_out_ss[] = {
 636         "Analogue.L", "Analogue.R",
 637         "AES.L", "AES.R",
 638         "SPDIF.L", "SPDIF.R",
 639         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 640         "ADAT.7", "ADAT.8",
 641         "Phone.L", "Phone.R"
 642 };
 643
 644 static char *texts_ports_aio_in_ds[] = {
 645         "Analogue.L", "Analogue.R",
 646         "AES.L", "AES.R",
 647         "SPDIF.L", "SPDIF.R",
 648         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
 649 };
 650
 651 static char *texts_ports_aio_out_ds[] = {
 652         "Analogue.L", "Analogue.R",
 653         "AES.L", "AES.R",
 654         "SPDIF.L", "SPDIF.R",
 655         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 656         "Phone.L", "Phone.R"
 657 };
 658
 659 static char *texts_ports_aio_in_qs[] = {
 660         "Analogue.L", "Analogue.R",
 661         "AES.L", "AES.R",
 662         "SPDIF.L", "SPDIF.R",
 663         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
 664 };
 665
 666 static char *texts_ports_aio_out_qs[] = {
 667         "Analogue.L", "Analogue.R",
 668         "AES.L", "AES.R",
 669         "SPDIF.L", "SPDIF.R",
 670         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 671         "Phone.L", "Phone.R"
 672 };
 673
 674 static char *texts_ports_aes32[] = {
 675         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 676         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 677         "AES.15", "AES.16"
 678 };
 679
 680 /* These tables map the ALSA channels 1..N to the channels that we
 681    need to use in order to find the relevant channel buffer. RME
 682    refers to this kind of mapping as between "the ADAT channel and
 683    the DMA channel." We index it using the logical audio channel,
 684    and the value is the DMA channel (i.e. channel buffer number)
 685    where the data for that channel can be read/written from/to.
 686 */
 687
 688 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 689         0, 1, 2, 3, 4, 5, 6, 7,
 690         8, 9, 10, 11, 12, 13, 14, 15,
 691         16, 17, 18, 19, 20, 21, 22, 23,
 692         24, 25, 26, 27, 28, 29, 30, 31,
 693         32, 33, 34, 35, 36, 37, 38, 39,
 694         40, 41, 42, 43, 44, 45, 46, 47,
 695         48, 49, 50, 51, 52, 53, 54, 55,
 696         56, 57, 58, 59, 60, 61, 62, 63
 697 };
 698
 699 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 700         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 701         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 702         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 703         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 704         0, 1,                   /* AES */
 705         2, 3,                   /* SPDIF */
 706         -1, -1, -1, -1,
 707         -1, -1, -1, -1, -1, -1, -1, -1,
 708         -1, -1, -1, -1, -1, -1, -1, -1,
 709         -1, -1, -1, -1, -1, -1, -1, -1,
 710 };
 711
 712 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 713         4, 5, 6, 7,             /* ADAT 1 */
 714         8, 9, 10, 11,           /* ADAT 2 */
 715         12, 13, 14, 15,         /* ADAT 3 */
 716         16, 17, 18, 19,         /* ADAT 4 */
 717         0, 1,                   /* AES */
 718         2, 3,                   /* SPDIF */
 719         -1, -1, -1, -1,
 720         -1, -1, -1, -1, -1, -1, -1, -1,
 721         -1, -1, -1, -1, -1, -1, -1, -1,
 722         -1, -1, -1, -1, -1, -1, -1, -1,
 723         -1, -1, -1, -1, -1, -1, -1, -1,
 724         -1, -1, -1, -1, -1, -1, -1, -1,
 725 };
 726
 727 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 728         4, 5,                   /* ADAT 1 */
 729         6, 7,                   /* ADAT 2 */
 730         8, 9,                   /* ADAT 3 */
 731         10, 11,                 /* ADAT 4 */
 732         0, 1,                   /* AES */
 733         2, 3,                   /* SPDIF */
 734         -1, -1, -1, -1,
 735         -1, -1, -1, -1, -1, -1, -1, -1,
 736         -1, -1, -1, -1, -1, -1, -1, -1,
 737         -1, -1, -1, -1, -1, -1, -1, -1,
 738         -1, -1, -1, -1, -1, -1, -1, -1,
 739         -1, -1, -1, -1, -1, -1, -1, -1,
 740         -1, -1, -1, -1, -1, -1, -1, -1,
 741 };
 742
 743 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 744         0, 1,                   /* line in */
 745         8, 9,                   /* aes in, */
 746         10, 11,                 /* spdif in */
 747         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 748         -1, -1,
 749         -1, -1, -1, -1, -1, -1, -1, -1,
 750         -1, -1, -1, -1, -1, -1, -1, -1,
 751         -1, -1, -1, -1, -1, -1, -1, -1,
 752         -1, -1, -1, -1, -1, -1, -1, -1,
 753         -1, -1, -1, -1, -1, -1, -1, -1,
 754         -1, -1, -1, -1, -1, -1, -1, -1,
 755 };
 756
 757 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 758         0, 1,                   /* line out */
 759         8, 9,                   /* aes out */
 760         10, 11,                 /* spdif out */
 761         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 762         6, 7,                   /* phone out */
 763         -1, -1, -1, -1, -1, -1, -1, -1,
 764         -1, -1, -1, -1, -1, -1, -1, -1,
 765         -1, -1, -1, -1, -1, -1, -1, -1,
 766         -1, -1, -1, -1, -1, -1, -1, -1,
 767         -1, -1, -1, -1, -1, -1, -1, -1,
 768         -1, -1, -1, -1, -1, -1, -1, -1,
 769 };
 770
 771 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 772         0, 1,                   /* line in */
 773         8, 9,                   /* aes in */
 774         10, 11,                 /* spdif in */
 775         12, 14, 16, 18,         /* adat in */
 776         -1, -1, -1, -1, -1, -1,
 777         -1, -1, -1, -1, -1, -1, -1, -1,
 778         -1, -1, -1, -1, -1, -1, -1, -1,
 779         -1, -1, -1, -1, -1, -1, -1, -1,
 780         -1, -1, -1, -1, -1, -1, -1, -1,
 781         -1, -1, -1, -1, -1, -1, -1, -1,
 782         -1, -1, -1, -1, -1, -1, -1, -1
 783 };
 784
 785 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 786         0, 1,                   /* line out */
 787         8, 9,                   /* aes out */
 788         10, 11,                 /* spdif out */
 789         12, 14, 16, 18,         /* adat out */
 790         6, 7,                   /* phone out */
 791         -1, -1, -1, -1,
 792         -1, -1, -1, -1, -1, -1, -1, -1,
 793         -1, -1, -1, -1, -1, -1, -1, -1,
 794         -1, -1, -1, -1, -1, -1, -1, -1,
 795         -1, -1, -1, -1, -1, -1, -1, -1,
 796         -1, -1, -1, -1, -1, -1, -1, -1,
 797         -1, -1, -1, -1, -1, -1, -1, -1
 798 };
 799
 800 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 801         0, 1,                   /* line in */
 802         8, 9,                   /* aes in */
 803         10, 11,                 /* spdif in */
 804         12, 16,                 /* adat in */
 805         -1, -1, -1, -1, -1, -1, -1, -1,
 806         -1, -1, -1, -1, -1, -1, -1, -1,
 807         -1, -1, -1, -1, -1, -1, -1, -1,
 808         -1, -1, -1, -1, -1, -1, -1, -1,
 809         -1, -1, -1, -1, -1, -1, -1, -1,
 810         -1, -1, -1, -1, -1, -1, -1, -1,
 811         -1, -1, -1, -1, -1, -1, -1, -1
 812 };
 813
 814 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 815         0, 1,                   /* line out */
 816         8, 9,                   /* aes out */
 817         10, 11,                 /* spdif out */
 818         12, 16,                 /* adat out */
 819         6, 7,                   /* phone out */
 820         -1, -1, -1, -1, -1, -1,
 821         -1, -1, -1, -1, -1, -1, -1, -1,
 822         -1, -1, -1, -1, -1, -1, -1, -1,
 823         -1, -1, -1, -1, -1, -1, -1, -1,
 824         -1, -1, -1, -1, -1, -1, -1, -1,
 825         -1, -1, -1, -1, -1, -1, -1, -1,
 826         -1, -1, -1, -1, -1, -1, -1, -1
 827 };
 828
 829 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 830         0, 1, 2, 3, 4, 5, 6, 7,
 831         8, 9, 10, 11, 12, 13, 14, 15,
 832         -1, -1, -1, -1, -1, -1, -1, -1,
 833         -1, -1, -1, -1, -1, -1, -1, -1,
 834         -1, -1, -1, -1, -1, -1, -1, -1,
 835         -1, -1, -1, -1, -1, -1, -1, -1,
 836         -1, -1, -1, -1, -1, -1, -1, -1,
 837         -1, -1, -1, -1, -1, -1, -1, -1
 838 };
 839
 840 struct hdspm_midi {
 841         struct hdspm *hdspm;
 842         int id;
 843         struct snd_rawmidi *rmidi;
 844         struct snd_rawmidi_substream *input;
 845         struct snd_rawmidi_substream *output;
 846         char istimer;           /* timer in use */
 847         struct timer_list timer;
 848         spinlock_t lock;
 849         int pending;
 850         int dataIn;
 851         int statusIn;
 852         int dataOut;
 853         int statusOut;
 854         int ie;
 855         int irq;
 856 };
 857
 858 struct hdspm_tco {
 859         int input;
 860         int framerate;
 861         int wordclock;
 862         int samplerate;
 863         int pull;
 864         int term; /* 0 = off, 1 = on */
 865 };
 866
 867 struct hdspm {
 868         spinlock_t lock;
 869         /* only one playback and/or capture stream */
 870         struct snd_pcm_substream *capture_substream;
 871         struct snd_pcm_substream *playback_substream;
 872
 873         char *card_name;             /* for procinfo */
 874         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 875
 876         uint8_t io_type;
 877
 878         int monitor_outs;       /* set up monitoring outs init flag */
 879
 880         u32 control_register;   /* cached value */
 881         u32 control2_register;  /* cached value */
 882         u32 settings_register;
 883
 884         struct hdspm_midi midi[4];
 885         struct tasklet_struct midi_tasklet;
 886
 887         size_t period_bytes;
 888         unsigned char ss_in_channels;
 889         unsigned char ds_in_channels;
 890         unsigned char qs_in_channels;
 891         unsigned char ss_out_channels;
 892         unsigned char ds_out_channels;
 893         unsigned char qs_out_channels;
 894
 895         unsigned char max_channels_in;
 896         unsigned char max_channels_out;
 897
 898         char *channel_map_in;
 899         char *channel_map_out;
 900
 901         char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 902         char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 903
 904         char **port_names_in;
 905         char **port_names_out;
 906
 907         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 908         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
 909
 910         unsigned char *playback_buffer; /* suitably aligned address */
 911         unsigned char *capture_buffer;  /* suitably aligned address */
 912
 913         pid_t capture_pid;      /* process id which uses capture */
 914         pid_t playback_pid;     /* process id which uses capture */
 915         int running;            /* running status */
 916
 917         int last_external_sample_rate;  /* samplerate mystic ... */
 918         int last_internal_sample_rate;
 919         int system_sample_rate;
 920
 921         int dev;                /* Hardware vars... */
 922         int irq;
 923         unsigned long port;
 924         void __iomem *iobase;
 925
 926         int irq_count;          /* for debug */
 927         int midiPorts;
 928
 929         struct snd_card *card;  /* one card */
 930         struct snd_pcm *pcm;            /* has one pcm */
 931         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 932         struct pci_dev *pci;    /* and an pci info */
 933
 934         /* Mixer vars */
 935         /* fast alsa mixer */
 936         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 937         /* but input to much, so not used */
 938         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 939         /* full mixer accessible over mixer ioctl or hwdep-device */
 940         struct hdspm_mixer *mixer;
 941
 942         struct hdspm_tco *tco;  /* NULL if no TCO detected */
 943
 944         char **texts_autosync;
 945         int texts_autosync_items;
 946
 947         cycles_t last_interrupt;
 948
 949         struct hdspm_peak_rms peak_rms;
 950 };
 951
 952
 953 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
 954         {
 955          .vendor = PCI_VENDOR_ID_XILINX,
 956          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 957          .subvendor = PCI_ANY_ID,
 958          .subdevice = PCI_ANY_ID,
 959          .class = 0,
 960          .class_mask = 0,
 961          .driver_data = 0},
 962         {0,}
 963 };
 964
 965 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
 966
 967 /* prototypes */
 968 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
 969                                                    struct hdspm * hdspm);
 970 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
 971                                           struct hdspm * hdspm);
 972
 973 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
 974 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
 975 static int hdspm_autosync_ref(struct hdspm *hdspm);
 976 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
 977 static void hdspm_set_sgbuf(struct hdspm *hdspm,
 978                             struct snd_pcm_substream *substream,
 979                              unsigned int reg, int channels);
 980
 981 static inline int HDSPM_bit2freq(int n)
 982 {
 983         static const int bit2freq_tab[] = {
 984                 0, 32000, 44100, 48000, 64000, 88200,
 985                 96000, 128000, 176400, 192000 };
 986         if (n < 1 || n > 9)
 987                 return 0;
 988         return bit2freq_tab[n];
 989 }
 990
 991 /* Write/read to/from HDSPM with Adresses in Bytes
 992    not words but only 32Bit writes are allowed */
 993
 994 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
 995                                unsigned int val)
 996 {
 997         writel(val, hdspm->iobase + reg);
 998 }
 999
1000 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1001 {
1002         return readl(hdspm->iobase + reg);
1003 }
1004
1005 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1006    mixer is write only on hardware so we have to cache him for read
1007    each fader is a u32, but uses only the first 16 bit */
1008
1009 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1010                                      unsigned int in)
1011 {
1012         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1013                 return 0;
1014
1015         return hdspm->mixer->ch[chan].in[in];
1016 }
1017
1018 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1019                                      unsigned int pb)
1020 {
1021         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1022                 return 0;
1023         return hdspm->mixer->ch[chan].pb[pb];
1024 }
1025
1026 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1027                                       unsigned int in, unsigned short data)
1028 {
1029         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1030                 return -1;
1031
1032         hdspm_write(hdspm,
1033                     HDSPM_MADI_mixerBase +
1034                     ((in + 128 * chan) * sizeof(u32)),
1035                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1036         return 0;
1037 }
1038
1039 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1040                                       unsigned int pb, unsigned short data)
1041 {
1042         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1043                 return -1;
1044
1045         hdspm_write(hdspm,
1046                     HDSPM_MADI_mixerBase +
1047                     ((64 + pb + 128 * chan) * sizeof(u32)),
1048                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1049         return 0;
1050 }
1051
1052
1053 /* enable DMA for specific channels, now available for DSP-MADI */
1054 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1055 {
1056         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1057 }
1058
1059 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1060 {
1061         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1062 }
1063
1064 /* check if same process is writing and reading */
1065 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1066 {
1067         unsigned long flags;
1068         int ret = 1;
1069
1070         spin_lock_irqsave(&hdspm->lock, flags);
1071         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1072             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1073                 ret = 0;
1074         }
1075         spin_unlock_irqrestore(&hdspm->lock, flags);
1076         return ret;
1077 }
1078
1079 /* check for external sample rate */
1080 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1081 {
1082         unsigned int status, status2, timecode;
1083         int syncref, rate = 0, rate_bits;
1084
1085         switch (hdspm->io_type) {
1086         case AES32:
1087                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1088                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1089                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1090
1091                 syncref = hdspm_autosync_ref(hdspm);
1092
1093                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1094                                 status & HDSPM_AES32_wcLock)
1095                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1096
1097                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1098                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1099                                 status2 & (HDSPM_LockAES >>
1100                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1101                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1102                 return 0;
1103                 break;
1104
1105         case MADIface:
1106                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1107
1108                 if (!(status & HDSPM_madiLock)) {
1109                         rate = 0;  /* no lock */
1110                 } else {
1111                         switch (status & (HDSPM_status1_freqMask)) {
1112                         case HDSPM_status1_F_0*1:
1113                                 rate = 32000; break;
1114                         case HDSPM_status1_F_0*2:
1115                                 rate = 44100; break;
1116                         case HDSPM_status1_F_0*3:
1117                                 rate = 48000; break;
1118                         case HDSPM_status1_F_0*4:
1119                                 rate = 64000; break;
1120                         case HDSPM_status1_F_0*5:
1121                                 rate = 88200; break;
1122                         case HDSPM_status1_F_0*6:
1123                                 rate = 96000; break;
1124                         case HDSPM_status1_F_0*7:
1125                                 rate = 128000; break;
1126                         case HDSPM_status1_F_0*8:
1127                                 rate = 176400; break;
1128                         case HDSPM_status1_F_0*9:
1129                                 rate = 192000; break;
1130                         default:
1131                                 rate = 0; break;
1132                         }
1133                 }
1134
1135                 break;
1136
1137         case MADI:
1138         case AIO:
1139         case RayDAT:
1140                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1141                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1142                 rate = 0;
1143
1144                 /* if wordclock has synced freq and wordclock is valid */
1145                 if ((status2 & HDSPM_wcLock) != 0 &&
1146                                 (status & HDSPM_SelSyncRef0) == 0) {
1147
1148                         rate_bits = status2 & HDSPM_wcFreqMask;
1149
1150
1151                         switch (rate_bits) {
1152                         case HDSPM_wcFreq32:
1153                                 rate = 32000;
1154                                 break;
1155                         case HDSPM_wcFreq44_1:
1156                                 rate = 44100;
1157                                 break;
1158                         case HDSPM_wcFreq48:
1159                                 rate = 48000;
1160                                 break;
1161                         case HDSPM_wcFreq64:
1162                                 rate = 64000;
1163                                 break;
1164                         case HDSPM_wcFreq88_2:
1165                                 rate = 88200;
1166                                 break;
1167                         case HDSPM_wcFreq96:
1168                                 rate = 96000;
1169                                 break;
1170                         default:
1171                                 rate = 0;
1172                                 break;
1173                         }
1174                 }
1175
1176                 /* if rate detected and Syncref is Word than have it,
1177                  * word has priority to MADI
1178                  */
1179                 if (rate != 0 &&
1180                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1181                         return rate;
1182
1183                 /* maybe a madi input (which is taken if sel sync is madi) */
1184                 if (status & HDSPM_madiLock) {
1185                         rate_bits = status & HDSPM_madiFreqMask;
1186
1187                         switch (rate_bits) {
1188                         case HDSPM_madiFreq32:
1189                                 rate = 32000;
1190                                 break;
1191                         case HDSPM_madiFreq44_1:
1192                                 rate = 44100;
1193                                 break;
1194                         case HDSPM_madiFreq48:
1195                                 rate = 48000;
1196                                 break;
1197                         case HDSPM_madiFreq64:
1198                                 rate = 64000;
1199                                 break;
1200                         case HDSPM_madiFreq88_2:
1201                                 rate = 88200;
1202                                 break;
1203                         case HDSPM_madiFreq96:
1204                                 rate = 96000;
1205                                 break;
1206                         case HDSPM_madiFreq128:
1207                                 rate = 128000;
1208                                 break;
1209                         case HDSPM_madiFreq176_4:
1210                                 rate = 176400;
1211                                 break;
1212                         case HDSPM_madiFreq192:
1213                                 rate = 192000;
1214                                 break;
1215                         default:
1216                                 rate = 0;
1217                                 break;
1218                         }
1219                 }
1220                 break;
1221         }
1222
1223         return rate;
1224 }
1225
1226 /* Latency function */
1227 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1228 {
1229         hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1230 }
1231
1232
1233 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1234 {
1235         int position;
1236
1237         position = hdspm_read(hdspm, HDSPM_statusRegister);
1238
1239         switch (hdspm->io_type) {
1240         case RayDAT:
1241         case AIO:
1242                 position &= HDSPM_BufferPositionMask;
1243                 position /= 4; /* Bytes per sample */
1244                 break;
1245         default:
1246                 position = (position & HDSPM_BufferID) ?
1247                         (hdspm->period_bytes / 4) : 0;
1248         }
1249
1250         return position;
1251 }
1252
1253
1254 static inline void hdspm_start_audio(struct hdspm * s)
1255 {
1256         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1257         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1258 }
1259
1260 static inline void hdspm_stop_audio(struct hdspm * s)
1261 {
1262         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1263         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1264 }
1265
1266 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1267 static void hdspm_silence_playback(struct hdspm *hdspm)
1268 {
1269         int i;
1270         int n = hdspm->period_bytes;
1271         void *buf = hdspm->playback_buffer;
1272
1273         if (buf == NULL)
1274                 return;
1275
1276         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1277                 memset(buf, 0, n);
1278                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1279         }
1280 }
1281
1282 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1283 {
1284         int n;
1285
1286         spin_lock_irq(&s->lock);
1287
1288         frames >>= 7;
1289         n = 0;
1290         while (frames) {
1291                 n++;
1292                 frames >>= 1;
1293         }
1294         s->control_register &= ~HDSPM_LatencyMask;
1295         s->control_register |= hdspm_encode_latency(n);
1296
1297         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1298
1299         hdspm_compute_period_size(s);
1300
1301         spin_unlock_irq(&s->lock);
1302
1303         return 0;
1304 }
1305
1306 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1307 {
1308         u64 freq_const;
1309
1310         if (period == 0)
1311                 return 0;
1312
1313         switch (hdspm->io_type) {
1314         case MADI:
1315         case AES32:
1316                 freq_const = 110069313433624ULL;
1317                 break;
1318         case RayDAT:
1319         case AIO:
1320                 freq_const = 104857600000000ULL;
1321                 break;
1322         case MADIface:
1323                 freq_const = 131072000000000ULL;
1324         }
1325
1326         return div_u64(freq_const, period);
1327 }
1328
1329
1330 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1331 {
1332         u64 n;
1333
1334         if (rate >= 112000)
1335                 rate /= 4;
1336         else if (rate >= 56000)
1337                 rate /= 2;
1338
1339         switch (hdspm->io_type) {
1340         case MADIface:
1341           n = 131072000000000ULL;  /* 125 MHz */
1342           break;
1343         case MADI:
1344         case AES32:
1345           n = 110069313433624ULL;  /* 105 MHz */
1346           break;
1347         case RayDAT:
1348         case AIO:
1349           n = 104857600000000ULL;  /* 100 MHz */
1350           break;
1351         }
1352
1353         n = div_u64(n, rate);
1354         /* n should be less than 2^32 for being written to FREQ register */
1355         snd_BUG_ON(n >> 32);
1356         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1357 }
1358
1359 /* dummy set rate lets see what happens */
1360 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1361 {
1362         int current_rate;
1363         int rate_bits;
1364         int not_set = 0;
1365         int current_speed, target_speed;
1366
1367         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1368            it (e.g. during module initialization).
1369          */
1370
1371         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1372
1373                 /* SLAVE --- */
1374                 if (called_internally) {
1375
1376                         /* request from ctl or card initialization
1377                            just make a warning an remember setting
1378                            for future master mode switching */
1379
1380                         snd_printk(KERN_WARNING "HDSPM: "
1381                                    "Warning: device is not running "
1382                                    "as a clock master.\n");
1383                         not_set = 1;
1384                 } else {
1385
1386                         /* hw_param request while in AutoSync mode */
1387                         int external_freq =
1388                             hdspm_external_sample_rate(hdspm);
1389
1390                         if (hdspm_autosync_ref(hdspm) ==
1391                             HDSPM_AUTOSYNC_FROM_NONE) {
1392
1393                                 snd_printk(KERN_WARNING "HDSPM: "
1394                                            "Detected no Externel Sync \n");
1395                                 not_set = 1;
1396
1397                         } else if (rate != external_freq) {
1398
1399                                 snd_printk(KERN_WARNING "HDSPM: "
1400                                            "Warning: No AutoSync source for "
1401                                            "requested rate\n");
1402                                 not_set = 1;
1403                         }
1404                 }
1405         }
1406
1407         current_rate = hdspm->system_sample_rate;
1408
1409         /* Changing between Singe, Double and Quad speed is not
1410            allowed if any substreams are open. This is because such a change
1411            causes a shift in the location of the DMA buffers and a reduction
1412            in the number of available buffers.
1413
1414            Note that a similar but essentially insoluble problem exists for
1415            externally-driven rate changes. All we can do is to flag rate
1416            changes in the read/write routines.
1417          */
1418
1419         if (current_rate <= 48000)
1420                 current_speed = HDSPM_SPEED_SINGLE;
1421         else if (current_rate <= 96000)
1422                 current_speed = HDSPM_SPEED_DOUBLE;
1423         else
1424                 current_speed = HDSPM_SPEED_QUAD;
1425
1426         if (rate <= 48000)
1427                 target_speed = HDSPM_SPEED_SINGLE;
1428         else if (rate <= 96000)
1429                 target_speed = HDSPM_SPEED_DOUBLE;
1430         else
1431                 target_speed = HDSPM_SPEED_QUAD;
1432
1433         switch (rate) {
1434         case 32000:
1435                 rate_bits = HDSPM_Frequency32KHz;
1436                 break;
1437         case 44100:
1438                 rate_bits = HDSPM_Frequency44_1KHz;
1439                 break;
1440         case 48000:
1441                 rate_bits = HDSPM_Frequency48KHz;
1442                 break;
1443         case 64000:
1444                 rate_bits = HDSPM_Frequency64KHz;
1445                 break;
1446         case 88200:
1447                 rate_bits = HDSPM_Frequency88_2KHz;
1448                 break;
1449         case 96000:
1450                 rate_bits = HDSPM_Frequency96KHz;
1451                 break;
1452         case 128000:
1453                 rate_bits = HDSPM_Frequency128KHz;
1454                 break;
1455         case 176400:
1456                 rate_bits = HDSPM_Frequency176_4KHz;
1457                 break;
1458         case 192000:
1459                 rate_bits = HDSPM_Frequency192KHz;
1460                 break;
1461         default:
1462                 return -EINVAL;
1463         }
1464
1465         if (current_speed != target_speed
1466             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1467                 snd_printk
1468                     (KERN_ERR "HDSPM: "
1469                      "cannot change from %s speed to %s speed mode "
1470                      "(capture PID = %d, playback PID = %d)\n",
1471                      hdspm_speed_names[current_speed],
1472                      hdspm_speed_names[target_speed],
1473                      hdspm->capture_pid, hdspm->playback_pid);
1474                 return -EBUSY;
1475         }
1476
1477         hdspm->control_register &= ~HDSPM_FrequencyMask;
1478         hdspm->control_register |= rate_bits;
1479         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1480
1481         /* For AES32, need to set DDS value in FREQ register
1482            For MADI, also apparently */
1483         hdspm_set_dds_value(hdspm, rate);
1484
1485         if (AES32 == hdspm->io_type && rate != current_rate)
1486                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1487
1488         hdspm->system_sample_rate = rate;
1489
1490         if (rate <= 48000) {
1491                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1492                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1493                 hdspm->max_channels_in = hdspm->ss_in_channels;
1494                 hdspm->max_channels_out = hdspm->ss_out_channels;
1495                 hdspm->port_names_in = hdspm->port_names_in_ss;
1496                 hdspm->port_names_out = hdspm->port_names_out_ss;
1497         } else if (rate <= 96000) {
1498                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1499                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1500                 hdspm->max_channels_in = hdspm->ds_in_channels;
1501                 hdspm->max_channels_out = hdspm->ds_out_channels;
1502                 hdspm->port_names_in = hdspm->port_names_in_ds;
1503                 hdspm->port_names_out = hdspm->port_names_out_ds;
1504         } else {
1505                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1506                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1507                 hdspm->max_channels_in = hdspm->qs_in_channels;
1508                 hdspm->max_channels_out = hdspm->qs_out_channels;
1509                 hdspm->port_names_in = hdspm->port_names_in_qs;
1510                 hdspm->port_names_out = hdspm->port_names_out_qs;
1511         }
1512
1513         if (not_set != 0)
1514                 return -1;
1515
1516         return 0;
1517 }
1518
1519 /* mainly for init to 0 on load */
1520 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1521 {
1522         int i, j;
1523         unsigned int gain;
1524
1525         if (sgain > UNITY_GAIN)
1526                 gain = UNITY_GAIN;
1527         else if (sgain < 0)
1528                 gain = 0;
1529         else
1530                 gain = sgain;
1531
1532         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1533                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1534                         hdspm_write_in_gain(hdspm, i, j, gain);
1535                         hdspm_write_pb_gain(hdspm, i, j, gain);
1536                 }
1537 }
1538
1539 /*----------------------------------------------------------------------------
1540    MIDI
1541   ----------------------------------------------------------------------------*/
1542
1543 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1544                                                       int id)
1545 {
1546         /* the hardware already does the relevant bit-mask with 0xff */
1547         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1548 }
1549
1550 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1551                                               int val)
1552 {
1553         /* the hardware already does the relevant bit-mask with 0xff */
1554         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1555 }
1556
1557 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1558 {
1559         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1560 }
1561
1562 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1563 {
1564         int fifo_bytes_used;
1565
1566         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1567
1568         if (fifo_bytes_used < 128)
1569                 return  128 - fifo_bytes_used;
1570         else
1571                 return 0;
1572 }
1573
1574 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1575 {
1576         while (snd_hdspm_midi_input_available (hdspm, id))
1577                 snd_hdspm_midi_read_byte (hdspm, id);
1578 }
1579
1580 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1581 {
1582         unsigned long flags;
1583         int n_pending;
1584         int to_write;
1585         int i;
1586         unsigned char buf[128];
1587
1588         /* Output is not interrupt driven */
1589
1590         spin_lock_irqsave (&hmidi->lock, flags);
1591         if (hmidi->output &&
1592             !snd_rawmidi_transmit_empty (hmidi->output)) {
1593                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1594                                                             hmidi->id);
1595                 if (n_pending > 0) {
1596                         if (n_pending > (int)sizeof (buf))
1597                                 n_pending = sizeof (buf);
1598
1599                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1600                                                          n_pending);
1601                         if (to_write > 0) {
1602                                 for (i = 0; i < to_write; ++i)
1603                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1604                                                                    hmidi->id,
1605                                                                    buf[i]);
1606                         }
1607                 }
1608         }
1609         spin_unlock_irqrestore (&hmidi->lock, flags);
1610         return 0;
1611 }
1612
1613 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1614 {
1615         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1616                                  * input FIFO size
1617                                  */
1618         unsigned long flags;
1619         int n_pending;
1620         int i;
1621
1622         spin_lock_irqsave (&hmidi->lock, flags);
1623         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1624         if (n_pending > 0) {
1625                 if (hmidi->input) {
1626                         if (n_pending > (int)sizeof (buf))
1627                                 n_pending = sizeof (buf);
1628                         for (i = 0; i < n_pending; ++i)
1629                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1630                                                                    hmidi->id);
1631                         if (n_pending)
1632                                 snd_rawmidi_receive (hmidi->input, buf,
1633                                                      n_pending);
1634                 } else {
1635                         /* flush the MIDI input FIFO */
1636                         while (n_pending--)
1637                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1638                                                           hmidi->id);
1639                 }
1640         }
1641         hmidi->pending = 0;
1642
1643         hmidi->hdspm->control_register |= hmidi->ie;
1644         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1645                     hmidi->hdspm->control_register);
1646
1647         spin_unlock_irqrestore (&hmidi->lock, flags);
1648         return snd_hdspm_midi_output_write (hmidi);
1649 }
1650
1651 static void
1652 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1653 {
1654         struct hdspm *hdspm;
1655         struct hdspm_midi *hmidi;
1656         unsigned long flags;
1657
1658         hmidi = substream->rmidi->private_data;
1659         hdspm = hmidi->hdspm;
1660
1661         spin_lock_irqsave (&hdspm->lock, flags);
1662         if (up) {
1663                 if (!(hdspm->control_register & hmidi->ie)) {
1664                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1665                         hdspm->control_register |= hmidi->ie;
1666                 }
1667         } else {
1668                 hdspm->control_register &= ~hmidi->ie;
1669         }
1670
1671         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1672         spin_unlock_irqrestore (&hdspm->lock, flags);
1673 }
1674
1675 static void snd_hdspm_midi_output_timer(unsigned long data)
1676 {
1677         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1678         unsigned long flags;
1679
1680         snd_hdspm_midi_output_write(hmidi);
1681         spin_lock_irqsave (&hmidi->lock, flags);
1682
1683         /* this does not bump hmidi->istimer, because the
1684            kernel automatically removed the timer when it
1685            expired, and we are now adding it back, thus
1686            leaving istimer wherever it was set before.
1687         */
1688
1689         if (hmidi->istimer) {
1690                 hmidi->timer.expires = 1 + jiffies;
1691                 add_timer(&hmidi->timer);
1692         }
1693
1694         spin_unlock_irqrestore (&hmidi->lock, flags);
1695 }
1696
1697 static void
1698 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1699 {
1700         struct hdspm_midi *hmidi;
1701         unsigned long flags;
1702
1703         hmidi = substream->rmidi->private_data;
1704         spin_lock_irqsave (&hmidi->lock, flags);
1705         if (up) {
1706                 if (!hmidi->istimer) {
1707                         init_timer(&hmidi->timer);
1708                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1709                         hmidi->timer.data = (unsigned long) hmidi;
1710                         hmidi->timer.expires = 1 + jiffies;
1711                         add_timer(&hmidi->timer);
1712                         hmidi->istimer++;
1713                 }
1714         } else {
1715                 if (hmidi->istimer && --hmidi->istimer <= 0)
1716                         del_timer (&hmidi->timer);
1717         }
1718         spin_unlock_irqrestore (&hmidi->lock, flags);
1719         if (up)
1720                 snd_hdspm_midi_output_write(hmidi);
1721 }
1722
1723 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1724 {
1725         struct hdspm_midi *hmidi;
1726
1727         hmidi = substream->rmidi->private_data;
1728         spin_lock_irq (&hmidi->lock);
1729         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1730         hmidi->input = substream;
1731         spin_unlock_irq (&hmidi->lock);
1732
1733         return 0;
1734 }
1735
1736 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1737 {
1738         struct hdspm_midi *hmidi;
1739
1740         hmidi = substream->rmidi->private_data;
1741         spin_lock_irq (&hmidi->lock);
1742         hmidi->output = substream;
1743         spin_unlock_irq (&hmidi->lock);
1744
1745         return 0;
1746 }
1747
1748 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1749 {
1750         struct hdspm_midi *hmidi;
1751
1752         snd_hdspm_midi_input_trigger (substream, 0);
1753
1754         hmidi = substream->rmidi->private_data;
1755         spin_lock_irq (&hmidi->lock);
1756         hmidi->input = NULL;
1757         spin_unlock_irq (&hmidi->lock);
1758
1759         return 0;
1760 }
1761
1762 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1763 {
1764         struct hdspm_midi *hmidi;
1765
1766         snd_hdspm_midi_output_trigger (substream, 0);
1767
1768         hmidi = substream->rmidi->private_data;
1769         spin_lock_irq (&hmidi->lock);
1770         hmidi->output = NULL;
1771         spin_unlock_irq (&hmidi->lock);
1772
1773         return 0;
1774 }
1775
1776 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1777 {
1778         .open =         snd_hdspm_midi_output_open,
1779         .close =        snd_hdspm_midi_output_close,
1780         .trigger =      snd_hdspm_midi_output_trigger,
1781 };
1782
1783 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1784 {
1785         .open =         snd_hdspm_midi_input_open,
1786         .close =        snd_hdspm_midi_input_close,
1787         .trigger =      snd_hdspm_midi_input_trigger,
1788 };
1789
1790 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1791                                             struct hdspm *hdspm, int id)
1792 {
1793         int err;
1794         char buf[32];
1795
1796         hdspm->midi[id].id = id;
1797         hdspm->midi[id].hdspm = hdspm;
1798         spin_lock_init (&hdspm->midi[id].lock);
1799
1800         if (0 == id) {
1801                 if (MADIface == hdspm->io_type) {
1802                         /* MIDI-over-MADI on HDSPe MADIface */
1803                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1804                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1805                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1806                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1807                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1808                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1809                 } else {
1810                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1811                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1812                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1813                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1814                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1815                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1816                 }
1817         } else if (1 == id) {
1818                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1819                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1820                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1821                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1822                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1823                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1824         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1825                 /* MIDI-over-MADI on HDSPe MADI */
1826                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1827                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1828                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1829                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1830                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1831                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1832         } else if (2 == id) {
1833                 /* TCO MTC, read only */
1834                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1835                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1836                 hdspm->midi[2].dataOut = -1;
1837                 hdspm->midi[2].statusOut = -1;
1838                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1839                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1840         } else if (3 == id) {
1841                 /* TCO MTC on HDSPe MADI */
1842                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1843                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1844                 hdspm->midi[3].dataOut = -1;
1845                 hdspm->midi[3].statusOut = -1;
1846                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1847                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1848         }
1849
1850         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1851                                         (MADIface == hdspm->io_type)))) {
1852                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1853                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1854                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1855                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1856                 } else {
1857                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1858                 }
1859                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1860                                 &hdspm->midi[id].rmidi);
1861                 if (err < 0)
1862                         return err;
1863
1864                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1865                                 card->id, id+1);
1866                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1867
1868                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1869                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1870                                 &snd_hdspm_midi_output);
1871                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1872                                 SNDRV_RAWMIDI_STREAM_INPUT,
1873                                 &snd_hdspm_midi_input);
1874
1875                 hdspm->midi[id].rmidi->info_flags |=
1876                         SNDRV_RAWMIDI_INFO_OUTPUT |
1877                         SNDRV_RAWMIDI_INFO_INPUT |
1878                         SNDRV_RAWMIDI_INFO_DUPLEX;
1879         } else {
1880                 /* TCO MTC, read only */
1881                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1882                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1883                                 &hdspm->midi[id].rmidi);
1884                 if (err < 0)
1885                         return err;
1886
1887                 sprintf(hdspm->midi[id].rmidi->name,
1888                                 "%s MTC %d", card->id, id+1);
1889                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1890
1891                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1892                                 SNDRV_RAWMIDI_STREAM_INPUT,
1893                                 &snd_hdspm_midi_input);
1894
1895                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1896         }
1897
1898         return 0;
1899 }
1900
1901
1902 static void hdspm_midi_tasklet(unsigned long arg)
1903 {
1904         struct hdspm *hdspm = (struct hdspm *)arg;
1905         int i = 0;
1906
1907         while (i < hdspm->midiPorts) {
1908                 if (hdspm->midi[i].pending)
1909                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
1910
1911                 i++;
1912         }
1913 }
1914
1915
1916 /*-----------------------------------------------------------------------------
1917   Status Interface
1918   ----------------------------------------------------------------------------*/
1919
1920 /* get the system sample rate which is set */
1921
1922
1923 /**
1924  * Calculate the real sample rate from the
1925  * current DDS value.
1926  **/
1927 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1928 {
1929         unsigned int period, rate;
1930
1931         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1932         rate = hdspm_calc_dds_value(hdspm, period);
1933
1934         return rate;
1935 }
1936
1937
1938 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1939 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1940   .name = xname, \
1941   .index = xindex, \
1942   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1943   .info = snd_hdspm_info_system_sample_rate, \
1944   .get = snd_hdspm_get_system_sample_rate \
1945 }
1946
1947 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1948                                              struct snd_ctl_elem_info *uinfo)
1949 {
1950         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1951         uinfo->count = 1;
1952         uinfo->value.integer.min = 27000;
1953         uinfo->value.integer.max = 207000;
1954         uinfo->value.integer.step = 1;
1955         return 0;
1956 }
1957
1958
1959 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1960                                             struct snd_ctl_elem_value *
1961                                             ucontrol)
1962 {
1963         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1964
1965         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1966         return 0;
1967 }
1968
1969
1970 /**
1971  * Returns the WordClock sample rate class for the given card.
1972  **/
1973 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1974 {
1975         int status;
1976
1977         switch (hdspm->io_type) {
1978         case RayDAT:
1979         case AIO:
1980                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
1981                 return (status >> 16) & 0xF;
1982                 break;
1983         default:
1984                 break;
1985         }
1986
1987
1988         return 0;
1989 }
1990
1991
1992 /**
1993  * Returns the TCO sample rate class for the given card.
1994  **/
1995 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
1996 {
1997         int status;
1998
1999         if (hdspm->tco) {
2000                 switch (hdspm->io_type) {
2001                 case RayDAT:
2002                 case AIO:
2003                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2004                         return (status >> 20) & 0xF;
2005                         break;
2006                 default:
2007                         break;
2008                 }
2009         }
2010
2011         return 0;
2012 }
2013
2014
2015 /**
2016  * Returns the SYNC_IN sample rate class for the given card.
2017  **/
2018 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2019 {
2020         int status;
2021
2022         if (hdspm->tco) {
2023                 switch (hdspm->io_type) {
2024                 case RayDAT:
2025                 case AIO:
2026                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2027                         return (status >> 12) & 0xF;
2028                         break;
2029                 default:
2030                         break;
2031                 }
2032         }
2033
2034         return 0;
2035 }
2036
2037
2038 /**
2039  * Returns the sample rate class for input source <idx> for
2040  * 'new style' cards like the AIO and RayDAT.
2041  **/
2042 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2043 {
2044         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2045
2046         return (status >> (idx*4)) & 0xF;
2047 }
2048
2049
2050
2051 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2052 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2053         .name = xname, \
2054         .private_value = xindex, \
2055         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2056         .info = snd_hdspm_info_autosync_sample_rate, \
2057         .get = snd_hdspm_get_autosync_sample_rate \
2058 }
2059
2060
2061 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2062                                                struct snd_ctl_elem_info *uinfo)
2063 {
2064         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2065         uinfo->count = 1;
2066         uinfo->value.enumerated.items = 10;
2067
2068         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2069                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2070         strcpy(uinfo->value.enumerated.name,
2071                         texts_freq[uinfo->value.enumerated.item]);
2072         return 0;
2073 }
2074
2075
2076 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2077                                               struct snd_ctl_elem_value *
2078                                               ucontrol)
2079 {
2080         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2081
2082         switch (hdspm->io_type) {
2083         case RayDAT:
2084                 switch (kcontrol->private_value) {
2085                 case 0:
2086                         ucontrol->value.enumerated.item[0] =
2087                                 hdspm_get_wc_sample_rate(hdspm);
2088                         break;
2089                 case 7:
2090                         ucontrol->value.enumerated.item[0] =
2091                                 hdspm_get_tco_sample_rate(hdspm);
2092                         break;
2093                 case 8:
2094                         ucontrol->value.enumerated.item[0] =
2095                                 hdspm_get_sync_in_sample_rate(hdspm);
2096                         break;
2097                 default:
2098                         ucontrol->value.enumerated.item[0] =
2099                                 hdspm_get_s1_sample_rate(hdspm,
2100                                                 kcontrol->private_value-1);
2101                 }
2102
2103         case AIO:
2104                 switch (kcontrol->private_value) {
2105                 case 0: /* WC */
2106                         ucontrol->value.enumerated.item[0] =
2107                                 hdspm_get_wc_sample_rate(hdspm);
2108                         break;
2109                 case 4: /* TCO */
2110                         ucontrol->value.enumerated.item[0] =
2111                                 hdspm_get_tco_sample_rate(hdspm);
2112                         break;
2113                 case 5: /* SYNC_IN */
2114                         ucontrol->value.enumerated.item[0] =
2115                                 hdspm_get_sync_in_sample_rate(hdspm);
2116                         break;
2117                 default:
2118                         ucontrol->value.enumerated.item[0] =
2119                                 hdspm_get_s1_sample_rate(hdspm,
2120                                                 ucontrol->id.index-1);
2121                 }
2122
2123         case AES32:
2124
2125                 switch (kcontrol->private_value) {
2126                 case 0: /* WC */
2127                         ucontrol->value.enumerated.item[0] =
2128                                 hdspm_get_wc_sample_rate(hdspm);
2129                         break;
2130                 case 9: /* TCO */
2131                         ucontrol->value.enumerated.item[0] =
2132                                 hdspm_get_tco_sample_rate(hdspm);
2133                         break;
2134                 case 10: /* SYNC_IN */
2135                         ucontrol->value.enumerated.item[0] =
2136                                 hdspm_get_sync_in_sample_rate(hdspm);
2137                         break;
2138                 default: /* AES1 to AES8 */
2139                         ucontrol->value.enumerated.item[0] =
2140                                 hdspm_get_s1_sample_rate(hdspm,
2141                                                 kcontrol->private_value-1);
2142                         break;
2143
2144                 }
2145         default:
2146                 break;
2147         }
2148
2149         return 0;
2150 }
2151
2152
2153 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2154 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2155         .name = xname, \
2156         .index = xindex, \
2157         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2158                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2159         .info = snd_hdspm_info_system_clock_mode, \
2160         .get = snd_hdspm_get_system_clock_mode, \
2161         .put = snd_hdspm_put_system_clock_mode, \
2162 }
2163
2164
2165 /**
2166  * Returns the system clock mode for the given card.
2167  * @returns 0 - master, 1 - slave
2168  **/
2169 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2170 {
2171         switch (hdspm->io_type) {
2172         case AIO:
2173         case RayDAT:
2174                 if (hdspm->settings_register & HDSPM_c0Master)
2175                         return 0;
2176                 break;
2177
2178         default:
2179                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2180                         return 0;
2181         }
2182
2183         return 1;
2184 }
2185
2186
2187 /**
2188  * Sets the system clock mode.
2189  * @param mode 0 - master, 1 - slave
2190  **/
2191 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2192 {
2193         switch (hdspm->io_type) {
2194         case AIO:
2195         case RayDAT:
2196                 if (0 == mode)
2197                         hdspm->settings_register |= HDSPM_c0Master;
2198                 else
2199                         hdspm->settings_register &= ~HDSPM_c0Master;
2200
2201                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2202                 break;
2203
2204         default:
2205                 if (0 == mode)
2206                         hdspm->control_register |= HDSPM_ClockModeMaster;
2207                 else
2208                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2209
2210                 hdspm_write(hdspm, HDSPM_controlRegister,
2211                                 hdspm->control_register);
2212         }
2213 }
2214
2215
2216 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2217                                             struct snd_ctl_elem_info *uinfo)
2218 {
2219         static char *texts[] = { "Master", "AutoSync" };
2220
2221         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2222         uinfo->count = 1;
2223         uinfo->value.enumerated.items = 2;
2224         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2225                 uinfo->value.enumerated.item =
2226                     uinfo->value.enumerated.items - 1;
2227         strcpy(uinfo->value.enumerated.name,
2228                texts[uinfo->value.enumerated.item]);
2229         return 0;
2230 }
2231
2232 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2233                                            struct snd_ctl_elem_value *ucontrol)
2234 {
2235         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2236
2237         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2238         return 0;
2239 }
2240
2241 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2242                                            struct snd_ctl_elem_value *ucontrol)
2243 {
2244         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2245         int val;
2246
2247         if (!snd_hdspm_use_is_exclusive(hdspm))
2248                 return -EBUSY;
2249
2250         val = ucontrol->value.enumerated.item[0];
2251         if (val < 0)
2252                 val = 0;
2253         else if (val > 1)
2254                 val = 1;
2255
2256         hdspm_set_system_clock_mode(hdspm, val);
2257
2258         return 0;
2259 }
2260
2261
2262 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2263 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2264         .name = xname, \
2265         .index = xindex, \
2266         .info = snd_hdspm_info_clock_source, \
2267         .get = snd_hdspm_get_clock_source, \
2268         .put = snd_hdspm_put_clock_source \
2269 }
2270
2271
2272 static int hdspm_clock_source(struct hdspm * hdspm)
2273 {
2274         switch (hdspm->system_sample_rate) {
2275         case 32000: return 0;
2276         case 44100: return 1;
2277         case 48000: return 2;
2278         case 64000: return 3;
2279         case 88200: return 4;
2280         case 96000: return 5;
2281         case 128000: return 6;
2282         case 176400: return 7;
2283         case 192000: return 8;
2284         }
2285
2286         return -1;
2287 }
2288
2289 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2290 {
2291         int rate;
2292         switch (mode) {
2293         case 0:
2294                 rate = 32000; break;
2295         case 1:
2296                 rate = 44100; break;
2297         case 2:
2298                 rate = 48000; break;
2299         case 3:
2300                 rate = 64000; break;
2301         case 4:
2302                 rate = 88200; break;
2303         case 5:
2304                 rate = 96000; break;
2305         case 6:
2306                 rate = 128000; break;
2307         case 7:
2308                 rate = 176400; break;
2309         case 8:
2310                 rate = 192000; break;
2311         default:
2312                 rate = 48000;
2313         }
2314         hdspm_set_rate(hdspm, rate, 1);
2315         return 0;
2316 }
2317
2318 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2319                                        struct snd_ctl_elem_info *uinfo)
2320 {
2321         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2322         uinfo->count = 1;
2323         uinfo->value.enumerated.items = 9;
2324
2325         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2326                 uinfo->value.enumerated.item =
2327                     uinfo->value.enumerated.items - 1;
2328
2329         strcpy(uinfo->value.enumerated.name,
2330                texts_freq[uinfo->value.enumerated.item+1]);
2331
2332         return 0;
2333 }
2334
2335 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2336                                       struct snd_ctl_elem_value *ucontrol)
2337 {
2338         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2339
2340         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2341         return 0;
2342 }
2343
2344 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2345                                       struct snd_ctl_elem_value *ucontrol)
2346 {
2347         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2348         int change;
2349         int val;
2350
2351         if (!snd_hdspm_use_is_exclusive(hdspm))
2352                 return -EBUSY;
2353         val = ucontrol->value.enumerated.item[0];
2354         if (val < 0)
2355                 val = 0;
2356         if (val > 9)
2357                 val = 9;
2358         spin_lock_irq(&hdspm->lock);
2359         if (val != hdspm_clock_source(hdspm))
2360                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2361         else
2362                 change = 0;
2363         spin_unlock_irq(&hdspm->lock);
2364         return change;
2365 }
2366
2367
2368 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2369 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2370         .name = xname, \
2371         .index = xindex, \
2372         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2373                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2374         .info = snd_hdspm_info_pref_sync_ref, \
2375         .get = snd_hdspm_get_pref_sync_ref, \
2376         .put = snd_hdspm_put_pref_sync_ref \
2377 }
2378
2379
2380 /**
2381  * Returns the current preferred sync reference setting.
2382  * The semantics of the return value are depending on the
2383  * card, please see the comments for clarification.
2384  **/
2385 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2386 {
2387         switch (hdspm->io_type) {
2388         case AES32:
2389                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2390                 case 0: return 0;  /* WC */
2391                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2392                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2393                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2394                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2395                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2396                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2397                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2398                                                     return 7; /* AES 7 */
2399                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2400                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2401                 }
2402                 break;
2403
2404         case MADI:
2405         case MADIface:
2406                 if (hdspm->tco) {
2407                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2408                         case 0: return 0;  /* WC */
2409                         case HDSPM_SyncRef0: return 1;  /* MADI */
2410                         case HDSPM_SyncRef1: return 2;  /* TCO */
2411                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2412                                              return 3;  /* SYNC_IN */
2413                         }
2414                 } else {
2415                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2416                         case 0: return 0;  /* WC */
2417                         case HDSPM_SyncRef0: return 1;  /* MADI */
2418                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2419                                              return 2;  /* SYNC_IN */
2420                         }
2421                 }
2422                 break;
2423
2424         case RayDAT:
2425                 if (hdspm->tco) {
2426                         switch ((hdspm->settings_register &
2427                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2428                         case 0: return 0;  /* WC */
2429                         case 3: return 1;  /* ADAT 1 */
2430                         case 4: return 2;  /* ADAT 2 */
2431                         case 5: return 3;  /* ADAT 3 */
2432                         case 6: return 4;  /* ADAT 4 */
2433                         case 1: return 5;  /* AES */
2434                         case 2: return 6;  /* SPDIF */
2435                         case 9: return 7;  /* TCO */
2436                         case 10: return 8; /* SYNC_IN */
2437                         }
2438                 } else {
2439                         switch ((hdspm->settings_register &
2440                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2441                         case 0: return 0;  /* WC */
2442                         case 3: return 1;  /* ADAT 1 */
2443                         case 4: return 2;  /* ADAT 2 */
2444                         case 5: return 3;  /* ADAT 3 */
2445                         case 6: return 4;  /* ADAT 4 */
2446                         case 1: return 5;  /* AES */
2447                         case 2: return 6;  /* SPDIF */
2448                         case 10: return 7; /* SYNC_IN */
2449                         }
2450                 }
2451
2452                 break;
2453
2454         case AIO:
2455                 if (hdspm->tco) {
2456                         switch ((hdspm->settings_register &
2457                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2458                         case 0: return 0;  /* WC */
2459                         case 3: return 1;  /* ADAT */
2460                         case 1: return 2;  /* AES */
2461                         case 2: return 3;  /* SPDIF */
2462                         case 9: return 4;  /* TCO */
2463                         case 10: return 5; /* SYNC_IN */
2464                         }
2465                 } else {
2466                         switch ((hdspm->settings_register &
2467                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2468                         case 0: return 0;  /* WC */
2469                         case 3: return 1;  /* ADAT */
2470                         case 1: return 2;  /* AES */
2471                         case 2: return 3;  /* SPDIF */
2472                         case 10: return 4; /* SYNC_IN */
2473                         }
2474                 }
2475
2476                 break;
2477         }
2478
2479         return -1;
2480 }
2481
2482
2483 /**
2484  * Set the preferred sync reference to <pref>. The semantics
2485  * of <pref> are depending on the card type, see the comments
2486  * for clarification.
2487  **/
2488 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2489 {
2490         int p = 0;
2491
2492         switch (hdspm->io_type) {
2493         case AES32:
2494                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2495                 switch (pref) {
2496                 case 0: /* WC  */
2497                         break;
2498                 case 1: /* AES 1 */
2499                         hdspm->control_register |= HDSPM_SyncRef0;
2500                         break;
2501                 case 2: /* AES 2 */
2502                         hdspm->control_register |= HDSPM_SyncRef1;
2503                         break;
2504                 case 3: /* AES 3 */
2505                         hdspm->control_register |=
2506                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2507                         break;
2508                 case 4: /* AES 4 */
2509                         hdspm->control_register |= HDSPM_SyncRef2;
2510                         break;
2511                 case 5: /* AES 5 */
2512                         hdspm->control_register |=
2513                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2514                         break;
2515                 case 6: /* AES 6 */
2516                         hdspm->control_register |=
2517                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2518                         break;
2519                 case 7: /* AES 7 */
2520                         hdspm->control_register |=
2521                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2522                         break;
2523                 case 8: /* AES 8 */
2524                         hdspm->control_register |= HDSPM_SyncRef3;
2525                         break;
2526                 case 9: /* TCO */
2527                         hdspm->control_register |=
2528                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2529                         break;
2530                 default:
2531                         return -1;
2532                 }
2533
2534                 break;
2535
2536         case MADI:
2537         case MADIface:
2538                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2539                 if (hdspm->tco) {
2540                         switch (pref) {
2541                         case 0: /* WC */
2542                                 break;
2543                         case 1: /* MADI */
2544                                 hdspm->control_register |= HDSPM_SyncRef0;
2545                                 break;
2546                         case 2: /* TCO */
2547                                 hdspm->control_register |= HDSPM_SyncRef1;
2548                                 break;
2549                         case 3: /* SYNC_IN */
2550                                 hdspm->control_register |=
2551                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2552                                 break;
2553                         default:
2554                                 return -1;
2555                         }
2556                 } else {
2557                         switch (pref) {
2558                         case 0: /* WC */
2559                                 break;
2560                         case 1: /* MADI */
2561                                 hdspm->control_register |= HDSPM_SyncRef0;
2562                                 break;
2563                         case 2: /* SYNC_IN */
2564                                 hdspm->control_register |=
2565                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2566                                 break;
2567                         default:
2568                                 return -1;
2569                         }
2570                 }
2571
2572                 break;
2573
2574         case RayDAT:
2575                 if (hdspm->tco) {
2576                         switch (pref) {
2577                         case 0: p = 0; break;  /* WC */
2578                         case 1: p = 3; break;  /* ADAT 1 */
2579                         case 2: p = 4; break;  /* ADAT 2 */
2580                         case 3: p = 5; break;  /* ADAT 3 */
2581                         case 4: p = 6; break;  /* ADAT 4 */
2582                         case 5: p = 1; break;  /* AES */
2583                         case 6: p = 2; break;  /* SPDIF */
2584                         case 7: p = 9; break;  /* TCO */
2585                         case 8: p = 10; break; /* SYNC_IN */
2586                         default: return -1;
2587                         }
2588                 } else {
2589                         switch (pref) {
2590                         case 0: p = 0; break;  /* WC */
2591                         case 1: p = 3; break;  /* ADAT 1 */
2592                         case 2: p = 4; break;  /* ADAT 2 */
2593                         case 3: p = 5; break;  /* ADAT 3 */
2594                         case 4: p = 6; break;  /* ADAT 4 */
2595                         case 5: p = 1; break;  /* AES */
2596                         case 6: p = 2; break;  /* SPDIF */
2597                         case 7: p = 10; break; /* SYNC_IN */
2598                         default: return -1;
2599                         }
2600                 }
2601                 break;
2602
2603         case AIO:
2604                 if (hdspm->tco) {
2605                         switch (pref) {
2606                         case 0: p = 0; break;  /* WC */
2607                         case 1: p = 3; break;  /* ADAT */
2608                         case 2: p = 1; break;  /* AES */
2609                         case 3: p = 2; break;  /* SPDIF */
2610                         case 4: p = 9; break;  /* TCO */
2611                         case 5: p = 10; break; /* SYNC_IN */
2612                         default: return -1;
2613                         }
2614                 } else {
2615                         switch (pref) {
2616                         case 0: p = 0; break;  /* WC */
2617                         case 1: p = 3; break;  /* ADAT */
2618                         case 2: p = 1; break;  /* AES */
2619                         case 3: p = 2; break;  /* SPDIF */
2620                         case 4: p = 10; break; /* SYNC_IN */
2621                         default: return -1;
2622                         }
2623                 }
2624                 break;
2625         }
2626
2627         switch (hdspm->io_type) {
2628         case RayDAT:
2629         case AIO:
2630                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2631                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2632                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2633                 break;
2634
2635         case MADI:
2636         case MADIface:
2637         case AES32:
2638                 hdspm_write(hdspm, HDSPM_controlRegister,
2639                                 hdspm->control_register);
2640         }
2641
2642         return 0;
2643 }
2644
2645
2646 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2647                                         struct snd_ctl_elem_info *uinfo)
2648 {
2649         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2650
2651         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2652         uinfo->count = 1;
2653         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2654
2655         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2656                 uinfo->value.enumerated.item =
2657                         uinfo->value.enumerated.items - 1;
2658
2659         strcpy(uinfo->value.enumerated.name,
2660                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2661
2662         return 0;
2663 }
2664
2665 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2666                                        struct snd_ctl_elem_value *ucontrol)
2667 {
2668         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2669         int psf = hdspm_pref_sync_ref(hdspm);
2670
2671         if (psf >= 0) {
2672                 ucontrol->value.enumerated.item[0] = psf;
2673                 return 0;
2674         }
2675
2676         return -1;
2677 }
2678
2679 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2680                                        struct snd_ctl_elem_value *ucontrol)
2681 {
2682         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2683         int val, change = 0;
2684
2685         if (!snd_hdspm_use_is_exclusive(hdspm))
2686                 return -EBUSY;
2687
2688         val = ucontrol->value.enumerated.item[0];
2689
2690         if (val < 0)
2691                 val = 0;
2692         else if (val >= hdspm->texts_autosync_items)
2693                 val = hdspm->texts_autosync_items-1;
2694
2695         spin_lock_irq(&hdspm->lock);
2696         if (val != hdspm_pref_sync_ref(hdspm))
2697                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2698
2699         spin_unlock_irq(&hdspm->lock);
2700         return change;
2701 }
2702
2703
2704 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2705 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2706   .name = xname, \
2707   .index = xindex, \
2708   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2709   .info = snd_hdspm_info_autosync_ref, \
2710   .get = snd_hdspm_get_autosync_ref, \
2711 }
2712
2713 static int hdspm_autosync_ref(struct hdspm *hdspm)
2714 {
2715         if (AES32 == hdspm->io_type) {
2716                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2717                 unsigned int syncref =
2718                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2719                 if (syncref == 0)
2720                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2721                 if (syncref <= 8)
2722                         return syncref;
2723                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2724         } else if (MADI == hdspm->io_type) {
2725                 /* This looks at the autosync selected sync reference */
2726                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2727
2728                 switch (status2 & HDSPM_SelSyncRefMask) {
2729                 case HDSPM_SelSyncRef_WORD:
2730                         return HDSPM_AUTOSYNC_FROM_WORD;
2731                 case HDSPM_SelSyncRef_MADI:
2732                         return HDSPM_AUTOSYNC_FROM_MADI;
2733                 case HDSPM_SelSyncRef_TCO:
2734                         return HDSPM_AUTOSYNC_FROM_TCO;
2735                 case HDSPM_SelSyncRef_SyncIn:
2736                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2737                 case HDSPM_SelSyncRef_NVALID:
2738                         return HDSPM_AUTOSYNC_FROM_NONE;
2739                 default:
2740                         return 0;
2741                 }
2742
2743         }
2744         return 0;
2745 }
2746
2747
2748 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2749                                        struct snd_ctl_elem_info *uinfo)
2750 {
2751         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2752
2753         if (AES32 == hdspm->io_type) {
2754                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2755                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2756
2757                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2758                 uinfo->count = 1;
2759                 uinfo->value.enumerated.items = 10;
2760                 if (uinfo->value.enumerated.item >=
2761                     uinfo->value.enumerated.items)
2762                         uinfo->value.enumerated.item =
2763                                 uinfo->value.enumerated.items - 1;
2764                 strcpy(uinfo->value.enumerated.name,
2765                                 texts[uinfo->value.enumerated.item]);
2766         } else if (MADI == hdspm->io_type) {
2767                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2768                         "Sync In", "None" };
2769
2770                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2771                 uinfo->count = 1;
2772                 uinfo->value.enumerated.items = 5;
2773                 if (uinfo->value.enumerated.item >=
2774                                 uinfo->value.enumerated.items)
2775                         uinfo->value.enumerated.item =
2776                                 uinfo->value.enumerated.items - 1;
2777                 strcpy(uinfo->value.enumerated.name,
2778                                 texts[uinfo->value.enumerated.item]);
2779         }
2780         return 0;
2781 }
2782
2783 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2784                                       struct snd_ctl_elem_value *ucontrol)
2785 {
2786         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2787
2788         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2789         return 0;
2790 }
2791
2792
2793 #define HDSPM_LINE_OUT(xname, xindex) \
2794 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2795   .name = xname, \
2796   .index = xindex, \
2797   .info = snd_hdspm_info_line_out, \
2798   .get = snd_hdspm_get_line_out, \
2799   .put = snd_hdspm_put_line_out \
2800 }
2801
2802 static int hdspm_line_out(struct hdspm * hdspm)
2803 {
2804         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2805 }
2806
2807
2808 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2809 {
2810         if (out)
2811                 hdspm->control_register |= HDSPM_LineOut;
2812         else
2813                 hdspm->control_register &= ~HDSPM_LineOut;
2814         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2815
2816         return 0;
2817 }
2818
2819 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
2820
2821 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2822                                   struct snd_ctl_elem_value *ucontrol)
2823 {
2824         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2825
2826         spin_lock_irq(&hdspm->lock);
2827         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2828         spin_unlock_irq(&hdspm->lock);
2829         return 0;
2830 }
2831
2832 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2833                                   struct snd_ctl_elem_value *ucontrol)
2834 {
2835         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2836         int change;
2837         unsigned int val;
2838
2839         if (!snd_hdspm_use_is_exclusive(hdspm))
2840                 return -EBUSY;
2841         val = ucontrol->value.integer.value[0] & 1;
2842         spin_lock_irq(&hdspm->lock);
2843         change = (int) val != hdspm_line_out(hdspm);
2844         hdspm_set_line_output(hdspm, val);
2845         spin_unlock_irq(&hdspm->lock);
2846         return change;
2847 }
2848
2849
2850 #define HDSPM_TX_64(xname, xindex) \
2851 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2852   .name = xname, \
2853   .index = xindex, \
2854   .info = snd_hdspm_info_tx_64, \
2855   .get = snd_hdspm_get_tx_64, \
2856   .put = snd_hdspm_put_tx_64 \
2857 }
2858
2859 static int hdspm_tx_64(struct hdspm * hdspm)
2860 {
2861         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2862 }
2863
2864 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2865 {
2866         if (out)
2867                 hdspm->control_register |= HDSPM_TX_64ch;
2868         else
2869                 hdspm->control_register &= ~HDSPM_TX_64ch;
2870         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2871
2872         return 0;
2873 }
2874
2875 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
2876
2877 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2878                                struct snd_ctl_elem_value *ucontrol)
2879 {
2880         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2881
2882         spin_lock_irq(&hdspm->lock);
2883         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2884         spin_unlock_irq(&hdspm->lock);
2885         return 0;
2886 }
2887
2888 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2889                                struct snd_ctl_elem_value *ucontrol)
2890 {
2891         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2892         int change;
2893         unsigned int val;
2894
2895         if (!snd_hdspm_use_is_exclusive(hdspm))
2896                 return -EBUSY;
2897         val = ucontrol->value.integer.value[0] & 1;
2898         spin_lock_irq(&hdspm->lock);
2899         change = (int) val != hdspm_tx_64(hdspm);
2900         hdspm_set_tx_64(hdspm, val);
2901         spin_unlock_irq(&hdspm->lock);
2902         return change;
2903 }
2904
2905
2906 #define HDSPM_C_TMS(xname, xindex) \
2907 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2908   .name = xname, \
2909   .index = xindex, \
2910   .info = snd_hdspm_info_c_tms, \
2911   .get = snd_hdspm_get_c_tms, \
2912   .put = snd_hdspm_put_c_tms \
2913 }
2914
2915 static int hdspm_c_tms(struct hdspm * hdspm)
2916 {
2917         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2918 }
2919
2920 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2921 {
2922         if (out)
2923                 hdspm->control_register |= HDSPM_clr_tms;
2924         else
2925                 hdspm->control_register &= ~HDSPM_clr_tms;
2926         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2927
2928         return 0;
2929 }
2930
2931 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
2932
2933 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2934                                struct snd_ctl_elem_value *ucontrol)
2935 {
2936         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2937
2938         spin_lock_irq(&hdspm->lock);
2939         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2940         spin_unlock_irq(&hdspm->lock);
2941         return 0;
2942 }
2943
2944 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2945                                struct snd_ctl_elem_value *ucontrol)
2946 {
2947         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2948         int change;
2949         unsigned int val;
2950
2951         if (!snd_hdspm_use_is_exclusive(hdspm))
2952                 return -EBUSY;
2953         val = ucontrol->value.integer.value[0] & 1;
2954         spin_lock_irq(&hdspm->lock);
2955         change = (int) val != hdspm_c_tms(hdspm);
2956         hdspm_set_c_tms(hdspm, val);
2957         spin_unlock_irq(&hdspm->lock);
2958         return change;
2959 }
2960
2961
2962 #define HDSPM_SAFE_MODE(xname, xindex) \
2963 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2964   .name = xname, \
2965   .index = xindex, \
2966   .info = snd_hdspm_info_safe_mode, \
2967   .get = snd_hdspm_get_safe_mode, \
2968   .put = snd_hdspm_put_safe_mode \
2969 }
2970
2971 static int hdspm_safe_mode(struct hdspm * hdspm)
2972 {
2973         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2974 }
2975
2976 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2977 {
2978         if (out)
2979                 hdspm->control_register |= HDSPM_AutoInp;
2980         else
2981                 hdspm->control_register &= ~HDSPM_AutoInp;
2982         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2983
2984         return 0;
2985 }
2986
2987 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
2988
2989 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2990                                    struct snd_ctl_elem_value *ucontrol)
2991 {
2992         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2993
2994         spin_lock_irq(&hdspm->lock);
2995         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2996         spin_unlock_irq(&hdspm->lock);
2997         return 0;
2998 }
2999
3000 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3001                                    struct snd_ctl_elem_value *ucontrol)
3002 {
3003         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3004         int change;
3005         unsigned int val;
3006
3007         if (!snd_hdspm_use_is_exclusive(hdspm))
3008                 return -EBUSY;
3009         val = ucontrol->value.integer.value[0] & 1;
3010         spin_lock_irq(&hdspm->lock);
3011         change = (int) val != hdspm_safe_mode(hdspm);
3012         hdspm_set_safe_mode(hdspm, val);
3013         spin_unlock_irq(&hdspm->lock);
3014         return change;
3015 }
3016
3017
3018 #define HDSPM_EMPHASIS(xname, xindex) \
3019 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3020   .name = xname, \
3021   .index = xindex, \
3022   .info = snd_hdspm_info_emphasis, \
3023   .get = snd_hdspm_get_emphasis, \
3024   .put = snd_hdspm_put_emphasis \
3025 }
3026
3027 static int hdspm_emphasis(struct hdspm * hdspm)
3028 {
3029         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3030 }
3031
3032 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3033 {
3034         if (emp)
3035                 hdspm->control_register |= HDSPM_Emphasis;
3036         else
3037                 hdspm->control_register &= ~HDSPM_Emphasis;
3038         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3039
3040         return 0;
3041 }
3042
3043 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
3044
3045 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3046                                   struct snd_ctl_elem_value *ucontrol)
3047 {
3048         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3049
3050         spin_lock_irq(&hdspm->lock);
3051         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3052         spin_unlock_irq(&hdspm->lock);
3053         return 0;
3054 }
3055
3056 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3057                                   struct snd_ctl_elem_value *ucontrol)
3058 {
3059         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3060         int change;
3061         unsigned int val;
3062
3063         if (!snd_hdspm_use_is_exclusive(hdspm))
3064                 return -EBUSY;
3065         val = ucontrol->value.integer.value[0] & 1;
3066         spin_lock_irq(&hdspm->lock);
3067         change = (int) val != hdspm_emphasis(hdspm);
3068         hdspm_set_emphasis(hdspm, val);
3069         spin_unlock_irq(&hdspm->lock);
3070         return change;
3071 }
3072
3073
3074 #define HDSPM_DOLBY(xname, xindex) \
3075 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3076   .name = xname, \
3077   .index = xindex, \
3078   .info = snd_hdspm_info_dolby, \
3079   .get = snd_hdspm_get_dolby, \
3080   .put = snd_hdspm_put_dolby \
3081 }
3082
3083 static int hdspm_dolby(struct hdspm * hdspm)
3084 {
3085         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3086 }
3087
3088 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3089 {
3090         if (dol)
3091                 hdspm->control_register |= HDSPM_Dolby;
3092         else
3093                 hdspm->control_register &= ~HDSPM_Dolby;
3094         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3095
3096         return 0;
3097 }
3098
3099 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
3100
3101 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3102                                struct snd_ctl_elem_value *ucontrol)
3103 {
3104         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3105
3106         spin_lock_irq(&hdspm->lock);
3107         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3108         spin_unlock_irq(&hdspm->lock);
3109         return 0;
3110 }
3111
3112 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3113                                struct snd_ctl_elem_value *ucontrol)
3114 {
3115         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3116         int change;
3117         unsigned int val;
3118
3119         if (!snd_hdspm_use_is_exclusive(hdspm))
3120                 return -EBUSY;
3121         val = ucontrol->value.integer.value[0] & 1;
3122         spin_lock_irq(&hdspm->lock);
3123         change = (int) val != hdspm_dolby(hdspm);
3124         hdspm_set_dolby(hdspm, val);
3125         spin_unlock_irq(&hdspm->lock);
3126         return change;
3127 }
3128
3129
3130 #define HDSPM_PROFESSIONAL(xname, xindex) \
3131 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3132   .name = xname, \
3133   .index = xindex, \
3134   .info = snd_hdspm_info_professional, \
3135   .get = snd_hdspm_get_professional, \
3136   .put = snd_hdspm_put_professional \
3137 }
3138
3139 static int hdspm_professional(struct hdspm * hdspm)
3140 {
3141         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3142 }
3143
3144 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3145 {
3146         if (dol)
3147                 hdspm->control_register |= HDSPM_Professional;
3148         else
3149                 hdspm->control_register &= ~HDSPM_Professional;
3150         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3151
3152         return 0;
3153 }
3154
3155 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
3156
3157 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3158                                       struct snd_ctl_elem_value *ucontrol)
3159 {
3160         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3161
3162         spin_lock_irq(&hdspm->lock);
3163         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3164         spin_unlock_irq(&hdspm->lock);
3165         return 0;
3166 }
3167
3168 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3169                                       struct snd_ctl_elem_value *ucontrol)
3170 {
3171         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3172         int change;
3173         unsigned int val;
3174
3175         if (!snd_hdspm_use_is_exclusive(hdspm))
3176                 return -EBUSY;
3177         val = ucontrol->value.integer.value[0] & 1;
3178         spin_lock_irq(&hdspm->lock);
3179         change = (int) val != hdspm_professional(hdspm);
3180         hdspm_set_professional(hdspm, val);
3181         spin_unlock_irq(&hdspm->lock);
3182         return change;
3183 }
3184
3185 #define HDSPM_INPUT_SELECT(xname, xindex) \
3186 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3187   .name = xname, \
3188   .index = xindex, \
3189   .info = snd_hdspm_info_input_select, \
3190   .get = snd_hdspm_get_input_select, \
3191   .put = snd_hdspm_put_input_select \
3192 }
3193
3194 static int hdspm_input_select(struct hdspm * hdspm)
3195 {
3196         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3197 }
3198
3199 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3200 {
3201         if (out)
3202                 hdspm->control_register |= HDSPM_InputSelect0;
3203         else
3204                 hdspm->control_register &= ~HDSPM_InputSelect0;
3205         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3206
3207         return 0;
3208 }
3209
3210 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3211                                        struct snd_ctl_elem_info *uinfo)
3212 {
3213         static char *texts[] = { "optical", "coaxial" };
3214
3215         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3216         uinfo->count = 1;
3217         uinfo->value.enumerated.items = 2;
3218
3219         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3220                 uinfo->value.enumerated.item =
3221                     uinfo->value.enumerated.items - 1;
3222         strcpy(uinfo->value.enumerated.name,
3223                texts[uinfo->value.enumerated.item]);
3224
3225         return 0;
3226 }
3227
3228 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3229                                       struct snd_ctl_elem_value *ucontrol)
3230 {
3231         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3232
3233         spin_lock_irq(&hdspm->lock);
3234         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3235         spin_unlock_irq(&hdspm->lock);
3236         return 0;
3237 }
3238
3239 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3240                                       struct snd_ctl_elem_value *ucontrol)
3241 {
3242         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3243         int change;
3244         unsigned int val;
3245
3246         if (!snd_hdspm_use_is_exclusive(hdspm))
3247                 return -EBUSY;
3248         val = ucontrol->value.integer.value[0] & 1;
3249         spin_lock_irq(&hdspm->lock);
3250         change = (int) val != hdspm_input_select(hdspm);
3251         hdspm_set_input_select(hdspm, val);
3252         spin_unlock_irq(&hdspm->lock);
3253         return change;
3254 }
3255
3256
3257 #define HDSPM_DS_WIRE(xname, xindex) \
3258 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3259   .name = xname, \
3260   .index = xindex, \
3261   .info = snd_hdspm_info_ds_wire, \
3262   .get = snd_hdspm_get_ds_wire, \
3263   .put = snd_hdspm_put_ds_wire \
3264 }
3265
3266 static int hdspm_ds_wire(struct hdspm * hdspm)
3267 {
3268         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3269 }
3270
3271 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3272 {
3273         if (ds)
3274                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3275         else
3276                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3277         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3278
3279         return 0;
3280 }
3281
3282 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3283                                   struct snd_ctl_elem_info *uinfo)
3284 {
3285         static char *texts[] = { "Single", "Double" };
3286
3287         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3288         uinfo->count = 1;
3289         uinfo->value.enumerated.items = 2;
3290
3291         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3292                 uinfo->value.enumerated.item =
3293                     uinfo->value.enumerated.items - 1;
3294         strcpy(uinfo->value.enumerated.name,
3295                texts[uinfo->value.enumerated.item]);
3296
3297         return 0;
3298 }
3299
3300 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3301                                  struct snd_ctl_elem_value *ucontrol)
3302 {
3303         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3304
3305         spin_lock_irq(&hdspm->lock);
3306         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3307         spin_unlock_irq(&hdspm->lock);
3308         return 0;
3309 }
3310
3311 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3312                                  struct snd_ctl_elem_value *ucontrol)
3313 {
3314         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3315         int change;
3316         unsigned int val;
3317
3318         if (!snd_hdspm_use_is_exclusive(hdspm))
3319                 return -EBUSY;
3320         val = ucontrol->value.integer.value[0] & 1;
3321         spin_lock_irq(&hdspm->lock);
3322         change = (int) val != hdspm_ds_wire(hdspm);
3323         hdspm_set_ds_wire(hdspm, val);
3324         spin_unlock_irq(&hdspm->lock);
3325         return change;
3326 }
3327
3328
3329 #define HDSPM_QS_WIRE(xname, xindex) \
3330 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3331   .name = xname, \
3332   .index = xindex, \
3333   .info = snd_hdspm_info_qs_wire, \
3334   .get = snd_hdspm_get_qs_wire, \
3335   .put = snd_hdspm_put_qs_wire \
3336 }
3337
3338 static int hdspm_qs_wire(struct hdspm * hdspm)
3339 {
3340         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3341                 return 1;
3342         if (hdspm->control_register & HDSPM_QS_QuadWire)
3343                 return 2;
3344         return 0;
3345 }
3346
3347 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3348 {
3349         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3350         switch (mode) {
3351         case 0:
3352                 break;
3353         case 1:
3354                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3355                 break;
3356         case 2:
3357                 hdspm->control_register |= HDSPM_QS_QuadWire;
3358                 break;
3359         }
3360         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3361
3362         return 0;
3363 }
3364
3365 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3366                                        struct snd_ctl_elem_info *uinfo)
3367 {
3368         static char *texts[] = { "Single", "Double", "Quad" };
3369
3370         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3371         uinfo->count = 1;
3372         uinfo->value.enumerated.items = 3;
3373
3374         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3375                 uinfo->value.enumerated.item =
3376                     uinfo->value.enumerated.items - 1;
3377         strcpy(uinfo->value.enumerated.name,
3378                texts[uinfo->value.enumerated.item]);
3379
3380         return 0;
3381 }
3382
3383 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3384                                       struct snd_ctl_elem_value *ucontrol)
3385 {
3386         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3387
3388         spin_lock_irq(&hdspm->lock);
3389         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3390         spin_unlock_irq(&hdspm->lock);
3391         return 0;
3392 }
3393
3394 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3395                                       struct snd_ctl_elem_value *ucontrol)
3396 {
3397         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3398         int change;
3399         int val;
3400
3401         if (!snd_hdspm_use_is_exclusive(hdspm))
3402                 return -EBUSY;
3403         val = ucontrol->value.integer.value[0];
3404         if (val < 0)
3405                 val = 0;
3406         if (val > 2)
3407                 val = 2;
3408         spin_lock_irq(&hdspm->lock);
3409         change = val != hdspm_qs_wire(hdspm);
3410         hdspm_set_qs_wire(hdspm, val);
3411         spin_unlock_irq(&hdspm->lock);
3412         return change;
3413 }
3414
3415
3416 #define HDSPM_MIXER(xname, xindex) \
3417 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3418   .name = xname, \
3419   .index = xindex, \
3420   .device = 0, \
3421   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3422                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3423   .info = snd_hdspm_info_mixer, \
3424   .get = snd_hdspm_get_mixer, \
3425   .put = snd_hdspm_put_mixer \
3426 }
3427
3428 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3429                                 struct snd_ctl_elem_info *uinfo)
3430 {
3431         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3432         uinfo->count = 3;
3433         uinfo->value.integer.min = 0;
3434         uinfo->value.integer.max = 65535;
3435         uinfo->value.integer.step = 1;
3436         return 0;
3437 }
3438
3439 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3440                                struct snd_ctl_elem_value *ucontrol)
3441 {
3442         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3443         int source;
3444         int destination;
3445
3446         source = ucontrol->value.integer.value[0];
3447         if (source < 0)
3448                 source = 0;
3449         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3450                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3451
3452         destination = ucontrol->value.integer.value[1];
3453         if (destination < 0)
3454                 destination = 0;
3455         else if (destination >= HDSPM_MAX_CHANNELS)
3456                 destination = HDSPM_MAX_CHANNELS - 1;
3457
3458         spin_lock_irq(&hdspm->lock);
3459         if (source >= HDSPM_MAX_CHANNELS)
3460                 ucontrol->value.integer.value[2] =
3461                     hdspm_read_pb_gain(hdspm, destination,
3462                                        source - HDSPM_MAX_CHANNELS);
3463         else
3464                 ucontrol->value.integer.value[2] =
3465                     hdspm_read_in_gain(hdspm, destination, source);
3466
3467         spin_unlock_irq(&hdspm->lock);
3468
3469         return 0;
3470 }
3471
3472 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3473                                struct snd_ctl_elem_value *ucontrol)
3474 {
3475         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3476         int change;
3477         int source;
3478         int destination;
3479         int gain;
3480
3481         if (!snd_hdspm_use_is_exclusive(hdspm))
3482                 return -EBUSY;
3483
3484         source = ucontrol->value.integer.value[0];
3485         destination = ucontrol->value.integer.value[1];
3486
3487         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3488                 return -1;
3489         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3490                 return -1;
3491
3492         gain = ucontrol->value.integer.value[2];
3493
3494         spin_lock_irq(&hdspm->lock);
3495
3496         if (source >= HDSPM_MAX_CHANNELS)
3497                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3498                                                     source -
3499                                                     HDSPM_MAX_CHANNELS);
3500         else
3501                 change = gain != hdspm_read_in_gain(hdspm, destination,
3502                                                     source);
3503
3504         if (change) {
3505                 if (source >= HDSPM_MAX_CHANNELS)
3506                         hdspm_write_pb_gain(hdspm, destination,
3507                                             source - HDSPM_MAX_CHANNELS,
3508                                             gain);
3509                 else
3510                         hdspm_write_in_gain(hdspm, destination, source,
3511                                             gain);
3512         }
3513         spin_unlock_irq(&hdspm->lock);
3514
3515         return change;
3516 }
3517
3518 /* The simple mixer control(s) provide gain control for the
3519    basic 1:1 mappings of playback streams to output
3520    streams.
3521 */
3522
3523 #define HDSPM_PLAYBACK_MIXER \
3524 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3525   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3526                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3527   .info = snd_hdspm_info_playback_mixer, \
3528   .get = snd_hdspm_get_playback_mixer, \
3529   .put = snd_hdspm_put_playback_mixer \
3530 }
3531
3532 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3533                                          struct snd_ctl_elem_info *uinfo)
3534 {
3535         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3536         uinfo->count = 1;
3537         uinfo->value.integer.min = 0;
3538         uinfo->value.integer.max = 64;
3539         uinfo->value.integer.step = 1;
3540         return 0;
3541 }
3542
3543 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3544                                         struct snd_ctl_elem_value *ucontrol)
3545 {
3546         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3547         int channel;
3548
3549         channel = ucontrol->id.index - 1;
3550
3551         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3552                 return -EINVAL;
3553
3554         spin_lock_irq(&hdspm->lock);
3555         ucontrol->value.integer.value[0] =
3556           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3557         spin_unlock_irq(&hdspm->lock);
3558
3559         return 0;
3560 }
3561
3562 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3563                                         struct snd_ctl_elem_value *ucontrol)
3564 {
3565         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3566         int change;
3567         int channel;
3568         int gain;
3569
3570         if (!snd_hdspm_use_is_exclusive(hdspm))
3571                 return -EBUSY;
3572
3573         channel = ucontrol->id.index - 1;
3574
3575         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3576                 return -EINVAL;
3577
3578         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3579
3580         spin_lock_irq(&hdspm->lock);
3581         change =
3582             gain != hdspm_read_pb_gain(hdspm, channel,
3583                                        channel);
3584         if (change)
3585                 hdspm_write_pb_gain(hdspm, channel, channel,
3586                                     gain);
3587         spin_unlock_irq(&hdspm->lock);
3588         return change;
3589 }
3590
3591 #define HDSPM_SYNC_CHECK(xname, xindex) \
3592 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3593         .name = xname, \
3594         .private_value = xindex, \
3595         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3596         .info = snd_hdspm_info_sync_check, \
3597         .get = snd_hdspm_get_sync_check \
3598 }
3599
3600
3601 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3602                                      struct snd_ctl_elem_info *uinfo)
3603 {
3604         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3605         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3606         uinfo->count = 1;
3607         uinfo->value.enumerated.items = 4;
3608         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3609                 uinfo->value.enumerated.item =
3610                         uinfo->value.enumerated.items - 1;
3611         strcpy(uinfo->value.enumerated.name,
3612                         texts[uinfo->value.enumerated.item]);
3613         return 0;
3614 }
3615
3616 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3617 {
3618         int status, status2;
3619
3620         switch (hdspm->io_type) {
3621         case AES32:
3622                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3623                 if (status & HDSPM_wcSync)
3624                         return 2;
3625                 else if (status & HDSPM_wcLock)
3626                         return 1;
3627                 return 0;
3628                 break;
3629
3630         case MADI:
3631                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3632                 if (status2 & HDSPM_wcLock) {
3633                         if (status2 & HDSPM_wcSync)
3634                                 return 2;
3635                         else
3636                                 return 1;
3637                 }
3638                 return 0;
3639                 break;
3640
3641         case RayDAT:
3642         case AIO:
3643                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3644
3645                 if (status & 0x2000000)
3646                         return 2;
3647                 else if (status & 0x1000000)
3648                         return 1;
3649                 return 0;
3650
3651                 break;
3652
3653         case MADIface:
3654                 break;
3655         }
3656
3657
3658         return 3;
3659 }
3660
3661
3662 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3663 {
3664         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3665         if (status & HDSPM_madiLock) {
3666                 if (status & HDSPM_madiSync)
3667                         return 2;
3668                 else
3669                         return 1;
3670         }
3671         return 0;
3672 }
3673
3674
3675 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3676 {
3677         int status, lock, sync;
3678
3679         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3680
3681         lock = (status & (0x1<<idx)) ? 1 : 0;
3682         sync = (status & (0x100<<idx)) ? 1 : 0;
3683
3684         if (lock && sync)
3685                 return 2;
3686         else if (lock)
3687                 return 1;
3688         return 0;
3689 }
3690
3691
3692 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3693 {
3694         int status, lock = 0, sync = 0;
3695
3696         switch (hdspm->io_type) {
3697         case RayDAT:
3698         case AIO:
3699                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3700                 lock = (status & 0x400) ? 1 : 0;
3701                 sync = (status & 0x800) ? 1 : 0;
3702                 break;
3703
3704         case MADI:
3705         case AES32:
3706                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3707                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3708                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3709                 break;
3710
3711         case MADIface:
3712                 break;
3713         }
3714
3715         if (lock && sync)
3716                 return 2;
3717         else if (lock)
3718                 return 1;
3719
3720         return 0;
3721 }
3722
3723 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3724 {
3725         int status2, lock, sync;
3726         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3727
3728         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3729         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3730
3731         if (sync)
3732                 return 2;
3733         else if (lock)
3734                 return 1;
3735         return 0;
3736 }
3737
3738
3739 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3740 {
3741         int status;
3742
3743         if (hdspm->tco) {
3744                 switch (hdspm->io_type) {
3745                 case MADI:
3746                 case AES32:
3747                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3748                         if (status & HDSPM_tcoLock) {
3749                                 if (status & HDSPM_tcoSync)
3750                                         return 2;
3751                                 else
3752                                         return 1;
3753                         }
3754                         return 0;
3755
3756                         break;
3757
3758                 case RayDAT:
3759                 case AIO:
3760                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3761
3762                         if (status & 0x8000000)
3763                                 return 2; /* Sync */
3764                         if (status & 0x4000000)
3765                                 return 1; /* Lock */
3766                         return 0; /* No signal */
3767                         break;
3768
3769                 default:
3770                         break;
3771                 }
3772         }
3773
3774         return 3; /* N/A */
3775 }
3776
3777
3778 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3779                                     struct snd_ctl_elem_value *ucontrol)
3780 {
3781         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3782         int val = -1;
3783
3784         switch (hdspm->io_type) {
3785         case RayDAT:
3786                 switch (kcontrol->private_value) {
3787                 case 0: /* WC */
3788                         val = hdspm_wc_sync_check(hdspm); break;
3789                 case 7: /* TCO */
3790                         val = hdspm_tco_sync_check(hdspm); break;
3791                 case 8: /* SYNC IN */
3792                         val = hdspm_sync_in_sync_check(hdspm); break;
3793                 default:
3794                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3795                 }
3796
3797         case AIO:
3798                 switch (kcontrol->private_value) {
3799                 case 0: /* WC */
3800                         val = hdspm_wc_sync_check(hdspm); break;
3801                 case 4: /* TCO */
3802                         val = hdspm_tco_sync_check(hdspm); break;
3803                 case 5: /* SYNC IN */
3804                         val = hdspm_sync_in_sync_check(hdspm); break;
3805                 default:
3806                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3807                 }
3808
3809         case MADI:
3810                 switch (kcontrol->private_value) {
3811                 case 0: /* WC */
3812                         val = hdspm_wc_sync_check(hdspm); break;
3813                 case 1: /* MADI */
3814                         val = hdspm_madi_sync_check(hdspm); break;
3815                 case 2: /* TCO */
3816                         val = hdspm_tco_sync_check(hdspm); break;
3817                 case 3: /* SYNC_IN */
3818                         val = hdspm_sync_in_sync_check(hdspm); break;
3819                 }
3820
3821         case MADIface:
3822                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3823                 break;
3824
3825         case AES32:
3826                 switch (kcontrol->private_value) {
3827                 case 0: /* WC */
3828                         val = hdspm_wc_sync_check(hdspm); break;
3829                 case 9: /* TCO */
3830                         val = hdspm_tco_sync_check(hdspm); break;
3831                 case 10 /* SYNC IN */:
3832                         val = hdspm_sync_in_sync_check(hdspm); break;
3833                 default: /* AES1 to AES8 */
3834                          val = hdspm_aes_sync_check(hdspm,
3835                                          kcontrol->private_value-1);
3836                 }
3837
3838         }
3839
3840         if (-1 == val)
3841                 val = 3;
3842
3843         ucontrol->value.enumerated.item[0] = val;
3844         return 0;
3845 }
3846
3847
3848
3849 /**
3850  * TCO controls
3851  **/
3852 static void hdspm_tco_write(struct hdspm *hdspm)
3853 {
3854         unsigned int tc[4] = { 0, 0, 0, 0};
3855
3856         switch (hdspm->tco->input) {
3857         case 0:
3858                 tc[2] |= HDSPM_TCO2_set_input_MSB;
3859                 break;
3860         case 1:
3861                 tc[2] |= HDSPM_TCO2_set_input_LSB;
3862                 break;
3863         default:
3864                 break;
3865         }
3866
3867         switch (hdspm->tco->framerate) {
3868         case 1:
3869                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3870                 break;
3871         case 2:
3872                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3873                 break;
3874         case 3:
3875                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3876                         HDSPM_TCO1_set_drop_frame_flag;
3877                 break;
3878         case 4:
3879                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3880                         HDSPM_TCO1_LTC_Format_MSB;
3881                 break;
3882         case 5:
3883                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3884                         HDSPM_TCO1_LTC_Format_MSB +
3885                         HDSPM_TCO1_set_drop_frame_flag;
3886                 break;
3887         default:
3888                 break;
3889         }
3890
3891         switch (hdspm->tco->wordclock) {
3892         case 1:
3893                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3894                 break;
3895         case 2:
3896                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3897                 break;
3898         default:
3899                 break;
3900         }
3901
3902         switch (hdspm->tco->samplerate) {
3903         case 1:
3904                 tc[2] |= HDSPM_TCO2_set_freq;
3905                 break;
3906         case 2:
3907                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3908                 break;
3909         default:
3910                 break;
3911         }
3912
3913         switch (hdspm->tco->pull) {
3914         case 1:
3915                 tc[2] |= HDSPM_TCO2_set_pull_up;
3916                 break;
3917         case 2:
3918                 tc[2] |= HDSPM_TCO2_set_pull_down;
3919                 break;
3920         case 3:
3921                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
3922                 break;
3923         case 4:
3924                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
3925                 break;
3926         default:
3927                 break;
3928         }
3929
3930         if (1 == hdspm->tco->term) {
3931                 tc[2] |= HDSPM_TCO2_set_term_75R;
3932         }
3933
3934         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
3935         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
3936         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
3937         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
3938 }
3939
3940
3941 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3942 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3943         .name = xname, \
3944         .index = xindex, \
3945         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3946                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3947         .info = snd_hdspm_info_tco_sample_rate, \
3948         .get = snd_hdspm_get_tco_sample_rate, \
3949         .put = snd_hdspm_put_tco_sample_rate \
3950 }
3951
3952 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
3953                                           struct snd_ctl_elem_info *uinfo)
3954 {
3955         static char *texts[] = { "44.1 kHz", "48 kHz" };
3956         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3957         uinfo->count = 1;
3958         uinfo->value.enumerated.items = 2;
3959
3960         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3961                 uinfo->value.enumerated.item =
3962                         uinfo->value.enumerated.items - 1;
3963
3964         strcpy(uinfo->value.enumerated.name,
3965                         texts[uinfo->value.enumerated.item]);
3966
3967         return 0;
3968 }
3969
3970 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
3971                                       struct snd_ctl_elem_value *ucontrol)
3972 {
3973         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3974
3975         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
3976
3977         return 0;
3978 }
3979
3980 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
3981                                          struct snd_ctl_elem_value *ucontrol)
3982 {
3983         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3984
3985         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
3986                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
3987
3988                 hdspm_tco_write(hdspm);
3989
3990                 return 1;
3991         }
3992
3993         return 0;
3994 }
3995
3996
3997 #define HDSPM_TCO_PULL(xname, xindex) \
3998 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3999         .name = xname, \
4000         .index = xindex, \
4001         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4002                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4003         .info = snd_hdspm_info_tco_pull, \
4004         .get = snd_hdspm_get_tco_pull, \
4005         .put = snd_hdspm_put_tco_pull \
4006 }
4007
4008 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4009                                    struct snd_ctl_elem_info *uinfo)
4010 {
4011         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4012         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4013         uinfo->count = 1;
4014         uinfo->value.enumerated.items = 5;
4015
4016         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4017                 uinfo->value.enumerated.item =
4018                         uinfo->value.enumerated.items - 1;
4019
4020         strcpy(uinfo->value.enumerated.name,
4021                         texts[uinfo->value.enumerated.item]);
4022
4023         return 0;
4024 }
4025
4026 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4027                                   struct snd_ctl_elem_value *ucontrol)
4028 {
4029         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4030
4031         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4032
4033         return 0;
4034 }
4035
4036 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4037                                   struct snd_ctl_elem_value *ucontrol)
4038 {
4039         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4040
4041         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4042                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4043
4044                 hdspm_tco_write(hdspm);
4045
4046                 return 1;
4047         }
4048
4049         return 0;
4050 }
4051
4052 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4053 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4054         .name = xname, \
4055         .index = xindex, \
4056         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4057                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4058         .info = snd_hdspm_info_tco_wck_conversion, \
4059         .get = snd_hdspm_get_tco_wck_conversion, \
4060         .put = snd_hdspm_put_tco_wck_conversion \
4061 }
4062
4063 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4064                                              struct snd_ctl_elem_info *uinfo)
4065 {
4066         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4067         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4068         uinfo->count = 1;
4069         uinfo->value.enumerated.items = 3;
4070
4071         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4072                 uinfo->value.enumerated.item =
4073                         uinfo->value.enumerated.items - 1;
4074
4075         strcpy(uinfo->value.enumerated.name,
4076                         texts[uinfo->value.enumerated.item]);
4077
4078         return 0;
4079 }
4080
4081 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4082                                             struct snd_ctl_elem_value *ucontrol)
4083 {
4084         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4085
4086         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4087
4088         return 0;
4089 }
4090
4091 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4092                                             struct snd_ctl_elem_value *ucontrol)
4093 {
4094         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4095
4096         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4097                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4098
4099                 hdspm_tco_write(hdspm);
4100
4101                 return 1;
4102         }
4103
4104         return 0;
4105 }
4106
4107
4108 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4109 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4110         .name = xname, \
4111         .index = xindex, \
4112         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4113                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4114         .info = snd_hdspm_info_tco_frame_rate, \
4115         .get = snd_hdspm_get_tco_frame_rate, \
4116         .put = snd_hdspm_put_tco_frame_rate \
4117 }
4118
4119 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4120                                           struct snd_ctl_elem_info *uinfo)
4121 {
4122         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4123                 "29.97 dfps", "30 fps", "30 dfps" };
4124         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4125         uinfo->count = 1;
4126         uinfo->value.enumerated.items = 6;
4127
4128         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4129                 uinfo->value.enumerated.item =
4130                         uinfo->value.enumerated.items - 1;
4131
4132         strcpy(uinfo->value.enumerated.name,
4133                         texts[uinfo->value.enumerated.item]);
4134
4135         return 0;
4136 }
4137
4138 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4139                                         struct snd_ctl_elem_value *ucontrol)
4140 {
4141         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4142
4143         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4144
4145         return 0;
4146 }
4147
4148 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4149                                         struct snd_ctl_elem_value *ucontrol)
4150 {
4151         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4152
4153         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4154                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4155
4156                 hdspm_tco_write(hdspm);
4157
4158                 return 1;
4159         }
4160
4161         return 0;
4162 }
4163
4164
4165 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4166 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4167         .name = xname, \
4168         .index = xindex, \
4169         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4170                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4171         .info = snd_hdspm_info_tco_sync_source, \
4172         .get = snd_hdspm_get_tco_sync_source, \
4173         .put = snd_hdspm_put_tco_sync_source \
4174 }
4175
4176 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4177                                           struct snd_ctl_elem_info *uinfo)
4178 {
4179         static char *texts[] = { "LTC", "Video", "WCK" };
4180         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4181         uinfo->count = 1;
4182         uinfo->value.enumerated.items = 3;
4183
4184         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4185                 uinfo->value.enumerated.item =
4186                         uinfo->value.enumerated.items - 1;
4187
4188         strcpy(uinfo->value.enumerated.name,
4189                         texts[uinfo->value.enumerated.item]);
4190
4191         return 0;
4192 }
4193
4194 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4195                                          struct snd_ctl_elem_value *ucontrol)
4196 {
4197         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4198
4199         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4200
4201         return 0;
4202 }
4203
4204 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4205                                          struct snd_ctl_elem_value *ucontrol)
4206 {
4207         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4208
4209         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4210                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4211
4212                 hdspm_tco_write(hdspm);
4213
4214                 return 1;
4215         }
4216
4217         return 0;
4218 }
4219
4220
4221 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4222 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4223         .name = xname, \
4224         .index = xindex, \
4225         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4226                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4227         .info = snd_hdspm_info_tco_word_term, \
4228         .get = snd_hdspm_get_tco_word_term, \
4229         .put = snd_hdspm_put_tco_word_term \
4230 }
4231
4232 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4233                                         struct snd_ctl_elem_info *uinfo)
4234 {
4235         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4236         uinfo->count = 1;
4237         uinfo->value.integer.min = 0;
4238         uinfo->value.integer.max = 1;
4239
4240         return 0;
4241 }
4242
4243
4244 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4245                                        struct snd_ctl_elem_value *ucontrol)
4246 {
4247         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4248
4249         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4250
4251         return 0;
4252 }
4253
4254
4255 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4256                                        struct snd_ctl_elem_value *ucontrol)
4257 {
4258         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4259
4260         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4261                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4262
4263                 hdspm_tco_write(hdspm);
4264
4265                 return 1;
4266         }
4267
4268         return 0;
4269 }
4270
4271
4272
4273
4274 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4275         HDSPM_MIXER("Mixer", 0),
4276         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4277         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4278         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4279         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4280         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4281         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4282         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4283         HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4284         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4285         HDSPM_LINE_OUT("Line Out", 0),
4286         HDSPM_TX_64("TX 64 channels mode", 0),
4287         HDSPM_C_TMS("Clear Track Marker", 0),
4288         HDSPM_SAFE_MODE("Safe Mode", 0),
4289         HDSPM_INPUT_SELECT("Input Select", 0)
4290 };
4291
4292
4293 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4294         HDSPM_MIXER("Mixer", 0),
4295         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4296         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4297         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4298         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4299         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4300         HDSPM_TX_64("TX 64 channels mode", 0),
4301         HDSPM_C_TMS("Clear Track Marker", 0),
4302         HDSPM_SAFE_MODE("Safe Mode", 0)
4303 };
4304
4305 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4306         HDSPM_MIXER("Mixer", 0),
4307         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4308         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4309         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4310         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4311         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4312         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4313         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4314         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4315         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4316         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4317         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4318         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4319         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4320         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4321         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4322         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4323         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4324         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4325
4326                 /*
4327                    HDSPM_INPUT_SELECT("Input Select", 0),
4328                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4329                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4330                    HDSPM_SPDIF_IN("SPDIF In", 0);
4331                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4332                    HDSPM_INPUT_LEVEL("Input Level", 0);
4333                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4334                    HDSPM_PHONES("Phones", 0);
4335                    */
4336 };
4337
4338 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4339         HDSPM_MIXER("Mixer", 0),
4340         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4341         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4342         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4343         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4344         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4345         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4346         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4347         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4348         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4349         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4350         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4351         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4352         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4353         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4354         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4355         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4356         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4357         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4358         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4359         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4360         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4361         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4362 };
4363
4364 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4365         HDSPM_MIXER("Mixer", 0),
4366         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4367         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4368         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4369         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4370         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4371         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4372         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4373         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4374         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4375         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4376         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4377         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4378         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4379         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4380         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4381         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4382         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4383         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4384         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4385         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4386         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4387         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4388         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4389         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4390         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4391         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4392         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4393         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4394         HDSPM_LINE_OUT("Line Out", 0),
4395         HDSPM_EMPHASIS("Emphasis", 0),
4396         HDSPM_DOLBY("Non Audio", 0),
4397         HDSPM_PROFESSIONAL("Professional", 0),
4398         HDSPM_C_TMS("Clear Track Marker", 0),
4399         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4400         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4401 };
4402
4403
4404
4405 /* Control elements for the optional TCO module */
4406 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4407         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4408         HDSPM_TCO_PULL("TCO Pull", 0),
4409         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4410         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4411         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4412         HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4413 };
4414
4415
4416 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4417
4418
4419 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4420 {
4421         int i;
4422
4423         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4424                 if (hdspm->system_sample_rate > 48000) {
4425                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4426                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4427                                 SNDRV_CTL_ELEM_ACCESS_READ |
4428                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4429                 } else {
4430                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4431                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4432                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4433                 }
4434                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4435                                 SNDRV_CTL_EVENT_MASK_INFO,
4436                                 &hdspm->playback_mixer_ctls[i]->id);
4437         }
4438
4439         return 0;
4440 }
4441
4442
4443 static int snd_hdspm_create_controls(struct snd_card *card,
4444                                         struct hdspm *hdspm)
4445 {
4446         unsigned int idx, limit;
4447         int err;
4448         struct snd_kcontrol *kctl;
4449         struct snd_kcontrol_new *list = NULL;
4450
4451         switch (hdspm->io_type) {
4452         case MADI:
4453                 list = snd_hdspm_controls_madi;
4454                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4455                 break;
4456         case MADIface:
4457                 list = snd_hdspm_controls_madiface;
4458                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4459                 break;
4460         case AIO:
4461                 list = snd_hdspm_controls_aio;
4462                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4463                 break;
4464         case RayDAT:
4465                 list = snd_hdspm_controls_raydat;
4466                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4467                 break;
4468         case AES32:
4469                 list = snd_hdspm_controls_aes32;
4470                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4471                 break;
4472         }
4473
4474         if (NULL != list) {
4475                 for (idx = 0; idx < limit; idx++) {
4476                         err = snd_ctl_add(card,
4477                                         snd_ctl_new1(&list[idx], hdspm));
4478                         if (err < 0)
4479                                 return err;
4480                 }
4481         }
4482
4483
4484         /* create simple 1:1 playback mixer controls */
4485         snd_hdspm_playback_mixer.name = "Chn";
4486         if (hdspm->system_sample_rate >= 128000) {
4487                 limit = hdspm->qs_out_channels;
4488         } else if (hdspm->system_sample_rate >= 64000) {
4489                 limit = hdspm->ds_out_channels;
4490         } else {
4491                 limit = hdspm->ss_out_channels;
4492         }
4493         for (idx = 0; idx < limit; ++idx) {
4494                 snd_hdspm_playback_mixer.index = idx + 1;
4495                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4496                 err = snd_ctl_add(card, kctl);
4497                 if (err < 0)
4498                         return err;
4499                 hdspm->playback_mixer_ctls[idx] = kctl;
4500         }
4501
4502
4503         if (hdspm->tco) {
4504                 /* add tco control elements */
4505                 list = snd_hdspm_controls_tco;
4506                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4507                 for (idx = 0; idx < limit; idx++) {
4508                         err = snd_ctl_add(card,
4509                                         snd_ctl_new1(&list[idx], hdspm));
4510                         if (err < 0)
4511                                 return err;
4512                 }
4513         }
4514
4515         return 0;
4516 }
4517
4518 /*------------------------------------------------------------
4519    /proc interface
4520  ------------------------------------------------------------*/
4521
4522 static void
4523 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4524                          struct snd_info_buffer *buffer)
4525 {
4526         struct hdspm *hdspm = entry->private_data;
4527         unsigned int status, status2, control, freq;
4528
4529         char *pref_sync_ref;
4530         char *autosync_ref;
4531         char *system_clock_mode;
4532         char *insel;
4533         int x, x2;
4534
4535         /* TCO stuff */
4536         int a, ltc, frames, seconds, minutes, hours;
4537         unsigned int period;
4538         u64 freq_const = 0;
4539         u32 rate;
4540
4541         status = hdspm_read(hdspm, HDSPM_statusRegister);
4542         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4543         control = hdspm->control_register;
4544         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4545
4546         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4547                         hdspm->card_name, hdspm->card->number + 1,
4548                         hdspm->firmware_rev,
4549                         (status2 & HDSPM_version0) |
4550                         (status2 & HDSPM_version1) | (status2 &
4551                                 HDSPM_version2));
4552
4553         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4554                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4555                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4556
4557         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4558                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4559
4560         snd_iprintf(buffer, "--- System ---\n");
4561
4562         snd_iprintf(buffer,
4563                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4564                 status & HDSPM_audioIRQPending,
4565                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4566                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4567                 hdspm->irq_count);
4568         snd_iprintf(buffer,
4569                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4570                 "estimated= %ld (bytes)\n",
4571                 ((status & HDSPM_BufferID) ? 1 : 0),
4572                 (status & HDSPM_BufferPositionMask),
4573                 (status & HDSPM_BufferPositionMask) %
4574                 (2 * (int)hdspm->period_bytes),
4575                 ((status & HDSPM_BufferPositionMask) - 64) %
4576                 (2 * (int)hdspm->period_bytes),
4577                 (long) hdspm_hw_pointer(hdspm) * 4);
4578
4579         snd_iprintf(buffer,
4580                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4581                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4582                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4583                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4584                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4585         snd_iprintf(buffer,
4586                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4587                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4588                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4589         snd_iprintf(buffer,
4590                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4591                 "status2=0x%x\n",
4592                 hdspm->control_register, hdspm->control2_register,
4593                 status, status2);
4594         if (status & HDSPM_tco_detect) {
4595                 snd_iprintf(buffer, "TCO module detected.\n");
4596                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4597                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4598                         snd_iprintf(buffer, "  LTC valid, ");
4599                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4600                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4601                         case 0:
4602                                 snd_iprintf(buffer, "24 fps, ");
4603                                 break;
4604                         case HDSPM_TCO1_LTC_Format_LSB:
4605                                 snd_iprintf(buffer, "25 fps, ");
4606                                 break;
4607                         case HDSPM_TCO1_LTC_Format_MSB:
4608                                 snd_iprintf(buffer, "29.97 fps, ");
4609                                 break;
4610                         default:
4611                                 snd_iprintf(buffer, "30 fps, ");
4612                                 break;
4613                         }
4614                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4615                                 snd_iprintf(buffer, "drop frame\n");
4616                         } else {
4617                                 snd_iprintf(buffer, "full frame\n");
4618                         }
4619                 } else {
4620                         snd_iprintf(buffer, "  no LTC\n");
4621                 }
4622                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4623                         snd_iprintf(buffer, "  Video: NTSC\n");
4624                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4625                         snd_iprintf(buffer, "  Video: PAL\n");
4626                 } else {
4627                         snd_iprintf(buffer, "  No video\n");
4628                 }
4629                 if (a & HDSPM_TCO1_TCO_lock) {
4630                         snd_iprintf(buffer, "  Sync: lock\n");
4631                 } else {
4632                         snd_iprintf(buffer, "  Sync: no lock\n");
4633                 }
4634
4635                 switch (hdspm->io_type) {
4636                 case MADI:
4637                 case AES32:
4638                         freq_const = 110069313433624ULL;
4639                         break;
4640                 case RayDAT:
4641                 case AIO:
4642                         freq_const = 104857600000000ULL;
4643                         break;
4644                 case MADIface:
4645                         break; /* no TCO possible */
4646                 }
4647
4648                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4649                 snd_iprintf(buffer, "    period: %u\n", period);
4650
4651
4652                 /* rate = freq_const/period; */
4653                 rate = div_u64(freq_const, period);
4654
4655                 if (control & HDSPM_QuadSpeed) {
4656                         rate *= 4;
4657                 } else if (control & HDSPM_DoubleSpeed) {
4658                         rate *= 2;
4659                 }
4660
4661                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4662                                 (unsigned int) rate);
4663
4664                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4665                 frames = ltc & 0xF;
4666                 ltc >>= 4;
4667                 frames += (ltc & 0x3) * 10;
4668                 ltc >>= 4;
4669                 seconds = ltc & 0xF;
4670                 ltc >>= 4;
4671                 seconds += (ltc & 0x7) * 10;
4672                 ltc >>= 4;
4673                 minutes = ltc & 0xF;
4674                 ltc >>= 4;
4675                 minutes += (ltc & 0x7) * 10;
4676                 ltc >>= 4;
4677                 hours = ltc & 0xF;
4678                 ltc >>= 4;
4679                 hours += (ltc & 0x3) * 10;
4680                 snd_iprintf(buffer,
4681                         "  LTC In: %02d:%02d:%02d:%02d\n",
4682                         hours, minutes, seconds, frames);
4683
4684         } else {
4685                 snd_iprintf(buffer, "No TCO module detected.\n");
4686         }
4687
4688         snd_iprintf(buffer, "--- Settings ---\n");
4689
4690         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4691                                                         HDSPM_LatencyMask));
4692
4693         snd_iprintf(buffer,
4694                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4695                 x, (unsigned long) hdspm->period_bytes);
4696
4697         snd_iprintf(buffer, "Line out: %s\n",
4698                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4699
4700         switch (hdspm->control_register & HDSPM_InputMask) {
4701         case HDSPM_InputOptical:
4702                 insel = "Optical";
4703                 break;
4704         case HDSPM_InputCoaxial:
4705                 insel = "Coaxial";
4706                 break;
4707         default:
4708                 insel = "Unkown";
4709         }
4710
4711         snd_iprintf(buffer,
4712                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4713                 "Auto Input %s\n",
4714                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4715                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4716                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4717
4718
4719         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4720                 system_clock_mode = "AutoSync";
4721         else
4722                 system_clock_mode = "Master";
4723         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4724
4725         switch (hdspm_pref_sync_ref(hdspm)) {
4726         case HDSPM_SYNC_FROM_WORD:
4727                 pref_sync_ref = "Word Clock";
4728                 break;
4729         case HDSPM_SYNC_FROM_MADI:
4730                 pref_sync_ref = "MADI Sync";
4731                 break;
4732         case HDSPM_SYNC_FROM_TCO:
4733                 pref_sync_ref = "TCO";
4734                 break;
4735         case HDSPM_SYNC_FROM_SYNC_IN:
4736                 pref_sync_ref = "Sync In";
4737                 break;
4738         default:
4739                 pref_sync_ref = "XXXX Clock";
4740                 break;
4741         }
4742         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4743                         pref_sync_ref);
4744
4745         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4746                         hdspm->system_sample_rate);
4747
4748
4749         snd_iprintf(buffer, "--- Status:\n");
4750
4751         x = status & HDSPM_madiSync;
4752         x2 = status2 & HDSPM_wcSync;
4753
4754         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4755                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4756                         "NoLock",
4757                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4758                         "NoLock");
4759
4760         switch (hdspm_autosync_ref(hdspm)) {
4761         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4762                 autosync_ref = "Sync In";
4763                 break;
4764         case HDSPM_AUTOSYNC_FROM_TCO:
4765                 autosync_ref = "TCO";
4766                 break;
4767         case HDSPM_AUTOSYNC_FROM_WORD:
4768                 autosync_ref = "Word Clock";
4769                 break;
4770         case HDSPM_AUTOSYNC_FROM_MADI:
4771                 autosync_ref = "MADI Sync";
4772                 break;
4773         case HDSPM_AUTOSYNC_FROM_NONE:
4774                 autosync_ref = "Input not valid";
4775                 break;
4776         default:
4777                 autosync_ref = "---";
4778                 break;
4779         }
4780         snd_iprintf(buffer,
4781                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4782                 autosync_ref, hdspm_external_sample_rate(hdspm),
4783                 (status & HDSPM_madiFreqMask) >> 22,
4784                 (status2 & HDSPM_wcFreqMask) >> 5);
4785
4786         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4787                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4788                 (status & HDSPM_RX_64ch) ? "64 channels" :
4789                 "56 channels");
4790
4791         snd_iprintf(buffer, "\n");
4792 }
4793
4794 static void
4795 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4796                           struct snd_info_buffer *buffer)
4797 {
4798         struct hdspm *hdspm = entry->private_data;
4799         unsigned int status;
4800         unsigned int status2;
4801         unsigned int timecode;
4802         int pref_syncref;
4803         char *autosync_ref;
4804         int x;
4805
4806         status = hdspm_read(hdspm, HDSPM_statusRegister);
4807         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4808         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4809
4810         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4811                     hdspm->card_name, hdspm->card->number + 1,
4812                     hdspm->firmware_rev);
4813
4814         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4815                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4816
4817         snd_iprintf(buffer, "--- System ---\n");
4818
4819         snd_iprintf(buffer,
4820                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4821                     status & HDSPM_audioIRQPending,
4822                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4823                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4824                     hdspm->irq_count);
4825         snd_iprintf(buffer,
4826                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4827                     "estimated= %ld (bytes)\n",
4828                     ((status & HDSPM_BufferID) ? 1 : 0),
4829                     (status & HDSPM_BufferPositionMask),
4830                     (status & HDSPM_BufferPositionMask) %
4831                     (2 * (int)hdspm->period_bytes),
4832                     ((status & HDSPM_BufferPositionMask) - 64) %
4833                     (2 * (int)hdspm->period_bytes),
4834                     (long) hdspm_hw_pointer(hdspm) * 4);
4835
4836         snd_iprintf(buffer,
4837                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4838                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4839                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4840                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4841                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4842         snd_iprintf(buffer,
4843                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4844                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4845                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4846         snd_iprintf(buffer,
4847                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4848                     "status2=0x%x\n",
4849                     hdspm->control_register, hdspm->control2_register,
4850                     status, status2);
4851
4852         snd_iprintf(buffer, "--- Settings ---\n");
4853
4854         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4855                                 HDSPM_LatencyMask));
4856
4857         snd_iprintf(buffer,
4858                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4859                     x, (unsigned long) hdspm->period_bytes);
4860
4861         snd_iprintf(buffer, "Line out: %s\n",
4862                     (hdspm->
4863                      control_register & HDSPM_LineOut) ? "on " : "off");
4864
4865         snd_iprintf(buffer,
4866                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4867                     (hdspm->
4868                      control_register & HDSPM_clr_tms) ? "on" : "off",
4869                     (hdspm->
4870                      control_register & HDSPM_Emphasis) ? "on" : "off",
4871                     (hdspm->
4872                      control_register & HDSPM_Dolby) ? "on" : "off");
4873
4874
4875         pref_syncref = hdspm_pref_sync_ref(hdspm);
4876         if (pref_syncref == 0)
4877                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4878         else
4879                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4880                                 pref_syncref);
4881
4882         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4883                     hdspm->system_sample_rate);
4884
4885         snd_iprintf(buffer, "Double speed: %s\n",
4886                         hdspm->control_register & HDSPM_DS_DoubleWire?
4887                         "Double wire" : "Single wire");
4888         snd_iprintf(buffer, "Quad speed: %s\n",
4889                         hdspm->control_register & HDSPM_QS_DoubleWire?
4890                         "Double wire" :
4891                         hdspm->control_register & HDSPM_QS_QuadWire?
4892                         "Quad wire" : "Single wire");
4893
4894         snd_iprintf(buffer, "--- Status:\n");
4895
4896         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
4897                     (status & HDSPM_AES32_wcLock) ? "Sync   " : "No Lock",
4898                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4899
4900         for (x = 0; x < 8; x++) {
4901                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
4902                             x+1,
4903                             (status2 & (HDSPM_LockAES >> x)) ?
4904                             "Sync   " : "No Lock",
4905                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4906         }
4907
4908         switch (hdspm_autosync_ref(hdspm)) {
4909         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
4910                 autosync_ref = "None"; break;
4911         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
4912                 autosync_ref = "Word Clock"; break;
4913         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
4914                 autosync_ref = "AES1"; break;
4915         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
4916                 autosync_ref = "AES2"; break;
4917         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
4918                 autosync_ref = "AES3"; break;
4919         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
4920                 autosync_ref = "AES4"; break;
4921         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
4922                 autosync_ref = "AES5"; break;
4923         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
4924                 autosync_ref = "AES6"; break;
4925         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
4926                 autosync_ref = "AES7"; break;
4927         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
4928                 autosync_ref = "AES8"; break;
4929         default:
4930                 autosync_ref = "---"; break;
4931         }
4932         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
4933
4934         snd_iprintf(buffer, "\n");
4935 }
4936
4937 static void
4938 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
4939                          struct snd_info_buffer *buffer)
4940 {
4941         struct hdspm *hdspm = entry->private_data;
4942         unsigned int status1, status2, status3, control, i;
4943         unsigned int lock, sync;
4944
4945         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
4946         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
4947         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
4948
4949         control = hdspm->control_register;
4950
4951         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
4952         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
4953         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
4954
4955
4956         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
4957
4958         snd_iprintf(buffer, "Clock mode      : %s\n",
4959                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
4960         snd_iprintf(buffer, "System frequency: %d Hz\n",
4961                 hdspm_get_system_sample_rate(hdspm));
4962
4963         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
4964
4965         lock = 0x1;
4966         sync = 0x100;
4967
4968         for (i = 0; i < 8; i++) {
4969                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4970                                 i,
4971                                 (status1 & lock) ? 1 : 0,
4972                                 (status1 & sync) ? 1 : 0,
4973                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
4974
4975                 lock = lock<<1;
4976                 sync = sync<<1;
4977         }
4978
4979         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
4980                         (status1 & 0x1000000) ? 1 : 0,
4981                         (status1 & 0x2000000) ? 1 : 0,
4982                         texts_freq[(status1 >> 16) & 0xF]);
4983
4984         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
4985                         (status1 & 0x4000000) ? 1 : 0,
4986                         (status1 & 0x8000000) ? 1 : 0,
4987                         texts_freq[(status1 >> 20) & 0xF]);
4988
4989         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4990                         (status3 & 0x400) ? 1 : 0,
4991                         (status3 & 0x800) ? 1 : 0,
4992                         texts_freq[(status2 >> 12) & 0xF]);
4993
4994 }
4995
4996 #ifdef CONFIG_SND_DEBUG
4997 static void
4998 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
4999                           struct snd_info_buffer *buffer)
5000 {
5001         struct hdspm *hdspm = entry->private_data;
5002
5003         int j,i;
5004
5005         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5006                 snd_iprintf(buffer, "0x%08X: ", i);
5007                 for (j = 0; j < 16; j += 4)
5008                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5009                 snd_iprintf(buffer, "\n");
5010         }
5011 }
5012 #endif
5013
5014
5015 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5016                           struct snd_info_buffer *buffer)
5017 {
5018         struct hdspm *hdspm = entry->private_data;
5019         int i;
5020
5021         snd_iprintf(buffer, "# generated by hdspm\n");
5022
5023         for (i = 0; i < hdspm->max_channels_in; i++) {
5024                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5025         }
5026 }
5027
5028 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5029                           struct snd_info_buffer *buffer)
5030 {
5031         struct hdspm *hdspm = entry->private_data;
5032         int i;
5033
5034         snd_iprintf(buffer, "# generated by hdspm\n");
5035
5036         for (i = 0; i < hdspm->max_channels_out; i++) {
5037                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5038         }
5039 }
5040
5041
5042 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5043 {
5044         struct snd_info_entry *entry;
5045
5046         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5047                 switch (hdspm->io_type) {
5048                 case AES32:
5049                         snd_info_set_text_ops(entry, hdspm,
5050                                         snd_hdspm_proc_read_aes32);
5051                         break;
5052                 case MADI:
5053                         snd_info_set_text_ops(entry, hdspm,
5054                                         snd_hdspm_proc_read_madi);
5055                         break;
5056                 case MADIface:
5057                         /* snd_info_set_text_ops(entry, hdspm,
5058                          snd_hdspm_proc_read_madiface); */
5059                         break;
5060                 case RayDAT:
5061                         snd_info_set_text_ops(entry, hdspm,
5062                                         snd_hdspm_proc_read_raydat);
5063                         break;
5064                 case AIO:
5065                         break;
5066                 }
5067         }
5068
5069         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5070                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5071         }
5072
5073         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5074                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5075         }
5076
5077 #ifdef CONFIG_SND_DEBUG
5078         /* debug file to read all hdspm registers */
5079         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5080                 snd_info_set_text_ops(entry, hdspm,
5081                                 snd_hdspm_proc_read_debug);
5082 #endif
5083 }
5084
5085 /*------------------------------------------------------------
5086    hdspm intitialize
5087  ------------------------------------------------------------*/
5088
5089 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5090 {
5091         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5092            hold it (e.g. during module initialization).
5093            */
5094
5095         /* set defaults:       */
5096
5097         hdspm->settings_register = 0;
5098
5099         switch (hdspm->io_type) {
5100         case MADI:
5101         case MADIface:
5102                 hdspm->control_register =
5103                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5104                 break;
5105
5106         case RayDAT:
5107         case AIO:
5108                 hdspm->settings_register = 0x1 + 0x1000;
5109                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5110                  * line_out */
5111                 hdspm->control_register =
5112                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5113                 break;
5114
5115         case AES32:
5116                 hdspm->control_register =
5117                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5118                         hdspm_encode_latency(7) | /* latency max=8192samples */
5119                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5120                         HDSPM_LineOut | /* Analog output in */
5121                         HDSPM_Professional;  /* Professional mode */
5122                 break;
5123         }
5124
5125         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5126
5127         if (AES32 == hdspm->io_type) {
5128                 /* No control2 register for AES32 */
5129 #ifdef SNDRV_BIG_ENDIAN
5130                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5131 #else
5132                 hdspm->control2_register = 0;
5133 #endif
5134
5135                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5136         }
5137         hdspm_compute_period_size(hdspm);
5138
5139         /* silence everything */
5140
5141         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5142
5143         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5144                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5145         }
5146
5147         /* set a default rate so that the channel map is set up. */
5148         hdspm_set_rate(hdspm, 48000, 1);
5149
5150         return 0;
5151 }
5152
5153
5154 /*------------------------------------------------------------
5155    interrupt
5156  ------------------------------------------------------------*/
5157
5158 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5159 {
5160         struct hdspm *hdspm = (struct hdspm *) dev_id;
5161         unsigned int status;
5162         int i, audio, midi, schedule = 0;
5163         /* cycles_t now; */
5164
5165         status = hdspm_read(hdspm, HDSPM_statusRegister);
5166
5167         audio = status & HDSPM_audioIRQPending;
5168         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5169                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5170
5171         /* now = get_cycles(); */
5172         /**
5173          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5174          *          6       4096   ~256053425     ~514672358
5175          *          5       2048   ~128024983     ~257373821
5176          *          4       1024    ~64023706     ~128718089
5177          *          3        512    ~32005945      ~64385999
5178          *          2        256    ~16003039      ~32260176
5179          *          1        128     ~7998738      ~16194507
5180          *          0         64     ~3998231       ~8191558
5181          **/
5182         /*
5183            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5184            now-hdspm->last_interrupt, status & 0xFFC0);
5185            hdspm->last_interrupt = now;
5186         */
5187
5188         if (!audio && !midi)
5189                 return IRQ_NONE;
5190
5191         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5192         hdspm->irq_count++;
5193
5194
5195         if (audio) {
5196                 if (hdspm->capture_substream)
5197                         snd_pcm_period_elapsed(hdspm->capture_substream);
5198
5199                 if (hdspm->playback_substream)
5200                         snd_pcm_period_elapsed(hdspm->playback_substream);
5201         }
5202
5203         if (midi) {
5204                 i = 0;
5205                 while (i < hdspm->midiPorts) {
5206                         if ((hdspm_read(hdspm,
5207                                 hdspm->midi[i].statusIn) & 0xff) &&
5208                                         (status & hdspm->midi[i].irq)) {
5209                                 /* we disable interrupts for this input until
5210                                  * processing is done
5211                                  */
5212                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5213                                 hdspm_write(hdspm, HDSPM_controlRegister,
5214                                                 hdspm->control_register);
5215                                 hdspm->midi[i].pending = 1;
5216                                 schedule = 1;
5217                         }
5218
5219                         i++;
5220                 }
5221
5222                 if (schedule)
5223                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5224         }
5225
5226         return IRQ_HANDLED;
5227 }
5228
5229 /*------------------------------------------------------------
5230    pcm interface
5231   ------------------------------------------------------------*/
5232
5233
5234 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5235                                               *substream)
5236 {
5237         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5238         return hdspm_hw_pointer(hdspm);
5239 }
5240
5241
5242 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5243 {
5244         struct snd_pcm_runtime *runtime = substream->runtime;
5245         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5246         struct snd_pcm_substream *other;
5247
5248         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5249                 other = hdspm->capture_substream;
5250         else
5251                 other = hdspm->playback_substream;
5252
5253         if (hdspm->running)
5254                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5255         else
5256                 runtime->status->hw_ptr = 0;
5257         if (other) {
5258                 struct snd_pcm_substream *s;
5259                 struct snd_pcm_runtime *oruntime = other->runtime;
5260                 snd_pcm_group_for_each_entry(s, substream) {
5261                         if (s == other) {
5262                                 oruntime->status->hw_ptr =
5263                                         runtime->status->hw_ptr;
5264                                 break;
5265                         }
5266                 }
5267         }
5268         return 0;
5269 }
5270
5271 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5272                                struct snd_pcm_hw_params *params)
5273 {
5274         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5275         int err;
5276         int i;
5277         pid_t this_pid;
5278         pid_t other_pid;
5279
5280         spin_lock_irq(&hdspm->lock);
5281
5282         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5283                 this_pid = hdspm->playback_pid;
5284                 other_pid = hdspm->capture_pid;
5285         } else {
5286                 this_pid = hdspm->capture_pid;
5287                 other_pid = hdspm->playback_pid;
5288         }
5289
5290         if (other_pid > 0 && this_pid != other_pid) {
5291
5292                 /* The other stream is open, and not by the same
5293                    task as this one. Make sure that the parameters
5294                    that matter are the same.
5295                    */
5296
5297                 if (params_rate(params) != hdspm->system_sample_rate) {
5298                         spin_unlock_irq(&hdspm->lock);
5299                         _snd_pcm_hw_param_setempty(params,
5300                                         SNDRV_PCM_HW_PARAM_RATE);
5301                         return -EBUSY;
5302                 }
5303
5304                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5305                         spin_unlock_irq(&hdspm->lock);
5306                         _snd_pcm_hw_param_setempty(params,
5307                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5308                         return -EBUSY;
5309                 }
5310
5311         }
5312         /* We're fine. */
5313         spin_unlock_irq(&hdspm->lock);
5314
5315         /* how to make sure that the rate matches an externally-set one ?   */
5316
5317         spin_lock_irq(&hdspm->lock);
5318         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5319         if (err < 0) {
5320                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5321                 spin_unlock_irq(&hdspm->lock);
5322                 _snd_pcm_hw_param_setempty(params,
5323                                 SNDRV_PCM_HW_PARAM_RATE);
5324                 return err;
5325         }
5326         spin_unlock_irq(&hdspm->lock);
5327
5328         err = hdspm_set_interrupt_interval(hdspm,
5329                         params_period_size(params));
5330         if (err < 0) {
5331                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5332                 _snd_pcm_hw_param_setempty(params,
5333                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5334                 return err;
5335         }
5336
5337         /* Memory allocation, takashi's method, dont know if we should
5338          * spinlock
5339          */
5340         /* malloc all buffer even if not enabled to get sure */
5341         /* Update for MADI rev 204: we need to allocate for all channels,
5342          * otherwise it doesn't work at 96kHz */
5343
5344         err =
5345                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5346         if (err < 0) {
5347                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5348                 return err;
5349         }
5350
5351         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5352
5353                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5354                                 params_channels(params));
5355
5356                 for (i = 0; i < params_channels(params); ++i)
5357                         snd_hdspm_enable_out(hdspm, i, 1);
5358
5359                 hdspm->playback_buffer =
5360                         (unsigned char *) substream->runtime->dma_area;
5361                 snd_printdd("Allocated sample buffer for playback at %p\n",
5362                                 hdspm->playback_buffer);
5363         } else {
5364                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5365                                 params_channels(params));
5366
5367                 for (i = 0; i < params_channels(params); ++i)
5368                         snd_hdspm_enable_in(hdspm, i, 1);
5369
5370                 hdspm->capture_buffer =
5371                         (unsigned char *) substream->runtime->dma_area;
5372                 snd_printdd("Allocated sample buffer for capture at %p\n",
5373                                 hdspm->capture_buffer);
5374         }
5375
5376         /*
5377            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5378            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5379            "playback" : "capture",
5380            snd_pcm_sgbuf_get_addr(substream, 0));
5381            */
5382         /*
5383            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5384            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5385            "playback" : "capture",
5386            params_rate(params), params_channels(params),
5387            params_buffer_size(params));
5388            */
5389
5390
5391         /* Switch to native float format if requested */
5392         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5393                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5394                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5395
5396                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5397         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5398                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5399                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5400
5401                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5402         }
5403         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5404
5405         return 0;
5406 }
5407
5408 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5409 {
5410         int i;
5411         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5412
5413         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5414
5415                 /* params_channels(params) should be enough,
5416                    but to get sure in case of error */
5417                 for (i = 0; i < hdspm->max_channels_out; ++i)
5418                         snd_hdspm_enable_out(hdspm, i, 0);
5419
5420                 hdspm->playback_buffer = NULL;
5421         } else {
5422                 for (i = 0; i < hdspm->max_channels_in; ++i)
5423                         snd_hdspm_enable_in(hdspm, i, 0);
5424
5425                 hdspm->capture_buffer = NULL;
5426
5427         }
5428
5429         snd_pcm_lib_free_pages(substream);
5430
5431         return 0;
5432 }
5433
5434
5435 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5436                 struct snd_pcm_channel_info *info)
5437 {
5438         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5439
5440         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5441                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5442                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5443                         return -EINVAL;
5444                 }
5445
5446                 if (hdspm->channel_map_out[info->channel] < 0) {
5447                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5448                         return -EINVAL;
5449                 }
5450
5451                 info->offset = hdspm->channel_map_out[info->channel] *
5452                         HDSPM_CHANNEL_BUFFER_BYTES;
5453         } else {
5454                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5455                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5456                         return -EINVAL;
5457                 }
5458
5459                 if (hdspm->channel_map_in[info->channel] < 0) {
5460                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5461                         return -EINVAL;
5462                 }
5463
5464                 info->offset = hdspm->channel_map_in[info->channel] *
5465                         HDSPM_CHANNEL_BUFFER_BYTES;
5466         }
5467
5468         info->first = 0;
5469         info->step = 32;
5470         return 0;
5471 }
5472
5473
5474 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5475                 unsigned int cmd, void *arg)
5476 {
5477         switch (cmd) {
5478         case SNDRV_PCM_IOCTL1_RESET:
5479                 return snd_hdspm_reset(substream);
5480
5481         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5482                 {
5483                         struct snd_pcm_channel_info *info = arg;
5484                         return snd_hdspm_channel_info(substream, info);
5485                 }
5486         default:
5487                 break;
5488         }
5489
5490         return snd_pcm_lib_ioctl(substream, cmd, arg);
5491 }
5492
5493 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5494 {
5495         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5496         struct snd_pcm_substream *other;
5497         int running;
5498
5499         spin_lock(&hdspm->lock);
5500         running = hdspm->running;
5501         switch (cmd) {
5502         case SNDRV_PCM_TRIGGER_START:
5503                 running |= 1 << substream->stream;
5504                 break;
5505         case SNDRV_PCM_TRIGGER_STOP:
5506                 running &= ~(1 << substream->stream);
5507                 break;
5508         default:
5509                 snd_BUG();
5510                 spin_unlock(&hdspm->lock);
5511                 return -EINVAL;
5512         }
5513         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5514                 other = hdspm->capture_substream;
5515         else
5516                 other = hdspm->playback_substream;
5517
5518         if (other) {
5519                 struct snd_pcm_substream *s;
5520                 snd_pcm_group_for_each_entry(s, substream) {
5521                         if (s == other) {
5522                                 snd_pcm_trigger_done(s, substream);
5523                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5524                                         running |= 1 << s->stream;
5525                                 else
5526                                         running &= ~(1 << s->stream);
5527                                 goto _ok;
5528                         }
5529                 }
5530                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5531                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5532                                         && substream->stream ==
5533                                         SNDRV_PCM_STREAM_CAPTURE)
5534                                 hdspm_silence_playback(hdspm);
5535                 } else {
5536                         if (running &&
5537                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5538                                 hdspm_silence_playback(hdspm);
5539                 }
5540         } else {
5541                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5542                         hdspm_silence_playback(hdspm);
5543         }
5544 _ok:
5545         snd_pcm_trigger_done(substream, substream);
5546         if (!hdspm->running && running)
5547                 hdspm_start_audio(hdspm);
5548         else if (hdspm->running && !running)
5549                 hdspm_stop_audio(hdspm);
5550         hdspm->running = running;
5551         spin_unlock(&hdspm->lock);
5552
5553         return 0;
5554 }
5555
5556 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5557 {
5558         return 0;
5559 }
5560
5561 static unsigned int period_sizes_old[] = {
5562         64, 128, 256, 512, 1024, 2048, 4096
5563 };
5564
5565 static unsigned int period_sizes_new[] = {
5566         32, 64, 128, 256, 512, 1024, 2048, 4096
5567 };
5568
5569 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5570 static unsigned int raydat_aio_buffer_sizes[] = {
5571         16384
5572 };
5573
5574 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5575         .info = (SNDRV_PCM_INFO_MMAP |
5576                  SNDRV_PCM_INFO_MMAP_VALID |
5577                  SNDRV_PCM_INFO_NONINTERLEAVED |
5578                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5579         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5580         .rates = (SNDRV_PCM_RATE_32000 |
5581                   SNDRV_PCM_RATE_44100 |
5582                   SNDRV_PCM_RATE_48000 |
5583                   SNDRV_PCM_RATE_64000 |
5584                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5585                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5586         .rate_min = 32000,
5587         .rate_max = 192000,
5588         .channels_min = 1,
5589         .channels_max = HDSPM_MAX_CHANNELS,
5590         .buffer_bytes_max =
5591             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5592         .period_bytes_min = (64 * 4),
5593         .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5594         .periods_min = 2,
5595         .periods_max = 512,
5596         .fifo_size = 0
5597 };
5598
5599 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5600         .info = (SNDRV_PCM_INFO_MMAP |
5601                  SNDRV_PCM_INFO_MMAP_VALID |
5602                  SNDRV_PCM_INFO_NONINTERLEAVED |
5603                  SNDRV_PCM_INFO_SYNC_START),
5604         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5605         .rates = (SNDRV_PCM_RATE_32000 |
5606                   SNDRV_PCM_RATE_44100 |
5607                   SNDRV_PCM_RATE_48000 |
5608                   SNDRV_PCM_RATE_64000 |
5609                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5610                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5611         .rate_min = 32000,
5612         .rate_max = 192000,
5613         .channels_min = 1,
5614         .channels_max = HDSPM_MAX_CHANNELS,
5615         .buffer_bytes_max =
5616             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5617         .period_bytes_min = (64 * 4),
5618         .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5619         .periods_min = 2,
5620         .periods_max = 512,
5621         .fifo_size = 0
5622 };
5623
5624 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5625         .count = ARRAY_SIZE(period_sizes_old),
5626         .list = period_sizes_old,
5627         .mask = 0
5628 };
5629
5630 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5631         .count = ARRAY_SIZE(period_sizes_new),
5632         .list = period_sizes_new,
5633         .mask = 0
5634 };
5635
5636 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5637         .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5638         .list = raydat_aio_buffer_sizes,
5639         .mask = 0
5640 };
5641
5642 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5643                                            struct snd_pcm_hw_rule *rule)
5644 {
5645         struct hdspm *hdspm = rule->private;
5646         struct snd_interval *c =
5647             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5648         struct snd_interval *r =
5649             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5650
5651         if (r->min > 96000 && r->max <= 192000) {
5652                 struct snd_interval t = {
5653                         .min = hdspm->qs_in_channels,
5654                         .max = hdspm->qs_in_channels,
5655                         .integer = 1,
5656                 };
5657                 return snd_interval_refine(c, &t);
5658         } else if (r->min > 48000 && r->max <= 96000) {
5659                 struct snd_interval t = {
5660                         .min = hdspm->ds_in_channels,
5661                         .max = hdspm->ds_in_channels,
5662                         .integer = 1,
5663                 };
5664                 return snd_interval_refine(c, &t);
5665         } else if (r->max < 64000) {
5666                 struct snd_interval t = {
5667                         .min = hdspm->ss_in_channels,
5668                         .max = hdspm->ss_in_channels,
5669                         .integer = 1,
5670                 };
5671                 return snd_interval_refine(c, &t);
5672         }
5673
5674         return 0;
5675 }
5676
5677 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5678                                            struct snd_pcm_hw_rule * rule)
5679 {
5680         struct hdspm *hdspm = rule->private;
5681         struct snd_interval *c =
5682             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5683         struct snd_interval *r =
5684             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5685
5686         if (r->min > 96000 && r->max <= 192000) {
5687                 struct snd_interval t = {
5688                         .min = hdspm->qs_out_channels,
5689                         .max = hdspm->qs_out_channels,
5690                         .integer = 1,
5691                 };
5692                 return snd_interval_refine(c, &t);
5693         } else if (r->min > 48000 && r->max <= 96000) {
5694                 struct snd_interval t = {
5695                         .min = hdspm->ds_out_channels,
5696                         .max = hdspm->ds_out_channels,
5697                         .integer = 1,
5698                 };
5699                 return snd_interval_refine(c, &t);
5700         } else if (r->max < 64000) {
5701                 struct snd_interval t = {
5702                         .min = hdspm->ss_out_channels,
5703                         .max = hdspm->ss_out_channels,
5704                         .integer = 1,
5705                 };
5706                 return snd_interval_refine(c, &t);
5707         } else {
5708         }
5709         return 0;
5710 }
5711
5712 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5713                                            struct snd_pcm_hw_rule * rule)
5714 {
5715         struct hdspm *hdspm = rule->private;
5716         struct snd_interval *c =
5717             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5718         struct snd_interval *r =
5719             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5720
5721         if (c->min >= hdspm->ss_in_channels) {
5722                 struct snd_interval t = {
5723                         .min = 32000,
5724                         .max = 48000,
5725                         .integer = 1,
5726                 };
5727                 return snd_interval_refine(r, &t);
5728         } else if (c->max <= hdspm->qs_in_channels) {
5729                 struct snd_interval t = {
5730                         .min = 128000,
5731                         .max = 192000,
5732                         .integer = 1,
5733                 };
5734                 return snd_interval_refine(r, &t);
5735         } else if (c->max <= hdspm->ds_in_channels) {
5736                 struct snd_interval t = {
5737                         .min = 64000,
5738                         .max = 96000,
5739                         .integer = 1,
5740                 };
5741                 return snd_interval_refine(r, &t);
5742         }
5743
5744         return 0;
5745 }
5746 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5747                                            struct snd_pcm_hw_rule *rule)
5748 {
5749         struct hdspm *hdspm = rule->private;
5750         struct snd_interval *c =
5751             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5752         struct snd_interval *r =
5753             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5754
5755         if (c->min >= hdspm->ss_out_channels) {
5756                 struct snd_interval t = {
5757                         .min = 32000,
5758                         .max = 48000,
5759                         .integer = 1,
5760                 };
5761                 return snd_interval_refine(r, &t);
5762         } else if (c->max <= hdspm->qs_out_channels) {
5763                 struct snd_interval t = {
5764                         .min = 128000,
5765                         .max = 192000,
5766                         .integer = 1,
5767                 };
5768                 return snd_interval_refine(r, &t);
5769         } else if (c->max <= hdspm->ds_out_channels) {
5770                 struct snd_interval t = {
5771                         .min = 64000,
5772                         .max = 96000,
5773                         .integer = 1,
5774                 };
5775                 return snd_interval_refine(r, &t);
5776         }
5777
5778         return 0;
5779 }
5780
5781 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5782                                       struct snd_pcm_hw_rule *rule)
5783 {
5784         unsigned int list[3];
5785         struct hdspm *hdspm = rule->private;
5786         struct snd_interval *c = hw_param_interval(params,
5787                         SNDRV_PCM_HW_PARAM_CHANNELS);
5788
5789         list[0] = hdspm->qs_in_channels;
5790         list[1] = hdspm->ds_in_channels;
5791         list[2] = hdspm->ss_in_channels;
5792         return snd_interval_list(c, 3, list, 0);
5793 }
5794
5795 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5796                                       struct snd_pcm_hw_rule *rule)
5797 {
5798         unsigned int list[3];
5799         struct hdspm *hdspm = rule->private;
5800         struct snd_interval *c = hw_param_interval(params,
5801                         SNDRV_PCM_HW_PARAM_CHANNELS);
5802
5803         list[0] = hdspm->qs_out_channels;
5804         list[1] = hdspm->ds_out_channels;
5805         list[2] = hdspm->ss_out_channels;
5806         return snd_interval_list(c, 3, list, 0);
5807 }
5808
5809
5810 static unsigned int hdspm_aes32_sample_rates[] = {
5811         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5812 };
5813
5814 static struct snd_pcm_hw_constraint_list
5815 hdspm_hw_constraints_aes32_sample_rates = {
5816         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5817         .list = hdspm_aes32_sample_rates,
5818         .mask = 0
5819 };
5820
5821 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5822 {
5823         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5824         struct snd_pcm_runtime *runtime = substream->runtime;
5825
5826         spin_lock_irq(&hdspm->lock);
5827
5828         snd_pcm_set_sync(substream);
5829
5830
5831         runtime->hw = snd_hdspm_playback_subinfo;
5832
5833         if (hdspm->capture_substream == NULL)
5834                 hdspm_stop_audio(hdspm);
5835
5836         hdspm->playback_pid = current->pid;
5837         hdspm->playback_substream = substream;
5838
5839         spin_unlock_irq(&hdspm->lock);
5840
5841         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5842
5843         switch (hdspm->io_type) {
5844         case AIO:
5845         case RayDAT:
5846                 snd_pcm_hw_constraint_list(runtime, 0,
5847                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5848                                 &hw_constraints_period_sizes_new);
5849                 snd_pcm_hw_constraint_list(runtime, 0,
5850                                 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5851                                 &hw_constraints_raydat_io_buffer);
5852
5853                 break;
5854
5855         default:
5856                 snd_pcm_hw_constraint_list(runtime, 0,
5857                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5858                                 &hw_constraints_period_sizes_old);
5859         }
5860
5861         if (AES32 == hdspm->io_type) {
5862                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5863                                 &hdspm_hw_constraints_aes32_sample_rates);
5864         } else {
5865                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5866                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5867                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5868         }
5869
5870         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5871                         snd_hdspm_hw_rule_out_channels, hdspm,
5872                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5873
5874         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5875                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
5876                         SNDRV_PCM_HW_PARAM_RATE, -1);
5877
5878         return 0;
5879 }
5880
5881 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5882 {
5883         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5884
5885         spin_lock_irq(&hdspm->lock);
5886
5887         hdspm->playback_pid = -1;
5888         hdspm->playback_substream = NULL;
5889
5890         spin_unlock_irq(&hdspm->lock);
5891
5892         return 0;
5893 }
5894
5895
5896 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5897 {
5898         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5899         struct snd_pcm_runtime *runtime = substream->runtime;
5900
5901         spin_lock_irq(&hdspm->lock);
5902         snd_pcm_set_sync(substream);
5903         runtime->hw = snd_hdspm_capture_subinfo;
5904
5905         if (hdspm->playback_substream == NULL)
5906                 hdspm_stop_audio(hdspm);
5907
5908         hdspm->capture_pid = current->pid;
5909         hdspm->capture_substream = substream;
5910
5911         spin_unlock_irq(&hdspm->lock);
5912
5913         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5914         switch (hdspm->io_type) {
5915         case AIO:
5916         case RayDAT:
5917           snd_pcm_hw_constraint_list(runtime, 0,
5918                                      SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5919                                      &hw_constraints_period_sizes_new);
5920           snd_pcm_hw_constraint_list(runtime, 0,
5921                                      SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5922                                      &hw_constraints_raydat_io_buffer);
5923           break;
5924
5925         default:
5926           snd_pcm_hw_constraint_list(runtime, 0,
5927                                      SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5928                                      &hw_constraints_period_sizes_old);
5929         }
5930
5931         if (AES32 == hdspm->io_type) {
5932                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5933                                 &hdspm_hw_constraints_aes32_sample_rates);
5934         } else {
5935                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5936                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
5937                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5938         }
5939
5940         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5941                         snd_hdspm_hw_rule_in_channels, hdspm,
5942                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5943
5944         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5945                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
5946                         SNDRV_PCM_HW_PARAM_RATE, -1);
5947
5948         return 0;
5949 }
5950
5951 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
5952 {
5953         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5954
5955         spin_lock_irq(&hdspm->lock);
5956
5957         hdspm->capture_pid = -1;
5958         hdspm->capture_substream = NULL;
5959
5960         spin_unlock_irq(&hdspm->lock);
5961         return 0;
5962 }
5963
5964 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
5965 {
5966         /* we have nothing to initialize but the call is required */
5967         return 0;
5968 }
5969
5970 static inline int copy_u32_le(void __user *dest, void __iomem *src)
5971 {
5972         u32 val = readl(src);
5973         return copy_to_user(dest, &val, 4);
5974 }
5975
5976 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
5977                 unsigned int cmd, unsigned long __user arg)
5978 {
5979         void __user *argp = (void __user *)arg;
5980         struct hdspm *hdspm = hw->private_data;
5981         struct hdspm_mixer_ioctl mixer;
5982         struct hdspm_config info;
5983         struct hdspm_status status;
5984         struct hdspm_version hdspm_version;
5985         struct hdspm_peak_rms *levels;
5986         struct hdspm_ltc ltc;
5987         unsigned int statusregister;
5988         long unsigned int s;
5989         int i = 0;
5990
5991         switch (cmd) {
5992
5993         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
5994                 levels = &hdspm->peak_rms;
5995                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
5996                         levels->input_peaks[i] =
5997                                 readl(hdspm->iobase +
5998                                                 HDSPM_MADI_INPUT_PEAK + i*4);
5999                         levels->playback_peaks[i] =
6000                                 readl(hdspm->iobase +
6001                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6002                         levels->output_peaks[i] =
6003                                 readl(hdspm->iobase +
6004                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6005
6006                         levels->input_rms[i] =
6007                                 ((uint64_t) readl(hdspm->iobase +
6008                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6009                                 (uint64_t) readl(hdspm->iobase +
6010                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6011                         levels->playback_rms[i] =
6012                                 ((uint64_t)readl(hdspm->iobase +
6013                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6014                                 (uint64_t)readl(hdspm->iobase +
6015                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6016                         levels->output_rms[i] =
6017                                 ((uint64_t)readl(hdspm->iobase +
6018                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6019                                 (uint64_t)readl(hdspm->iobase +
6020                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6021                 }
6022
6023                 if (hdspm->system_sample_rate > 96000) {
6024                         levels->speed = qs;
6025                 } else if (hdspm->system_sample_rate > 48000) {
6026                         levels->speed = ds;
6027                 } else {
6028                         levels->speed = ss;
6029                 }
6030                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6031
6032                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6033                 if (0 != s) {
6034                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6035                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6036                          */
6037                         return -EFAULT;
6038                 }
6039                 break;
6040
6041         case SNDRV_HDSPM_IOCTL_GET_LTC:
6042                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6043                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6044                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6045                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6046                                 HDSPM_TCO1_LTC_Format_MSB)) {
6047                         case 0:
6048                                 ltc.format = fps_24;
6049                                 break;
6050                         case HDSPM_TCO1_LTC_Format_LSB:
6051                                 ltc.format = fps_25;
6052                                 break;
6053                         case HDSPM_TCO1_LTC_Format_MSB:
6054                                 ltc.format = fps_2997;
6055                                 break;
6056                         default:
6057                                 ltc.format = 30;
6058                                 break;
6059                         }
6060                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6061                                 ltc.frame = drop_frame;
6062                         } else {
6063                                 ltc.frame = full_frame;
6064                         }
6065                 } else {
6066                         ltc.format = format_invalid;
6067                         ltc.frame = frame_invalid;
6068                 }
6069                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6070                         ltc.input_format = ntsc;
6071                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6072                         ltc.input_format = pal;
6073                 } else {
6074                         ltc.input_format = no_video;
6075                 }
6076
6077                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6078                 if (0 != s) {
6079                         /*
6080                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6081                         return -EFAULT;
6082                 }
6083
6084                 break;
6085
6086         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6087
6088                 memset(&info, 0, sizeof(info));
6089                 spin_lock_irq(&hdspm->lock);
6090                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6091                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6092
6093                 info.system_sample_rate = hdspm->system_sample_rate;
6094                 info.autosync_sample_rate =
6095                         hdspm_external_sample_rate(hdspm);
6096                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6097                 info.clock_source = hdspm_clock_source(hdspm);
6098                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6099                 info.line_out = hdspm_line_out(hdspm);
6100                 info.passthru = 0;
6101                 spin_unlock_irq(&hdspm->lock);
6102                 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6103                         return -EFAULT;
6104                 break;
6105
6106         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6107                 status.card_type = hdspm->io_type;
6108
6109                 status.autosync_source = hdspm_autosync_ref(hdspm);
6110
6111                 status.card_clock = 110069313433624ULL;
6112                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6113
6114                 switch (hdspm->io_type) {
6115                 case MADI:
6116                 case MADIface:
6117                         status.card_specific.madi.sync_wc =
6118                                 hdspm_wc_sync_check(hdspm);
6119                         status.card_specific.madi.sync_madi =
6120                                 hdspm_madi_sync_check(hdspm);
6121                         status.card_specific.madi.sync_tco =
6122                                 hdspm_tco_sync_check(hdspm);
6123                         status.card_specific.madi.sync_in =
6124                                 hdspm_sync_in_sync_check(hdspm);
6125
6126                         statusregister =
6127                                 hdspm_read(hdspm, HDSPM_statusRegister);
6128                         status.card_specific.madi.madi_input =
6129                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6130                         status.card_specific.madi.channel_format =
6131                                 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6132                         /* TODO: Mac driver sets it when f_s>48kHz */
6133                         status.card_specific.madi.frame_format = 0;
6134
6135                 default:
6136                         break;
6137                 }
6138
6139                 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6140                         return -EFAULT;
6141
6142
6143                 break;
6144
6145         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6146                 hdspm_version.card_type = hdspm->io_type;
6147                 strncpy(hdspm_version.cardname, hdspm->card_name,
6148                                 sizeof(hdspm_version.cardname));
6149                 hdspm_version.serial = (hdspm_read(hdspm,
6150                                         HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6151                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6152                 hdspm_version.addons = 0;
6153                 if (hdspm->tco)
6154                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6155
6156                 if (copy_to_user((void __user *) arg, &hdspm_version,
6157                                         sizeof(hdspm_version)))
6158                         return -EFAULT;
6159                 break;
6160
6161         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6162                 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6163                         return -EFAULT;
6164                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6165                                         sizeof(struct hdspm_mixer)))
6166                         return -EFAULT;
6167                 break;
6168
6169         default:
6170                 return -EINVAL;
6171         }
6172         return 0;
6173 }
6174
6175 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6176         .open = snd_hdspm_playback_open,
6177         .close = snd_hdspm_playback_release,
6178         .ioctl = snd_hdspm_ioctl,
6179         .hw_params = snd_hdspm_hw_params,
6180         .hw_free = snd_hdspm_hw_free,
6181         .prepare = snd_hdspm_prepare,
6182         .trigger = snd_hdspm_trigger,
6183         .pointer = snd_hdspm_hw_pointer,
6184         .page = snd_pcm_sgbuf_ops_page,
6185 };
6186
6187 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6188         .open = snd_hdspm_capture_open,
6189         .close = snd_hdspm_capture_release,
6190         .ioctl = snd_hdspm_ioctl,
6191         .hw_params = snd_hdspm_hw_params,
6192         .hw_free = snd_hdspm_hw_free,
6193         .prepare = snd_hdspm_prepare,
6194         .trigger = snd_hdspm_trigger,
6195         .pointer = snd_hdspm_hw_pointer,
6196         .page = snd_pcm_sgbuf_ops_page,
6197 };
6198
6199 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6200                                             struct hdspm * hdspm)
6201 {
6202         struct snd_hwdep *hw;
6203         int err;
6204
6205         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6206         if (err < 0)
6207                 return err;
6208
6209         hdspm->hwdep = hw;
6210         hw->private_data = hdspm;
6211         strcpy(hw->name, "HDSPM hwdep interface");
6212
6213         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6214         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6215         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6216
6217         return 0;
6218 }
6219
6220
6221 /*------------------------------------------------------------
6222    memory interface
6223  ------------------------------------------------------------*/
6224 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6225 {
6226         int err;
6227         struct snd_pcm *pcm;
6228         size_t wanted;
6229
6230         pcm = hdspm->pcm;
6231
6232         wanted = HDSPM_DMA_AREA_BYTES;
6233
6234         err =
6235              snd_pcm_lib_preallocate_pages_for_all(pcm,
6236                                                    SNDRV_DMA_TYPE_DEV_SG,
6237                                                    snd_dma_pci_data(hdspm->pci),
6238                                                    wanted,
6239                                                    wanted);
6240         if (err < 0) {
6241                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6242
6243                 return err;
6244         } else
6245                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6246
6247         return 0;
6248 }
6249
6250
6251 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6252                             struct snd_pcm_substream *substream,
6253                              unsigned int reg, int channels)
6254 {
6255         int i;
6256
6257         /* continuous memory segment */
6258         for (i = 0; i < (channels * 16); i++)
6259                 hdspm_write(hdspm, reg + 4 * i,
6260                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6261 }
6262
6263
6264 /* ------------- ALSA Devices ---------------------------- */
6265 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6266                                           struct hdspm *hdspm)
6267 {
6268         struct snd_pcm *pcm;
6269         int err;
6270
6271         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6272         if (err < 0)
6273                 return err;
6274
6275         hdspm->pcm = pcm;
6276         pcm->private_data = hdspm;
6277         strcpy(pcm->name, hdspm->card_name);
6278
6279         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6280                         &snd_hdspm_playback_ops);
6281         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6282                         &snd_hdspm_capture_ops);
6283
6284         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6285
6286         err = snd_hdspm_preallocate_memory(hdspm);
6287         if (err < 0)
6288                 return err;
6289
6290         return 0;
6291 }
6292
6293 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6294 {
6295         int i;
6296
6297         for (i = 0; i < hdspm->midiPorts; i++)
6298                 snd_hdspm_flush_midi_input(hdspm, i);
6299 }
6300
6301 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6302                                                    struct hdspm * hdspm)
6303 {
6304         int err, i;
6305
6306         snd_printdd("Create card...\n");
6307         err = snd_hdspm_create_pcm(card, hdspm);
6308         if (err < 0)
6309                 return err;
6310
6311         i = 0;
6312         while (i < hdspm->midiPorts) {
6313                 err = snd_hdspm_create_midi(card, hdspm, i);
6314                 if (err < 0) {
6315                         return err;
6316                 }
6317                 i++;
6318         }
6319
6320         err = snd_hdspm_create_controls(card, hdspm);
6321         if (err < 0)
6322                 return err;
6323
6324         err = snd_hdspm_create_hwdep(card, hdspm);
6325         if (err < 0)
6326                 return err;
6327
6328         snd_printdd("proc init...\n");
6329         snd_hdspm_proc_init(hdspm);
6330
6331         hdspm->system_sample_rate = -1;
6332         hdspm->last_external_sample_rate = -1;
6333         hdspm->last_internal_sample_rate = -1;
6334         hdspm->playback_pid = -1;
6335         hdspm->capture_pid = -1;
6336         hdspm->capture_substream = NULL;
6337         hdspm->playback_substream = NULL;
6338
6339         snd_printdd("Set defaults...\n");
6340         err = snd_hdspm_set_defaults(hdspm);
6341         if (err < 0)
6342                 return err;
6343
6344         snd_printdd("Update mixer controls...\n");
6345         hdspm_update_simple_mixer_controls(hdspm);
6346
6347         snd_printdd("Initializeing complete ???\n");
6348
6349         err = snd_card_register(card);
6350         if (err < 0) {
6351                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6352                 return err;
6353         }
6354
6355         snd_printdd("... yes now\n");
6356
6357         return 0;
6358 }
6359
6360 static int __devinit snd_hdspm_create(struct snd_card *card,
6361                 struct hdspm *hdspm) {
6362
6363         struct pci_dev *pci = hdspm->pci;
6364         int err;
6365         unsigned long io_extent;
6366
6367         hdspm->irq = -1;
6368         hdspm->card = card;
6369
6370         spin_lock_init(&hdspm->lock);
6371
6372         pci_read_config_word(hdspm->pci,
6373                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6374
6375         strcpy(card->mixername, "Xilinx FPGA");
6376         strcpy(card->driver, "HDSPM");
6377
6378         switch (hdspm->firmware_rev) {
6379         case HDSPM_MADI_REV:
6380                 hdspm->io_type = MADI;
6381                 hdspm->card_name = "RME MADI";
6382                 hdspm->midiPorts = 3;
6383                 break;
6384         case HDSPM_RAYDAT_REV:
6385                 hdspm->io_type = RayDAT;
6386                 hdspm->card_name = "RME RayDAT";
6387                 hdspm->midiPorts = 2;
6388                 break;
6389         case HDSPM_AIO_REV:
6390                 hdspm->io_type = AIO;
6391                 hdspm->card_name = "RME AIO";
6392                 hdspm->midiPorts = 1;
6393                 break;
6394         case HDSPM_MADIFACE_REV:
6395                 hdspm->io_type = MADIface;
6396                 hdspm->card_name = "RME MADIface";
6397                 hdspm->midiPorts = 1;
6398                 break;
6399         case HDSPM_AES_REV:
6400         case HDSPM_AES32_REV:
6401         case HDSPM_AES32_OLD_REV:
6402                 hdspm->io_type = AES32;
6403                 hdspm->card_name = "RME AES32";
6404                 hdspm->midiPorts = 2;
6405                 break;
6406         default:
6407                 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
6408                                 hdspm->firmware_rev);
6409                 return -ENODEV;
6410         }
6411
6412         err = pci_enable_device(pci);
6413         if (err < 0)
6414                 return err;
6415
6416         pci_set_master(hdspm->pci);
6417
6418         err = pci_request_regions(pci, "hdspm");
6419         if (err < 0)
6420                 return err;
6421
6422         hdspm->port = pci_resource_start(pci, 0);
6423         io_extent = pci_resource_len(pci, 0);
6424
6425         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6426                         hdspm->port, hdspm->port + io_extent - 1);
6427
6428         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6429         if (!hdspm->iobase) {
6430                 snd_printk(KERN_ERR "HDSPM: "
6431                                 "unable to remap region 0x%lx-0x%lx\n",
6432                                 hdspm->port, hdspm->port + io_extent - 1);
6433                 return -EBUSY;
6434         }
6435         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6436                         (unsigned long)hdspm->iobase, hdspm->port,
6437                         hdspm->port + io_extent - 1);
6438
6439         if (request_irq(pci->irq, snd_hdspm_interrupt,
6440                                 IRQF_SHARED, "hdspm", hdspm)) {
6441                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6442                 return -EBUSY;
6443         }
6444
6445         snd_printdd("use IRQ %d\n", pci->irq);
6446
6447         hdspm->irq = pci->irq;
6448
6449         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6450                         sizeof(struct hdspm_mixer));
6451         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6452         if (!hdspm->mixer) {
6453                 snd_printk(KERN_ERR "HDSPM: "
6454                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6455                                 (int)sizeof(struct hdspm_mixer));
6456                 return err;
6457         }
6458
6459         hdspm->port_names_in = NULL;
6460         hdspm->port_names_out = NULL;
6461
6462         switch (hdspm->io_type) {
6463         case AES32:
6464                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6465                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6466                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6467
6468                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6469                         channel_map_aes32;
6470                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6471                         channel_map_aes32;
6472                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6473                         channel_map_aes32;
6474                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6475                         texts_ports_aes32;
6476                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6477                         texts_ports_aes32;
6478                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6479                         texts_ports_aes32;
6480
6481                 hdspm->max_channels_out = hdspm->max_channels_in =
6482                         AES32_CHANNELS;
6483                 hdspm->port_names_in = hdspm->port_names_out =
6484                         texts_ports_aes32;
6485                 hdspm->channel_map_in = hdspm->channel_map_out =
6486                         channel_map_aes32;
6487
6488                 break;
6489
6490         case MADI:
6491         case MADIface:
6492                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6493                         MADI_SS_CHANNELS;
6494                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6495                         MADI_DS_CHANNELS;
6496                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6497                         MADI_QS_CHANNELS;
6498
6499                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6500                         channel_map_unity_ss;
6501                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6502                         channel_map_unity_ss;
6503                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6504                         channel_map_unity_ss;
6505
6506                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6507                         texts_ports_madi;
6508                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6509                         texts_ports_madi;
6510                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6511                         texts_ports_madi;
6512                 break;
6513
6514         case AIO:
6515                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6516                         snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6517                 }
6518
6519                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6520                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6521                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6522                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6523                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6524                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6525
6526                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6527                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6528                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6529
6530                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6531                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6532                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6533
6534                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6535                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6536                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6537                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6538                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6539                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6540
6541                 break;
6542
6543         case RayDAT:
6544                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6545                         RAYDAT_SS_CHANNELS;
6546                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6547                         RAYDAT_DS_CHANNELS;
6548                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6549                         RAYDAT_QS_CHANNELS;
6550
6551                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6552                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6553
6554                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6555                         channel_map_raydat_ss;
6556                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6557                         channel_map_raydat_ds;
6558                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6559                         channel_map_raydat_qs;
6560                 hdspm->channel_map_in = hdspm->channel_map_out =
6561                         channel_map_raydat_ss;
6562
6563                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6564                         texts_ports_raydat_ss;
6565                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6566                         texts_ports_raydat_ds;
6567                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6568                         texts_ports_raydat_qs;
6569
6570
6571                 break;
6572
6573         }
6574
6575         /* TCO detection */
6576         switch (hdspm->io_type) {
6577         case AIO:
6578         case RayDAT:
6579                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6580                                 HDSPM_s2_tco_detect) {
6581                         hdspm->midiPorts++;
6582                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6583                                         GFP_KERNEL);
6584                         if (NULL != hdspm->tco) {
6585                                 hdspm_tco_write(hdspm);
6586                         }
6587                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6588                 } else {
6589                         hdspm->tco = NULL;
6590                 }
6591                 break;
6592
6593         case MADI:
6594                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6595                         hdspm->midiPorts++;
6596                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6597                                         GFP_KERNEL);
6598                         if (NULL != hdspm->tco) {
6599                                 hdspm_tco_write(hdspm);
6600                         }
6601                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6602                 } else {
6603                         hdspm->tco = NULL;
6604                 }
6605                 break;
6606
6607         default:
6608                 hdspm->tco = NULL;
6609         }
6610
6611         /* texts */
6612         switch (hdspm->io_type) {
6613         case AES32:
6614                 if (hdspm->tco) {
6615                         hdspm->texts_autosync = texts_autosync_aes_tco;
6616                         hdspm->texts_autosync_items = 10;
6617                 } else {
6618                         hdspm->texts_autosync = texts_autosync_aes;
6619                         hdspm->texts_autosync_items = 9;
6620                 }
6621                 break;
6622
6623         case MADI:
6624                 if (hdspm->tco) {
6625                         hdspm->texts_autosync = texts_autosync_madi_tco;
6626                         hdspm->texts_autosync_items = 4;
6627                 } else {
6628                         hdspm->texts_autosync = texts_autosync_madi;
6629                         hdspm->texts_autosync_items = 3;
6630                 }
6631                 break;
6632
6633         case MADIface:
6634
6635                 break;
6636
6637         case RayDAT:
6638                 if (hdspm->tco) {
6639                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6640                         hdspm->texts_autosync_items = 9;
6641                 } else {
6642                         hdspm->texts_autosync = texts_autosync_raydat;
6643                         hdspm->texts_autosync_items = 8;
6644                 }
6645                 break;
6646
6647         case AIO:
6648                 if (hdspm->tco) {
6649                         hdspm->texts_autosync = texts_autosync_aio_tco;
6650                         hdspm->texts_autosync_items = 6;
6651                 } else {
6652                         hdspm->texts_autosync = texts_autosync_aio;
6653                         hdspm->texts_autosync_items = 5;
6654                 }
6655                 break;
6656
6657         }
6658
6659         tasklet_init(&hdspm->midi_tasklet,
6660                         hdspm_midi_tasklet, (unsigned long) hdspm);
6661
6662         snd_printdd("create alsa devices.\n");
6663         err = snd_hdspm_create_alsa_devices(card, hdspm);
6664         if (err < 0)
6665                 return err;
6666
6667         snd_hdspm_initialize_midi_flush(hdspm);
6668
6669         return 0;
6670 }
6671
6672
6673 static int snd_hdspm_free(struct hdspm * hdspm)
6674 {
6675
6676         if (hdspm->port) {
6677
6678                 /* stop th audio, and cancel all interrupts */
6679                 hdspm->control_register &=
6680                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6681                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6682                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6683                 hdspm_write(hdspm, HDSPM_controlRegister,
6684                             hdspm->control_register);
6685         }
6686
6687         if (hdspm->irq >= 0)
6688                 free_irq(hdspm->irq, (void *) hdspm);
6689
6690         kfree(hdspm->mixer);
6691
6692         if (hdspm->iobase)
6693                 iounmap(hdspm->iobase);
6694
6695         if (hdspm->port)
6696                 pci_release_regions(hdspm->pci);
6697
6698         pci_disable_device(hdspm->pci);
6699         return 0;
6700 }
6701
6702
6703 static void snd_hdspm_card_free(struct snd_card *card)
6704 {
6705         struct hdspm *hdspm = card->private_data;
6706
6707         if (hdspm)
6708                 snd_hdspm_free(hdspm);
6709 }
6710
6711
6712 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6713                                      const struct pci_device_id *pci_id)
6714 {
6715         static int dev;
6716         struct hdspm *hdspm;
6717         struct snd_card *card;
6718         int err;
6719
6720         if (dev >= SNDRV_CARDS)
6721                 return -ENODEV;
6722         if (!enable[dev]) {
6723                 dev++;
6724                 return -ENOENT;
6725         }
6726
6727         err = snd_card_create(index[dev], id[dev],
6728                         THIS_MODULE, sizeof(struct hdspm), &card);
6729         if (err < 0)
6730                 return err;
6731
6732         hdspm = card->private_data;
6733         card->private_free = snd_hdspm_card_free;
6734         hdspm->dev = dev;
6735         hdspm->pci = pci;
6736
6737         snd_card_set_dev(card, &pci->dev);
6738
6739         err = snd_hdspm_create(card, hdspm);
6740         if (err < 0) {
6741                 snd_card_free(card);
6742                 return err;
6743         }
6744
6745         if (hdspm->io_type != MADIface) {
6746                 sprintf(card->shortname, "%s_%x",
6747                         hdspm->card_name,
6748                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6749                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6750                         hdspm->card_name,
6751                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6752                         hdspm->port, hdspm->irq);
6753         } else {
6754                 sprintf(card->shortname, "%s", hdspm->card_name);
6755                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6756                                 hdspm->card_name, hdspm->port, hdspm->irq);
6757         }
6758
6759         err = snd_card_register(card);
6760         if (err < 0) {
6761                 snd_card_free(card);
6762                 return err;
6763         }
6764
6765         pci_set_drvdata(pci, card);
6766
6767         dev++;
6768         return 0;
6769 }
6770
6771 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6772 {
6773         snd_card_free(pci_get_drvdata(pci));
6774         pci_set_drvdata(pci, NULL);
6775 }
6776
6777 static struct pci_driver driver = {
6778         .name = "RME Hammerfall DSP MADI",
6779         .id_table = snd_hdspm_ids,
6780         .probe = snd_hdspm_probe,
6781         .remove = __devexit_p(snd_hdspm_remove),
6782 };
6783
6784
6785 static int __init alsa_card_hdspm_init(void)
6786 {
6787         return pci_register_driver(&driver);
6788 }
6789
6790 static void __exit alsa_card_hdspm_exit(void)
6791 {
6792         pci_unregister_driver(&driver);
6793 }
6794
6795 module_init(alsa_card_hdspm_init)
6796 module_exit(alsa_card_hdspm_exit)