sound/pci/rme96.c

   1 /*
   2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   3  *   interfaces
   4  *
   5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   6  *
   7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   8  *      code.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/module.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/info.h>
  34 #include <sound/control.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/asoundef.h>
  38 #include <sound/initval.h>
  39
  40 #include <asm/io.h>
  41
  42 /* note, two last pcis should be equal, it is not a bug */
  43
  44 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  46                    "Digi96/8 PAD");
  47 MODULE_LICENSE("GPL");
  48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  49                 "{RME,Digi96/8},"
  50                 "{RME,Digi96/8 PRO},"
  51                 "{RME,Digi96/8 PST},"
  52                 "{RME,Digi96/8 PAD}}");
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  57
  58 module_param_array(index, int, NULL, 0444);
  59 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  60 module_param_array(id, charp, NULL, 0444);
  61 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  62 module_param_array(enable, bool, NULL, 0444);
  63 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  64
  65 /*
  66  * Defines for RME Digi96 series, from internal RME reference documents
  67  * dated 12.01.00
  68  */
  69
  70 #define RME96_SPDIF_NCHANNELS 2
  71
  72 /* Playback and capture buffer size */
  73 #define RME96_BUFFER_SIZE 0x10000
  74
  75 /* IO area size */
  76 #define RME96_IO_SIZE 0x60000
  77
  78 /* IO area offsets */
  79 #define RME96_IO_PLAY_BUFFER      0x0
  80 #define RME96_IO_REC_BUFFER       0x10000
  81 #define RME96_IO_CONTROL_REGISTER 0x20000
  82 #define RME96_IO_ADDITIONAL_REG   0x20004
  83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  84 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  85 #define RME96_IO_SET_PLAY_POS     0x40000
  86 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  87 #define RME96_IO_SET_REC_POS      0x50000
  88 #define RME96_IO_RESET_REC_POS    0x5FFFC
  89 #define RME96_IO_GET_PLAY_POS     0x20000
  90 #define RME96_IO_GET_REC_POS      0x30000
  91
  92 /* Write control register bits */
  93 #define RME96_WCR_START     (1 << 0)
  94 #define RME96_WCR_START_2   (1 << 1)
  95 #define RME96_WCR_GAIN_0    (1 << 2)
  96 #define RME96_WCR_GAIN_1    (1 << 3)
  97 #define RME96_WCR_MODE24    (1 << 4)
  98 #define RME96_WCR_MODE24_2  (1 << 5)
  99 #define RME96_WCR_BM        (1 << 6)
 100 #define RME96_WCR_BM_2      (1 << 7)
 101 #define RME96_WCR_ADAT      (1 << 8)
 102 #define RME96_WCR_FREQ_0    (1 << 9)
 103 #define RME96_WCR_FREQ_1    (1 << 10)
 104 #define RME96_WCR_DS        (1 << 11)
 105 #define RME96_WCR_PRO       (1 << 12)
 106 #define RME96_WCR_EMP       (1 << 13)
 107 #define RME96_WCR_SEL       (1 << 14)
 108 #define RME96_WCR_MASTER    (1 << 15)
 109 #define RME96_WCR_PD        (1 << 16)
 110 #define RME96_WCR_INP_0     (1 << 17)
 111 #define RME96_WCR_INP_1     (1 << 18)
 112 #define RME96_WCR_THRU_0    (1 << 19)
 113 #define RME96_WCR_THRU_1    (1 << 20)
 114 #define RME96_WCR_THRU_2    (1 << 21)
 115 #define RME96_WCR_THRU_3    (1 << 22)
 116 #define RME96_WCR_THRU_4    (1 << 23)
 117 #define RME96_WCR_THRU_5    (1 << 24)
 118 #define RME96_WCR_THRU_6    (1 << 25)
 119 #define RME96_WCR_THRU_7    (1 << 26)
 120 #define RME96_WCR_DOLBY     (1 << 27)
 121 #define RME96_WCR_MONITOR_0 (1 << 28)
 122 #define RME96_WCR_MONITOR_1 (1 << 29)
 123 #define RME96_WCR_ISEL      (1 << 30)
 124 #define RME96_WCR_IDIS      (1 << 31)
 125
 126 #define RME96_WCR_BITPOS_GAIN_0 2
 127 #define RME96_WCR_BITPOS_GAIN_1 3
 128 #define RME96_WCR_BITPOS_FREQ_0 9
 129 #define RME96_WCR_BITPOS_FREQ_1 10
 130 #define RME96_WCR_BITPOS_INP_0 17
 131 #define RME96_WCR_BITPOS_INP_1 18
 132 #define RME96_WCR_BITPOS_MONITOR_0 28
 133 #define RME96_WCR_BITPOS_MONITOR_1 29
 134
 135 /* Read control register bits */
 136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 137 #define RME96_RCR_IRQ_2     (1 << 16)
 138 #define RME96_RCR_T_OUT     (1 << 17)
 139 #define RME96_RCR_DEV_ID_0  (1 << 21)
 140 #define RME96_RCR_DEV_ID_1  (1 << 22)
 141 #define RME96_RCR_LOCK      (1 << 23)
 142 #define RME96_RCR_VERF      (1 << 26)
 143 #define RME96_RCR_F0        (1 << 27)
 144 #define RME96_RCR_F1        (1 << 28)
 145 #define RME96_RCR_F2        (1 << 29)
 146 #define RME96_RCR_AUTOSYNC  (1 << 30)
 147 #define RME96_RCR_IRQ       (1 << 31)
 148
 149 #define RME96_RCR_BITPOS_F0 27
 150 #define RME96_RCR_BITPOS_F1 28
 151 #define RME96_RCR_BITPOS_F2 29
 152
 153 /* Additional register bits */
 154 #define RME96_AR_WSEL       (1 << 0)
 155 #define RME96_AR_ANALOG     (1 << 1)
 156 #define RME96_AR_FREQPAD_0  (1 << 2)
 157 #define RME96_AR_FREQPAD_1  (1 << 3)
 158 #define RME96_AR_FREQPAD_2  (1 << 4)
 159 #define RME96_AR_PD2        (1 << 5)
 160 #define RME96_AR_DAC_EN     (1 << 6)
 161 #define RME96_AR_CLATCH     (1 << 7)
 162 #define RME96_AR_CCLK       (1 << 8)
 163 #define RME96_AR_CDATA      (1 << 9)
 164
 165 #define RME96_AR_BITPOS_F0 2
 166 #define RME96_AR_BITPOS_F1 3
 167 #define RME96_AR_BITPOS_F2 4
 168
 169 /* Monitor tracks */
 170 #define RME96_MONITOR_TRACKS_1_2 0
 171 #define RME96_MONITOR_TRACKS_3_4 1
 172 #define RME96_MONITOR_TRACKS_5_6 2
 173 #define RME96_MONITOR_TRACKS_7_8 3
 174
 175 /* Attenuation */
 176 #define RME96_ATTENUATION_0 0
 177 #define RME96_ATTENUATION_6 1
 178 #define RME96_ATTENUATION_12 2
 179 #define RME96_ATTENUATION_18 3
 180
 181 /* Input types */
 182 #define RME96_INPUT_OPTICAL 0
 183 #define RME96_INPUT_COAXIAL 1
 184 #define RME96_INPUT_INTERNAL 2
 185 #define RME96_INPUT_XLR 3
 186 #define RME96_INPUT_ANALOG 4
 187
 188 /* Clock modes */
 189 #define RME96_CLOCKMODE_SLAVE 0
 190 #define RME96_CLOCKMODE_MASTER 1
 191 #define RME96_CLOCKMODE_WORDCLOCK 2
 192
 193 /* Block sizes in bytes */
 194 #define RME96_SMALL_BLOCK_SIZE 2048
 195 #define RME96_LARGE_BLOCK_SIZE 8192
 196
 197 /* Volume control */
 198 #define RME96_AD1852_VOL_BITS 14
 199 #define RME96_AD1855_VOL_BITS 10
 200
 201
 202 struct rme96 {
 203         spinlock_t    lock;
 204         int irq;
 205         unsigned long port;
 206         void __iomem *iobase;
 207
 208         u32 wcreg;    /* cached write control register value */
 209         u32 wcreg_spdif;                /* S/PDIF setup */
 210         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 211         u32 rcreg;    /* cached read control register value */
 212         u32 areg;     /* cached additional register value */
 213         u16 vol[2]; /* cached volume of analog output */
 214
 215         u8 rev; /* card revision number */
 216
 217         struct snd_pcm_substream *playback_substream;
 218         struct snd_pcm_substream *capture_substream;
 219
 220         int playback_frlog; /* log2 of framesize */
 221         int capture_frlog;
 222
 223         size_t playback_periodsize; /* in bytes, zero if not used */
 224         size_t capture_periodsize; /* in bytes, zero if not used */
 225
 226         struct snd_card *card;
 227         struct snd_pcm *spdif_pcm;
 228         struct snd_pcm *adat_pcm;
 229         struct pci_dev     *pci;
 230         struct snd_kcontrol   *spdif_ctl;
 231 };
 232
 233 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
 234         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
 235         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
 236         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
 237         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
 238         { 0, }
 239 };
 240
 241 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 242
 243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 245 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 246 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
 247                                      (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 248 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 249 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 250                                   ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
 251 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 252
 253 static int
 254 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
 255
 256 static int
 257 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
 258
 259 static int
 260 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
 261                            int cmd);
 262
 263 static int
 264 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
 265                           int cmd);
 266
 267 static snd_pcm_uframes_t
 268 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
 269
 270 static snd_pcm_uframes_t
 271 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
 272
 273 static void __devinit
 274 snd_rme96_proc_init(struct rme96 *rme96);
 275
 276 static int
 277 snd_rme96_create_switches(struct snd_card *card,
 278                           struct rme96 *rme96);
 279
 280 static int
 281 snd_rme96_getinputtype(struct rme96 *rme96);
 282
 283 static inline unsigned int
 284 snd_rme96_playback_ptr(struct rme96 *rme96)
 285 {
 286         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 287                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 288 }
 289
 290 static inline unsigned int
 291 snd_rme96_capture_ptr(struct rme96 *rme96)
 292 {
 293         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 294                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 295 }
 296
 297 static int
 298 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
 299                            int channel, /* not used (interleaved data) */
 300                            snd_pcm_uframes_t pos,
 301                            snd_pcm_uframes_t count)
 302 {
 303         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 304         count <<= rme96->playback_frlog;
 305         pos <<= rme96->playback_frlog;
 306         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 307                   0, count);
 308         return 0;
 309 }
 310
 311 static int
 312 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
 313                         int channel, /* not used (interleaved data) */
 314                         snd_pcm_uframes_t pos,
 315                         void __user *src,
 316                         snd_pcm_uframes_t count)
 317 {
 318         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 319         count <<= rme96->playback_frlog;
 320         pos <<= rme96->playback_frlog;
 321         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
 322                             count);
 323         return 0;
 324 }
 325
 326 static int
 327 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
 328                        int channel, /* not used (interleaved data) */
 329                        snd_pcm_uframes_t pos,
 330                        void __user *dst,
 331                        snd_pcm_uframes_t count)
 332 {
 333         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 334         count <<= rme96->capture_frlog;
 335         pos <<= rme96->capture_frlog;
 336         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
 337                             count);
 338         return 0;
 339 }
 340
 341 /*
 342  * Digital output capabilities (S/PDIF)
 343  */
 344 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
 345 {
 346         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 347                               SNDRV_PCM_INFO_MMAP_VALID |
 348                               SNDRV_PCM_INFO_INTERLEAVED |
 349                               SNDRV_PCM_INFO_PAUSE),
 350         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 351                               SNDRV_PCM_FMTBIT_S32_LE),
 352         .rates =             (SNDRV_PCM_RATE_32000 |
 353                               SNDRV_PCM_RATE_44100 |
 354                               SNDRV_PCM_RATE_48000 |
 355                               SNDRV_PCM_RATE_64000 |
 356                               SNDRV_PCM_RATE_88200 |
 357                               SNDRV_PCM_RATE_96000),
 358         .rate_min =          32000,
 359         .rate_max =          96000,
 360         .channels_min =      2,
 361         .channels_max =      2,
 362         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 363         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 364         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 365         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 366         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 367         .fifo_size =         0,
 368 };
 369
 370 /*
 371  * Digital input capabilities (S/PDIF)
 372  */
 373 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
 374 {
 375         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 376                               SNDRV_PCM_INFO_MMAP_VALID |
 377                               SNDRV_PCM_INFO_INTERLEAVED |
 378                               SNDRV_PCM_INFO_PAUSE),
 379         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 380                               SNDRV_PCM_FMTBIT_S32_LE),
 381         .rates =             (SNDRV_PCM_RATE_32000 |
 382                               SNDRV_PCM_RATE_44100 |
 383                               SNDRV_PCM_RATE_48000 |
 384                               SNDRV_PCM_RATE_64000 |
 385                               SNDRV_PCM_RATE_88200 |
 386                               SNDRV_PCM_RATE_96000),
 387         .rate_min =          32000,
 388         .rate_max =          96000,
 389         .channels_min =      2,
 390         .channels_max =      2,
 391         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 392         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 393         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 394         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 395         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 396         .fifo_size =         0,
 397 };
 398
 399 /*
 400  * Digital output capabilities (ADAT)
 401  */
 402 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
 403 {
 404         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 405                               SNDRV_PCM_INFO_MMAP_VALID |
 406                               SNDRV_PCM_INFO_INTERLEAVED |
 407                               SNDRV_PCM_INFO_PAUSE),
 408         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 409                               SNDRV_PCM_FMTBIT_S32_LE),
 410         .rates =             (SNDRV_PCM_RATE_44100 |
 411                               SNDRV_PCM_RATE_48000),
 412         .rate_min =          44100,
 413         .rate_max =          48000,
 414         .channels_min =      8,
 415         .channels_max =      8,
 416         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 417         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 418         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 419         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 420         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 421         .fifo_size =         0,
 422 };
 423
 424 /*
 425  * Digital input capabilities (ADAT)
 426  */
 427 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
 428 {
 429         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 430                               SNDRV_PCM_INFO_MMAP_VALID |
 431                               SNDRV_PCM_INFO_INTERLEAVED |
 432                               SNDRV_PCM_INFO_PAUSE),
 433         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 434                               SNDRV_PCM_FMTBIT_S32_LE),
 435         .rates =             (SNDRV_PCM_RATE_44100 |
 436                               SNDRV_PCM_RATE_48000),
 437         .rate_min =          44100,
 438         .rate_max =          48000,
 439         .channels_min =      8,
 440         .channels_max =      8,
 441         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 442         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 443         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 444         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 445         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 446         .fifo_size =         0,
 447 };
 448
 449 /*
 450  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 451  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 452  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 453  * edge of CLATCH after the last data bit clocks in the whole data word.
 454  * A fast processor could probably drive the SPI interface faster than the
 455  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 456  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 457  *
 458  * NOTE: increased delay from 1 to 10, since there where problems setting
 459  * the volume.
 460  */
 461 static void
 462 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
 463 {
 464         int i;
 465
 466         for (i = 0; i < 16; i++) {
 467                 if (val & 0x8000) {
 468                         rme96->areg |= RME96_AR_CDATA;
 469                 } else {
 470                         rme96->areg &= ~RME96_AR_CDATA;
 471                 }
 472                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 473                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 474                 udelay(10);
 475                 rme96->areg |= RME96_AR_CCLK;
 476                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 477                 udelay(10);
 478                 val <<= 1;
 479         }
 480         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 481         rme96->areg |= RME96_AR_CLATCH;
 482         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 483         udelay(10);
 484         rme96->areg &= ~RME96_AR_CLATCH;
 485         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 486 }
 487
 488 static void
 489 snd_rme96_apply_dac_volume(struct rme96 *rme96)
 490 {
 491         if (RME96_DAC_IS_1852(rme96)) {
 492                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 493                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 494         } else if (RME96_DAC_IS_1855(rme96)) {
 495                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 496                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 497         }
 498 }
 499
 500 static void
 501 snd_rme96_reset_dac(struct rme96 *rme96)
 502 {
 503         writel(rme96->wcreg | RME96_WCR_PD,
 504                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 505         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 506 }
 507
 508 static int
 509 snd_rme96_getmontracks(struct rme96 *rme96)
 510 {
 511         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 512                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 513 }
 514
 515 static int
 516 snd_rme96_setmontracks(struct rme96 *rme96,
 517                        int montracks)
 518 {
 519         if (montracks & 1) {
 520                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 521         } else {
 522                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 523         }
 524         if (montracks & 2) {
 525                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 526         } else {
 527                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 528         }
 529         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 530         return 0;
 531 }
 532
 533 static int
 534 snd_rme96_getattenuation(struct rme96 *rme96)
 535 {
 536         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 537                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 538 }
 539
 540 static int
 541 snd_rme96_setattenuation(struct rme96 *rme96,
 542                          int attenuation)
 543 {
 544         switch (attenuation) {
 545         case 0:
 546                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 547                         ~RME96_WCR_GAIN_1;
 548                 break;
 549         case 1:
 550                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 551                         ~RME96_WCR_GAIN_1;
 552                 break;
 553         case 2:
 554                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 555                         RME96_WCR_GAIN_1;
 556                 break;
 557         case 3:
 558                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 559                         RME96_WCR_GAIN_1;
 560                 break;
 561         default:
 562                 return -EINVAL;
 563         }
 564         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 565         return 0;
 566 }
 567
 568 static int
 569 snd_rme96_capture_getrate(struct rme96 *rme96,
 570                           int *is_adat)
 571 {
 572         int n, rate;
 573
 574         *is_adat = 0;
 575         if (rme96->areg & RME96_AR_ANALOG) {
 576                 /* Analog input, overrides S/PDIF setting */
 577                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 578                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 579                 switch (n) {
 580                 case 1:
 581                         rate = 32000;
 582                         break;
 583                 case 2:
 584                         rate = 44100;
 585                         break;
 586                 case 3:
 587                         rate = 48000;
 588                         break;
 589                 default:
 590                         return -1;
 591                 }
 592                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 593         }
 594
 595         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 596         if (rme96->rcreg & RME96_RCR_LOCK) {
 597                 /* ADAT rate */
 598                 *is_adat = 1;
 599                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 600                         return 48000;
 601                 }
 602                 return 44100;
 603         }
 604
 605         if (rme96->rcreg & RME96_RCR_VERF) {
 606                 return -1;
 607         }
 608
 609         /* S/PDIF rate */
 610         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 611                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 612                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 613
 614         switch (n) {
 615         case 0:
 616                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 617                         return 64000;
 618                 }
 619                 return -1;
 620         case 3: return 96000;
 621         case 4: return 88200;
 622         case 5: return 48000;
 623         case 6: return 44100;
 624         case 7: return 32000;
 625         default:
 626                 break;
 627         }
 628         return -1;
 629 }
 630
 631 static int
 632 snd_rme96_playback_getrate(struct rme96 *rme96)
 633 {
 634         int rate, dummy;
 635
 636         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 637             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 638             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 639         {
 640                 /* slave clock */
 641                 return rate;
 642         }
 643         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 644                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 645         switch (rate) {
 646         case 1:
 647                 rate = 32000;
 648                 break;
 649         case 2:
 650                 rate = 44100;
 651                 break;
 652         case 3:
 653                 rate = 48000;
 654                 break;
 655         default:
 656                 return -1;
 657         }
 658         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 659 }
 660
 661 static int
 662 snd_rme96_playback_setrate(struct rme96 *rme96,
 663                            int rate)
 664 {
 665         int ds;
 666
 667         ds = rme96->wcreg & RME96_WCR_DS;
 668         switch (rate) {
 669         case 32000:
 670                 rme96->wcreg &= ~RME96_WCR_DS;
 671                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 672                         ~RME96_WCR_FREQ_1;
 673                 break;
 674         case 44100:
 675                 rme96->wcreg &= ~RME96_WCR_DS;
 676                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 677                         ~RME96_WCR_FREQ_0;
 678                 break;
 679         case 48000:
 680                 rme96->wcreg &= ~RME96_WCR_DS;
 681                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 682                         RME96_WCR_FREQ_1;
 683                 break;
 684         case 64000:
 685                 rme96->wcreg |= RME96_WCR_DS;
 686                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 687                         ~RME96_WCR_FREQ_1;
 688                 break;
 689         case 88200:
 690                 rme96->wcreg |= RME96_WCR_DS;
 691                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 692                         ~RME96_WCR_FREQ_0;
 693                 break;
 694         case 96000:
 695                 rme96->wcreg |= RME96_WCR_DS;
 696                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 697                         RME96_WCR_FREQ_1;
 698                 break;
 699         default:
 700                 return -EINVAL;
 701         }
 702         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 703             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 704         {
 705                 /* change to/from double-speed: reset the DAC (if available) */
 706                 snd_rme96_reset_dac(rme96);
 707                 return 1; /* need to restore volume */
 708         } else {
 709                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 710                 return 0;
 711         }
 712 }
 713
 714 static int
 715 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
 716                                  int rate)
 717 {
 718         switch (rate) {
 719         case 32000:
 720                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 721                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 722                 break;
 723         case 44100:
 724                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 725                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 726                 break;
 727         case 48000:
 728                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 729                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 730                 break;
 731         case 64000:
 732                 if (rme96->rev < 4) {
 733                         return -EINVAL;
 734                 }
 735                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 736                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 737                 break;
 738         case 88200:
 739                 if (rme96->rev < 4) {
 740                         return -EINVAL;
 741                 }
 742                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 743                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 744                 break;
 745         case 96000:
 746                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 747                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 748                 break;
 749         default:
 750                 return -EINVAL;
 751         }
 752         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 753         return 0;
 754 }
 755
 756 static int
 757 snd_rme96_setclockmode(struct rme96 *rme96,
 758                        int mode)
 759 {
 760         switch (mode) {
 761         case RME96_CLOCKMODE_SLAVE:
 762                 /* AutoSync */
 763                 rme96->wcreg &= ~RME96_WCR_MASTER;
 764                 rme96->areg &= ~RME96_AR_WSEL;
 765                 break;
 766         case RME96_CLOCKMODE_MASTER:
 767                 /* Internal */
 768                 rme96->wcreg |= RME96_WCR_MASTER;
 769                 rme96->areg &= ~RME96_AR_WSEL;
 770                 break;
 771         case RME96_CLOCKMODE_WORDCLOCK:
 772                 /* Word clock is a master mode */
 773                 rme96->wcreg |= RME96_WCR_MASTER;
 774                 rme96->areg |= RME96_AR_WSEL;
 775                 break;
 776         default:
 777                 return -EINVAL;
 778         }
 779         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 780         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 781         return 0;
 782 }
 783
 784 static int
 785 snd_rme96_getclockmode(struct rme96 *rme96)
 786 {
 787         if (rme96->areg & RME96_AR_WSEL) {
 788                 return RME96_CLOCKMODE_WORDCLOCK;
 789         }
 790         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 791                 RME96_CLOCKMODE_SLAVE;
 792 }
 793
 794 static int
 795 snd_rme96_setinputtype(struct rme96 *rme96,
 796                        int type)
 797 {
 798         int n;
 799
 800         switch (type) {
 801         case RME96_INPUT_OPTICAL:
 802                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 803                         ~RME96_WCR_INP_1;
 804                 break;
 805         case RME96_INPUT_COAXIAL:
 806                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 807                         ~RME96_WCR_INP_1;
 808                 break;
 809         case RME96_INPUT_INTERNAL:
 810                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 811                         RME96_WCR_INP_1;
 812                 break;
 813         case RME96_INPUT_XLR:
 814                 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 815                      rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
 816                     (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 817                      rme96->rev > 4))
 818                 {
 819                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 820                         return -EINVAL;
 821                 }
 822                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 823                         RME96_WCR_INP_1;
 824                 break;
 825         case RME96_INPUT_ANALOG:
 826                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 827                         return -EINVAL;
 828                 }
 829                 rme96->areg |= RME96_AR_ANALOG;
 830                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 831                 if (rme96->rev < 4) {
 832                         /*
 833                          * Revision less than 004 does not support 64 and
 834                          * 88.2 kHz
 835                          */
 836                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 837                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 838                         }
 839                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 840                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 841                         }
 842                 }
 843                 return 0;
 844         default:
 845                 return -EINVAL;
 846         }
 847         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 848                 rme96->areg &= ~RME96_AR_ANALOG;
 849                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 850         }
 851         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 852         return 0;
 853 }
 854
 855 static int
 856 snd_rme96_getinputtype(struct rme96 *rme96)
 857 {
 858         if (rme96->areg & RME96_AR_ANALOG) {
 859                 return RME96_INPUT_ANALOG;
 860         }
 861         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 862                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 863 }
 864
 865 static void
 866 snd_rme96_setframelog(struct rme96 *rme96,
 867                       int n_channels,
 868                       int is_playback)
 869 {
 870         int frlog;
 871
 872         if (n_channels == 2) {
 873                 frlog = 1;
 874         } else {
 875                 /* assume 8 channels */
 876                 frlog = 3;
 877         }
 878         if (is_playback) {
 879                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 880                 rme96->playback_frlog = frlog;
 881         } else {
 882                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 883                 rme96->capture_frlog = frlog;
 884         }
 885 }
 886
 887 static int
 888 snd_rme96_playback_setformat(struct rme96 *rme96,
 889                              int format)
 890 {
 891         switch (format) {
 892         case SNDRV_PCM_FORMAT_S16_LE:
 893                 rme96->wcreg &= ~RME96_WCR_MODE24;
 894                 break;
 895         case SNDRV_PCM_FORMAT_S32_LE:
 896                 rme96->wcreg |= RME96_WCR_MODE24;
 897                 break;
 898         default:
 899                 return -EINVAL;
 900         }
 901         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 902         return 0;
 903 }
 904
 905 static int
 906 snd_rme96_capture_setformat(struct rme96 *rme96,
 907                             int format)
 908 {
 909         switch (format) {
 910         case SNDRV_PCM_FORMAT_S16_LE:
 911                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 912                 break;
 913         case SNDRV_PCM_FORMAT_S32_LE:
 914                 rme96->wcreg |= RME96_WCR_MODE24_2;
 915                 break;
 916         default:
 917                 return -EINVAL;
 918         }
 919         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 920         return 0;
 921 }
 922
 923 static void
 924 snd_rme96_set_period_properties(struct rme96 *rme96,
 925                                 size_t period_bytes)
 926 {
 927         switch (period_bytes) {
 928         case RME96_LARGE_BLOCK_SIZE:
 929                 rme96->wcreg &= ~RME96_WCR_ISEL;
 930                 break;
 931         case RME96_SMALL_BLOCK_SIZE:
 932                 rme96->wcreg |= RME96_WCR_ISEL;
 933                 break;
 934         default:
 935                 snd_BUG();
 936                 break;
 937         }
 938         rme96->wcreg &= ~RME96_WCR_IDIS;
 939         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 940 }
 941
 942 static int
 943 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
 944                              struct snd_pcm_hw_params *params)
 945 {
 946         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 947         struct snd_pcm_runtime *runtime = substream->runtime;
 948         int err, rate, dummy;
 949         bool apply_dac_volume = false;
 950
 951         runtime->dma_area = (void __force *)(rme96->iobase +
 952                                              RME96_IO_PLAY_BUFFER);
 953         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
 954         runtime->dma_bytes = RME96_BUFFER_SIZE;
 955
 956         spin_lock_irq(&rme96->lock);
 957         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 958             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 959             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 960         {
 961                 /* slave clock */
 962                 if ((int)params_rate(params) != rate) {
 963                         err = -EIO;
 964                         goto error;
 965                 }
 966         } else {
 967                 err = snd_rme96_playback_setrate(rme96, params_rate(params));
 968                 if (err < 0)
 969                         goto error;
 970                 apply_dac_volume = err > 0; /* need to restore volume later? */
 971         }
 972
 973         err = snd_rme96_playback_setformat(rme96, params_format(params));
 974         if (err < 0)
 975                 goto error;
 976         snd_rme96_setframelog(rme96, params_channels(params), 1);
 977         if (rme96->capture_periodsize != 0) {
 978                 if (params_period_size(params) << rme96->playback_frlog !=
 979                     rme96->capture_periodsize)
 980                 {
 981                         err = -EBUSY;
 982                         goto error;
 983                 }
 984         }
 985         rme96->playback_periodsize =
 986                 params_period_size(params) << rme96->playback_frlog;
 987         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
 988         /* S/PDIF setup */
 989         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
 990                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
 991                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 992         }
 993
 994         err = 0;
 995  error:
 996         spin_unlock_irq(&rme96->lock);
 997         if (apply_dac_volume) {
 998                 usleep_range(3000, 10000);
 999                 snd_rme96_apply_dac_volume(rme96);
1000         }
1001
1002         return err;
1003 }
1004
1005 static int
1006 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1007                             struct snd_pcm_hw_params *params)
1008 {
1009         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1010         struct snd_pcm_runtime *runtime = substream->runtime;
1011         int err, isadat, rate;
1012
1013         runtime->dma_area = (void __force *)(rme96->iobase +
1014                                              RME96_IO_REC_BUFFER);
1015         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1016         runtime->dma_bytes = RME96_BUFFER_SIZE;
1017
1018         spin_lock_irq(&rme96->lock);
1019         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1020                 spin_unlock_irq(&rme96->lock);
1021                 return err;
1022         }
1023         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1024                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1025                                                             params_rate(params))) < 0)
1026                 {
1027                         spin_unlock_irq(&rme96->lock);
1028                         return err;
1029                 }
1030         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1031                 if ((int)params_rate(params) != rate) {
1032                         spin_unlock_irq(&rme96->lock);
1033                         return -EIO;
1034                 }
1035                 if ((isadat && runtime->hw.channels_min == 2) ||
1036                     (!isadat && runtime->hw.channels_min == 8))
1037                 {
1038                         spin_unlock_irq(&rme96->lock);
1039                         return -EIO;
1040                 }
1041         }
1042         snd_rme96_setframelog(rme96, params_channels(params), 0);
1043         if (rme96->playback_periodsize != 0) {
1044                 if (params_period_size(params) << rme96->capture_frlog !=
1045                     rme96->playback_periodsize)
1046                 {
1047                         spin_unlock_irq(&rme96->lock);
1048                         return -EBUSY;
1049                 }
1050         }
1051         rme96->capture_periodsize =
1052                 params_period_size(params) << rme96->capture_frlog;
1053         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1054         spin_unlock_irq(&rme96->lock);
1055
1056         return 0;
1057 }
1058
1059 static void
1060 snd_rme96_playback_start(struct rme96 *rme96,
1061                          int from_pause)
1062 {
1063         if (!from_pause) {
1064                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1065         }
1066
1067         rme96->wcreg |= RME96_WCR_START;
1068         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1069 }
1070
1071 static void
1072 snd_rme96_capture_start(struct rme96 *rme96,
1073                         int from_pause)
1074 {
1075         if (!from_pause) {
1076                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1077         }
1078
1079         rme96->wcreg |= RME96_WCR_START_2;
1080         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1081 }
1082
1083 static void
1084 snd_rme96_playback_stop(struct rme96 *rme96)
1085 {
1086         /*
1087          * Check if there is an unconfirmed IRQ, if so confirm it, or else
1088          * the hardware will not stop generating interrupts
1089          */
1090         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1091         if (rme96->rcreg & RME96_RCR_IRQ) {
1092                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1093         }
1094         rme96->wcreg &= ~RME96_WCR_START;
1095         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1096 }
1097
1098 static void
1099 snd_rme96_capture_stop(struct rme96 *rme96)
1100 {
1101         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1102         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1103                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1104         }
1105         rme96->wcreg &= ~RME96_WCR_START_2;
1106         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1107 }
1108
1109 static irqreturn_t
1110 snd_rme96_interrupt(int irq,
1111                     void *dev_id)
1112 {
1113         struct rme96 *rme96 = (struct rme96 *)dev_id;
1114
1115         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1116         /* fastpath out, to ease interrupt sharing */
1117         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1118               (rme96->rcreg & RME96_RCR_IRQ_2)))
1119         {
1120                 return IRQ_NONE;
1121         }
1122
1123         if (rme96->rcreg & RME96_RCR_IRQ) {
1124                 /* playback */
1125                 snd_pcm_period_elapsed(rme96->playback_substream);
1126                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1127         }
1128         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1129                 /* capture */
1130                 snd_pcm_period_elapsed(rme96->capture_substream);
1131                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1132         }
1133         return IRQ_HANDLED;
1134 }
1135
1136 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1137
1138 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1139         .count = ARRAY_SIZE(period_bytes),
1140         .list = period_bytes,
1141         .mask = 0
1142 };
1143
1144 static void
1145 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1146                                  struct snd_pcm_runtime *runtime)
1147 {
1148         unsigned int size;
1149
1150         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1151                                      RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1152         if ((size = rme96->playback_periodsize) != 0 ||
1153             (size = rme96->capture_periodsize) != 0)
1154                 snd_pcm_hw_constraint_minmax(runtime,
1155                                              SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1156                                              size, size);
1157         else
1158                 snd_pcm_hw_constraint_list(runtime, 0,
1159                                            SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1160                                            &hw_constraints_period_bytes);
1161 }
1162
1163 static int
1164 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1165 {
1166         int rate, dummy;
1167         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1168         struct snd_pcm_runtime *runtime = substream->runtime;
1169
1170         spin_lock_irq(&rme96->lock);
1171         if (rme96->playback_substream != NULL) {
1172                 spin_unlock_irq(&rme96->lock);
1173                 return -EBUSY;
1174         }
1175         rme96->wcreg &= ~RME96_WCR_ADAT;
1176         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1177         rme96->playback_substream = substream;
1178         spin_unlock_irq(&rme96->lock);
1179
1180         runtime->hw = snd_rme96_playback_spdif_info;
1181         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1182             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1183             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1184         {
1185                 /* slave clock */
1186                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1187                 runtime->hw.rate_min = rate;
1188                 runtime->hw.rate_max = rate;
1189         }
1190         rme96_set_buffer_size_constraint(rme96, runtime);
1191
1192         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1193         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1194         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1195                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1196         return 0;
1197 }
1198
1199 static int
1200 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1201 {
1202         int isadat, rate;
1203         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1204         struct snd_pcm_runtime *runtime = substream->runtime;
1205
1206         runtime->hw = snd_rme96_capture_spdif_info;
1207         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1208             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1209         {
1210                 if (isadat) {
1211                         return -EIO;
1212                 }
1213                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1214                 runtime->hw.rate_min = rate;
1215                 runtime->hw.rate_max = rate;
1216         }
1217
1218         spin_lock_irq(&rme96->lock);
1219         if (rme96->capture_substream != NULL) {
1220                 spin_unlock_irq(&rme96->lock);
1221                 return -EBUSY;
1222         }
1223         rme96->capture_substream = substream;
1224         spin_unlock_irq(&rme96->lock);
1225
1226         rme96_set_buffer_size_constraint(rme96, runtime);
1227         return 0;
1228 }
1229
1230 static int
1231 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1232 {
1233         int rate, dummy;
1234         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1235         struct snd_pcm_runtime *runtime = substream->runtime;
1236
1237         spin_lock_irq(&rme96->lock);
1238         if (rme96->playback_substream != NULL) {
1239                 spin_unlock_irq(&rme96->lock);
1240                 return -EBUSY;
1241         }
1242         rme96->wcreg |= RME96_WCR_ADAT;
1243         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1244         rme96->playback_substream = substream;
1245         spin_unlock_irq(&rme96->lock);
1246
1247         runtime->hw = snd_rme96_playback_adat_info;
1248         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1249             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1250             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1251         {
1252                 /* slave clock */
1253                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1254                 runtime->hw.rate_min = rate;
1255                 runtime->hw.rate_max = rate;
1256         }
1257         rme96_set_buffer_size_constraint(rme96, runtime);
1258         return 0;
1259 }
1260
1261 static int
1262 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1263 {
1264         int isadat, rate;
1265         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1266         struct snd_pcm_runtime *runtime = substream->runtime;
1267
1268         runtime->hw = snd_rme96_capture_adat_info;
1269         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1270                 /* makes no sense to use analog input. Note that analog
1271                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1272                 return -EIO;
1273         }
1274         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1275                 if (!isadat) {
1276                         return -EIO;
1277                 }
1278                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1279                 runtime->hw.rate_min = rate;
1280                 runtime->hw.rate_max = rate;
1281         }
1282
1283         spin_lock_irq(&rme96->lock);
1284         if (rme96->capture_substream != NULL) {
1285                 spin_unlock_irq(&rme96->lock);
1286                 return -EBUSY;
1287         }
1288         rme96->capture_substream = substream;
1289         spin_unlock_irq(&rme96->lock);
1290
1291         rme96_set_buffer_size_constraint(rme96, runtime);
1292         return 0;
1293 }
1294
1295 static int
1296 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1297 {
1298         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1299         int spdif = 0;
1300
1301         spin_lock_irq(&rme96->lock);
1302         if (RME96_ISPLAYING(rme96)) {
1303                 snd_rme96_playback_stop(rme96);
1304         }
1305         rme96->playback_substream = NULL;
1306         rme96->playback_periodsize = 0;
1307         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1308         spin_unlock_irq(&rme96->lock);
1309         if (spdif) {
1310                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1311                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1312                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1313         }
1314         return 0;
1315 }
1316
1317 static int
1318 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1319 {
1320         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1321
1322         spin_lock_irq(&rme96->lock);
1323         if (RME96_ISRECORDING(rme96)) {
1324                 snd_rme96_capture_stop(rme96);
1325         }
1326         rme96->capture_substream = NULL;
1327         rme96->capture_periodsize = 0;
1328         spin_unlock_irq(&rme96->lock);
1329         return 0;
1330 }
1331
1332 static int
1333 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1334 {
1335         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1336
1337         spin_lock_irq(&rme96->lock);
1338         if (RME96_ISPLAYING(rme96)) {
1339                 snd_rme96_playback_stop(rme96);
1340         }
1341         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1342         spin_unlock_irq(&rme96->lock);
1343         return 0;
1344 }
1345
1346 static int
1347 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1348 {
1349         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1350
1351         spin_lock_irq(&rme96->lock);
1352         if (RME96_ISRECORDING(rme96)) {
1353                 snd_rme96_capture_stop(rme96);
1354         }
1355         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1356         spin_unlock_irq(&rme96->lock);
1357         return 0;
1358 }
1359
1360 static int
1361 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1362                            int cmd)
1363 {
1364         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1365
1366         switch (cmd) {
1367         case SNDRV_PCM_TRIGGER_START:
1368                 if (!RME96_ISPLAYING(rme96)) {
1369                         if (substream != rme96->playback_substream) {
1370                                 return -EBUSY;
1371                         }
1372                         snd_rme96_playback_start(rme96, 0);
1373                 }
1374                 break;
1375
1376         case SNDRV_PCM_TRIGGER_STOP:
1377                 if (RME96_ISPLAYING(rme96)) {
1378                         if (substream != rme96->playback_substream) {
1379                                 return -EBUSY;
1380                         }
1381                         snd_rme96_playback_stop(rme96);
1382                 }
1383                 break;
1384
1385         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1386                 if (RME96_ISPLAYING(rme96)) {
1387                         snd_rme96_playback_stop(rme96);
1388                 }
1389                 break;
1390
1391         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1392                 if (!RME96_ISPLAYING(rme96)) {
1393                         snd_rme96_playback_start(rme96, 1);
1394                 }
1395                 break;
1396
1397         default:
1398                 return -EINVAL;
1399         }
1400         return 0;
1401 }
1402
1403 static int
1404 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1405                           int cmd)
1406 {
1407         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1408
1409         switch (cmd) {
1410         case SNDRV_PCM_TRIGGER_START:
1411                 if (!RME96_ISRECORDING(rme96)) {
1412                         if (substream != rme96->capture_substream) {
1413                                 return -EBUSY;
1414                         }
1415                         snd_rme96_capture_start(rme96, 0);
1416                 }
1417                 break;
1418
1419         case SNDRV_PCM_TRIGGER_STOP:
1420                 if (RME96_ISRECORDING(rme96)) {
1421                         if (substream != rme96->capture_substream) {
1422                                 return -EBUSY;
1423                         }
1424                         snd_rme96_capture_stop(rme96);
1425                 }
1426                 break;
1427
1428         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1429                 if (RME96_ISRECORDING(rme96)) {
1430                         snd_rme96_capture_stop(rme96);
1431                 }
1432                 break;
1433
1434         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1435                 if (!RME96_ISRECORDING(rme96)) {
1436                         snd_rme96_capture_start(rme96, 1);
1437                 }
1438                 break;
1439
1440         default:
1441                 return -EINVAL;
1442         }
1443
1444         return 0;
1445 }
1446
1447 static snd_pcm_uframes_t
1448 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1449 {
1450         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1451         return snd_rme96_playback_ptr(rme96);
1452 }
1453
1454 static snd_pcm_uframes_t
1455 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1456 {
1457         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1458         return snd_rme96_capture_ptr(rme96);
1459 }
1460
1461 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1462         .open =         snd_rme96_playback_spdif_open,
1463         .close =        snd_rme96_playback_close,
1464         .ioctl =        snd_pcm_lib_ioctl,
1465         .hw_params =    snd_rme96_playback_hw_params,
1466         .prepare =      snd_rme96_playback_prepare,
1467         .trigger =      snd_rme96_playback_trigger,
1468         .pointer =      snd_rme96_playback_pointer,
1469         .copy =         snd_rme96_playback_copy,
1470         .silence =      snd_rme96_playback_silence,
1471         .mmap =         snd_pcm_lib_mmap_iomem,
1472 };
1473
1474 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1475         .open =         snd_rme96_capture_spdif_open,
1476         .close =        snd_rme96_capture_close,
1477         .ioctl =        snd_pcm_lib_ioctl,
1478         .hw_params =    snd_rme96_capture_hw_params,
1479         .prepare =      snd_rme96_capture_prepare,
1480         .trigger =      snd_rme96_capture_trigger,
1481         .pointer =      snd_rme96_capture_pointer,
1482         .copy =         snd_rme96_capture_copy,
1483         .mmap =         snd_pcm_lib_mmap_iomem,
1484 };
1485
1486 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1487         .open =         snd_rme96_playback_adat_open,
1488         .close =        snd_rme96_playback_close,
1489         .ioctl =        snd_pcm_lib_ioctl,
1490         .hw_params =    snd_rme96_playback_hw_params,
1491         .prepare =      snd_rme96_playback_prepare,
1492         .trigger =      snd_rme96_playback_trigger,
1493         .pointer =      snd_rme96_playback_pointer,
1494         .copy =         snd_rme96_playback_copy,
1495         .silence =      snd_rme96_playback_silence,
1496         .mmap =         snd_pcm_lib_mmap_iomem,
1497 };
1498
1499 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1500         .open =         snd_rme96_capture_adat_open,
1501         .close =        snd_rme96_capture_close,
1502         .ioctl =        snd_pcm_lib_ioctl,
1503         .hw_params =    snd_rme96_capture_hw_params,
1504         .prepare =      snd_rme96_capture_prepare,
1505         .trigger =      snd_rme96_capture_trigger,
1506         .pointer =      snd_rme96_capture_pointer,
1507         .copy =         snd_rme96_capture_copy,
1508         .mmap =         snd_pcm_lib_mmap_iomem,
1509 };
1510
1511 static void
1512 snd_rme96_free(void *private_data)
1513 {
1514         struct rme96 *rme96 = (struct rme96 *)private_data;
1515
1516         if (rme96 == NULL) {
1517                 return;
1518         }
1519         if (rme96->irq >= 0) {
1520                 snd_rme96_playback_stop(rme96);
1521                 snd_rme96_capture_stop(rme96);
1522                 rme96->areg &= ~RME96_AR_DAC_EN;
1523                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1524                 free_irq(rme96->irq, (void *)rme96);
1525                 rme96->irq = -1;
1526         }
1527         if (rme96->iobase) {
1528                 iounmap(rme96->iobase);
1529                 rme96->iobase = NULL;
1530         }
1531         if (rme96->port) {
1532                 pci_release_regions(rme96->pci);
1533                 rme96->port = 0;
1534         }
1535         pci_disable_device(rme96->pci);
1536 }
1537
1538 static void
1539 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1540 {
1541         struct rme96 *rme96 = pcm->private_data;
1542         rme96->spdif_pcm = NULL;
1543 }
1544
1545 static void
1546 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1547 {
1548         struct rme96 *rme96 = pcm->private_data;
1549         rme96->adat_pcm = NULL;
1550 }
1551
1552 static int __devinit
1553 snd_rme96_create(struct rme96 *rme96)
1554 {
1555         struct pci_dev *pci = rme96->pci;
1556         int err;
1557
1558         rme96->irq = -1;
1559         spin_lock_init(&rme96->lock);
1560
1561         if ((err = pci_enable_device(pci)) < 0)
1562                 return err;
1563
1564         if ((err = pci_request_regions(pci, "RME96")) < 0)
1565                 return err;
1566         rme96->port = pci_resource_start(rme96->pci, 0);
1567
1568         rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1569         if (!rme96->iobase) {
1570                 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1571                 return -ENOMEM;
1572         }
1573
1574         if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1575                         KBUILD_MODNAME, rme96)) {
1576                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1577                 return -EBUSY;
1578         }
1579         rme96->irq = pci->irq;
1580
1581         /* read the card's revision number */
1582         pci_read_config_byte(pci, 8, &rme96->rev);
1583
1584         /* set up ALSA pcm device for S/PDIF */
1585         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1586                                1, 1, &rme96->spdif_pcm)) < 0)
1587         {
1588                 return err;
1589         }
1590         rme96->spdif_pcm->private_data = rme96;
1591         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1592         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1593         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1594         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1595
1596         rme96->spdif_pcm->info_flags = 0;
1597
1598         /* set up ALSA pcm device for ADAT */
1599         if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1600                 /* ADAT is not available on the base model */
1601                 rme96->adat_pcm = NULL;
1602         } else {
1603                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1604                                        1, 1, &rme96->adat_pcm)) < 0)
1605                 {
1606                         return err;
1607                 }
1608                 rme96->adat_pcm->private_data = rme96;
1609                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1610                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1611                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1612                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1613
1614                 rme96->adat_pcm->info_flags = 0;
1615         }
1616
1617         rme96->playback_periodsize = 0;
1618         rme96->capture_periodsize = 0;
1619
1620         /* make sure playback/capture is stopped, if by some reason active */
1621         snd_rme96_playback_stop(rme96);
1622         snd_rme96_capture_stop(rme96);
1623
1624         /* set default values in registers */
1625         rme96->wcreg =
1626                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1627                 RME96_WCR_SEL |    /* normal playback */
1628                 RME96_WCR_MASTER | /* set to master clock mode */
1629                 RME96_WCR_INP_0;   /* set coaxial input */
1630
1631         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1632
1633         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1634         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1635
1636         /* reset the ADC */
1637         writel(rme96->areg | RME96_AR_PD2,
1638                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1639         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1640
1641         /* reset and enable the DAC (order is important). */
1642         snd_rme96_reset_dac(rme96);
1643         rme96->areg |= RME96_AR_DAC_EN;
1644         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1645
1646         /* reset playback and record buffer pointers */
1647         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1648         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1649
1650         /* reset volume */
1651         rme96->vol[0] = rme96->vol[1] = 0;
1652         if (RME96_HAS_ANALOG_OUT(rme96)) {
1653                 snd_rme96_apply_dac_volume(rme96);
1654         }
1655
1656         /* init switch interface */
1657         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1658                 return err;
1659         }
1660
1661         /* init proc interface */
1662         snd_rme96_proc_init(rme96);
1663
1664         return 0;
1665 }
1666
1667 /*
1668  * proc interface
1669  */
1670
1671 static void
1672 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1673 {
1674         int n;
1675         struct rme96 *rme96 = entry->private_data;
1676
1677         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1678
1679         snd_iprintf(buffer, rme96->card->longname);
1680         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1681
1682         snd_iprintf(buffer, "\nGeneral settings\n");
1683         if (rme96->wcreg & RME96_WCR_IDIS) {
1684                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1685                             "disabled)\n");
1686         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1687                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1688         } else {
1689                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1690         }
1691         snd_iprintf(buffer, "\nInput settings\n");
1692         switch (snd_rme96_getinputtype(rme96)) {
1693         case RME96_INPUT_OPTICAL:
1694                 snd_iprintf(buffer, "  input: optical");
1695                 break;
1696         case RME96_INPUT_COAXIAL:
1697                 snd_iprintf(buffer, "  input: coaxial");
1698                 break;
1699         case RME96_INPUT_INTERNAL:
1700                 snd_iprintf(buffer, "  input: internal");
1701                 break;
1702         case RME96_INPUT_XLR:
1703                 snd_iprintf(buffer, "  input: XLR");
1704                 break;
1705         case RME96_INPUT_ANALOG:
1706                 snd_iprintf(buffer, "  input: analog");
1707                 break;
1708         }
1709         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1710                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1711         } else {
1712                 if (n) {
1713                         snd_iprintf(buffer, " (8 channels)\n");
1714                 } else {
1715                         snd_iprintf(buffer, " (2 channels)\n");
1716                 }
1717                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1718                             snd_rme96_capture_getrate(rme96, &n));
1719         }
1720         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1721                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1722         } else {
1723                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1724         }
1725
1726         snd_iprintf(buffer, "\nOutput settings\n");
1727         if (rme96->wcreg & RME96_WCR_SEL) {
1728                 snd_iprintf(buffer, "  output signal: normal playback\n");
1729         } else {
1730                 snd_iprintf(buffer, "  output signal: same as input\n");
1731         }
1732         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1733                     snd_rme96_playback_getrate(rme96));
1734         if (rme96->wcreg & RME96_WCR_MODE24) {
1735                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1736         } else {
1737                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1738         }
1739         if (rme96->areg & RME96_AR_WSEL) {
1740                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1741         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1742                 snd_iprintf(buffer, "  sample clock source: internal\n");
1743         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1744                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1745         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1746                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1747         } else {
1748                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1749         }
1750         if (rme96->wcreg & RME96_WCR_PRO) {
1751                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1752         } else {
1753                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1754         }
1755         if (rme96->wcreg & RME96_WCR_EMP) {
1756                 snd_iprintf(buffer, "  emphasis: on\n");
1757         } else {
1758                 snd_iprintf(buffer, "  emphasis: off\n");
1759         }
1760         if (rme96->wcreg & RME96_WCR_DOLBY) {
1761                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1762         } else {
1763                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1764         }
1765         if (RME96_HAS_ANALOG_IN(rme96)) {
1766                 snd_iprintf(buffer, "\nAnalog output settings\n");
1767                 switch (snd_rme96_getmontracks(rme96)) {
1768                 case RME96_MONITOR_TRACKS_1_2:
1769                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1770                         break;
1771                 case RME96_MONITOR_TRACKS_3_4:
1772                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1773                         break;
1774                 case RME96_MONITOR_TRACKS_5_6:
1775                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1776                         break;
1777                 case RME96_MONITOR_TRACKS_7_8:
1778                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1779                         break;
1780                 }
1781                 switch (snd_rme96_getattenuation(rme96)) {
1782                 case RME96_ATTENUATION_0:
1783                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1784                         break;
1785                 case RME96_ATTENUATION_6:
1786                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1787                         break;
1788                 case RME96_ATTENUATION_12:
1789                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1790                         break;
1791                 case RME96_ATTENUATION_18:
1792                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1793                         break;
1794                 }
1795                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1796                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1797         }
1798 }
1799
1800 static void __devinit
1801 snd_rme96_proc_init(struct rme96 *rme96)
1802 {
1803         struct snd_info_entry *entry;
1804
1805         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1806                 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1807 }
1808
1809 /*
1810  * control interface
1811  */
1812
1813 #define snd_rme96_info_loopback_control         snd_ctl_boolean_mono_info
1814
1815 static int
1816 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1817 {
1818         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1819
1820         spin_lock_irq(&rme96->lock);
1821         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1822         spin_unlock_irq(&rme96->lock);
1823         return 0;
1824 }
1825 static int
1826 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1827 {
1828         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1829         unsigned int val;
1830         int change;
1831
1832         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1833         spin_lock_irq(&rme96->lock);
1834         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1835         change = val != rme96->wcreg;
1836         rme96->wcreg = val;
1837         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1838         spin_unlock_irq(&rme96->lock);
1839         return change;
1840 }
1841
1842 static int
1843 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1844 {
1845         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1846         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1847         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1848
1849         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1850         uinfo->count = 1;
1851         switch (rme96->pci->device) {
1852         case PCI_DEVICE_ID_RME_DIGI96:
1853         case PCI_DEVICE_ID_RME_DIGI96_8:
1854                 uinfo->value.enumerated.items = 3;
1855                 break;
1856         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1857                 uinfo->value.enumerated.items = 4;
1858                 break;
1859         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1860                 if (rme96->rev > 4) {
1861                         /* PST */
1862                         uinfo->value.enumerated.items = 4;
1863                         texts[3] = _texts[4]; /* Analog instead of XLR */
1864                 } else {
1865                         /* PAD */
1866                         uinfo->value.enumerated.items = 5;
1867                 }
1868                 break;
1869         default:
1870                 snd_BUG();
1871                 break;
1872         }
1873         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1874                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1875         }
1876         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1877         return 0;
1878 }
1879 static int
1880 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1881 {
1882         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1883         unsigned int items = 3;
1884
1885         spin_lock_irq(&rme96->lock);
1886         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1887
1888         switch (rme96->pci->device) {
1889         case PCI_DEVICE_ID_RME_DIGI96:
1890         case PCI_DEVICE_ID_RME_DIGI96_8:
1891                 items = 3;
1892                 break;
1893         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1894                 items = 4;
1895                 break;
1896         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1897                 if (rme96->rev > 4) {
1898                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1899                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1900                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1901                         }
1902                         items = 4;
1903                 } else {
1904                         items = 5;
1905                 }
1906                 break;
1907         default:
1908                 snd_BUG();
1909                 break;
1910         }
1911         if (ucontrol->value.enumerated.item[0] >= items) {
1912                 ucontrol->value.enumerated.item[0] = items - 1;
1913         }
1914
1915         spin_unlock_irq(&rme96->lock);
1916         return 0;
1917 }
1918 static int
1919 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1920 {
1921         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1922         unsigned int val;
1923         int change, items = 3;
1924
1925         switch (rme96->pci->device) {
1926         case PCI_DEVICE_ID_RME_DIGI96:
1927         case PCI_DEVICE_ID_RME_DIGI96_8:
1928                 items = 3;
1929                 break;
1930         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1931                 items = 4;
1932                 break;
1933         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1934                 if (rme96->rev > 4) {
1935                         items = 4;
1936                 } else {
1937                         items = 5;
1938                 }
1939                 break;
1940         default:
1941                 snd_BUG();
1942                 break;
1943         }
1944         val = ucontrol->value.enumerated.item[0] % items;
1945
1946         /* special case for PST */
1947         if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1948                 if (val == RME96_INPUT_XLR) {
1949                         val = RME96_INPUT_ANALOG;
1950                 }
1951         }
1952
1953         spin_lock_irq(&rme96->lock);
1954         change = (int)val != snd_rme96_getinputtype(rme96);
1955         snd_rme96_setinputtype(rme96, val);
1956         spin_unlock_irq(&rme96->lock);
1957         return change;
1958 }
1959
1960 static int
1961 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1962 {
1963         static char *texts[3] = { "AutoSync", "Internal", "Word" };
1964
1965         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1966         uinfo->count = 1;
1967         uinfo->value.enumerated.items = 3;
1968         if (uinfo->value.enumerated.item > 2) {
1969                 uinfo->value.enumerated.item = 2;
1970         }
1971         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1972         return 0;
1973 }
1974 static int
1975 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1976 {
1977         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1978
1979         spin_lock_irq(&rme96->lock);
1980         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1981         spin_unlock_irq(&rme96->lock);
1982         return 0;
1983 }
1984 static int
1985 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1986 {
1987         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1988         unsigned int val;
1989         int change;
1990
1991         val = ucontrol->value.enumerated.item[0] % 3;
1992         spin_lock_irq(&rme96->lock);
1993         change = (int)val != snd_rme96_getclockmode(rme96);
1994         snd_rme96_setclockmode(rme96, val);
1995         spin_unlock_irq(&rme96->lock);
1996         return change;
1997 }
1998
1999 static int
2000 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2001 {
2002         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2003
2004         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2005         uinfo->count = 1;
2006         uinfo->value.enumerated.items = 4;
2007         if (uinfo->value.enumerated.item > 3) {
2008                 uinfo->value.enumerated.item = 3;
2009         }
2010         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2011         return 0;
2012 }
2013 static int
2014 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2015 {
2016         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2017
2018         spin_lock_irq(&rme96->lock);
2019         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2020         spin_unlock_irq(&rme96->lock);
2021         return 0;
2022 }
2023 static int
2024 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2025 {
2026         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2027         unsigned int val;
2028         int change;
2029
2030         val = ucontrol->value.enumerated.item[0] % 4;
2031         spin_lock_irq(&rme96->lock);
2032
2033         change = (int)val != snd_rme96_getattenuation(rme96);
2034         snd_rme96_setattenuation(rme96, val);
2035         spin_unlock_irq(&rme96->lock);
2036         return change;
2037 }
2038
2039 static int
2040 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2041 {
2042         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2043
2044         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2045         uinfo->count = 1;
2046         uinfo->value.enumerated.items = 4;
2047         if (uinfo->value.enumerated.item > 3) {
2048                 uinfo->value.enumerated.item = 3;
2049         }
2050         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2051         return 0;
2052 }
2053 static int
2054 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2055 {
2056         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2057
2058         spin_lock_irq(&rme96->lock);
2059         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2060         spin_unlock_irq(&rme96->lock);
2061         return 0;
2062 }
2063 static int
2064 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2065 {
2066         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2067         unsigned int val;
2068         int change;
2069
2070         val = ucontrol->value.enumerated.item[0] % 4;
2071         spin_lock_irq(&rme96->lock);
2072         change = (int)val != snd_rme96_getmontracks(rme96);
2073         snd_rme96_setmontracks(rme96, val);
2074         spin_unlock_irq(&rme96->lock);
2075         return change;
2076 }
2077
2078 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2079 {
2080         u32 val = 0;
2081         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2082         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2083         if (val & RME96_WCR_PRO)
2084                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2085         else
2086                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2087         return val;
2088 }
2089
2090 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2091 {
2092         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2093                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2094         if (val & RME96_WCR_PRO)
2095                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2096         else
2097                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2098 }
2099
2100 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2101 {
2102         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2103         uinfo->count = 1;
2104         return 0;
2105 }
2106
2107 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2108 {
2109         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2110
2111         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2112         return 0;
2113 }
2114
2115 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2116 {
2117         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2118         int change;
2119         u32 val;
2120
2121         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2122         spin_lock_irq(&rme96->lock);
2123         change = val != rme96->wcreg_spdif;
2124         rme96->wcreg_spdif = val;
2125         spin_unlock_irq(&rme96->lock);
2126         return change;
2127 }
2128
2129 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2130 {
2131         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2132         uinfo->count = 1;
2133         return 0;
2134 }
2135
2136 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2137 {
2138         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2139
2140         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2141         return 0;
2142 }
2143
2144 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2145 {
2146         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2147         int change;
2148         u32 val;
2149
2150         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2151         spin_lock_irq(&rme96->lock);
2152         change = val != rme96->wcreg_spdif_stream;
2153         rme96->wcreg_spdif_stream = val;
2154         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2155         rme96->wcreg |= val;
2156         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2157         spin_unlock_irq(&rme96->lock);
2158         return change;
2159 }
2160
2161 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2162 {
2163         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2164         uinfo->count = 1;
2165         return 0;
2166 }
2167
2168 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2169 {
2170         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2171         return 0;
2172 }
2173
2174 static int
2175 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2176 {
2177         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2178
2179         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2180         uinfo->count = 2;
2181         uinfo->value.integer.min = 0;
2182         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2183         return 0;
2184 }
2185
2186 static int
2187 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2188 {
2189         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2190
2191         spin_lock_irq(&rme96->lock);
2192         u->value.integer.value[0] = rme96->vol[0];
2193         u->value.integer.value[1] = rme96->vol[1];
2194         spin_unlock_irq(&rme96->lock);
2195
2196         return 0;
2197 }
2198
2199 static int
2200 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2201 {
2202         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2203         int change = 0;
2204         unsigned int vol, maxvol;
2205
2206
2207         if (!RME96_HAS_ANALOG_OUT(rme96))
2208                 return -EINVAL;
2209         maxvol = RME96_185X_MAX_OUT(rme96);
2210         spin_lock_irq(&rme96->lock);
2211         vol = u->value.integer.value[0];
2212         if (vol != rme96->vol[0] && vol <= maxvol) {
2213                 rme96->vol[0] = vol;
2214                 change = 1;
2215         }
2216         vol = u->value.integer.value[1];
2217         if (vol != rme96->vol[1] && vol <= maxvol) {
2218                 rme96->vol[1] = vol;
2219                 change = 1;
2220         }
2221         if (change)
2222                 snd_rme96_apply_dac_volume(rme96);
2223         spin_unlock_irq(&rme96->lock);
2224
2225         return change;
2226 }
2227
2228 static struct snd_kcontrol_new snd_rme96_controls[] = {
2229 {
2230         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2231         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2232         .info =         snd_rme96_control_spdif_info,
2233         .get =          snd_rme96_control_spdif_get,
2234         .put =          snd_rme96_control_spdif_put
2235 },
2236 {
2237         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2238         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2239         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2240         .info =         snd_rme96_control_spdif_stream_info,
2241         .get =          snd_rme96_control_spdif_stream_get,
2242         .put =          snd_rme96_control_spdif_stream_put
2243 },
2244 {
2245         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2246         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2247         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2248         .info =         snd_rme96_control_spdif_mask_info,
2249         .get =          snd_rme96_control_spdif_mask_get,
2250         .private_value = IEC958_AES0_NONAUDIO |
2251                         IEC958_AES0_PROFESSIONAL |
2252                         IEC958_AES0_CON_EMPHASIS
2253 },
2254 {
2255         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2256         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2257         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2258         .info =         snd_rme96_control_spdif_mask_info,
2259         .get =          snd_rme96_control_spdif_mask_get,
2260         .private_value = IEC958_AES0_NONAUDIO |
2261                         IEC958_AES0_PROFESSIONAL |
2262                         IEC958_AES0_PRO_EMPHASIS
2263 },
2264 {
2265         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2266         .name =         "Input Connector",
2267         .info =         snd_rme96_info_inputtype_control,
2268         .get =          snd_rme96_get_inputtype_control,
2269         .put =          snd_rme96_put_inputtype_control
2270 },
2271 {
2272         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2273         .name =         "Loopback Input",
2274         .info =         snd_rme96_info_loopback_control,
2275         .get =          snd_rme96_get_loopback_control,
2276         .put =          snd_rme96_put_loopback_control
2277 },
2278 {
2279         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2280         .name =         "Sample Clock Source",
2281         .info =         snd_rme96_info_clockmode_control,
2282         .get =          snd_rme96_get_clockmode_control,
2283         .put =          snd_rme96_put_clockmode_control
2284 },
2285 {
2286         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2287         .name =         "Monitor Tracks",
2288         .info =         snd_rme96_info_montracks_control,
2289         .get =          snd_rme96_get_montracks_control,
2290         .put =          snd_rme96_put_montracks_control
2291 },
2292 {
2293         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2294         .name =         "Attenuation",
2295         .info =         snd_rme96_info_attenuation_control,
2296         .get =          snd_rme96_get_attenuation_control,
2297         .put =          snd_rme96_put_attenuation_control
2298 },
2299 {
2300         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2301         .name =         "DAC Playback Volume",
2302         .info =         snd_rme96_dac_volume_info,
2303         .get =          snd_rme96_dac_volume_get,
2304         .put =          snd_rme96_dac_volume_put
2305 }
2306 };
2307
2308 static int
2309 snd_rme96_create_switches(struct snd_card *card,
2310                           struct rme96 *rme96)
2311 {
2312         int idx, err;
2313         struct snd_kcontrol *kctl;
2314
2315         for (idx = 0; idx < 7; idx++) {
2316                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2317                         return err;
2318                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2319                         rme96->spdif_ctl = kctl;
2320         }
2321
2322         if (RME96_HAS_ANALOG_OUT(rme96)) {
2323                 for (idx = 7; idx < 10; idx++)
2324                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2325                                 return err;
2326         }
2327
2328         return 0;
2329 }
2330
2331 /*
2332  * Card initialisation
2333  */
2334
2335 static void snd_rme96_card_free(struct snd_card *card)
2336 {
2337         snd_rme96_free(card->private_data);
2338 }
2339
2340 static int __devinit
2341 snd_rme96_probe(struct pci_dev *pci,
2342                 const struct pci_device_id *pci_id)
2343 {
2344         static int dev;
2345         struct rme96 *rme96;
2346         struct snd_card *card;
2347         int err;
2348         u8 val;
2349
2350         if (dev >= SNDRV_CARDS) {
2351                 return -ENODEV;
2352         }
2353         if (!enable[dev]) {
2354                 dev++;
2355                 return -ENOENT;
2356         }
2357         err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2358                               sizeof(struct rme96), &card);
2359         if (err < 0)
2360                 return err;
2361         card->private_free = snd_rme96_card_free;
2362         rme96 = card->private_data;
2363         rme96->card = card;
2364         rme96->pci = pci;
2365         snd_card_set_dev(card, &pci->dev);
2366         if ((err = snd_rme96_create(rme96)) < 0) {
2367                 snd_card_free(card);
2368                 return err;
2369         }
2370
2371         strcpy(card->driver, "Digi96");
2372         switch (rme96->pci->device) {
2373         case PCI_DEVICE_ID_RME_DIGI96:
2374                 strcpy(card->shortname, "RME Digi96");
2375                 break;
2376         case PCI_DEVICE_ID_RME_DIGI96_8:
2377                 strcpy(card->shortname, "RME Digi96/8");
2378                 break;
2379         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2380                 strcpy(card->shortname, "RME Digi96/8 PRO");
2381                 break;
2382         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2383                 pci_read_config_byte(rme96->pci, 8, &val);
2384                 if (val < 5) {
2385                         strcpy(card->shortname, "RME Digi96/8 PAD");
2386                 } else {
2387                         strcpy(card->shortname, "RME Digi96/8 PST");
2388                 }
2389                 break;
2390         }
2391         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2392                 rme96->port, rme96->irq);
2393
2394         if ((err = snd_card_register(card)) < 0) {
2395                 snd_card_free(card);
2396                 return err;
2397         }
2398         pci_set_drvdata(pci, card);
2399         dev++;
2400         return 0;
2401 }
2402
2403 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2404 {
2405         snd_card_free(pci_get_drvdata(pci));
2406         pci_set_drvdata(pci, NULL);
2407 }
2408
2409 static struct pci_driver driver = {
2410         .name = KBUILD_MODNAME,
2411         .id_table = snd_rme96_ids,
2412         .probe = snd_rme96_probe,
2413         .remove = __devexit_p(snd_rme96_remove),
2414 };
2415
2416 static int __init alsa_card_rme96_init(void)
2417 {
2418         return pci_register_driver(&driver);
2419 }
2420
2421 static void __exit alsa_card_rme96_exit(void)
2422 {
2423         pci_unregister_driver(&driver);
2424 }
2425
2426 module_init(alsa_card_rme96_init)
2427 module_exit(alsa_card_rme96_exit)