sound/pci/oxygen/oxygen_lib.c

   1 /*
   2  * C-Media CMI8788 driver - main driver module
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  *  This driver is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License, version 2.
   9  *
  10  *  This driver is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this driver; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mutex.h>
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <sound/ac97_codec.h>
  26 #include <sound/asoundef.h>
  27 #include <sound/core.h>
  28 #include <sound/info.h>
  29 #include <sound/mpu401.h>
  30 #include <sound/pcm.h>
  31 #include "oxygen.h"
  32 #include "cm9780.h"
  33
  34 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  35 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
  36 MODULE_LICENSE("GPL v2");
  37
  38 #define DRIVER "oxygen"
  39
  40 static inline int oxygen_uart_input_ready(struct oxygen *chip)
  41 {
  42         return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
  43 }
  44
  45 static void oxygen_read_uart(struct oxygen *chip)
  46 {
  47         if (unlikely(!oxygen_uart_input_ready(chip))) {
  48                 /* no data, but read it anyway to clear the interrupt */
  49                 oxygen_read8(chip, OXYGEN_MPU401);
  50                 return;
  51         }
  52         do {
  53                 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
  54                 if (data == MPU401_ACK)
  55                         continue;
  56                 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
  57                         chip->uart_input_count = 0;
  58                 chip->uart_input[chip->uart_input_count++] = data;
  59         } while (oxygen_uart_input_ready(chip));
  60         if (chip->model.uart_input)
  61                 chip->model.uart_input(chip);
  62 }
  63
  64 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
  65 {
  66         struct oxygen *chip = dev_id;
  67         unsigned int status, clear, elapsed_streams, i;
  68
  69         status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
  70         if (!status)
  71                 return IRQ_NONE;
  72
  73         spin_lock(&chip->reg_lock);
  74
  75         clear = status & (OXYGEN_CHANNEL_A |
  76                           OXYGEN_CHANNEL_B |
  77                           OXYGEN_CHANNEL_C |
  78                           OXYGEN_CHANNEL_SPDIF |
  79                           OXYGEN_CHANNEL_MULTICH |
  80                           OXYGEN_CHANNEL_AC97 |
  81                           OXYGEN_INT_SPDIF_IN_DETECT |
  82                           OXYGEN_INT_GPIO |
  83                           OXYGEN_INT_AC97);
  84         if (clear) {
  85                 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
  86                         chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
  87                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  88                                chip->interrupt_mask & ~clear);
  89                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  90                                chip->interrupt_mask);
  91         }
  92
  93         elapsed_streams = status & chip->pcm_running;
  94
  95         spin_unlock(&chip->reg_lock);
  96
  97         for (i = 0; i < PCM_COUNT; ++i)
  98                 if ((elapsed_streams & (1 << i)) && chip->streams[i])
  99                         snd_pcm_period_elapsed(chip->streams[i]);
 100
 101         if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
 102                 spin_lock(&chip->reg_lock);
 103                 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 104                 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
 105                          OXYGEN_SPDIF_RATE_INT)) {
 106                         /* write the interrupt bit(s) to clear */
 107                         oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
 108                         schedule_work(&chip->spdif_input_bits_work);
 109                 }
 110                 spin_unlock(&chip->reg_lock);
 111         }
 112
 113         if (status & OXYGEN_INT_GPIO)
 114                 schedule_work(&chip->gpio_work);
 115
 116         if (status & OXYGEN_INT_MIDI) {
 117                 if (chip->midi)
 118                         snd_mpu401_uart_interrupt(0, chip->midi->private_data);
 119                 else
 120                         oxygen_read_uart(chip);
 121         }
 122
 123         if (status & OXYGEN_INT_AC97)
 124                 wake_up(&chip->ac97_waitqueue);
 125
 126         return IRQ_HANDLED;
 127 }
 128
 129 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
 130 {
 131         struct oxygen *chip = container_of(work, struct oxygen,
 132                                            spdif_input_bits_work);
 133         u32 reg;
 134
 135         /*
 136          * This function gets called when there is new activity on the SPDIF
 137          * input, or when we lose lock on the input signal, or when the rate
 138          * changes.
 139          */
 140         msleep(1);
 141         spin_lock_irq(&chip->reg_lock);
 142         reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 143         if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 144                     OXYGEN_SPDIF_LOCK_STATUS))
 145             == OXYGEN_SPDIF_SENSE_STATUS) {
 146                 /*
 147                  * If we detect activity on the SPDIF input but cannot lock to
 148                  * a signal, the clock bit is likely to be wrong.
 149                  */
 150                 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
 151                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 152                 spin_unlock_irq(&chip->reg_lock);
 153                 msleep(1);
 154                 spin_lock_irq(&chip->reg_lock);
 155                 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 156                 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 157                             OXYGEN_SPDIF_LOCK_STATUS))
 158                     == OXYGEN_SPDIF_SENSE_STATUS) {
 159                         /* nothing detected with either clock; give up */
 160                         if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
 161                             == OXYGEN_SPDIF_IN_CLOCK_192) {
 162                                 /*
 163                                  * Reset clock to <= 96 kHz because this is
 164                                  * more likely to be received next time.
 165                                  */
 166                                 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
 167                                 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
 168                                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 169                         }
 170                 }
 171         }
 172         spin_unlock_irq(&chip->reg_lock);
 173
 174         if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
 175                 spin_lock_irq(&chip->reg_lock);
 176                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 177                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
 178                                chip->interrupt_mask);
 179                 spin_unlock_irq(&chip->reg_lock);
 180
 181                 /*
 182                  * We don't actually know that any channel status bits have
 183                  * changed, but let's send a notification just to be sure.
 184                  */
 185                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
 186                                &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
 187         }
 188 }
 189
 190 static void oxygen_gpio_changed(struct work_struct *work)
 191 {
 192         struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
 193
 194         if (chip->model.gpio_changed)
 195                 chip->model.gpio_changed(chip);
 196 }
 197
 198 #ifdef CONFIG_PROC_FS
 199 static void oxygen_proc_read(struct snd_info_entry *entry,
 200                              struct snd_info_buffer *buffer)
 201 {
 202         struct oxygen *chip = entry->private_data;
 203         int i, j;
 204
 205         snd_iprintf(buffer, "CMI8788\n\n");
 206         for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
 207                 snd_iprintf(buffer, "%02x:", i);
 208                 for (j = 0; j < 0x10; ++j)
 209                         snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
 210                 snd_iprintf(buffer, "\n");
 211         }
 212         if (mutex_lock_interruptible(&chip->mutex) < 0)
 213                 return;
 214         if (chip->has_ac97_0) {
 215                 snd_iprintf(buffer, "\nAC97\n");
 216                 for (i = 0; i < 0x80; i += 0x10) {
 217                         snd_iprintf(buffer, "%02x:", i);
 218                         for (j = 0; j < 0x10; j += 2)
 219                                 snd_iprintf(buffer, " %04x",
 220                                             oxygen_read_ac97(chip, 0, i + j));
 221                         snd_iprintf(buffer, "\n");
 222                 }
 223         }
 224         if (chip->has_ac97_1) {
 225                 snd_iprintf(buffer, "\nAC97 2\n");
 226                 for (i = 0; i < 0x80; i += 0x10) {
 227                         snd_iprintf(buffer, "%02x:", i);
 228                         for (j = 0; j < 0x10; j += 2)
 229                                 snd_iprintf(buffer, " %04x",
 230                                             oxygen_read_ac97(chip, 1, i + j));
 231                         snd_iprintf(buffer, "\n");
 232                 }
 233         }
 234         mutex_unlock(&chip->mutex);
 235 }
 236
 237 static void oxygen_proc_init(struct oxygen *chip)
 238 {
 239         struct snd_info_entry *entry;
 240
 241         if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
 242                 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
 243 }
 244 #else
 245 #define oxygen_proc_init(chip)
 246 #endif
 247
 248 static const struct pci_device_id *
 249 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
 250 {
 251         u16 subdevice;
 252
 253         /*
 254          * Make sure the EEPROM pins are available, i.e., not used for SPI.
 255          * (This function is called before we initialize or use SPI.)
 256          */
 257         oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
 258                            OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 259         /*
 260          * Read the subsystem device ID directly from the EEPROM, because the
 261          * chip didn't if the first EEPROM word was overwritten.
 262          */
 263         subdevice = oxygen_read_eeprom(chip, 2);
 264         /* use default ID if EEPROM is missing */
 265         if (subdevice == 0xffff)
 266                 subdevice = 0x8788;
 267         /*
 268          * We use only the subsystem device ID for searching because it is
 269          * unique even without the subsystem vendor ID, which may have been
 270          * overwritten in the EEPROM.
 271          */
 272         for (; ids->vendor; ++ids)
 273                 if (ids->subdevice == subdevice &&
 274                     ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
 275                         return ids;
 276         return NULL;
 277 }
 278
 279 static void oxygen_restore_eeprom(struct oxygen *chip,
 280                                   const struct pci_device_id *id)
 281 {
 282         u16 eeprom_id;
 283
 284         eeprom_id = oxygen_read_eeprom(chip, 0);
 285         if (eeprom_id != OXYGEN_EEPROM_ID &&
 286             (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
 287                 /*
 288                  * This function gets called only when a known card model has
 289                  * been detected, i.e., we know there is a valid subsystem
 290                  * product ID at index 2 in the EEPROM.  Therefore, we have
 291                  * been able to deduce the correct subsystem vendor ID, and
 292                  * this is enough information to restore the original EEPROM
 293                  * contents.
 294                  */
 295                 oxygen_write_eeprom(chip, 1, id->subvendor);
 296                 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
 297
 298                 oxygen_set_bits8(chip, OXYGEN_MISC,
 299                                  OXYGEN_MISC_WRITE_PCI_SUBID);
 300                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
 301                                       id->subvendor);
 302                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
 303                                       id->subdevice);
 304                 oxygen_clear_bits8(chip, OXYGEN_MISC,
 305                                    OXYGEN_MISC_WRITE_PCI_SUBID);
 306
 307                 snd_printk(KERN_INFO "EEPROM ID restored\n");
 308         }
 309 }
 310
 311 static void configure_pcie_bridge(struct pci_dev *pci)
 312 {
 313         enum { PI7C9X110 };
 314         static const struct pci_device_id bridge_ids[] = {
 315                 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
 316                 { }
 317         };
 318         struct pci_dev *bridge;
 319         const struct pci_device_id *id;
 320         u32 tmp;
 321
 322         if (!pci->bus || !pci->bus->self)
 323                 return;
 324         bridge = pci->bus->self;
 325
 326         id = pci_match_id(bridge_ids, bridge);
 327         if (!id)
 328                 return;
 329
 330         switch (id->driver_data) {
 331         case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
 332                 pci_read_config_dword(bridge, 0x40, &tmp);
 333                 tmp |= 1;       /* park the PCI arbiter to the sound chip */
 334                 pci_write_config_dword(bridge, 0x40, tmp);
 335                 break;
 336         }
 337 }
 338
 339 static void oxygen_init(struct oxygen *chip)
 340 {
 341         unsigned int i;
 342
 343         chip->dac_routing = 1;
 344         for (i = 0; i < 8; ++i)
 345                 chip->dac_volume[i] = chip->model.dac_volume_min;
 346         chip->dac_mute = 1;
 347         chip->spdif_playback_enable = 1;
 348         chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
 349                 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
 350         chip->spdif_pcm_bits = chip->spdif_bits;
 351
 352         if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
 353                 chip->revision = 2;
 354         else
 355                 chip->revision = 1;
 356
 357         if (chip->revision == 1)
 358                 oxygen_set_bits8(chip, OXYGEN_MISC,
 359                                  OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
 360
 361         i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
 362         chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
 363         chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
 364
 365         oxygen_write8_masked(chip, OXYGEN_FUNCTION,
 366                              OXYGEN_FUNCTION_RESET_CODEC |
 367                              chip->model.function_flags,
 368                              OXYGEN_FUNCTION_RESET_CODEC |
 369                              OXYGEN_FUNCTION_2WIRE_SPI_MASK |
 370                              OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 371         oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
 372         oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
 373         oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
 374                       OXYGEN_PLAY_CHANNELS_2 |
 375                       OXYGEN_DMA_A_BURST_8 |
 376                       OXYGEN_DMA_MULTICH_BURST_8);
 377         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 378         oxygen_write8_masked(chip, OXYGEN_MISC,
 379                              chip->model.misc_flags,
 380                              OXYGEN_MISC_WRITE_PCI_SUBID |
 381                              OXYGEN_MISC_REC_C_FROM_SPDIF |
 382                              OXYGEN_MISC_REC_B_FROM_AC97 |
 383                              OXYGEN_MISC_REC_A_FROM_MULTICH |
 384                              OXYGEN_MISC_MIDI);
 385         oxygen_write8(chip, OXYGEN_REC_FORMAT,
 386                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
 387                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
 388                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
 389         oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
 390                       (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
 391                       (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
 392         oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
 393         oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
 394                        OXYGEN_RATE_48000 | chip->model.dac_i2s_format |
 395                        OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
 396                        OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
 397         if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
 398                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 399                                OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
 400                                OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
 401                                OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
 402         else
 403                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 404                                OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
 405         if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
 406                                          CAPTURE_2_FROM_I2S_2))
 407                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 408                                OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
 409                                OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
 410                                OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
 411         else
 412                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 413                                OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
 414         oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
 415                        OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
 416         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 417                             OXYGEN_SPDIF_OUT_ENABLE |
 418                             OXYGEN_SPDIF_LOOPBACK);
 419         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 420                 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
 421                                       OXYGEN_SPDIF_SENSE_MASK |
 422                                       OXYGEN_SPDIF_LOCK_MASK |
 423                                       OXYGEN_SPDIF_RATE_MASK |
 424                                       OXYGEN_SPDIF_LOCK_PAR |
 425                                       OXYGEN_SPDIF_IN_CLOCK_96,
 426                                       OXYGEN_SPDIF_SENSE_MASK |
 427                                       OXYGEN_SPDIF_LOCK_MASK |
 428                                       OXYGEN_SPDIF_RATE_MASK |
 429                                       OXYGEN_SPDIF_SENSE_PAR |
 430                                       OXYGEN_SPDIF_LOCK_PAR |
 431                                       OXYGEN_SPDIF_IN_CLOCK_MASK);
 432         else
 433                 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 434                                     OXYGEN_SPDIF_SENSE_MASK |
 435                                     OXYGEN_SPDIF_LOCK_MASK |
 436                                     OXYGEN_SPDIF_RATE_MASK);
 437         oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
 438         oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
 439                        OXYGEN_2WIRE_LENGTH_8 |
 440                        OXYGEN_2WIRE_INTERRUPT_MASK |
 441                        OXYGEN_2WIRE_SPEED_STANDARD);
 442         oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
 443         oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
 444         oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
 445         oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
 446                        OXYGEN_PLAY_MULTICH_I2S_DAC |
 447                        OXYGEN_PLAY_SPDIF_SPDIF |
 448                        (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
 449                        (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
 450                        (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
 451                        (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
 452         oxygen_write8(chip, OXYGEN_REC_ROUTING,
 453                       OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
 454                       OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
 455                       OXYGEN_REC_C_ROUTE_SPDIF);
 456         oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
 457         oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
 458                       (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
 459                       (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
 460                       (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
 461                       (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
 462
 463         if (chip->has_ac97_0 | chip->has_ac97_1)
 464                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
 465                               OXYGEN_AC97_INT_READ_DONE |
 466                               OXYGEN_AC97_INT_WRITE_DONE);
 467         else
 468                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
 469         oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
 470         oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
 471         if (!(chip->has_ac97_0 | chip->has_ac97_1))
 472                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 473                                   OXYGEN_AC97_CLOCK_DISABLE);
 474         if (!chip->has_ac97_0) {
 475                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 476                                   OXYGEN_AC97_NO_CODEC_0);
 477         } else {
 478                 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
 479                 msleep(1);
 480                 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
 481                                      CM9780_GPIO0IO | CM9780_GPIO1IO);
 482                 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
 483                                      CM9780_BSTSEL | CM9780_STRO_MIC |
 484                                      CM9780_MIX2FR | CM9780_PCBSW);
 485                 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
 486                                      CM9780_RSOE | CM9780_CBOE |
 487                                      CM9780_SSOE | CM9780_FROE |
 488                                      CM9780_MIC2MIC | CM9780_LI2LI);
 489                 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
 490                 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
 491                 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
 492                 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
 493                 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
 494                 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
 495                 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
 496                 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
 497                 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
 498                 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
 499                 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
 500                                        CM9780_GPO0);
 501                 /* power down unused ADCs and DACs */
 502                 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
 503                                      AC97_PD_PR0 | AC97_PD_PR1);
 504                 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
 505                                      AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
 506         }
 507         if (chip->has_ac97_1) {
 508                 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
 509                                   OXYGEN_AC97_CODEC1_SLOT3 |
 510                                   OXYGEN_AC97_CODEC1_SLOT4);
 511                 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
 512                 msleep(1);
 513                 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
 514                 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
 515                 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
 516                 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
 517                 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
 518                 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
 519                 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
 520                 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
 521                 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
 522                 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
 523                 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
 524                 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
 525         }
 526 }
 527
 528 static void oxygen_shutdown(struct oxygen *chip)
 529 {
 530         spin_lock_irq(&chip->reg_lock);
 531         chip->interrupt_mask = 0;
 532         chip->pcm_running = 0;
 533         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 534         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 535         spin_unlock_irq(&chip->reg_lock);
 536 }
 537
 538 static void oxygen_card_free(struct snd_card *card)
 539 {
 540         struct oxygen *chip = card->private_data;
 541
 542         oxygen_shutdown(chip);
 543         if (chip->irq >= 0)
 544                 free_irq(chip->irq, chip);
 545         flush_scheduled_work();
 546         chip->model.cleanup(chip);
 547         kfree(chip->model_data);
 548         mutex_destroy(&chip->mutex);
 549         pci_release_regions(chip->pci);
 550         pci_disable_device(chip->pci);
 551 }
 552
 553 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
 554                      struct module *owner,
 555                      const struct pci_device_id *ids,
 556                      int (*get_model)(struct oxygen *chip,
 557                                       const struct pci_device_id *id
 558                                      )
 559                     )
 560 {
 561         struct snd_card *card;
 562         struct oxygen *chip;
 563         const struct pci_device_id *pci_id;
 564         int err;
 565
 566         err = snd_card_create(index, id, owner, sizeof(*chip), &card);
 567         if (err < 0)
 568                 return err;
 569
 570         chip = card->private_data;
 571         chip->card = card;
 572         chip->pci = pci;
 573         chip->irq = -1;
 574         spin_lock_init(&chip->reg_lock);
 575         mutex_init(&chip->mutex);
 576         INIT_WORK(&chip->spdif_input_bits_work,
 577                   oxygen_spdif_input_bits_changed);
 578         INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
 579         init_waitqueue_head(&chip->ac97_waitqueue);
 580
 581         err = pci_enable_device(pci);
 582         if (err < 0)
 583                 goto err_card;
 584
 585         err = pci_request_regions(pci, DRIVER);
 586         if (err < 0) {
 587                 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
 588                 goto err_pci_enable;
 589         }
 590
 591         if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
 592             pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
 593                 snd_printk(KERN_ERR "invalid PCI I/O range\n");
 594                 err = -ENXIO;
 595                 goto err_pci_regions;
 596         }
 597         chip->addr = pci_resource_start(pci, 0);
 598
 599         pci_id = oxygen_search_pci_id(chip, ids);
 600         if (!pci_id) {
 601                 err = -ENODEV;
 602                 goto err_pci_regions;
 603         }
 604         oxygen_restore_eeprom(chip, pci_id);
 605         err = get_model(chip, pci_id);
 606         if (err < 0)
 607                 goto err_pci_regions;
 608
 609         if (chip->model.model_data_size) {
 610                 chip->model_data = kzalloc(chip->model.model_data_size,
 611                                            GFP_KERNEL);
 612                 if (!chip->model_data) {
 613                         err = -ENOMEM;
 614                         goto err_pci_regions;
 615                 }
 616         }
 617
 618         pci_set_master(pci);
 619         snd_card_set_dev(card, &pci->dev);
 620         card->private_free = oxygen_card_free;
 621
 622         configure_pcie_bridge(pci);
 623         oxygen_init(chip);
 624         chip->model.init(chip);
 625
 626         err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
 627                           DRIVER, chip);
 628         if (err < 0) {
 629                 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
 630                 goto err_card;
 631         }
 632         chip->irq = pci->irq;
 633
 634         strcpy(card->driver, chip->model.chip);
 635         strcpy(card->shortname, chip->model.shortname);
 636         sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
 637                 chip->model.longname, chip->revision, chip->addr, chip->irq);
 638         strcpy(card->mixername, chip->model.chip);
 639         snd_component_add(card, chip->model.chip);
 640
 641         err = oxygen_pcm_init(chip);
 642         if (err < 0)
 643                 goto err_card;
 644
 645         err = oxygen_mixer_init(chip);
 646         if (err < 0)
 647                 goto err_card;
 648
 649         if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
 650                 unsigned int info_flags = MPU401_INFO_INTEGRATED;
 651                 if (chip->model.device_config & MIDI_OUTPUT)
 652                         info_flags |= MPU401_INFO_OUTPUT;
 653                 if (chip->model.device_config & MIDI_INPUT)
 654                         info_flags |= MPU401_INFO_INPUT;
 655                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
 656                                           chip->addr + OXYGEN_MPU401,
 657                                           info_flags, 0, 0,
 658                                           &chip->midi);
 659                 if (err < 0)
 660                         goto err_card;
 661         }
 662
 663         oxygen_proc_init(chip);
 664
 665         spin_lock_irq(&chip->reg_lock);
 666         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 667                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 668         if (chip->has_ac97_0 | chip->has_ac97_1)
 669                 chip->interrupt_mask |= OXYGEN_INT_AC97;
 670         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 671         spin_unlock_irq(&chip->reg_lock);
 672
 673         err = snd_card_register(card);
 674         if (err < 0)
 675                 goto err_card;
 676
 677         pci_set_drvdata(pci, card);
 678         return 0;
 679
 680 err_pci_regions:
 681         pci_release_regions(pci);
 682 err_pci_enable:
 683         pci_disable_device(pci);
 684 err_card:
 685         snd_card_free(card);
 686         return err;
 687 }
 688 EXPORT_SYMBOL(oxygen_pci_probe);
 689
 690 void oxygen_pci_remove(struct pci_dev *pci)
 691 {
 692         snd_card_free(pci_get_drvdata(pci));
 693         pci_set_drvdata(pci, NULL);
 694 }
 695 EXPORT_SYMBOL(oxygen_pci_remove);
 696
 697 #ifdef CONFIG_PM
 698 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
 699 {
 700         struct snd_card *card = pci_get_drvdata(pci);
 701         struct oxygen *chip = card->private_data;
 702         unsigned int i, saved_interrupt_mask;
 703
 704         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 705
 706         for (i = 0; i < PCM_COUNT; ++i)
 707                 if (chip->streams[i])
 708                         snd_pcm_suspend(chip->streams[i]);
 709
 710         if (chip->model.suspend)
 711                 chip->model.suspend(chip);
 712
 713         spin_lock_irq(&chip->reg_lock);
 714         saved_interrupt_mask = chip->interrupt_mask;
 715         chip->interrupt_mask = 0;
 716         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 717         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 718         spin_unlock_irq(&chip->reg_lock);
 719
 720         synchronize_irq(chip->irq);
 721         flush_scheduled_work();
 722         chip->interrupt_mask = saved_interrupt_mask;
 723
 724         pci_disable_device(pci);
 725         pci_save_state(pci);
 726         pci_set_power_state(pci, pci_choose_state(pci, state));
 727         return 0;
 728 }
 729 EXPORT_SYMBOL(oxygen_pci_suspend);
 730
 731 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
 732         0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
 733         0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
 734 };
 735 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
 736         { 0x18284fa2, 0x03060000 },
 737         { 0x00007fa6, 0x00200000 }
 738 };
 739
 740 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
 741 {
 742         return bitmap[bit / 32] & (1 << (bit & 31));
 743 }
 744
 745 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
 746 {
 747         unsigned int i;
 748
 749         oxygen_write_ac97(chip, codec, AC97_RESET, 0);
 750         msleep(1);
 751         for (i = 1; i < 0x40; ++i)
 752                 if (is_bit_set(ac97_registers_to_restore[codec], i))
 753                         oxygen_write_ac97(chip, codec, i * 2,
 754                                           chip->saved_ac97_registers[codec][i]);
 755 }
 756
 757 int oxygen_pci_resume(struct pci_dev *pci)
 758 {
 759         struct snd_card *card = pci_get_drvdata(pci);
 760         struct oxygen *chip = card->private_data;
 761         unsigned int i;
 762
 763         pci_set_power_state(pci, PCI_D0);
 764         pci_restore_state(pci);
 765         if (pci_enable_device(pci) < 0) {
 766                 snd_printk(KERN_ERR "cannot reenable device");
 767                 snd_card_disconnect(card);
 768                 return -EIO;
 769         }
 770         pci_set_master(pci);
 771
 772         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 773         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 774         for (i = 0; i < OXYGEN_IO_SIZE; ++i)
 775                 if (is_bit_set(registers_to_restore, i))
 776                         oxygen_write8(chip, i, chip->saved_registers._8[i]);
 777         if (chip->has_ac97_0)
 778                 oxygen_restore_ac97(chip, 0);
 779         if (chip->has_ac97_1)
 780                 oxygen_restore_ac97(chip, 1);
 781
 782         if (chip->model.resume)
 783                 chip->model.resume(chip);
 784
 785         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 786
 787         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 788         return 0;
 789 }
 790 EXPORT_SYMBOL(oxygen_pci_resume);
 791 #endif /* CONFIG_PM */
 792
 793 void oxygen_pci_shutdown(struct pci_dev *pci)
 794 {
 795         struct snd_card *card = pci_get_drvdata(pci);
 796         struct oxygen *chip = card->private_data;
 797
 798         oxygen_shutdown(chip);
 799         chip->model.cleanup(chip);
 800 }
 801 EXPORT_SYMBOL(oxygen_pci_shutdown);