sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/moduleparam.h>
  43 #include <sound/core.h>
  44 #include <sound/info.h>
  45 #include <sound/control.h>
  46 #include <sound/pcm.h>
  47 #include <sound/mpu401.h>
  48 #include <sound/ac97_codec.h>
  49 #include <sound/initval.h>
  50
  51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  53 MODULE_LICENSE("GPL");
  54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  55                 "{ESS,ES1988},"
  56                 "{ESS,Allegro PCI},"
  57                 "{ESS,Allegro-1 PCI},"
  58                 "{ESS,Canyon3D-2/LE PCI}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  68 module_param_array(id, charp, NULL, 0444);
  69 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  70 module_param_array(enable, bool, NULL, 0444);
  71 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  72 module_param_array(external_amp, bool, NULL, 0444);
  73 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  74 module_param_array(amp_gpio, int, NULL, 0444);
  75 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  76
  77 #define MAX_PLAYBACKS   2
  78 #define MAX_CAPTURES    1
  79 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  80
  81
  82 /*
  83  * maestro3 registers
  84  */
  85
  86 /* Allegro PCI configuration registers */
  87 #define PCI_LEGACY_AUDIO_CTRL   0x40
  88 #define SOUND_BLASTER_ENABLE    0x00000001
  89 #define FM_SYNTHESIS_ENABLE     0x00000002
  90 #define GAME_PORT_ENABLE        0x00000004
  91 #define MPU401_IO_ENABLE        0x00000008
  92 #define MPU401_IRQ_ENABLE       0x00000010
  93 #define ALIAS_10BIT_IO          0x00000020
  94 #define SB_DMA_MASK             0x000000C0
  95 #define SB_DMA_0                0x00000040
  96 #define SB_DMA_1                0x00000040
  97 #define SB_DMA_R                0x00000080
  98 #define SB_DMA_3                0x000000C0
  99 #define SB_IRQ_MASK             0x00000700
 100 #define SB_IRQ_5                0x00000000
 101 #define SB_IRQ_7                0x00000100
 102 #define SB_IRQ_9                0x00000200
 103 #define SB_IRQ_10               0x00000300
 104 #define MIDI_IRQ_MASK           0x00003800
 105 #define SERIAL_IRQ_ENABLE       0x00004000
 106 #define DISABLE_LEGACY          0x00008000
 107
 108 #define PCI_ALLEGRO_CONFIG      0x50
 109 #define SB_ADDR_240             0x00000004
 110 #define MPU_ADDR_MASK           0x00000018
 111 #define MPU_ADDR_330            0x00000000
 112 #define MPU_ADDR_300            0x00000008
 113 #define MPU_ADDR_320            0x00000010
 114 #define MPU_ADDR_340            0x00000018
 115 #define USE_PCI_TIMING          0x00000040
 116 #define POSTED_WRITE_ENABLE     0x00000080
 117 #define DMA_POLICY_MASK         0x00000700
 118 #define DMA_DDMA                0x00000000
 119 #define DMA_TDMA                0x00000100
 120 #define DMA_PCPCI               0x00000200
 121 #define DMA_WBDMA16             0x00000400
 122 #define DMA_WBDMA4              0x00000500
 123 #define DMA_WBDMA2              0x00000600
 124 #define DMA_WBDMA1              0x00000700
 125 #define DMA_SAFE_GUARD          0x00000800
 126 #define HI_PERF_GP_ENABLE       0x00001000
 127 #define PIC_SNOOP_MODE_0        0x00002000
 128 #define PIC_SNOOP_MODE_1        0x00004000
 129 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 130 #define RING_IN_ENABLE          0x00010000
 131 #define SPDIF_TEST_MODE         0x00020000
 132 #define CLK_MULT_MODE_SELECT_2  0x00040000
 133 #define EEPROM_WRITE_ENABLE     0x00080000
 134 #define CODEC_DIR_IN            0x00100000
 135 #define HV_BUTTON_FROM_GD       0x00200000
 136 #define REDUCED_DEBOUNCE        0x00400000
 137 #define HV_CTRL_ENABLE          0x00800000
 138 #define SPDIF_ENABLE            0x01000000
 139 #define CLK_DIV_SELECT          0x06000000
 140 #define CLK_DIV_BY_48           0x00000000
 141 #define CLK_DIV_BY_49           0x02000000
 142 #define CLK_DIV_BY_50           0x04000000
 143 #define CLK_DIV_RESERVED        0x06000000
 144 #define PM_CTRL_ENABLE          0x08000000
 145 #define CLK_MULT_MODE_SELECT    0x30000000
 146 #define CLK_MULT_MODE_SHIFT     28
 147 #define CLK_MULT_MODE_0         0x00000000
 148 #define CLK_MULT_MODE_1         0x10000000
 149 #define CLK_MULT_MODE_2         0x20000000
 150 #define CLK_MULT_MODE_3         0x30000000
 151 #define INT_CLK_SELECT          0x40000000
 152 #define INT_CLK_MULT_RESET      0x80000000
 153
 154 /* M3 */
 155 #define INT_CLK_SRC_NOT_PCI     0x00100000
 156 #define INT_CLK_MULT_ENABLE     0x80000000
 157
 158 #define PCI_ACPI_CONTROL        0x54
 159 #define PCI_ACPI_D0             0x00000000
 160 #define PCI_ACPI_D1             0xB4F70000
 161 #define PCI_ACPI_D2             0xB4F7B4F7
 162
 163 #define PCI_USER_CONFIG         0x58
 164 #define EXT_PCI_MASTER_ENABLE   0x00000001
 165 #define SPDIF_OUT_SELECT        0x00000002
 166 #define TEST_PIN_DIR_CTRL       0x00000004
 167 #define AC97_CODEC_TEST         0x00000020
 168 #define TRI_STATE_BUFFER        0x00000080
 169 #define IN_CLK_12MHZ_SELECT     0x00000100
 170 #define MULTI_FUNC_DISABLE      0x00000200
 171 #define EXT_MASTER_PAIR_SEL     0x00000400
 172 #define PCI_MASTER_SUPPORT      0x00000800
 173 #define STOP_CLOCK_ENABLE       0x00001000
 174 #define EAPD_DRIVE_ENABLE       0x00002000
 175 #define REQ_TRI_STATE_ENABLE    0x00004000
 176 #define REQ_LOW_ENABLE          0x00008000
 177 #define MIDI_1_ENABLE           0x00010000
 178 #define MIDI_2_ENABLE           0x00020000
 179 #define SB_AUDIO_SYNC           0x00040000
 180 #define HV_CTRL_TEST            0x00100000
 181 #define SOUNDBLASTER_TEST       0x00400000
 182
 183 #define PCI_USER_CONFIG_C       0x5C
 184
 185 #define PCI_DDMA_CTRL           0x60
 186 #define DDMA_ENABLE             0x00000001
 187
 188
 189 /* Allegro registers */
 190 #define HOST_INT_CTRL           0x18
 191 #define SB_INT_ENABLE           0x0001
 192 #define MPU401_INT_ENABLE       0x0002
 193 #define ASSP_INT_ENABLE         0x0010
 194 #define RING_INT_ENABLE         0x0020
 195 #define HV_INT_ENABLE           0x0040
 196 #define CLKRUN_GEN_ENABLE       0x0100
 197 #define HV_CTRL_TO_PME          0x0400
 198 #define SOFTWARE_RESET_ENABLE   0x8000
 199
 200 /*
 201  * should be using the above defines, probably.
 202  */
 203 #define REGB_ENABLE_RESET               0x01
 204 #define REGB_STOP_CLOCK                 0x10
 205
 206 #define HOST_INT_STATUS         0x1A
 207 #define SB_INT_PENDING          0x01
 208 #define MPU401_INT_PENDING      0x02
 209 #define ASSP_INT_PENDING        0x10
 210 #define RING_INT_PENDING        0x20
 211 #define HV_INT_PENDING          0x40
 212
 213 #define HARDWARE_VOL_CTRL       0x1B
 214 #define SHADOW_MIX_REG_VOICE    0x1C
 215 #define HW_VOL_COUNTER_VOICE    0x1D
 216 #define SHADOW_MIX_REG_MASTER   0x1E
 217 #define HW_VOL_COUNTER_MASTER   0x1F
 218
 219 #define CODEC_COMMAND           0x30
 220 #define CODEC_READ_B            0x80
 221
 222 #define CODEC_STATUS            0x30
 223 #define CODEC_BUSY_B            0x01
 224
 225 #define CODEC_DATA              0x32
 226
 227 #define RING_BUS_CTRL_A         0x36
 228 #define RAC_PME_ENABLE          0x0100
 229 #define RAC_SDFS_ENABLE         0x0200
 230 #define LAC_PME_ENABLE          0x0400
 231 #define LAC_SDFS_ENABLE         0x0800
 232 #define SERIAL_AC_LINK_ENABLE   0x1000
 233 #define IO_SRAM_ENABLE          0x2000
 234 #define IIS_INPUT_ENABLE        0x8000
 235
 236 #define RING_BUS_CTRL_B         0x38
 237 #define SECOND_CODEC_ID_MASK    0x0003
 238 #define SPDIF_FUNC_ENABLE       0x0010
 239 #define SECOND_AC_ENABLE        0x0020
 240 #define SB_MODULE_INTF_ENABLE   0x0040
 241 #define SSPE_ENABLE             0x0040
 242 #define M3I_DOCK_ENABLE         0x0080
 243
 244 #define SDO_OUT_DEST_CTRL       0x3A
 245 #define COMMAND_ADDR_OUT        0x0003
 246 #define PCM_LR_OUT_LOCAL        0x0000
 247 #define PCM_LR_OUT_REMOTE       0x0004
 248 #define PCM_LR_OUT_MUTE         0x0008
 249 #define PCM_LR_OUT_BOTH         0x000C
 250 #define LINE1_DAC_OUT_LOCAL     0x0000
 251 #define LINE1_DAC_OUT_REMOTE    0x0010
 252 #define LINE1_DAC_OUT_MUTE      0x0020
 253 #define LINE1_DAC_OUT_BOTH      0x0030
 254 #define PCM_CLS_OUT_LOCAL       0x0000
 255 #define PCM_CLS_OUT_REMOTE      0x0040
 256 #define PCM_CLS_OUT_MUTE        0x0080
 257 #define PCM_CLS_OUT_BOTH        0x00C0
 258 #define PCM_RLF_OUT_LOCAL       0x0000
 259 #define PCM_RLF_OUT_REMOTE      0x0100
 260 #define PCM_RLF_OUT_MUTE        0x0200
 261 #define PCM_RLF_OUT_BOTH        0x0300
 262 #define LINE2_DAC_OUT_LOCAL     0x0000
 263 #define LINE2_DAC_OUT_REMOTE    0x0400
 264 #define LINE2_DAC_OUT_MUTE      0x0800
 265 #define LINE2_DAC_OUT_BOTH      0x0C00
 266 #define HANDSET_OUT_LOCAL       0x0000
 267 #define HANDSET_OUT_REMOTE      0x1000
 268 #define HANDSET_OUT_MUTE        0x2000
 269 #define HANDSET_OUT_BOTH        0x3000
 270 #define IO_CTRL_OUT_LOCAL       0x0000
 271 #define IO_CTRL_OUT_REMOTE      0x4000
 272 #define IO_CTRL_OUT_MUTE        0x8000
 273 #define IO_CTRL_OUT_BOTH        0xC000
 274
 275 #define SDO_IN_DEST_CTRL        0x3C
 276 #define STATUS_ADDR_IN          0x0003
 277 #define PCM_LR_IN_LOCAL         0x0000
 278 #define PCM_LR_IN_REMOTE        0x0004
 279 #define PCM_LR_RESERVED         0x0008
 280 #define PCM_LR_IN_BOTH          0x000C
 281 #define LINE1_ADC_IN_LOCAL      0x0000
 282 #define LINE1_ADC_IN_REMOTE     0x0010
 283 #define LINE1_ADC_IN_MUTE       0x0020
 284 #define MIC_ADC_IN_LOCAL        0x0000
 285 #define MIC_ADC_IN_REMOTE       0x0040
 286 #define MIC_ADC_IN_MUTE         0x0080
 287 #define LINE2_DAC_IN_LOCAL      0x0000
 288 #define LINE2_DAC_IN_REMOTE     0x0400
 289 #define LINE2_DAC_IN_MUTE       0x0800
 290 #define HANDSET_IN_LOCAL        0x0000
 291 #define HANDSET_IN_REMOTE       0x1000
 292 #define HANDSET_IN_MUTE         0x2000
 293 #define IO_STATUS_IN_LOCAL      0x0000
 294 #define IO_STATUS_IN_REMOTE     0x4000
 295
 296 #define SPDIF_IN_CTRL           0x3E
 297 #define SPDIF_IN_ENABLE         0x0001
 298
 299 #define GPIO_DATA               0x60
 300 #define GPIO_DATA_MASK          0x0FFF
 301 #define GPIO_HV_STATUS          0x3000
 302 #define GPIO_PME_STATUS         0x4000
 303
 304 #define GPIO_MASK               0x64
 305 #define GPIO_DIRECTION          0x68
 306 #define GPO_PRIMARY_AC97        0x0001
 307 #define GPI_LINEOUT_SENSE       0x0004
 308 #define GPO_SECONDARY_AC97      0x0008
 309 #define GPI_VOL_DOWN            0x0010
 310 #define GPI_VOL_UP              0x0020
 311 #define GPI_IIS_CLK             0x0040
 312 #define GPI_IIS_LRCLK           0x0080
 313 #define GPI_IIS_DATA            0x0100
 314 #define GPI_DOCKING_STATUS      0x0100
 315 #define GPI_HEADPHONE_SENSE     0x0200
 316 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 317
 318 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 319 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 320
 321 /* M3 */
 322 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 323
 324 #define ASSP_INDEX_PORT         0x80
 325 #define ASSP_MEMORY_PORT        0x82
 326 #define ASSP_DATA_PORT          0x84
 327
 328 #define MPU401_DATA_PORT        0x98
 329 #define MPU401_STATUS_PORT      0x99
 330
 331 #define CLK_MULT_DATA_PORT      0x9C
 332
 333 #define ASSP_CONTROL_A          0xA2
 334 #define ASSP_0_WS_ENABLE        0x01
 335 #define ASSP_CTRL_A_RESERVED1   0x02
 336 #define ASSP_CTRL_A_RESERVED2   0x04
 337 #define ASSP_CLK_49MHZ_SELECT   0x08
 338 #define FAST_PLU_ENABLE         0x10
 339 #define ASSP_CTRL_A_RESERVED3   0x20
 340 #define DSP_CLK_36MHZ_SELECT    0x40
 341
 342 #define ASSP_CONTROL_B          0xA4
 343 #define RESET_ASSP              0x00
 344 #define RUN_ASSP                0x01
 345 #define ENABLE_ASSP_CLOCK       0x00
 346 #define STOP_ASSP_CLOCK         0x10
 347 #define RESET_TOGGLE            0x40
 348
 349 #define ASSP_CONTROL_C          0xA6
 350 #define ASSP_HOST_INT_ENABLE    0x01
 351 #define FM_ADDR_REMAP_DISABLE   0x02
 352 #define HOST_WRITE_PORT_ENABLE  0x08
 353
 354 #define ASSP_HOST_INT_STATUS    0xAC
 355 #define DSP2HOST_REQ_PIORECORD  0x01
 356 #define DSP2HOST_REQ_I2SRATE    0x02
 357 #define DSP2HOST_REQ_TIMER      0x04
 358
 359 /* AC97 registers */
 360 /* XXX fix this crap up */
 361 /*#define AC97_RESET              0x00*/
 362
 363 #define AC97_VOL_MUTE_B         0x8000
 364 #define AC97_VOL_M              0x1F
 365 #define AC97_LEFT_VOL_S         8
 366
 367 #define AC97_MASTER_VOL         0x02
 368 #define AC97_LINE_LEVEL_VOL     0x04
 369 #define AC97_MASTER_MONO_VOL    0x06
 370 #define AC97_PC_BEEP_VOL        0x0A
 371 #define AC97_PC_BEEP_VOL_M      0x0F
 372 #define AC97_SROUND_MASTER_VOL  0x38
 373 #define AC97_PC_BEEP_VOL_S      1
 374
 375 /*#define AC97_PHONE_VOL          0x0C
 376 #define AC97_MIC_VOL            0x0E*/
 377 #define AC97_MIC_20DB_ENABLE    0x40
 378
 379 /*#define AC97_LINEIN_VOL         0x10
 380 #define AC97_CD_VOL             0x12
 381 #define AC97_VIDEO_VOL          0x14
 382 #define AC97_AUX_VOL            0x16*/
 383 #define AC97_PCM_OUT_VOL        0x18
 384 /*#define AC97_RECORD_SELECT      0x1A*/
 385 #define AC97_RECORD_MIC         0x00
 386 #define AC97_RECORD_CD          0x01
 387 #define AC97_RECORD_VIDEO       0x02
 388 #define AC97_RECORD_AUX         0x03
 389 #define AC97_RECORD_MONO_MUX    0x02
 390 #define AC97_RECORD_DIGITAL     0x03
 391 #define AC97_RECORD_LINE        0x04
 392 #define AC97_RECORD_STEREO      0x05
 393 #define AC97_RECORD_MONO        0x06
 394 #define AC97_RECORD_PHONE       0x07
 395
 396 /*#define AC97_RECORD_GAIN        0x1C*/
 397 #define AC97_RECORD_VOL_M       0x0F
 398
 399 /*#define AC97_GENERAL_PURPOSE    0x20*/
 400 #define AC97_POWER_DOWN_CTRL    0x26
 401 #define AC97_ADC_READY          0x0001
 402 #define AC97_DAC_READY          0x0002
 403 #define AC97_ANALOG_READY       0x0004
 404 #define AC97_VREF_ON            0x0008
 405 #define AC97_PR0                0x0100
 406 #define AC97_PR1                0x0200
 407 #define AC97_PR2                0x0400
 408 #define AC97_PR3                0x0800
 409 #define AC97_PR4                0x1000
 410
 411 #define AC97_RESERVED1          0x28
 412
 413 #define AC97_VENDOR_TEST        0x5A
 414
 415 #define AC97_CLOCK_DELAY        0x5C
 416 #define AC97_LINEOUT_MUX_SEL    0x0001
 417 #define AC97_MONO_MUX_SEL       0x0002
 418 #define AC97_CLOCK_DELAY_SEL    0x1F
 419 #define AC97_DAC_CDS_SHIFT      6
 420 #define AC97_ADC_CDS_SHIFT      11
 421
 422 #define AC97_MULTI_CHANNEL_SEL  0x74
 423
 424 /*#define AC97_VENDOR_ID1         0x7C
 425 #define AC97_VENDOR_ID2         0x7E*/
 426
 427 /*
 428  * ASSP control regs
 429  */
 430 #define DSP_PORT_TIMER_COUNT    0x06
 431
 432 #define DSP_PORT_MEMORY_INDEX   0x80
 433
 434 #define DSP_PORT_MEMORY_TYPE    0x82
 435 #define MEMTYPE_INTERNAL_CODE   0x0002
 436 #define MEMTYPE_INTERNAL_DATA   0x0003
 437 #define MEMTYPE_MASK            0x0003
 438
 439 #define DSP_PORT_MEMORY_DATA    0x84
 440
 441 #define DSP_PORT_CONTROL_REG_A  0xA2
 442 #define DSP_PORT_CONTROL_REG_B  0xA4
 443 #define DSP_PORT_CONTROL_REG_C  0xA6
 444
 445 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 446 #define REV_A_CODE_MEMORY_END           0x0FFF
 447 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 448 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 449
 450 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 451 #define REV_B_CODE_MEMORY_END           0x0BFF
 452 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 453 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 454
 455 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 456 #define REV_A_DATA_MEMORY_END           0x2FFF
 457 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 458 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 459
 460 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 461 #define REV_B_DATA_MEMORY_END           0x2BFF
 462 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 463 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 464
 465
 466 #define NUM_UNITS_KERNEL_CODE          16
 467 #define NUM_UNITS_KERNEL_DATA           2
 468
 469 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 470 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 471
 472 /*
 473  * Kernel data layout
 474  */
 475
 476 #define DP_SHIFT_COUNT                  7
 477
 478 #define KDATA_BASE_ADDR                 0x1000
 479 #define KDATA_BASE_ADDR2                0x1080
 480
 481 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 482 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 483 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 484 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 485 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 486 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 487 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 488 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 489 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 490
 491 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 492 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 493
 494 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 495 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 496 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 497 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 498 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 499 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 500 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 501 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 502 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 503 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 504
 505 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 506 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 507
 508 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 509 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 510
 511 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 512 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 513
 514 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 515 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 516 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 517
 518 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 519 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 520 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 521 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 522 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 523
 524 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 525 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 526 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 527
 528 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 529 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 530 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 531
 532 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 533 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 534 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 535 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 536 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 537 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 538 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 539 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 540 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 541 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 542
 543 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 544 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 545 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 546
 547 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 548 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 549
 550 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 551 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 552 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 553
 554 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 555 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 556 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 557 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 558 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 559 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 560
 561 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 562 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 563 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 564 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 565 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 566 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 567
 568 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 569 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 570 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 571 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 572 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 573 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 574
 575 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 576 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 577 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 578 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 579
 580 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 581 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 582
 583 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 584 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 585
 586 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 587 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 588 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 589 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 590 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 591
 592 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 593 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 594
 595 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 596 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 597 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 598
 599 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 600 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 601
 602 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 603
 604 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 605 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 606 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 607 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 608 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 609 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 610 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 611 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 612 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 613 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 614 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 615 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 616
 617 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 618 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 619 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 620 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 621
 622 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 623 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 624
 625 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 626 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 627 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 628 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 629
 630 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 631 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 632 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 633 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 634 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 635
 636 /*
 637  * second 'segment' (?) reserved for mixer
 638  * buffers..
 639  */
 640
 641 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 642 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 643 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 644 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 645 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 646 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 647 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 648 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 649 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 650 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 651 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 652 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 653 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 654 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 655 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 656 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 657
 658 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 659 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 660 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 661 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 662 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 663 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 664 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 665 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 666 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 667 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 668 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 669
 670 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 671 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 672 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 673 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 674 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 675 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 676
 677 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 678 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 679 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 680 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 681
 682 /*
 683  * client data area offsets
 684  */
 685 #define CDATA_INSTANCE_READY            0x00
 686
 687 #define CDATA_HOST_SRC_ADDRL            0x01
 688 #define CDATA_HOST_SRC_ADDRH            0x02
 689 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 690 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 691 #define CDATA_HOST_SRC_CURRENTL         0x05
 692 #define CDATA_HOST_SRC_CURRENTH         0x06
 693
 694 #define CDATA_IN_BUF_CONNECT            0x07
 695 #define CDATA_OUT_BUF_CONNECT           0x08
 696
 697 #define CDATA_IN_BUF_BEGIN              0x09
 698 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 699 #define CDATA_IN_BUF_HEAD               0x0B
 700 #define CDATA_IN_BUF_TAIL               0x0C
 701 #define CDATA_OUT_BUF_BEGIN             0x0D
 702 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 703 #define CDATA_OUT_BUF_HEAD              0x0F
 704 #define CDATA_OUT_BUF_TAIL              0x10
 705
 706 #define CDATA_DMA_CONTROL               0x11
 707 #define CDATA_RESERVED                  0x12
 708
 709 #define CDATA_FREQUENCY                 0x13
 710 #define CDATA_LEFT_VOLUME               0x14
 711 #define CDATA_RIGHT_VOLUME              0x15
 712 #define CDATA_LEFT_SUR_VOL              0x16
 713 #define CDATA_RIGHT_SUR_VOL             0x17
 714
 715 #define CDATA_HEADER_LEN                0x18
 716
 717 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 718 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 719 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 720 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 721 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 722 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 723 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 724 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 725
 726 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 727 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 728 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 729 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 730 #define MINISRC_BIQUAD_STAGE    2
 731 #define MINISRC_COEF_LOC          0x175
 732
 733 #define DMACONTROL_BLOCK_MASK           0x000F
 734 #define  DMAC_BLOCK0_SELECTOR           0x0000
 735 #define  DMAC_BLOCK1_SELECTOR           0x0001
 736 #define  DMAC_BLOCK2_SELECTOR           0x0002
 737 #define  DMAC_BLOCK3_SELECTOR           0x0003
 738 #define  DMAC_BLOCK4_SELECTOR           0x0004
 739 #define  DMAC_BLOCK5_SELECTOR           0x0005
 740 #define  DMAC_BLOCK6_SELECTOR           0x0006
 741 #define  DMAC_BLOCK7_SELECTOR           0x0007
 742 #define  DMAC_BLOCK8_SELECTOR           0x0008
 743 #define  DMAC_BLOCK9_SELECTOR           0x0009
 744 #define  DMAC_BLOCKA_SELECTOR           0x000A
 745 #define  DMAC_BLOCKB_SELECTOR           0x000B
 746 #define  DMAC_BLOCKC_SELECTOR           0x000C
 747 #define  DMAC_BLOCKD_SELECTOR           0x000D
 748 #define  DMAC_BLOCKE_SELECTOR           0x000E
 749 #define  DMAC_BLOCKF_SELECTOR           0x000F
 750 #define DMACONTROL_PAGE_MASK            0x00F0
 751 #define  DMAC_PAGE0_SELECTOR            0x0030
 752 #define  DMAC_PAGE1_SELECTOR            0x0020
 753 #define  DMAC_PAGE2_SELECTOR            0x0010
 754 #define  DMAC_PAGE3_SELECTOR            0x0000
 755 #define DMACONTROL_AUTOREPEAT           0x1000
 756 #define DMACONTROL_STOPPED              0x2000
 757 #define DMACONTROL_DIRECTION            0x0100
 758
 759 /*
 760  * an arbitrary volume we set the internal
 761  * volume settings to so that the ac97 volume
 762  * range is a little less insane.  0x7fff is
 763  * max.
 764  */
 765 #define ARB_VOLUME ( 0x6800 )
 766
 767 /*
 768  */
 769
 770 typedef struct snd_m3_dma m3_dma_t;
 771 typedef struct snd_m3 m3_t;
 772
 773 /* quirk lists */
 774 struct m3_quirk {
 775         const char *name;       /* device name */
 776         u16 vendor, device;     /* subsystem ids */
 777         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 778         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 779                                    (e.g. for IrDA on Dell Inspirons) */
 780 };
 781
 782 struct m3_list {
 783         int curlen;
 784         int mem_addr;
 785         int max;
 786 };
 787
 788 struct snd_m3_dma {
 789
 790         int number;
 791         m3_t *chip;
 792         snd_pcm_substream_t *substream;
 793
 794         struct assp_instance {
 795                 unsigned short code, data;
 796         } inst;
 797
 798         int running;
 799         int opened;
 800
 801         unsigned long buffer_addr;
 802         int dma_size;
 803         int period_size;
 804         unsigned int hwptr;
 805         int count;
 806
 807         int index[3];
 808         struct m3_list *index_list[3];
 809
 810         int in_lists;
 811
 812         struct list_head list;
 813
 814 };
 815
 816 struct snd_m3 {
 817
 818         snd_card_t *card;
 819
 820         unsigned long iobase;
 821
 822         int irq;
 823         unsigned int allegro_flag : 1;
 824
 825         ac97_t *ac97;
 826
 827         snd_pcm_t *pcm;
 828
 829         struct pci_dev *pci;
 830         struct m3_quirk *quirk;
 831
 832         int dacs_active;
 833         int timer_users;
 834
 835         struct m3_list  msrc_list;
 836         struct m3_list  mixer_list;
 837         struct m3_list  adc1_list;
 838         struct m3_list  dma_list;
 839
 840         /* for storing reset state..*/
 841         u8 reset_state;
 842
 843         int external_amp;
 844         int amp_gpio;
 845
 846         /* midi */
 847         snd_rawmidi_t *rmidi;
 848
 849         /* pcm streams */
 850         int num_substreams;
 851         m3_dma_t *substreams;
 852
 853         spinlock_t reg_lock;
 854         spinlock_t ac97_lock;
 855
 856         snd_kcontrol_t *master_switch;
 857         snd_kcontrol_t *master_volume;
 858         struct tasklet_struct hwvol_tq;
 859
 860 #ifdef CONFIG_PM
 861         u16 *suspend_mem;
 862 #endif
 863 };
 864
 865 /*
 866  * pci ids
 867  */
 868
 869 #ifndef PCI_VENDOR_ID_ESS
 870 #define PCI_VENDOR_ID_ESS         0x125D
 871 #endif
 872 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
 873 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 874 #endif
 875 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
 876 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
 877 #endif
 878 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
 879 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE  0x1990
 880 #endif
 881 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
 882 #define PCI_DEVICE_ID_ESS_CANYON3D_2    0x1992
 883 #endif
 884 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
 885 #define PCI_DEVICE_ID_ESS_MAESTRO3      0x1998
 886 #endif
 887 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
 888 #define PCI_DEVICE_ID_ESS_MAESTRO3_1    0x1999
 889 #endif
 890 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
 891 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW   0x199a
 892 #endif
 893 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
 894 #define PCI_DEVICE_ID_ESS_MAESTRO3_2    0x199b
 895 #endif
 896
 897 static struct pci_device_id snd_m3_ids[] = {
 898         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 899          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 900         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 901          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 902         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 903          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 904         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 905          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 906         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 907          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 908         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 909          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 910         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 911          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 912         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 913          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 914         {0,},
 915 };
 916
 917 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 918
 919 static struct m3_quirk m3_quirk_list[] = {
 920         /* panasonic CF-28 "toughbook" */
 921         {
 922                 .name = "Panasonic CF-28",
 923                 .vendor = 0x10f7,
 924                 .device = 0x833e,
 925                 .amp_gpio = 0x0d,
 926         },
 927         /* panasonic CF-72 "toughbook" */
 928         {
 929                 .name = "Panasonic CF-72",
 930                 .vendor = 0x10f7,
 931                 .device = 0x833d,
 932                 .amp_gpio = 0x0d,
 933         },
 934         /* Dell Inspiron 4000 */
 935         {
 936                 .name = "Dell Inspiron 4000",
 937                 .vendor = 0x1028,
 938                 .device = 0x00b0,
 939                 .amp_gpio = -1,
 940                 .irda_workaround = 1,
 941         },
 942         /* Dell Inspiron 8000 */
 943         {
 944                 .name = "Dell Inspiron 8000",
 945                 .vendor = 0x1028,
 946                 .device = 0x00a4,
 947                 .amp_gpio = -1,
 948                 .irda_workaround = 1,
 949         },
 950         /* Dell Inspiron 8100 */
 951         {
 952                 .name = "Dell Inspiron 8100",
 953                 .vendor = 0x1028,
 954                 .device = 0x00e6,
 955                 .amp_gpio = -1,
 956                 .irda_workaround = 1,
 957         },
 958         /* NEC LM800J/7 */
 959         {
 960                 .name = "NEC LM800J/7",
 961                 .vendor = 0x1033,
 962                 .device = 0x80f1,
 963                 .amp_gpio = 0x03,
 964         },
 965         /* LEGEND ZhaoYang 3100CF */
 966         {
 967                 .name = "LEGEND ZhaoYang 3100CF",
 968                 .vendor = 0x1509,
 969                 .device = 0x1740,
 970                 .amp_gpio = 0x03,
 971         },
 972         /* END */
 973         { NULL }
 974 };
 975
 976
 977 /*
 978  * lowlevel functions
 979  */
 980
 981 #define big_mdelay(msec) do {\
 982         set_current_state(TASK_UNINTERRUPTIBLE);\
 983         schedule_timeout(((msec) * HZ) / 1000);\
 984 } while (0)
 985
 986 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
 987 {
 988         outw(value, chip->iobase + reg);
 989 }
 990
 991 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
 992 {
 993         return inw(chip->iobase + reg);
 994 }
 995
 996 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
 997 {
 998         outb(value, chip->iobase + reg);
 999 }
1000
1001 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
1002 {
1003         return inb(chip->iobase + reg);
1004 }
1005
1006 /*
1007  * access 16bit words to the code or data regions of the dsp's memory.
1008  * index addresses 16bit words.
1009  */
1010 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1011 {
1012         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1013         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1014         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1015 }
1016
1017 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1018 {
1019         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1020         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1021         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1022 }
1023
1024 static void snd_m3_assp_halt(m3_t *chip)
1025 {
1026         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1027         big_mdelay(10);
1028         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1029 }
1030
1031 static void snd_m3_assp_continue(m3_t *chip)
1032 {
1033         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1034 }
1035
1036
1037 /*
1038  * This makes me sad. the maestro3 has lists
1039  * internally that must be packed.. 0 terminates,
1040  * apparently, or maybe all unused entries have
1041  * to be 0, the lists have static lengths set
1042  * by the binary code images.
1043  */
1044
1045 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1046 {
1047         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1048                           list->mem_addr + list->curlen,
1049                           val);
1050         return list->curlen++;
1051 }
1052
1053 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1054 {
1055         u16  val;
1056         int lastindex = list->curlen - 1;
1057
1058         if (index != lastindex) {
1059                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1060                                        list->mem_addr + lastindex);
1061                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1062                                   list->mem_addr + index,
1063                                   val);
1064         }
1065
1066         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1067                           list->mem_addr + lastindex,
1068                           0);
1069
1070         list->curlen--;
1071 }
1072
1073 static void snd_m3_inc_timer_users(m3_t *chip)
1074 {
1075         chip->timer_users++;
1076         if (chip->timer_users != 1)
1077                 return;
1078
1079         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1080                           KDATA_TIMER_COUNT_RELOAD,
1081                           240);
1082
1083         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084                           KDATA_TIMER_COUNT_CURRENT,
1085                           240);
1086
1087         snd_m3_outw(chip,
1088                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1089                     HOST_INT_CTRL);
1090 }
1091
1092 static void snd_m3_dec_timer_users(m3_t *chip)
1093 {
1094         chip->timer_users--;
1095         if (chip->timer_users > 0)
1096                 return;
1097
1098         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1099                           KDATA_TIMER_COUNT_RELOAD,
1100                           0);
1101
1102         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1103                           KDATA_TIMER_COUNT_CURRENT,
1104                           0);
1105
1106         snd_m3_outw(chip,
1107                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1108                     HOST_INT_CTRL);
1109 }
1110
1111 /*
1112  * start/stop
1113  */
1114
1115 /* spinlock held! */
1116 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1117 {
1118         if (! s || ! subs)
1119                 return -EINVAL;
1120
1121         snd_m3_inc_timer_users(chip);
1122         switch (subs->stream) {
1123         case SNDRV_PCM_STREAM_PLAYBACK:
1124                 chip->dacs_active++;
1125                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1126                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1127                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1128                                   KDATA_MIXER_TASK_NUMBER,
1129                                   chip->dacs_active);
1130                 break;
1131         case SNDRV_PCM_STREAM_CAPTURE:
1132                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1133                                   KDATA_ADC1_REQUEST, 1);
1134                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1136                 break;
1137         }
1138         return 0;
1139 }
1140
1141 /* spinlock held! */
1142 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1143 {
1144         if (! s || ! subs)
1145                 return -EINVAL;
1146
1147         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1148                           s->inst.data + CDATA_INSTANCE_READY, 0);
1149         snd_m3_dec_timer_users(chip);
1150         switch (subs->stream) {
1151         case SNDRV_PCM_STREAM_PLAYBACK:
1152                 chip->dacs_active--;
1153                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1154                                   KDATA_MIXER_TASK_NUMBER,
1155                                   chip->dacs_active);
1156                 break;
1157         case SNDRV_PCM_STREAM_CAPTURE:
1158                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1159                                   KDATA_ADC1_REQUEST, 0);
1160                 break;
1161         }
1162         return 0;
1163 }
1164
1165 static int
1166 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1167 {
1168         m3_t *chip = snd_pcm_substream_chip(subs);
1169         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1170         int err = -EINVAL;
1171
1172         snd_assert(s != NULL, return -ENXIO);
1173
1174         spin_lock(&chip->reg_lock);
1175         switch (cmd) {
1176         case SNDRV_PCM_TRIGGER_START:
1177         case SNDRV_PCM_TRIGGER_RESUME:
1178                 if (s->running)
1179                         err = -EBUSY;
1180                 else {
1181                         s->running = 1;
1182                         err = snd_m3_pcm_start(chip, s, subs);
1183                 }
1184                 break;
1185         case SNDRV_PCM_TRIGGER_STOP:
1186         case SNDRV_PCM_TRIGGER_SUSPEND:
1187                 if (! s->running)
1188                         err = 0; /* should return error? */
1189                 else {
1190                         s->running = 0;
1191                         err = snd_m3_pcm_stop(chip, s, subs);
1192                 }
1193                 break;
1194         }
1195         spin_unlock(&chip->reg_lock);
1196         return err;
1197 }
1198
1199 /*
1200  * setup
1201  */
1202 static void
1203 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1204 {
1205         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1206         snd_pcm_runtime_t *runtime = subs->runtime;
1207
1208         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1209                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1210                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1211         } else {
1212                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1213                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1214         }
1215         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1216         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1217
1218         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1219         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1220         s->hwptr = 0;
1221         s->count = 0;
1222
1223 #define LO(x) ((x) & 0xffff)
1224 #define HI(x) LO((x) >> 16)
1225
1226         /* host dma buffer pointers */
1227         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1228                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1229                           LO(s->buffer_addr));
1230
1231         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1232                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1233                           HI(s->buffer_addr));
1234
1235         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1236                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1237                           LO(s->buffer_addr + s->dma_size));
1238
1239         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1240                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1241                           HI(s->buffer_addr + s->dma_size));
1242
1243         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1244                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1245                           LO(s->buffer_addr));
1246
1247         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1248                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1249                           HI(s->buffer_addr));
1250 #undef LO
1251 #undef HI
1252
1253         /* dsp buffers */
1254
1255         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1256                           s->inst.data + CDATA_IN_BUF_BEGIN,
1257                           dsp_in_buffer);
1258
1259         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1260                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1261                           dsp_in_buffer + (dsp_in_size / 2));
1262
1263         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1264                           s->inst.data + CDATA_IN_BUF_HEAD,
1265                           dsp_in_buffer);
1266
1267         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1268                           s->inst.data + CDATA_IN_BUF_TAIL,
1269                           dsp_in_buffer);
1270
1271         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1272                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1273                           dsp_out_buffer);
1274
1275         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1276                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1277                           dsp_out_buffer + (dsp_out_size / 2));
1278
1279         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1280                           s->inst.data + CDATA_OUT_BUF_HEAD,
1281                           dsp_out_buffer);
1282
1283         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1284                           s->inst.data + CDATA_OUT_BUF_TAIL,
1285                           dsp_out_buffer);
1286 }
1287
1288 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1289 {
1290         u32 freq;
1291
1292         /*
1293          * put us in the lists if we're not already there
1294          */
1295         if (! s->in_lists) {
1296                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1297                                               s->inst.data >> DP_SHIFT_COUNT);
1298                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1299                                               s->inst.data >> DP_SHIFT_COUNT);
1300                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1301                                               s->inst.data >> DP_SHIFT_COUNT);
1302                 s->in_lists = 1;
1303         }
1304
1305         /* write to 'mono' word */
1306         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1307                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1308                           runtime->channels == 2 ? 0 : 1);
1309         /* write to '8bit' word */
1310         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1311                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1312                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1313
1314         /* set up dac/adc rate */
1315         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1316         if (freq)
1317                 freq--;
1318
1319         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1320                           s->inst.data + CDATA_FREQUENCY,
1321                           freq);
1322 }
1323
1324
1325 static struct play_vals {
1326         u16 addr, val;
1327 } pv[] = {
1328         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1329         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1330         {SRC3_DIRECTION_OFFSET, 0} ,
1331         /* +1, +2 are stereo/16 bit */
1332         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1333         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1334         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1335         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1336         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1337         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1338         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1339         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1340         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1341         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1342         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1343         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1344         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1345         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1346         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1347         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1348         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1349 };
1350
1351
1352 /* the mode passed should be already shifted and masked */
1353 static void
1354 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1355 {
1356         unsigned int i;
1357
1358         /*
1359          * some per client initializers
1360          */
1361
1362         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1363                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1364                           s->inst.data + 40 + 8);
1365
1366         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1367                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1368                           s->inst.code + MINISRC_COEF_LOC);
1369
1370         /* enable or disable low pass filter? */
1371         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1372                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1373                           subs->runtime->rate > 45000 ? 0xff : 0);
1374
1375         /* tell it which way dma is going? */
1376         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1377                           s->inst.data + CDATA_DMA_CONTROL,
1378                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1379
1380         /*
1381          * set an armload of static initializers
1382          */
1383         for (i = 0; i < ARRAY_SIZE(pv); i++)
1384                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1385                                   s->inst.data + pv[i].addr, pv[i].val);
1386 }
1387
1388 /*
1389  *    Native record driver
1390  */
1391 static struct rec_vals {
1392         u16 addr, val;
1393 } rv[] = {
1394         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1395         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1396         {SRC3_DIRECTION_OFFSET, 1} ,
1397         /* +1, +2 are stereo/16 bit */
1398         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1399         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1400         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1401         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1402         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1403         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1404         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1405         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1406         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1407         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1408         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1409         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1410         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1411         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1412         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1413         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1414         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1415         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1416         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1417 };
1418
1419 static void
1420 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1421 {
1422         unsigned int i;
1423
1424         /*
1425          * some per client initializers
1426          */
1427
1428         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1429                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1430                           s->inst.data + 40 + 8);
1431
1432         /* tell it which way dma is going? */
1433         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1434                           s->inst.data + CDATA_DMA_CONTROL,
1435                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1436                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1437
1438         /*
1439          * set an armload of static initializers
1440          */
1441         for (i = 0; i < ARRAY_SIZE(rv); i++)
1442                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1443                                   s->inst.data + rv[i].addr, rv[i].val);
1444 }
1445
1446 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1447                                 snd_pcm_hw_params_t * hw_params)
1448 {
1449         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1450         int err;
1451
1452         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1453                 return err;
1454         /* set buffer address */
1455         s->buffer_addr = substream->runtime->dma_addr;
1456         if (s->buffer_addr & 0x3) {
1457                 snd_printk("oh my, not aligned\n");
1458                 s->buffer_addr = s->buffer_addr & ~0x3;
1459         }
1460         return 0;
1461 }
1462
1463 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1464 {
1465         m3_dma_t *s;
1466
1467         if (substream->runtime->private_data == NULL)
1468                 return 0;
1469         s = (m3_dma_t*) substream->runtime->private_data;
1470         snd_pcm_lib_free_pages(substream);
1471         s->buffer_addr = 0;
1472         return 0;
1473 }
1474
1475 static int
1476 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1477 {
1478         m3_t *chip = snd_pcm_substream_chip(subs);
1479         snd_pcm_runtime_t *runtime = subs->runtime;
1480         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1481
1482         snd_assert(s != NULL, return -ENXIO);
1483
1484         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1485             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1486                 return -EINVAL;
1487         if (runtime->rate > 48000 ||
1488             runtime->rate < 8000)
1489                 return -EINVAL;
1490
1491         spin_lock_irq(&chip->reg_lock);
1492
1493         snd_m3_pcm_setup1(chip, s, subs);
1494
1495         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1496                 snd_m3_playback_setup(chip, s, subs);
1497         else
1498                 snd_m3_capture_setup(chip, s, subs);
1499
1500         snd_m3_pcm_setup2(chip, s, runtime);
1501
1502         spin_unlock_irq(&chip->reg_lock);
1503
1504         return 0;
1505 }
1506
1507 /*
1508  * get current pointer
1509  */
1510 static unsigned int
1511 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1512 {
1513         u16 hi = 0, lo = 0;
1514         int retry = 10;
1515         u32 addr;
1516
1517         /*
1518          * try and get a valid answer
1519          */
1520         while (retry--) {
1521                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1522                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1523
1524                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1525                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1526
1527                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1528                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1529                         break;
1530         }
1531         addr = lo | ((u32)hi<<16);
1532         return (unsigned int)(addr - s->buffer_addr);
1533 }
1534
1535 static snd_pcm_uframes_t
1536 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1537 {
1538         m3_t *chip = snd_pcm_substream_chip(subs);
1539         unsigned int ptr;
1540         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1541         snd_assert(s != NULL, return 0);
1542
1543         spin_lock(&chip->reg_lock);
1544         ptr = snd_m3_get_pointer(chip, s, subs);
1545         spin_unlock(&chip->reg_lock);
1546         return bytes_to_frames(subs->runtime, ptr);
1547 }
1548
1549
1550 /* update pointer */
1551 /* spinlock held! */
1552 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1553 {
1554         snd_pcm_substream_t *subs = s->substream;
1555         unsigned int hwptr;
1556         int diff;
1557
1558         if (! s->running)
1559                 return;
1560
1561         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1562         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1563         s->hwptr = hwptr;
1564         s->count += diff;
1565         if (s->count >= (signed)s->period_size) {
1566                 s->count %= s->period_size;
1567                 spin_unlock(&chip->reg_lock);
1568                 snd_pcm_period_elapsed(subs);
1569                 spin_lock(&chip->reg_lock);
1570         }
1571 }
1572
1573 static void snd_m3_update_hw_volume(unsigned long private_data)
1574 {
1575         m3_t *chip = (m3_t *) private_data;
1576         int x, val;
1577         unsigned long flags;
1578
1579         /* Figure out which volume control button was pushed,
1580            based on differences from the default register
1581            values. */
1582         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1583
1584         /* Reset the volume control registers. */
1585         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1586         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1587         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1588         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1589
1590         if (!chip->master_switch || !chip->master_volume)
1591                 return;
1592
1593         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1594         spin_lock_irqsave(&chip->ac97_lock, flags);
1595
1596         val = chip->ac97->regs[AC97_MASTER_VOL];
1597         switch (x) {
1598         case 0x88:
1599                 /* mute */
1600                 val ^= 0x8000;
1601                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1602                 outw(val, chip->iobase + CODEC_DATA);
1603                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1604                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1605                                &chip->master_switch->id);
1606                 break;
1607         case 0xaa:
1608                 /* volume up */
1609                 if ((val & 0x7f) > 0)
1610                         val--;
1611                 if ((val & 0x7f00) > 0)
1612                         val -= 0x0100;
1613                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1614                 outw(val, chip->iobase + CODEC_DATA);
1615                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1616                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1617                                &chip->master_volume->id);
1618                 break;
1619         case 0x66:
1620                 /* volume down */
1621                 if ((val & 0x7f) < 0x1f)
1622                         val++;
1623                 if ((val & 0x7f00) < 0x1f00)
1624                         val += 0x0100;
1625                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1626                 outw(val, chip->iobase + CODEC_DATA);
1627                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1628                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1629                                &chip->master_volume->id);
1630                 break;
1631         }
1632         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1633 }
1634
1635 static irqreturn_t
1636 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1637 {
1638         m3_t *chip = dev_id;
1639         u8 status;
1640         int i;
1641
1642         status = inb(chip->iobase + HOST_INT_STATUS);
1643
1644         if (status == 0xff)
1645                 return IRQ_NONE;
1646
1647         if (status & HV_INT_PENDING)
1648                 tasklet_hi_schedule(&chip->hwvol_tq);
1649
1650         /*
1651          * ack an assp int if its running
1652          * and has an int pending
1653          */
1654         if (status & ASSP_INT_PENDING) {
1655                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1656                 if (!(ctl & STOP_ASSP_CLOCK)) {
1657                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1658                         if (ctl & DSP2HOST_REQ_TIMER) {
1659                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1660                                 /* update adc/dac info if it was a timer int */
1661                                 spin_lock(&chip->reg_lock);
1662                                 for (i = 0; i < chip->num_substreams; i++) {
1663                                         m3_dma_t *s = &chip->substreams[i];
1664                                         if (s->running)
1665                                                 snd_m3_update_ptr(chip, s);
1666                                 }
1667                                 spin_unlock(&chip->reg_lock);
1668                         }
1669                 }
1670         }
1671
1672 #if 0 /* TODO: not supported yet */
1673         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1674                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1675 #endif
1676
1677         /* ack ints */
1678         outb(status, chip->iobase + HOST_INT_STATUS);
1679
1680         return IRQ_HANDLED;
1681 }
1682
1683
1684 /*
1685  */
1686
1687 static snd_pcm_hardware_t snd_m3_playback =
1688 {
1689         .info =                 (SNDRV_PCM_INFO_MMAP |
1690                                  SNDRV_PCM_INFO_INTERLEAVED |
1691                                  SNDRV_PCM_INFO_MMAP_VALID |
1692                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1693                                  /*SNDRV_PCM_INFO_PAUSE |*/
1694                                  SNDRV_PCM_INFO_RESUME),
1695         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1696         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1697         .rate_min =             8000,
1698         .rate_max =             48000,
1699         .channels_min =         1,
1700         .channels_max =         2,
1701         .buffer_bytes_max =     (512*1024),
1702         .period_bytes_min =     64,
1703         .period_bytes_max =     (512*1024),
1704         .periods_min =          1,
1705         .periods_max =          1024,
1706 };
1707
1708 static snd_pcm_hardware_t snd_m3_capture =
1709 {
1710         .info =                 (SNDRV_PCM_INFO_MMAP |
1711                                  SNDRV_PCM_INFO_INTERLEAVED |
1712                                  SNDRV_PCM_INFO_MMAP_VALID |
1713                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1714                                  /*SNDRV_PCM_INFO_PAUSE |*/
1715                                  SNDRV_PCM_INFO_RESUME),
1716         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1717         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1718         .rate_min =             8000,
1719         .rate_max =             48000,
1720         .channels_min =         1,
1721         .channels_max =         2,
1722         .buffer_bytes_max =     (512*1024),
1723         .period_bytes_min =     64,
1724         .period_bytes_max =     (512*1024),
1725         .periods_min =          1,
1726         .periods_max =          1024,
1727 };
1728
1729
1730 /*
1731  */
1732
1733 static int
1734 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1735 {
1736         int i;
1737         m3_dma_t *s;
1738
1739         spin_lock_irq(&chip->reg_lock);
1740         for (i = 0; i < chip->num_substreams; i++) {
1741                 s = &chip->substreams[i];
1742                 if (! s->opened)
1743                         goto __found;
1744         }
1745         spin_unlock_irq(&chip->reg_lock);
1746         return -ENOMEM;
1747 __found:
1748         s->opened = 1;
1749         s->running = 0;
1750         spin_unlock_irq(&chip->reg_lock);
1751
1752         subs->runtime->private_data = s;
1753         s->substream = subs;
1754
1755         /* set list owners */
1756         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1757                 s->index_list[0] = &chip->mixer_list;
1758         } else
1759                 s->index_list[0] = &chip->adc1_list;
1760         s->index_list[1] = &chip->msrc_list;
1761         s->index_list[2] = &chip->dma_list;
1762
1763         return 0;
1764 }
1765
1766 static void
1767 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1768 {
1769         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1770
1771         if (s == NULL)
1772                 return; /* not opened properly */
1773
1774         spin_lock_irq(&chip->reg_lock);
1775         if (s->substream && s->running)
1776                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1777         if (s->in_lists) {
1778                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1779                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1780                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1781                 s->in_lists = 0;
1782         }
1783         s->running = 0;
1784         s->opened = 0;
1785         spin_unlock_irq(&chip->reg_lock);
1786 }
1787
1788 static int
1789 snd_m3_playback_open(snd_pcm_substream_t *subs)
1790 {
1791         m3_t *chip = snd_pcm_substream_chip(subs);
1792         snd_pcm_runtime_t *runtime = subs->runtime;
1793         int err;
1794
1795         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1796                 return err;
1797
1798         runtime->hw = snd_m3_playback;
1799         snd_pcm_set_sync(subs);
1800
1801         return 0;
1802 }
1803
1804 static int
1805 snd_m3_playback_close(snd_pcm_substream_t *subs)
1806 {
1807         m3_t *chip = snd_pcm_substream_chip(subs);
1808
1809         snd_m3_substream_close(chip, subs);
1810         return 0;
1811 }
1812
1813 static int
1814 snd_m3_capture_open(snd_pcm_substream_t *subs)
1815 {
1816         m3_t *chip = snd_pcm_substream_chip(subs);
1817         snd_pcm_runtime_t *runtime = subs->runtime;
1818         int err;
1819
1820         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1821                 return err;
1822
1823         runtime->hw = snd_m3_capture;
1824         snd_pcm_set_sync(subs);
1825
1826         return 0;
1827 }
1828
1829 static int
1830 snd_m3_capture_close(snd_pcm_substream_t *subs)
1831 {
1832         m3_t *chip = snd_pcm_substream_chip(subs);
1833
1834         snd_m3_substream_close(chip, subs);
1835         return 0;
1836 }
1837
1838 /*
1839  * create pcm instance
1840  */
1841
1842 static snd_pcm_ops_t snd_m3_playback_ops = {
1843         .open =         snd_m3_playback_open,
1844         .close =        snd_m3_playback_close,
1845         .ioctl =        snd_pcm_lib_ioctl,
1846         .hw_params =    snd_m3_pcm_hw_params,
1847         .hw_free =      snd_m3_pcm_hw_free,
1848         .prepare =      snd_m3_pcm_prepare,
1849         .trigger =      snd_m3_pcm_trigger,
1850         .pointer =      snd_m3_pcm_pointer,
1851 };
1852
1853 static snd_pcm_ops_t snd_m3_capture_ops = {
1854         .open =         snd_m3_capture_open,
1855         .close =        snd_m3_capture_close,
1856         .ioctl =        snd_pcm_lib_ioctl,
1857         .hw_params =    snd_m3_pcm_hw_params,
1858         .hw_free =      snd_m3_pcm_hw_free,
1859         .prepare =      snd_m3_pcm_prepare,
1860         .trigger =      snd_m3_pcm_trigger,
1861         .pointer =      snd_m3_pcm_pointer,
1862 };
1863
1864 static int __devinit
1865 snd_m3_pcm(m3_t * chip, int device)
1866 {
1867         snd_pcm_t *pcm;
1868         int err;
1869
1870         err = snd_pcm_new(chip->card, chip->card->driver, device,
1871                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1872         if (err < 0)
1873                 return err;
1874
1875         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1876         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1877
1878         pcm->private_data = chip;
1879         pcm->info_flags = 0;
1880         strcpy(pcm->name, chip->card->driver);
1881         chip->pcm = pcm;
1882
1883         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1884                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1885
1886         return 0;
1887 }
1888
1889
1890 /*
1891  * ac97 interface
1892  */
1893
1894 /*
1895  * Wait for the ac97 serial bus to be free.
1896  * return nonzero if the bus is still busy.
1897  */
1898 static int snd_m3_ac97_wait(m3_t *chip)
1899 {
1900         int i = 10000;
1901
1902         do {
1903                 if (! (snd_m3_inb(chip, 0x30) & 1))
1904                         return 0;
1905         } while (i-- > 0);
1906
1907         snd_printk("ac97 serial bus busy\n");
1908         return 1;
1909 }
1910
1911 static unsigned short
1912 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1913 {
1914         m3_t *chip = ac97->private_data;
1915         unsigned long flags;
1916         unsigned short data;
1917
1918         if (snd_m3_ac97_wait(chip))
1919                 return 0xffff;
1920         spin_lock_irqsave(&chip->ac97_lock, flags);
1921         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1922         if (snd_m3_ac97_wait(chip))
1923                 return 0xffff;
1924         data = snd_m3_inw(chip, CODEC_DATA);
1925         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1926         return data;
1927 }
1928
1929 static void
1930 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1931 {
1932         m3_t *chip = ac97->private_data;
1933         unsigned long flags;
1934
1935         if (snd_m3_ac97_wait(chip))
1936                 return;
1937         spin_lock_irqsave(&chip->ac97_lock, flags);
1938         snd_m3_outw(chip, val, CODEC_DATA);
1939         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1940         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1941 }
1942
1943
1944 static void snd_m3_remote_codec_config(int io, int isremote)
1945 {
1946         isremote = isremote ? 1 : 0;
1947
1948         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1949              io + RING_BUS_CTRL_B);
1950         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1951              io + SDO_OUT_DEST_CTRL);
1952         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1953              io + SDO_IN_DEST_CTRL);
1954 }
1955
1956 /*
1957  * hack, returns non zero on err
1958  */
1959 static int snd_m3_try_read_vendor(m3_t *chip)
1960 {
1961         u16 ret;
1962
1963         if (snd_m3_ac97_wait(chip))
1964                 return 1;
1965
1966         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1967
1968         if (snd_m3_ac97_wait(chip))
1969                 return 1;
1970
1971         ret = snd_m3_inw(chip, 0x32);
1972
1973         return (ret == 0) || (ret == 0xffff);
1974 }
1975
1976 static void snd_m3_ac97_reset(m3_t *chip)
1977 {
1978         u16 dir;
1979         int delay1 = 0, delay2 = 0, i;
1980         int io = chip->iobase;
1981
1982         if (chip->allegro_flag) {
1983                 /*
1984                  * the onboard codec on the allegro seems
1985                  * to want to wait a very long time before
1986                  * coming back to life
1987                  */
1988                 delay1 = 50;
1989                 delay2 = 800;
1990         } else {
1991                 /* maestro3 */
1992                 delay1 = 20;
1993                 delay2 = 500;
1994         }
1995
1996         for (i = 0; i < 5; i++) {
1997                 dir = inw(io + GPIO_DIRECTION);
1998                 if (! chip->quirk || ! chip->quirk->irda_workaround)
1999                         dir |= 0x10; /* assuming pci bus master? */
2000
2001                 snd_m3_remote_codec_config(io, 0);
2002
2003                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2004                 udelay(20);
2005
2006                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2007                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2008                 outw(0, io + GPIO_DATA);
2009                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2010
2011                 set_current_state(TASK_UNINTERRUPTIBLE);
2012                 schedule_timeout((delay1 * HZ) / 1000);
2013
2014                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2015                 udelay(5);
2016                 /* ok, bring back the ac-link */
2017                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2018                 outw(~0, io + GPIO_MASK);
2019
2020                 set_current_state(TASK_UNINTERRUPTIBLE);
2021                 schedule_timeout((delay2 * HZ) / 1000);
2022
2023                 if (! snd_m3_try_read_vendor(chip))
2024                         break;
2025
2026                 delay1 += 10;
2027                 delay2 += 100;
2028
2029                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2030                            delay1, delay2);
2031         }
2032
2033 #if 0
2034         /* more gung-ho reset that doesn't
2035          * seem to work anywhere :)
2036          */
2037         tmp = inw(io + RING_BUS_CTRL_A);
2038         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2039         big_mdelay(20);
2040         outw(tmp, io + RING_BUS_CTRL_A);
2041         big_mdelay(50);
2042 #endif
2043 }
2044
2045 static int __devinit snd_m3_mixer(m3_t *chip)
2046 {
2047         ac97_bus_t *pbus;
2048         ac97_template_t ac97;
2049         snd_ctl_elem_id_t id;
2050         int err;
2051         static ac97_bus_ops_t ops = {
2052                 .write = snd_m3_ac97_write,
2053                 .read = snd_m3_ac97_read,
2054         };
2055
2056         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2057                 return err;
2058
2059         memset(&ac97, 0, sizeof(ac97));
2060         ac97.private_data = chip;
2061         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2062                 return err;
2063
2064         /* seems ac97 PCM needs initialization.. hack hack.. */
2065         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2066         set_current_state(TASK_UNINTERRUPTIBLE);
2067         schedule_timeout(HZ / 10);
2068         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2069
2070         memset(&id, 0, sizeof(id));
2071         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2072         strcpy(id.name, "Master Playback Switch");
2073         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2074         memset(&id, 0, sizeof(id));
2075         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2076         strcpy(id.name, "Master Playback Volume");
2077         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2078
2079         return 0;
2080 }
2081
2082
2083 /*
2084  * DSP Code images
2085  */
2086
2087 static u16 assp_kernel_image[] __devinitdata = {
2088     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2089     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2090     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2091     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2092     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2093     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2094     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2095     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2096     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2097     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2098     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2099     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2100     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2101     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2102     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2103     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2104     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2105     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2106     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2107     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2108     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2109     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2110     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2111     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2112     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2113     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2114     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2115     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2116     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2117     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2118     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2119     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2120     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2121     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2122     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2123     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2124     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2125     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2126     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2127     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2128     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2129     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2130     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2131     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2132     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2133     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2134     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2135     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2136     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2137     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2138     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2139     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2140     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2141     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2142     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2143     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2144     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2145     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2146     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2147     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2148     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2149     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2150     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2151     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2152     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2153     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2154     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2155     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2156     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2157     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2158     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2159     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2160     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2161     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2162     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2163     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2164     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2165     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2166     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2167     0xBE3A,
2168 };
2169
2170 /*
2171  * Mini sample rate converter code image
2172  * that is to be loaded at 0x400 on the DSP.
2173  */
2174 static u16 assp_minisrc_image[] __devinitdata = {
2175
2176     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2177     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2178     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2179     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2180     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2181     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2182     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2183     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2184     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2185     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2186     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2187     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2188     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2189     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2190     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2191     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2192     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2193     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2194     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2195     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2196     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2197     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2198     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2199     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2200     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2201     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2202     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2203     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2204     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2205     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2206     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2207     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2208     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2209 };
2210
2211
2212 /*
2213  * initialize ASSP
2214  */
2215
2216 #define MINISRC_LPF_LEN 10
2217 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2218         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2219         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2220 };
2221
2222 static void __devinit snd_m3_assp_init(m3_t *chip)
2223 {
2224         unsigned int i;
2225
2226         /* zero kernel data */
2227         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2228                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2229                                   KDATA_BASE_ADDR + i, 0);
2230
2231         /* zero mixer data? */
2232         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2233                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2234                                   KDATA_BASE_ADDR2 + i, 0);
2235
2236         /* init dma pointer */
2237         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2238                           KDATA_CURRENT_DMA,
2239                           KDATA_DMA_XFER0);
2240
2241         /* write kernel into code memory.. */
2242         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2243                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2244                                   REV_B_CODE_MEMORY_BEGIN + i,
2245                                   assp_kernel_image[i]);
2246         }
2247
2248         /*
2249          * We only have this one client and we know that 0x400
2250          * is free in our kernel's mem map, so lets just
2251          * drop it there.  It seems that the minisrc doesn't
2252          * need vectors, so we won't bother with them..
2253          */
2254         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2255                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2256                                   0x400 + i,
2257                                   assp_minisrc_image[i]);
2258         }
2259
2260         /*
2261          * write the coefficients for the low pass filter?
2262          */
2263         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2264                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2265                                   0x400 + MINISRC_COEF_LOC + i,
2266                                   minisrc_lpf[i]);
2267         }
2268
2269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2270                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2271                           0x8000);
2272
2273         /*
2274          * the minisrc is the only thing on
2275          * our task list..
2276          */
2277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2278                           KDATA_TASK0,
2279                           0x400);
2280
2281         /*
2282          * init the mixer number..
2283          */
2284
2285         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2286                           KDATA_MIXER_TASK_NUMBER,0);
2287
2288         /*
2289          * EXTREME KERNEL MASTER VOLUME
2290          */
2291         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2292                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2293         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2294                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2295
2296         chip->mixer_list.curlen = 0;
2297         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2298         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2299         chip->adc1_list.curlen = 0;
2300         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2301         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2302         chip->dma_list.curlen = 0;
2303         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2304         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2305         chip->msrc_list.curlen = 0;
2306         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2307         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2308 }
2309
2310
2311 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2312 {
2313         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2314                                MINISRC_IN_BUFFER_SIZE / 2 +
2315                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2316         int address, i;
2317
2318         /*
2319          * the revb memory map has 0x1100 through 0x1c00
2320          * free.
2321          */
2322
2323         /*
2324          * align instance address to 256 bytes so that it's
2325          * shifted list address is aligned.
2326          * list address = (mem address >> 1) >> 7;
2327          */
2328         data_bytes = (data_bytes + 255) & ~255;
2329         address = 0x1100 + ((data_bytes/2) * index);
2330
2331         if ((address + (data_bytes/2)) >= 0x1c00) {
2332                 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2333                            data_bytes, index, address);
2334                 return -ENOMEM;
2335         }
2336
2337         s->number = index;
2338         s->inst.code = 0x400;
2339         s->inst.data = address;
2340
2341         for (i = data_bytes / 2; i > 0; address++, i--) {
2342                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2343                                   address, 0);
2344         }
2345
2346         return 0;
2347 }
2348
2349
2350 /*
2351  * this works for the reference board, have to find
2352  * out about others
2353  *
2354  * this needs more magic for 4 speaker, but..
2355  */
2356 static void
2357 snd_m3_amp_enable(m3_t *chip, int enable)
2358 {
2359         int io = chip->iobase;
2360         u16 gpo, polarity;
2361
2362         if (! chip->external_amp)
2363                 return;
2364
2365         polarity = enable ? 0 : 1;
2366         polarity = polarity << chip->amp_gpio;
2367         gpo = 1 << chip->amp_gpio;
2368
2369         outw(~gpo, io + GPIO_MASK);
2370
2371         outw(inw(io + GPIO_DIRECTION) | gpo,
2372              io + GPIO_DIRECTION);
2373
2374         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2375              io + GPIO_DATA);
2376
2377         outw(0xffff, io + GPIO_MASK);
2378 }
2379
2380 static int
2381 snd_m3_chip_init(m3_t *chip)
2382 {
2383         struct pci_dev *pcidev = chip->pci;
2384         unsigned long io = chip->iobase;
2385         u32 n;
2386         u16 w;
2387         u8 t; /* makes as much sense as 'n', no? */
2388
2389         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2390         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2391                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2392                DISABLE_LEGACY);
2393         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2394
2395         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2396         n &= ~HV_BUTTON_FROM_GD;
2397         n |= HV_CTRL_ENABLE | REDUCED_DEBOUNCE;
2398         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2399         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2400
2401         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2402         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2403         n &= ~INT_CLK_SELECT;
2404         if (!chip->allegro_flag) {
2405                 n &= ~INT_CLK_MULT_ENABLE;
2406                 n |= INT_CLK_SRC_NOT_PCI;
2407         }
2408         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2409         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2410
2411         if (chip->allegro_flag) {
2412                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2413                 n |= IN_CLK_12MHZ_SELECT;
2414                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2415         }
2416
2417         t = inb(chip->iobase + ASSP_CONTROL_A);
2418         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2419         t |= ASSP_CLK_49MHZ_SELECT;
2420         t |= ASSP_0_WS_ENABLE;
2421         outb(t, chip->iobase + ASSP_CONTROL_A);
2422
2423         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2424
2425         outb(0x00, io + HARDWARE_VOL_CTRL);
2426         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2427         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2428         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2429         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2430
2431         return 0;
2432 }
2433
2434 static void
2435 snd_m3_enable_ints(m3_t *chip)
2436 {
2437         unsigned long io = chip->iobase;
2438
2439         /* TODO: MPU401 not supported yet */
2440         outw(ASSP_INT_ENABLE | HV_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
2441         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2442              io + ASSP_CONTROL_C);
2443 }
2444
2445
2446 /*
2447  */
2448
2449 static int snd_m3_free(m3_t *chip)
2450 {
2451         m3_dma_t *s;
2452         int i;
2453
2454         if (chip->substreams) {
2455                 spin_lock_irq(&chip->reg_lock);
2456                 for (i = 0; i < chip->num_substreams; i++) {
2457                         s = &chip->substreams[i];
2458                         /* check surviving pcms; this should not happen though.. */
2459                         if (s->substream && s->running)
2460                                 snd_m3_pcm_stop(chip, s, s->substream);
2461                 }
2462                 spin_unlock_irq(&chip->reg_lock);
2463                 kfree(chip->substreams);
2464         }
2465         if (chip->iobase) {
2466                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2467         }
2468
2469 #ifdef CONFIG_PM
2470         vfree(chip->suspend_mem);
2471 #endif
2472
2473         if (chip->irq >= 0) {
2474                 synchronize_irq(chip->irq);
2475                 free_irq(chip->irq, (void *)chip);
2476         }
2477
2478         if (chip->iobase)
2479                 pci_release_regions(chip->pci);
2480
2481         pci_disable_device(chip->pci);
2482         kfree(chip);
2483         return 0;
2484 }
2485
2486
2487 /*
2488  * APM support
2489  */
2490 #ifdef CONFIG_PM
2491 static int m3_suspend(snd_card_t *card, pm_message_t state)
2492 {
2493         m3_t *chip = card->pm_private_data;
2494         int i, index;
2495
2496         if (chip->suspend_mem == NULL)
2497                 return 0;
2498
2499         snd_pcm_suspend_all(chip->pcm);
2500         snd_ac97_suspend(chip->ac97);
2501
2502         big_mdelay(10); /* give the assp a chance to idle.. */
2503
2504         snd_m3_assp_halt(chip);
2505
2506         /* save dsp image */
2507         index = 0;
2508         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2509                 chip->suspend_mem[index++] =
2510                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2511         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2512                 chip->suspend_mem[index++] =
2513                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2514
2515         /* power down apci registers */
2516         snd_m3_outw(chip, 0xffff, 0x54);
2517         snd_m3_outw(chip, 0xffff, 0x56);
2518
2519         pci_disable_device(chip->pci);
2520         return 0;
2521 }
2522
2523 static int m3_resume(snd_card_t *card)
2524 {
2525         m3_t *chip = card->pm_private_data;
2526         int i, index;
2527
2528         if (chip->suspend_mem == NULL)
2529                 return 0;
2530
2531         pci_enable_device(chip->pci);
2532         pci_set_master(chip->pci);
2533
2534         /* first lets just bring everything back. .*/
2535         snd_m3_outw(chip, 0, 0x54);
2536         snd_m3_outw(chip, 0, 0x56);
2537
2538         snd_m3_chip_init(chip);
2539         snd_m3_assp_halt(chip);
2540         snd_m3_ac97_reset(chip);
2541
2542         /* restore dsp image */
2543         index = 0;
2544         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2545                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2546                                   chip->suspend_mem[index++]);
2547         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2548                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2549                                   chip->suspend_mem[index++]);
2550
2551         /* tell the dma engine to restart itself */
2552         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2553                           KDATA_DMA_ACTIVE, 0);
2554
2555         /* restore ac97 registers */
2556         snd_ac97_resume(chip->ac97);
2557
2558         snd_m3_assp_continue(chip);
2559         snd_m3_enable_ints(chip);
2560         snd_m3_amp_enable(chip, 1);
2561
2562         return 0;
2563 }
2564 #endif /* CONFIG_PM */
2565
2566
2567 /*
2568  */
2569
2570 static int snd_m3_dev_free(snd_device_t *device)
2571 {
2572         m3_t *chip = device->device_data;
2573         return snd_m3_free(chip);
2574 }
2575
2576 static int __devinit
2577 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2578               int enable_amp,
2579               int amp_gpio,
2580               m3_t **chip_ret)
2581 {
2582         m3_t *chip;
2583         int i, err;
2584         struct m3_quirk *quirk;
2585         u16 subsystem_vendor, subsystem_device;
2586         static snd_device_ops_t ops = {
2587                 .dev_free =     snd_m3_dev_free,
2588         };
2589
2590         *chip_ret = NULL;
2591
2592         if (pci_enable_device(pci))
2593                 return -EIO;
2594
2595         /* check, if we can restrict PCI DMA transfers to 28 bits */
2596         if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2597             pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2598                 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2599                 pci_disable_device(pci);
2600                 return -ENXIO;
2601         }
2602
2603         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2604         if (chip == NULL) {
2605                 pci_disable_device(pci);
2606                 return -ENOMEM;
2607         }
2608
2609         spin_lock_init(&chip->reg_lock);
2610         switch (pci->device) {
2611         case PCI_DEVICE_ID_ESS_ALLEGRO:
2612         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2613         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2614         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2615                 chip->allegro_flag = 1;
2616                 break;
2617         }
2618
2619         chip->card = card;
2620         chip->pci = pci;
2621         chip->irq = -1;
2622
2623         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2624         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2625
2626         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2627                 if (subsystem_vendor == quirk->vendor &&
2628                     subsystem_device == quirk->device) {
2629                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2630                         chip->quirk = quirk;
2631                         break;
2632                 }
2633         }
2634
2635         chip->external_amp = enable_amp;
2636         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2637                 chip->amp_gpio = amp_gpio;
2638         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2639                 chip->amp_gpio = chip->quirk->amp_gpio;
2640         else if (chip->allegro_flag)
2641                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2642         else /* presumably this is for all 'maestro3's.. */
2643                 chip->amp_gpio = GPO_EXT_AMP_M3;
2644
2645         chip->num_substreams = NR_DSPS;
2646         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2647         if (chip->substreams == NULL) {
2648                 kfree(chip);
2649                 pci_disable_device(pci);
2650                 return -ENOMEM;
2651         }
2652         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2653
2654         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2655                 snd_m3_free(chip);
2656                 return err;
2657         }
2658         chip->iobase = pci_resource_start(pci, 0);
2659
2660         /* just to be sure */
2661         pci_set_master(pci);
2662
2663         snd_m3_chip_init(chip);
2664         snd_m3_assp_halt(chip);
2665
2666         snd_m3_ac97_reset(chip);
2667
2668         snd_m3_assp_init(chip);
2669         snd_m3_amp_enable(chip, 1);
2670
2671         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2672                         card->driver, (void *)chip)) {
2673                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2674                 snd_m3_free(chip);
2675                 return -ENOMEM;
2676         }
2677         chip->irq = pci->irq;
2678
2679 #ifdef CONFIG_PM
2680         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2681         if (chip->suspend_mem == NULL)
2682                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2683         else
2684                 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2685 #endif
2686
2687         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2688                 snd_m3_free(chip);
2689                 return err;
2690         }
2691
2692         spin_lock_init(&chip->ac97_lock);
2693         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2694
2695         if ((err = snd_m3_mixer(chip)) < 0)
2696                 return err;
2697
2698         for (i = 0; i < chip->num_substreams; i++) {
2699                 m3_dma_t *s = &chip->substreams[i];
2700                 s->chip = chip;
2701                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2702                         return err;
2703         }
2704
2705         if ((err = snd_m3_pcm(chip, 0)) < 0)
2706                 return err;
2707
2708         snd_m3_enable_ints(chip);
2709         snd_m3_assp_continue(chip);
2710
2711         snd_card_set_dev(card, &pci->dev);
2712
2713         *chip_ret = chip;
2714
2715         return 0;
2716 }
2717
2718 /*
2719  */
2720 static int __devinit
2721 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2722 {
2723         static int dev;
2724         snd_card_t *card;
2725         m3_t *chip;
2726         int err;
2727
2728         /* don't pick up modems */
2729         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2730                 return -ENODEV;
2731
2732         if (dev >= SNDRV_CARDS)
2733                 return -ENODEV;
2734         if (!enable[dev]) {
2735                 dev++;
2736                 return -ENOENT;
2737         }
2738
2739         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2740         if (card == NULL)
2741                 return -ENOMEM;
2742
2743         switch (pci->device) {
2744         case PCI_DEVICE_ID_ESS_ALLEGRO:
2745         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2746                 strcpy(card->driver, "Allegro");
2747                 break;
2748         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2749         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2750                 strcpy(card->driver, "Canyon3D-2");
2751                 break;
2752         default:
2753                 strcpy(card->driver, "Maestro3");
2754                 break;
2755         }
2756
2757         if ((err = snd_m3_create(card, pci,
2758                                  external_amp[dev],
2759                                  amp_gpio[dev],
2760                                  &chip)) < 0) {
2761                 snd_card_free(card);
2762                 return err;
2763         }
2764
2765         sprintf(card->shortname, "ESS %s PCI", card->driver);
2766         sprintf(card->longname, "%s at 0x%lx, irq %d",
2767                 card->shortname, chip->iobase, chip->irq);
2768
2769         if ((err = snd_card_register(card)) < 0) {
2770                 snd_card_free(card);
2771                 return err;
2772         }
2773
2774 #if 0 /* TODO: not supported yet */
2775         /* TODO enable midi irq and i/o */
2776         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2777                                   chip->iobase + MPU401_DATA_PORT, 1,
2778                                   chip->irq, 0, &chip->rmidi);
2779         if (err < 0)
2780                 printk(KERN_WARNING "maestro3: no midi support.\n");
2781 #endif
2782
2783         pci_set_drvdata(pci, card);
2784         dev++;
2785         return 0;
2786 }
2787
2788 static void __devexit snd_m3_remove(struct pci_dev *pci)
2789 {
2790         snd_card_free(pci_get_drvdata(pci));
2791         pci_set_drvdata(pci, NULL);
2792 }
2793
2794 static struct pci_driver driver = {
2795         .name = "Maestro3",
2796         .id_table = snd_m3_ids,
2797         .probe = snd_m3_probe,
2798         .remove = __devexit_p(snd_m3_remove),
2799         SND_PCI_PM_CALLBACKS
2800 };
2801
2802 static int __init alsa_card_m3_init(void)
2803 {
2804         return pci_register_driver(&driver);
2805 }
2806
2807 static void __exit alsa_card_m3_exit(void)
2808 {
2809         pci_unregister_driver(&driver);
2810 }
2811
2812 module_init(alsa_card_m3_init)
2813 module_exit(alsa_card_m3_exit)