sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/moduleparam.h>
  43 #include <sound/core.h>
  44 #include <sound/info.h>
  45 #include <sound/control.h>
  46 #include <sound/pcm.h>
  47 #include <sound/mpu401.h>
  48 #include <sound/ac97_codec.h>
  49 #include <sound/initval.h>
  50
  51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  53 MODULE_LICENSE("GPL");
  54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  55                 "{ESS,ES1988},"
  56                 "{ESS,Allegro PCI},"
  57                 "{ESS,Allegro-1 PCI},"
  58                 "{ESS,Canyon3D-2/LE PCI}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  68 module_param_array(id, charp, NULL, 0444);
  69 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  70 module_param_array(enable, bool, NULL, 0444);
  71 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  72 module_param_array(external_amp, bool, NULL, 0444);
  73 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  74 module_param_array(amp_gpio, int, NULL, 0444);
  75 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  76
  77 #define MAX_PLAYBACKS   2
  78 #define MAX_CAPTURES    1
  79 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  80
  81
  82 /*
  83  * maestro3 registers
  84  */
  85
  86 /* Allegro PCI configuration registers */
  87 #define PCI_LEGACY_AUDIO_CTRL   0x40
  88 #define SOUND_BLASTER_ENABLE    0x00000001
  89 #define FM_SYNTHESIS_ENABLE     0x00000002
  90 #define GAME_PORT_ENABLE        0x00000004
  91 #define MPU401_IO_ENABLE        0x00000008
  92 #define MPU401_IRQ_ENABLE       0x00000010
  93 #define ALIAS_10BIT_IO          0x00000020
  94 #define SB_DMA_MASK             0x000000C0
  95 #define SB_DMA_0                0x00000040
  96 #define SB_DMA_1                0x00000040
  97 #define SB_DMA_R                0x00000080
  98 #define SB_DMA_3                0x000000C0
  99 #define SB_IRQ_MASK             0x00000700
 100 #define SB_IRQ_5                0x00000000
 101 #define SB_IRQ_7                0x00000100
 102 #define SB_IRQ_9                0x00000200
 103 #define SB_IRQ_10               0x00000300
 104 #define MIDI_IRQ_MASK           0x00003800
 105 #define SERIAL_IRQ_ENABLE       0x00004000
 106 #define DISABLE_LEGACY          0x00008000
 107
 108 #define PCI_ALLEGRO_CONFIG      0x50
 109 #define SB_ADDR_240             0x00000004
 110 #define MPU_ADDR_MASK           0x00000018
 111 #define MPU_ADDR_330            0x00000000
 112 #define MPU_ADDR_300            0x00000008
 113 #define MPU_ADDR_320            0x00000010
 114 #define MPU_ADDR_340            0x00000018
 115 #define USE_PCI_TIMING          0x00000040
 116 #define POSTED_WRITE_ENABLE     0x00000080
 117 #define DMA_POLICY_MASK         0x00000700
 118 #define DMA_DDMA                0x00000000
 119 #define DMA_TDMA                0x00000100
 120 #define DMA_PCPCI               0x00000200
 121 #define DMA_WBDMA16             0x00000400
 122 #define DMA_WBDMA4              0x00000500
 123 #define DMA_WBDMA2              0x00000600
 124 #define DMA_WBDMA1              0x00000700
 125 #define DMA_SAFE_GUARD          0x00000800
 126 #define HI_PERF_GP_ENABLE       0x00001000
 127 #define PIC_SNOOP_MODE_0        0x00002000
 128 #define PIC_SNOOP_MODE_1        0x00004000
 129 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 130 #define RING_IN_ENABLE          0x00010000
 131 #define SPDIF_TEST_MODE         0x00020000
 132 #define CLK_MULT_MODE_SELECT_2  0x00040000
 133 #define EEPROM_WRITE_ENABLE     0x00080000
 134 #define CODEC_DIR_IN            0x00100000
 135 #define HV_BUTTON_FROM_GD       0x00200000
 136 #define REDUCED_DEBOUNCE        0x00400000
 137 #define HV_CTRL_ENABLE          0x00800000
 138 #define SPDIF_ENABLE            0x01000000
 139 #define CLK_DIV_SELECT          0x06000000
 140 #define CLK_DIV_BY_48           0x00000000
 141 #define CLK_DIV_BY_49           0x02000000
 142 #define CLK_DIV_BY_50           0x04000000
 143 #define CLK_DIV_RESERVED        0x06000000
 144 #define PM_CTRL_ENABLE          0x08000000
 145 #define CLK_MULT_MODE_SELECT    0x30000000
 146 #define CLK_MULT_MODE_SHIFT     28
 147 #define CLK_MULT_MODE_0         0x00000000
 148 #define CLK_MULT_MODE_1         0x10000000
 149 #define CLK_MULT_MODE_2         0x20000000
 150 #define CLK_MULT_MODE_3         0x30000000
 151 #define INT_CLK_SELECT          0x40000000
 152 #define INT_CLK_MULT_RESET      0x80000000
 153
 154 /* M3 */
 155 #define INT_CLK_SRC_NOT_PCI     0x00100000
 156 #define INT_CLK_MULT_ENABLE     0x80000000
 157
 158 #define PCI_ACPI_CONTROL        0x54
 159 #define PCI_ACPI_D0             0x00000000
 160 #define PCI_ACPI_D1             0xB4F70000
 161 #define PCI_ACPI_D2             0xB4F7B4F7
 162
 163 #define PCI_USER_CONFIG         0x58
 164 #define EXT_PCI_MASTER_ENABLE   0x00000001
 165 #define SPDIF_OUT_SELECT        0x00000002
 166 #define TEST_PIN_DIR_CTRL       0x00000004
 167 #define AC97_CODEC_TEST         0x00000020
 168 #define TRI_STATE_BUFFER        0x00000080
 169 #define IN_CLK_12MHZ_SELECT     0x00000100
 170 #define MULTI_FUNC_DISABLE      0x00000200
 171 #define EXT_MASTER_PAIR_SEL     0x00000400
 172 #define PCI_MASTER_SUPPORT      0x00000800
 173 #define STOP_CLOCK_ENABLE       0x00001000
 174 #define EAPD_DRIVE_ENABLE       0x00002000
 175 #define REQ_TRI_STATE_ENABLE    0x00004000
 176 #define REQ_LOW_ENABLE          0x00008000
 177 #define MIDI_1_ENABLE           0x00010000
 178 #define MIDI_2_ENABLE           0x00020000
 179 #define SB_AUDIO_SYNC           0x00040000
 180 #define HV_CTRL_TEST            0x00100000
 181 #define SOUNDBLASTER_TEST       0x00400000
 182
 183 #define PCI_USER_CONFIG_C       0x5C
 184
 185 #define PCI_DDMA_CTRL           0x60
 186 #define DDMA_ENABLE             0x00000001
 187
 188
 189 /* Allegro registers */
 190 #define HOST_INT_CTRL           0x18
 191 #define SB_INT_ENABLE           0x0001
 192 #define MPU401_INT_ENABLE       0x0002
 193 #define ASSP_INT_ENABLE         0x0010
 194 #define RING_INT_ENABLE         0x0020
 195 #define HV_INT_ENABLE           0x0040
 196 #define CLKRUN_GEN_ENABLE       0x0100
 197 #define HV_CTRL_TO_PME          0x0400
 198 #define SOFTWARE_RESET_ENABLE   0x8000
 199
 200 /*
 201  * should be using the above defines, probably.
 202  */
 203 #define REGB_ENABLE_RESET               0x01
 204 #define REGB_STOP_CLOCK                 0x10
 205
 206 #define HOST_INT_STATUS         0x1A
 207 #define SB_INT_PENDING          0x01
 208 #define MPU401_INT_PENDING      0x02
 209 #define ASSP_INT_PENDING        0x10
 210 #define RING_INT_PENDING        0x20
 211 #define HV_INT_PENDING          0x40
 212
 213 #define HARDWARE_VOL_CTRL       0x1B
 214 #define SHADOW_MIX_REG_VOICE    0x1C
 215 #define HW_VOL_COUNTER_VOICE    0x1D
 216 #define SHADOW_MIX_REG_MASTER   0x1E
 217 #define HW_VOL_COUNTER_MASTER   0x1F
 218
 219 #define CODEC_COMMAND           0x30
 220 #define CODEC_READ_B            0x80
 221
 222 #define CODEC_STATUS            0x30
 223 #define CODEC_BUSY_B            0x01
 224
 225 #define CODEC_DATA              0x32
 226
 227 #define RING_BUS_CTRL_A         0x36
 228 #define RAC_PME_ENABLE          0x0100
 229 #define RAC_SDFS_ENABLE         0x0200
 230 #define LAC_PME_ENABLE          0x0400
 231 #define LAC_SDFS_ENABLE         0x0800
 232 #define SERIAL_AC_LINK_ENABLE   0x1000
 233 #define IO_SRAM_ENABLE          0x2000
 234 #define IIS_INPUT_ENABLE        0x8000
 235
 236 #define RING_BUS_CTRL_B         0x38
 237 #define SECOND_CODEC_ID_MASK    0x0003
 238 #define SPDIF_FUNC_ENABLE       0x0010
 239 #define SECOND_AC_ENABLE        0x0020
 240 #define SB_MODULE_INTF_ENABLE   0x0040
 241 #define SSPE_ENABLE             0x0040
 242 #define M3I_DOCK_ENABLE         0x0080
 243
 244 #define SDO_OUT_DEST_CTRL       0x3A
 245 #define COMMAND_ADDR_OUT        0x0003
 246 #define PCM_LR_OUT_LOCAL        0x0000
 247 #define PCM_LR_OUT_REMOTE       0x0004
 248 #define PCM_LR_OUT_MUTE         0x0008
 249 #define PCM_LR_OUT_BOTH         0x000C
 250 #define LINE1_DAC_OUT_LOCAL     0x0000
 251 #define LINE1_DAC_OUT_REMOTE    0x0010
 252 #define LINE1_DAC_OUT_MUTE      0x0020
 253 #define LINE1_DAC_OUT_BOTH      0x0030
 254 #define PCM_CLS_OUT_LOCAL       0x0000
 255 #define PCM_CLS_OUT_REMOTE      0x0040
 256 #define PCM_CLS_OUT_MUTE        0x0080
 257 #define PCM_CLS_OUT_BOTH        0x00C0
 258 #define PCM_RLF_OUT_LOCAL       0x0000
 259 #define PCM_RLF_OUT_REMOTE      0x0100
 260 #define PCM_RLF_OUT_MUTE        0x0200
 261 #define PCM_RLF_OUT_BOTH        0x0300
 262 #define LINE2_DAC_OUT_LOCAL     0x0000
 263 #define LINE2_DAC_OUT_REMOTE    0x0400
 264 #define LINE2_DAC_OUT_MUTE      0x0800
 265 #define LINE2_DAC_OUT_BOTH      0x0C00
 266 #define HANDSET_OUT_LOCAL       0x0000
 267 #define HANDSET_OUT_REMOTE      0x1000
 268 #define HANDSET_OUT_MUTE        0x2000
 269 #define HANDSET_OUT_BOTH        0x3000
 270 #define IO_CTRL_OUT_LOCAL       0x0000
 271 #define IO_CTRL_OUT_REMOTE      0x4000
 272 #define IO_CTRL_OUT_MUTE        0x8000
 273 #define IO_CTRL_OUT_BOTH        0xC000
 274
 275 #define SDO_IN_DEST_CTRL        0x3C
 276 #define STATUS_ADDR_IN          0x0003
 277 #define PCM_LR_IN_LOCAL         0x0000
 278 #define PCM_LR_IN_REMOTE        0x0004
 279 #define PCM_LR_RESERVED         0x0008
 280 #define PCM_LR_IN_BOTH          0x000C
 281 #define LINE1_ADC_IN_LOCAL      0x0000
 282 #define LINE1_ADC_IN_REMOTE     0x0010
 283 #define LINE1_ADC_IN_MUTE       0x0020
 284 #define MIC_ADC_IN_LOCAL        0x0000
 285 #define MIC_ADC_IN_REMOTE       0x0040
 286 #define MIC_ADC_IN_MUTE         0x0080
 287 #define LINE2_DAC_IN_LOCAL      0x0000
 288 #define LINE2_DAC_IN_REMOTE     0x0400
 289 #define LINE2_DAC_IN_MUTE       0x0800
 290 #define HANDSET_IN_LOCAL        0x0000
 291 #define HANDSET_IN_REMOTE       0x1000
 292 #define HANDSET_IN_MUTE         0x2000
 293 #define IO_STATUS_IN_LOCAL      0x0000
 294 #define IO_STATUS_IN_REMOTE     0x4000
 295
 296 #define SPDIF_IN_CTRL           0x3E
 297 #define SPDIF_IN_ENABLE         0x0001
 298
 299 #define GPIO_DATA               0x60
 300 #define GPIO_DATA_MASK          0x0FFF
 301 #define GPIO_HV_STATUS          0x3000
 302 #define GPIO_PME_STATUS         0x4000
 303
 304 #define GPIO_MASK               0x64
 305 #define GPIO_DIRECTION          0x68
 306 #define GPO_PRIMARY_AC97        0x0001
 307 #define GPI_LINEOUT_SENSE       0x0004
 308 #define GPO_SECONDARY_AC97      0x0008
 309 #define GPI_VOL_DOWN            0x0010
 310 #define GPI_VOL_UP              0x0020
 311 #define GPI_IIS_CLK             0x0040
 312 #define GPI_IIS_LRCLK           0x0080
 313 #define GPI_IIS_DATA            0x0100
 314 #define GPI_DOCKING_STATUS      0x0100
 315 #define GPI_HEADPHONE_SENSE     0x0200
 316 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 317
 318 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 319 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 320
 321 /* M3 */
 322 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 323
 324 #define ASSP_INDEX_PORT         0x80
 325 #define ASSP_MEMORY_PORT        0x82
 326 #define ASSP_DATA_PORT          0x84
 327
 328 #define MPU401_DATA_PORT        0x98
 329 #define MPU401_STATUS_PORT      0x99
 330
 331 #define CLK_MULT_DATA_PORT      0x9C
 332
 333 #define ASSP_CONTROL_A          0xA2
 334 #define ASSP_0_WS_ENABLE        0x01
 335 #define ASSP_CTRL_A_RESERVED1   0x02
 336 #define ASSP_CTRL_A_RESERVED2   0x04
 337 #define ASSP_CLK_49MHZ_SELECT   0x08
 338 #define FAST_PLU_ENABLE         0x10
 339 #define ASSP_CTRL_A_RESERVED3   0x20
 340 #define DSP_CLK_36MHZ_SELECT    0x40
 341
 342 #define ASSP_CONTROL_B          0xA4
 343 #define RESET_ASSP              0x00
 344 #define RUN_ASSP                0x01
 345 #define ENABLE_ASSP_CLOCK       0x00
 346 #define STOP_ASSP_CLOCK         0x10
 347 #define RESET_TOGGLE            0x40
 348
 349 #define ASSP_CONTROL_C          0xA6
 350 #define ASSP_HOST_INT_ENABLE    0x01
 351 #define FM_ADDR_REMAP_DISABLE   0x02
 352 #define HOST_WRITE_PORT_ENABLE  0x08
 353
 354 #define ASSP_HOST_INT_STATUS    0xAC
 355 #define DSP2HOST_REQ_PIORECORD  0x01
 356 #define DSP2HOST_REQ_I2SRATE    0x02
 357 #define DSP2HOST_REQ_TIMER      0x04
 358
 359 /* AC97 registers */
 360 /* XXX fix this crap up */
 361 /*#define AC97_RESET              0x00*/
 362
 363 #define AC97_VOL_MUTE_B         0x8000
 364 #define AC97_VOL_M              0x1F
 365 #define AC97_LEFT_VOL_S         8
 366
 367 #define AC97_MASTER_VOL         0x02
 368 #define AC97_LINE_LEVEL_VOL     0x04
 369 #define AC97_MASTER_MONO_VOL    0x06
 370 #define AC97_PC_BEEP_VOL        0x0A
 371 #define AC97_PC_BEEP_VOL_M      0x0F
 372 #define AC97_SROUND_MASTER_VOL  0x38
 373 #define AC97_PC_BEEP_VOL_S      1
 374
 375 /*#define AC97_PHONE_VOL          0x0C
 376 #define AC97_MIC_VOL            0x0E*/
 377 #define AC97_MIC_20DB_ENABLE    0x40
 378
 379 /*#define AC97_LINEIN_VOL         0x10
 380 #define AC97_CD_VOL             0x12
 381 #define AC97_VIDEO_VOL          0x14
 382 #define AC97_AUX_VOL            0x16*/
 383 #define AC97_PCM_OUT_VOL        0x18
 384 /*#define AC97_RECORD_SELECT      0x1A*/
 385 #define AC97_RECORD_MIC         0x00
 386 #define AC97_RECORD_CD          0x01
 387 #define AC97_RECORD_VIDEO       0x02
 388 #define AC97_RECORD_AUX         0x03
 389 #define AC97_RECORD_MONO_MUX    0x02
 390 #define AC97_RECORD_DIGITAL     0x03
 391 #define AC97_RECORD_LINE        0x04
 392 #define AC97_RECORD_STEREO      0x05
 393 #define AC97_RECORD_MONO        0x06
 394 #define AC97_RECORD_PHONE       0x07
 395
 396 /*#define AC97_RECORD_GAIN        0x1C*/
 397 #define AC97_RECORD_VOL_M       0x0F
 398
 399 /*#define AC97_GENERAL_PURPOSE    0x20*/
 400 #define AC97_POWER_DOWN_CTRL    0x26
 401 #define AC97_ADC_READY          0x0001
 402 #define AC97_DAC_READY          0x0002
 403 #define AC97_ANALOG_READY       0x0004
 404 #define AC97_VREF_ON            0x0008
 405 #define AC97_PR0                0x0100
 406 #define AC97_PR1                0x0200
 407 #define AC97_PR2                0x0400
 408 #define AC97_PR3                0x0800
 409 #define AC97_PR4                0x1000
 410
 411 #define AC97_RESERVED1          0x28
 412
 413 #define AC97_VENDOR_TEST        0x5A
 414
 415 #define AC97_CLOCK_DELAY        0x5C
 416 #define AC97_LINEOUT_MUX_SEL    0x0001
 417 #define AC97_MONO_MUX_SEL       0x0002
 418 #define AC97_CLOCK_DELAY_SEL    0x1F
 419 #define AC97_DAC_CDS_SHIFT      6
 420 #define AC97_ADC_CDS_SHIFT      11
 421
 422 #define AC97_MULTI_CHANNEL_SEL  0x74
 423
 424 /*#define AC97_VENDOR_ID1         0x7C
 425 #define AC97_VENDOR_ID2         0x7E*/
 426
 427 /*
 428  * ASSP control regs
 429  */
 430 #define DSP_PORT_TIMER_COUNT    0x06
 431
 432 #define DSP_PORT_MEMORY_INDEX   0x80
 433
 434 #define DSP_PORT_MEMORY_TYPE    0x82
 435 #define MEMTYPE_INTERNAL_CODE   0x0002
 436 #define MEMTYPE_INTERNAL_DATA   0x0003
 437 #define MEMTYPE_MASK            0x0003
 438
 439 #define DSP_PORT_MEMORY_DATA    0x84
 440
 441 #define DSP_PORT_CONTROL_REG_A  0xA2
 442 #define DSP_PORT_CONTROL_REG_B  0xA4
 443 #define DSP_PORT_CONTROL_REG_C  0xA6
 444
 445 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 446 #define REV_A_CODE_MEMORY_END           0x0FFF
 447 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 448 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 449
 450 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 451 #define REV_B_CODE_MEMORY_END           0x0BFF
 452 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 453 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 454
 455 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 456 #define REV_A_DATA_MEMORY_END           0x2FFF
 457 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 458 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 459
 460 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 461 #define REV_B_DATA_MEMORY_END           0x2BFF
 462 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 463 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 464
 465
 466 #define NUM_UNITS_KERNEL_CODE          16
 467 #define NUM_UNITS_KERNEL_DATA           2
 468
 469 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 470 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 471
 472 /*
 473  * Kernel data layout
 474  */
 475
 476 #define DP_SHIFT_COUNT                  7
 477
 478 #define KDATA_BASE_ADDR                 0x1000
 479 #define KDATA_BASE_ADDR2                0x1080
 480
 481 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 482 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 483 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 484 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 485 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 486 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 487 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 488 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 489 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 490
 491 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 492 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 493
 494 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 495 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 496 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 497 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 498 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 499 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 500 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 501 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 502 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 503 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 504
 505 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 506 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 507
 508 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 509 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 510
 511 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 512 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 513
 514 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 515 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 516 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 517
 518 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 519 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 520 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 521 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 522 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 523
 524 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 525 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 526 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 527
 528 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 529 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 530 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 531
 532 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 533 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 534 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 535 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 536 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 537 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 538 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 539 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 540 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 541 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 542
 543 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 544 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 545 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 546
 547 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 548 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 549
 550 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 551 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 552 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 553
 554 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 555 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 556 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 557 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 558 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 559 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 560
 561 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 562 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 563 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 564 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 565 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 566 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 567
 568 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 569 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 570 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 571 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 572 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 573 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 574
 575 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 576 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 577 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 578 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 579
 580 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 581 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 582
 583 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 584 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 585
 586 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 587 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 588 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 589 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 590 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 591
 592 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 593 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 594
 595 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 596 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 597 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 598
 599 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 600 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 601
 602 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 603
 604 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 605 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 606 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 607 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 608 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 609 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 610 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 611 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 612 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 613 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 614 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 615 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 616
 617 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 618 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 619 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 620 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 621
 622 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 623 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 624
 625 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 626 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 627 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 628 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 629
 630 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 631 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 632 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 633 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 634 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 635
 636 /*
 637  * second 'segment' (?) reserved for mixer
 638  * buffers..
 639  */
 640
 641 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 642 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 643 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 644 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 645 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 646 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 647 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 648 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 649 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 650 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 651 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 652 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 653 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 654 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 655 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 656 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 657
 658 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 659 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 660 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 661 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 662 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 663 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 664 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 665 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 666 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 667 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 668 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 669
 670 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 671 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 672 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 673 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 674 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 675 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 676
 677 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 678 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 679 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 680 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 681
 682 /*
 683  * client data area offsets
 684  */
 685 #define CDATA_INSTANCE_READY            0x00
 686
 687 #define CDATA_HOST_SRC_ADDRL            0x01
 688 #define CDATA_HOST_SRC_ADDRH            0x02
 689 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 690 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 691 #define CDATA_HOST_SRC_CURRENTL         0x05
 692 #define CDATA_HOST_SRC_CURRENTH         0x06
 693
 694 #define CDATA_IN_BUF_CONNECT            0x07
 695 #define CDATA_OUT_BUF_CONNECT           0x08
 696
 697 #define CDATA_IN_BUF_BEGIN              0x09
 698 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 699 #define CDATA_IN_BUF_HEAD               0x0B
 700 #define CDATA_IN_BUF_TAIL               0x0C
 701 #define CDATA_OUT_BUF_BEGIN             0x0D
 702 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 703 #define CDATA_OUT_BUF_HEAD              0x0F
 704 #define CDATA_OUT_BUF_TAIL              0x10
 705
 706 #define CDATA_DMA_CONTROL               0x11
 707 #define CDATA_RESERVED                  0x12
 708
 709 #define CDATA_FREQUENCY                 0x13
 710 #define CDATA_LEFT_VOLUME               0x14
 711 #define CDATA_RIGHT_VOLUME              0x15
 712 #define CDATA_LEFT_SUR_VOL              0x16
 713 #define CDATA_RIGHT_SUR_VOL             0x17
 714
 715 #define CDATA_HEADER_LEN                0x18
 716
 717 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 718 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 719 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 720 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 721 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 722 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 723 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 724 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 725
 726 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 727 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 728 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 729 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 730 #define MINISRC_BIQUAD_STAGE    2
 731 #define MINISRC_COEF_LOC          0x175
 732
 733 #define DMACONTROL_BLOCK_MASK           0x000F
 734 #define  DMAC_BLOCK0_SELECTOR           0x0000
 735 #define  DMAC_BLOCK1_SELECTOR           0x0001
 736 #define  DMAC_BLOCK2_SELECTOR           0x0002
 737 #define  DMAC_BLOCK3_SELECTOR           0x0003
 738 #define  DMAC_BLOCK4_SELECTOR           0x0004
 739 #define  DMAC_BLOCK5_SELECTOR           0x0005
 740 #define  DMAC_BLOCK6_SELECTOR           0x0006
 741 #define  DMAC_BLOCK7_SELECTOR           0x0007
 742 #define  DMAC_BLOCK8_SELECTOR           0x0008
 743 #define  DMAC_BLOCK9_SELECTOR           0x0009
 744 #define  DMAC_BLOCKA_SELECTOR           0x000A
 745 #define  DMAC_BLOCKB_SELECTOR           0x000B
 746 #define  DMAC_BLOCKC_SELECTOR           0x000C
 747 #define  DMAC_BLOCKD_SELECTOR           0x000D
 748 #define  DMAC_BLOCKE_SELECTOR           0x000E
 749 #define  DMAC_BLOCKF_SELECTOR           0x000F
 750 #define DMACONTROL_PAGE_MASK            0x00F0
 751 #define  DMAC_PAGE0_SELECTOR            0x0030
 752 #define  DMAC_PAGE1_SELECTOR            0x0020
 753 #define  DMAC_PAGE2_SELECTOR            0x0010
 754 #define  DMAC_PAGE3_SELECTOR            0x0000
 755 #define DMACONTROL_AUTOREPEAT           0x1000
 756 #define DMACONTROL_STOPPED              0x2000
 757 #define DMACONTROL_DIRECTION            0x0100
 758
 759 /*
 760  * an arbitrary volume we set the internal
 761  * volume settings to so that the ac97 volume
 762  * range is a little less insane.  0x7fff is
 763  * max.
 764  */
 765 #define ARB_VOLUME ( 0x6800 )
 766
 767 /*
 768  */
 769
 770 typedef struct snd_m3_dma m3_dma_t;
 771 typedef struct snd_m3 m3_t;
 772
 773 /* quirk lists */
 774 struct m3_quirk {
 775         const char *name;       /* device name */
 776         u16 vendor, device;     /* subsystem ids */
 777         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 778         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 779                                    (e.g. for IrDA on Dell Inspirons) */
 780 };
 781
 782 struct m3_hv_quirk {
 783         u16 vendor, device, subsystem_vendor, subsystem_device;
 784         u32 config;             /* ALLEGRO_CONFIG hardware volume bits */
 785         int is_omnibook;        /* Do HP OmniBook GPIO magic? */
 786 };
 787
 788 struct m3_list {
 789         int curlen;
 790         int mem_addr;
 791         int max;
 792 };
 793
 794 struct snd_m3_dma {
 795
 796         int number;
 797         m3_t *chip;
 798         snd_pcm_substream_t *substream;
 799
 800         struct assp_instance {
 801                 unsigned short code, data;
 802         } inst;
 803
 804         int running;
 805         int opened;
 806
 807         unsigned long buffer_addr;
 808         int dma_size;
 809         int period_size;
 810         unsigned int hwptr;
 811         int count;
 812
 813         int index[3];
 814         struct m3_list *index_list[3];
 815
 816         int in_lists;
 817
 818         struct list_head list;
 819
 820 };
 821
 822 struct snd_m3 {
 823
 824         snd_card_t *card;
 825
 826         unsigned long iobase;
 827
 828         int irq;
 829         unsigned int allegro_flag : 1;
 830
 831         ac97_t *ac97;
 832
 833         snd_pcm_t *pcm;
 834
 835         struct pci_dev *pci;
 836         struct m3_quirk *quirk;
 837         struct m3_hv_quirk *hv_quirk;
 838
 839         int dacs_active;
 840         int timer_users;
 841
 842         struct m3_list  msrc_list;
 843         struct m3_list  mixer_list;
 844         struct m3_list  adc1_list;
 845         struct m3_list  dma_list;
 846
 847         /* for storing reset state..*/
 848         u8 reset_state;
 849
 850         int external_amp;
 851         int amp_gpio;
 852
 853         /* midi */
 854         snd_rawmidi_t *rmidi;
 855
 856         /* pcm streams */
 857         int num_substreams;
 858         m3_dma_t *substreams;
 859
 860         spinlock_t reg_lock;
 861         spinlock_t ac97_lock;
 862
 863         snd_kcontrol_t *master_switch;
 864         snd_kcontrol_t *master_volume;
 865         struct tasklet_struct hwvol_tq;
 866
 867 #ifdef CONFIG_PM
 868         u16 *suspend_mem;
 869 #endif
 870 };
 871
 872 /*
 873  * pci ids
 874  */
 875
 876 #ifndef PCI_VENDOR_ID_ESS
 877 #define PCI_VENDOR_ID_ESS         0x125D
 878 #endif
 879 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
 880 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 881 #endif
 882 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
 883 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
 884 #endif
 885 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
 886 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE  0x1990
 887 #endif
 888 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
 889 #define PCI_DEVICE_ID_ESS_CANYON3D_2    0x1992
 890 #endif
 891 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
 892 #define PCI_DEVICE_ID_ESS_MAESTRO3      0x1998
 893 #endif
 894 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
 895 #define PCI_DEVICE_ID_ESS_MAESTRO3_1    0x1999
 896 #endif
 897 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
 898 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW   0x199a
 899 #endif
 900 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
 901 #define PCI_DEVICE_ID_ESS_MAESTRO3_2    0x199b
 902 #endif
 903
 904 static struct pci_device_id snd_m3_ids[] = {
 905         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 906          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 907         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 908          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 909         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 910          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 911         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 912          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 913         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 914          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 915         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 916          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 917         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 918          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 919         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 920          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 921         {0,},
 922 };
 923
 924 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 925
 926 static struct m3_quirk m3_quirk_list[] = {
 927         /* panasonic CF-28 "toughbook" */
 928         {
 929                 .name = "Panasonic CF-28",
 930                 .vendor = 0x10f7,
 931                 .device = 0x833e,
 932                 .amp_gpio = 0x0d,
 933         },
 934         /* panasonic CF-72 "toughbook" */
 935         {
 936                 .name = "Panasonic CF-72",
 937                 .vendor = 0x10f7,
 938                 .device = 0x833d,
 939                 .amp_gpio = 0x0d,
 940         },
 941         /* Dell Inspiron 4000 */
 942         {
 943                 .name = "Dell Inspiron 4000",
 944                 .vendor = 0x1028,
 945                 .device = 0x00b0,
 946                 .amp_gpio = -1,
 947                 .irda_workaround = 1,
 948         },
 949         /* Dell Inspiron 8000 */
 950         {
 951                 .name = "Dell Inspiron 8000",
 952                 .vendor = 0x1028,
 953                 .device = 0x00a4,
 954                 .amp_gpio = -1,
 955                 .irda_workaround = 1,
 956         },
 957         /* Dell Inspiron 8100 */
 958         {
 959                 .name = "Dell Inspiron 8100",
 960                 .vendor = 0x1028,
 961                 .device = 0x00e6,
 962                 .amp_gpio = -1,
 963                 .irda_workaround = 1,
 964         },
 965         /* NEC LM800J/7 */
 966         {
 967                 .name = "NEC LM800J/7",
 968                 .vendor = 0x1033,
 969                 .device = 0x80f1,
 970                 .amp_gpio = 0x03,
 971         },
 972         /* LEGEND ZhaoYang 3100CF */
 973         {
 974                 .name = "LEGEND ZhaoYang 3100CF",
 975                 .vendor = 0x1509,
 976                 .device = 0x1740,
 977                 .amp_gpio = 0x03,
 978         },
 979         /* END */
 980         { NULL }
 981 };
 982
 983 /* These values came from the Windows driver. */
 984 static struct m3_hv_quirk m3_hv_quirk_list[] = {
 985         /* Allegro chips */
 986         { 0x125D, 0x1988, 0x0E11, 0x002E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 987         { 0x125D, 0x1988, 0x0E11, 0x0094, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 988         { 0x125D, 0x1988, 0x0E11, 0xB112, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 989         { 0x125D, 0x1988, 0x0E11, 0xB114, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 990         { 0x125D, 0x1988, 0x103C, 0x0012, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 991         { 0x125D, 0x1988, 0x103C, 0x0018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 992         { 0x125D, 0x1988, 0x103C, 0x001C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 993         { 0x125D, 0x1988, 0x103C, 0x001D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 994         { 0x125D, 0x1988, 0x103C, 0x001E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 995         { 0x125D, 0x1988, 0x107B, 0x3350, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 996         { 0x125D, 0x1988, 0x10F7, 0x8338, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 997         { 0x125D, 0x1988, 0x10F7, 0x833C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 998         { 0x125D, 0x1988, 0x10F7, 0x833D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 999         { 0x125D, 0x1988, 0x10F7, 0x833E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1000         { 0x125D, 0x1988, 0x10F7, 0x833F, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1001         { 0x125D, 0x1988, 0x13BD, 0x1018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1002         { 0x125D, 0x1988, 0x13BD, 0x1019, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1003         { 0x125D, 0x1988, 0x13BD, 0x101A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1004         { 0x125D, 0x1988, 0x14FF, 0x0F03, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1005         { 0x125D, 0x1988, 0x14FF, 0x0F04, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1006         { 0x125D, 0x1988, 0x14FF, 0x0F05, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1007         { 0x125D, 0x1988, 0x156D, 0xB400, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1008         { 0x125D, 0x1988, 0x156D, 0xB795, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1009         { 0x125D, 0x1988, 0x156D, 0xB797, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1010         { 0x125D, 0x1988, 0x156D, 0xC700, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
1011         { 0x125D, 0x1988, 0x1033, 0x80F1, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1012         { 0x125D, 0x1988, 0x103C, 0x001A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, /* HP OmniBook 6100 */
1013         { 0x125D, 0x1988, 0x107B, 0x340A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1014         { 0x125D, 0x1988, 0x107B, 0x3450, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1015         { 0x125D, 0x1988, 0x109F, 0x3134, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1016         { 0x125D, 0x1988, 0x109F, 0x3161, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1017         { 0x125D, 0x1988, 0x144D, 0x3280, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1018         { 0x125D, 0x1988, 0x144D, 0x3281, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1019         { 0x125D, 0x1988, 0x144D, 0xC002, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1020         { 0x125D, 0x1988, 0x144D, 0xC003, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1021         { 0x125D, 0x1988, 0x1509, 0x1740, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1022         { 0x125D, 0x1988, 0x1610, 0x0010, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
1023         { 0x125D, 0x1988, 0x1042, 0x1042, HV_CTRL_ENABLE, 0 },
1024         { 0x125D, 0x1988, 0x107B, 0x9500, HV_CTRL_ENABLE, 0 },
1025         { 0x125D, 0x1988, 0x14FF, 0x0F06, HV_CTRL_ENABLE, 0 },
1026         { 0x125D, 0x1988, 0x1558, 0x8586, HV_CTRL_ENABLE, 0 },
1027         { 0x125D, 0x1988, 0x161F, 0x2011, HV_CTRL_ENABLE, 0 },
1028         /* Maestro3 chips */
1029         { 0x125D, 0x1998, 0x103C, 0x000E, HV_CTRL_ENABLE, 0 },
1030         { 0x125D, 0x1998, 0x103C, 0x0010, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 6000 */
1031         { 0x125D, 0x1998, 0x103C, 0x0011, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 500 */
1032         { 0x125D, 0x1998, 0x103C, 0x001B, HV_CTRL_ENABLE, 0 },
1033         { 0x125D, 0x1998, 0x104D, 0x80A6, HV_CTRL_ENABLE, 0 },
1034         { 0x125D, 0x1998, 0x104D, 0x80AA, HV_CTRL_ENABLE, 0 },
1035         { 0x125D, 0x1998, 0x107B, 0x5300, HV_CTRL_ENABLE, 0 },
1036         { 0x125D, 0x1998, 0x110A, 0x1998, HV_CTRL_ENABLE, 0 },
1037         { 0x125D, 0x1998, 0x13BD, 0x1015, HV_CTRL_ENABLE, 0 },
1038         { 0x125D, 0x1998, 0x13BD, 0x101C, HV_CTRL_ENABLE, 0 },
1039         { 0x125D, 0x1998, 0x13BD, 0x1802, HV_CTRL_ENABLE, 0 },
1040         { 0x125D, 0x1998, 0x1599, 0x0715, HV_CTRL_ENABLE, 0 },
1041         { 0x125D, 0x1998, 0x5643, 0x5643, HV_CTRL_ENABLE, 0 },
1042         { 0x125D, 0x199A, 0x144D, 0x3260, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1043         { 0x125D, 0x199A, 0x144D, 0x3261, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1044         { 0x125D, 0x199A, 0x144D, 0xC000, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1045         { 0x125D, 0x199A, 0x144D, 0xC001, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1046         { 0 }
1047 };
1048
1049 /*
1050  * lowlevel functions
1051  */
1052
1053 static inline void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
1054 {
1055         outw(value, chip->iobase + reg);
1056 }
1057
1058 static inline u16 snd_m3_inw(m3_t *chip, unsigned long reg)
1059 {
1060         return inw(chip->iobase + reg);
1061 }
1062
1063 static inline void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
1064 {
1065         outb(value, chip->iobase + reg);
1066 }
1067
1068 static inline u8 snd_m3_inb(m3_t *chip, unsigned long reg)
1069 {
1070         return inb(chip->iobase + reg);
1071 }
1072
1073 /*
1074  * access 16bit words to the code or data regions of the dsp's memory.
1075  * index addresses 16bit words.
1076  */
1077 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1078 {
1079         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1080         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1081         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1082 }
1083
1084 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1085 {
1086         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1087         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1088         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1089 }
1090
1091 static void snd_m3_assp_halt(m3_t *chip)
1092 {
1093         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1094         msleep(10);
1095         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1096 }
1097
1098 static void snd_m3_assp_continue(m3_t *chip)
1099 {
1100         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1101 }
1102
1103
1104 /*
1105  * This makes me sad. the maestro3 has lists
1106  * internally that must be packed.. 0 terminates,
1107  * apparently, or maybe all unused entries have
1108  * to be 0, the lists have static lengths set
1109  * by the binary code images.
1110  */
1111
1112 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1113 {
1114         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1115                           list->mem_addr + list->curlen,
1116                           val);
1117         return list->curlen++;
1118 }
1119
1120 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1121 {
1122         u16  val;
1123         int lastindex = list->curlen - 1;
1124
1125         if (index != lastindex) {
1126                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1127                                        list->mem_addr + lastindex);
1128                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1129                                   list->mem_addr + index,
1130                                   val);
1131         }
1132
1133         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1134                           list->mem_addr + lastindex,
1135                           0);
1136
1137         list->curlen--;
1138 }
1139
1140 static void snd_m3_inc_timer_users(m3_t *chip)
1141 {
1142         chip->timer_users++;
1143         if (chip->timer_users != 1)
1144                 return;
1145
1146         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1147                           KDATA_TIMER_COUNT_RELOAD,
1148                           240);
1149
1150         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1151                           KDATA_TIMER_COUNT_CURRENT,
1152                           240);
1153
1154         snd_m3_outw(chip,
1155                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1156                     HOST_INT_CTRL);
1157 }
1158
1159 static void snd_m3_dec_timer_users(m3_t *chip)
1160 {
1161         chip->timer_users--;
1162         if (chip->timer_users > 0)
1163                 return;
1164
1165         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1166                           KDATA_TIMER_COUNT_RELOAD,
1167                           0);
1168
1169         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1170                           KDATA_TIMER_COUNT_CURRENT,
1171                           0);
1172
1173         snd_m3_outw(chip,
1174                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1175                     HOST_INT_CTRL);
1176 }
1177
1178 /*
1179  * start/stop
1180  */
1181
1182 /* spinlock held! */
1183 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1184 {
1185         if (! s || ! subs)
1186                 return -EINVAL;
1187
1188         snd_m3_inc_timer_users(chip);
1189         switch (subs->stream) {
1190         case SNDRV_PCM_STREAM_PLAYBACK:
1191                 chip->dacs_active++;
1192                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1193                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1194                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1195                                   KDATA_MIXER_TASK_NUMBER,
1196                                   chip->dacs_active);
1197                 break;
1198         case SNDRV_PCM_STREAM_CAPTURE:
1199                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1200                                   KDATA_ADC1_REQUEST, 1);
1201                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1202                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1203                 break;
1204         }
1205         return 0;
1206 }
1207
1208 /* spinlock held! */
1209 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1210 {
1211         if (! s || ! subs)
1212                 return -EINVAL;
1213
1214         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1215                           s->inst.data + CDATA_INSTANCE_READY, 0);
1216         snd_m3_dec_timer_users(chip);
1217         switch (subs->stream) {
1218         case SNDRV_PCM_STREAM_PLAYBACK:
1219                 chip->dacs_active--;
1220                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1221                                   KDATA_MIXER_TASK_NUMBER,
1222                                   chip->dacs_active);
1223                 break;
1224         case SNDRV_PCM_STREAM_CAPTURE:
1225                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1226                                   KDATA_ADC1_REQUEST, 0);
1227                 break;
1228         }
1229         return 0;
1230 }
1231
1232 static int
1233 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1234 {
1235         m3_t *chip = snd_pcm_substream_chip(subs);
1236         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1237         int err = -EINVAL;
1238
1239         snd_assert(s != NULL, return -ENXIO);
1240
1241         spin_lock(&chip->reg_lock);
1242         switch (cmd) {
1243         case SNDRV_PCM_TRIGGER_START:
1244         case SNDRV_PCM_TRIGGER_RESUME:
1245                 if (s->running)
1246                         err = -EBUSY;
1247                 else {
1248                         s->running = 1;
1249                         err = snd_m3_pcm_start(chip, s, subs);
1250                 }
1251                 break;
1252         case SNDRV_PCM_TRIGGER_STOP:
1253         case SNDRV_PCM_TRIGGER_SUSPEND:
1254                 if (! s->running)
1255                         err = 0; /* should return error? */
1256                 else {
1257                         s->running = 0;
1258                         err = snd_m3_pcm_stop(chip, s, subs);
1259                 }
1260                 break;
1261         }
1262         spin_unlock(&chip->reg_lock);
1263         return err;
1264 }
1265
1266 /*
1267  * setup
1268  */
1269 static void
1270 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1271 {
1272         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1273         snd_pcm_runtime_t *runtime = subs->runtime;
1274
1275         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1276                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1277                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1278         } else {
1279                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1280                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1281         }
1282         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1283         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1284
1285         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1286         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1287         s->hwptr = 0;
1288         s->count = 0;
1289
1290 #define LO(x) ((x) & 0xffff)
1291 #define HI(x) LO((x) >> 16)
1292
1293         /* host dma buffer pointers */
1294         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1295                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1296                           LO(s->buffer_addr));
1297
1298         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1299                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1300                           HI(s->buffer_addr));
1301
1302         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1303                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1304                           LO(s->buffer_addr + s->dma_size));
1305
1306         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1307                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1308                           HI(s->buffer_addr + s->dma_size));
1309
1310         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1311                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1312                           LO(s->buffer_addr));
1313
1314         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1315                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1316                           HI(s->buffer_addr));
1317 #undef LO
1318 #undef HI
1319
1320         /* dsp buffers */
1321
1322         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1323                           s->inst.data + CDATA_IN_BUF_BEGIN,
1324                           dsp_in_buffer);
1325
1326         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1327                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1328                           dsp_in_buffer + (dsp_in_size / 2));
1329
1330         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1331                           s->inst.data + CDATA_IN_BUF_HEAD,
1332                           dsp_in_buffer);
1333
1334         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1335                           s->inst.data + CDATA_IN_BUF_TAIL,
1336                           dsp_in_buffer);
1337
1338         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1339                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1340                           dsp_out_buffer);
1341
1342         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1343                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1344                           dsp_out_buffer + (dsp_out_size / 2));
1345
1346         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1347                           s->inst.data + CDATA_OUT_BUF_HEAD,
1348                           dsp_out_buffer);
1349
1350         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1351                           s->inst.data + CDATA_OUT_BUF_TAIL,
1352                           dsp_out_buffer);
1353 }
1354
1355 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1356 {
1357         u32 freq;
1358
1359         /*
1360          * put us in the lists if we're not already there
1361          */
1362         if (! s->in_lists) {
1363                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1364                                               s->inst.data >> DP_SHIFT_COUNT);
1365                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1366                                               s->inst.data >> DP_SHIFT_COUNT);
1367                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1368                                               s->inst.data >> DP_SHIFT_COUNT);
1369                 s->in_lists = 1;
1370         }
1371
1372         /* write to 'mono' word */
1373         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1375                           runtime->channels == 2 ? 0 : 1);
1376         /* write to '8bit' word */
1377         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1378                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1379                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1380
1381         /* set up dac/adc rate */
1382         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1383         if (freq)
1384                 freq--;
1385
1386         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1387                           s->inst.data + CDATA_FREQUENCY,
1388                           freq);
1389 }
1390
1391
1392 static struct play_vals {
1393         u16 addr, val;
1394 } pv[] = {
1395         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1396         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1397         {SRC3_DIRECTION_OFFSET, 0} ,
1398         /* +1, +2 are stereo/16 bit */
1399         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1400         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1401         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1402         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1403         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1404         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1405         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1406         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1407         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1408         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1409         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1410         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1411         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1412         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1413         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1414         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1415         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1416 };
1417
1418
1419 /* the mode passed should be already shifted and masked */
1420 static void
1421 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1422 {
1423         unsigned int i;
1424
1425         /*
1426          * some per client initializers
1427          */
1428
1429         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1430                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1431                           s->inst.data + 40 + 8);
1432
1433         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1434                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1435                           s->inst.code + MINISRC_COEF_LOC);
1436
1437         /* enable or disable low pass filter? */
1438         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1439                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1440                           subs->runtime->rate > 45000 ? 0xff : 0);
1441
1442         /* tell it which way dma is going? */
1443         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1444                           s->inst.data + CDATA_DMA_CONTROL,
1445                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1446
1447         /*
1448          * set an armload of static initializers
1449          */
1450         for (i = 0; i < ARRAY_SIZE(pv); i++)
1451                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1452                                   s->inst.data + pv[i].addr, pv[i].val);
1453 }
1454
1455 /*
1456  *    Native record driver
1457  */
1458 static struct rec_vals {
1459         u16 addr, val;
1460 } rv[] = {
1461         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1462         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1463         {SRC3_DIRECTION_OFFSET, 1} ,
1464         /* +1, +2 are stereo/16 bit */
1465         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1466         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1467         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1468         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1469         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1470         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1471         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1472         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1473         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1474         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1475         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1476         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1477         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1478         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1479         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1480         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1481         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1482         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1483         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1484 };
1485
1486 static void
1487 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1488 {
1489         unsigned int i;
1490
1491         /*
1492          * some per client initializers
1493          */
1494
1495         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1496                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1497                           s->inst.data + 40 + 8);
1498
1499         /* tell it which way dma is going? */
1500         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1501                           s->inst.data + CDATA_DMA_CONTROL,
1502                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1503                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1504
1505         /*
1506          * set an armload of static initializers
1507          */
1508         for (i = 0; i < ARRAY_SIZE(rv); i++)
1509                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1510                                   s->inst.data + rv[i].addr, rv[i].val);
1511 }
1512
1513 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1514                                 snd_pcm_hw_params_t * hw_params)
1515 {
1516         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1517         int err;
1518
1519         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1520                 return err;
1521         /* set buffer address */
1522         s->buffer_addr = substream->runtime->dma_addr;
1523         if (s->buffer_addr & 0x3) {
1524                 snd_printk("oh my, not aligned\n");
1525                 s->buffer_addr = s->buffer_addr & ~0x3;
1526         }
1527         return 0;
1528 }
1529
1530 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1531 {
1532         m3_dma_t *s;
1533
1534         if (substream->runtime->private_data == NULL)
1535                 return 0;
1536         s = (m3_dma_t*) substream->runtime->private_data;
1537         snd_pcm_lib_free_pages(substream);
1538         s->buffer_addr = 0;
1539         return 0;
1540 }
1541
1542 static int
1543 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1544 {
1545         m3_t *chip = snd_pcm_substream_chip(subs);
1546         snd_pcm_runtime_t *runtime = subs->runtime;
1547         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1548
1549         snd_assert(s != NULL, return -ENXIO);
1550
1551         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1552             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1553                 return -EINVAL;
1554         if (runtime->rate > 48000 ||
1555             runtime->rate < 8000)
1556                 return -EINVAL;
1557
1558         spin_lock_irq(&chip->reg_lock);
1559
1560         snd_m3_pcm_setup1(chip, s, subs);
1561
1562         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1563                 snd_m3_playback_setup(chip, s, subs);
1564         else
1565                 snd_m3_capture_setup(chip, s, subs);
1566
1567         snd_m3_pcm_setup2(chip, s, runtime);
1568
1569         spin_unlock_irq(&chip->reg_lock);
1570
1571         return 0;
1572 }
1573
1574 /*
1575  * get current pointer
1576  */
1577 static unsigned int
1578 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1579 {
1580         u16 hi = 0, lo = 0;
1581         int retry = 10;
1582         u32 addr;
1583
1584         /*
1585          * try and get a valid answer
1586          */
1587         while (retry--) {
1588                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1589                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1590
1591                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1592                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1593
1594                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1595                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1596                         break;
1597         }
1598         addr = lo | ((u32)hi<<16);
1599         return (unsigned int)(addr - s->buffer_addr);
1600 }
1601
1602 static snd_pcm_uframes_t
1603 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1604 {
1605         m3_t *chip = snd_pcm_substream_chip(subs);
1606         unsigned int ptr;
1607         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1608         snd_assert(s != NULL, return 0);
1609
1610         spin_lock(&chip->reg_lock);
1611         ptr = snd_m3_get_pointer(chip, s, subs);
1612         spin_unlock(&chip->reg_lock);
1613         return bytes_to_frames(subs->runtime, ptr);
1614 }
1615
1616
1617 /* update pointer */
1618 /* spinlock held! */
1619 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1620 {
1621         snd_pcm_substream_t *subs = s->substream;
1622         unsigned int hwptr;
1623         int diff;
1624
1625         if (! s->running)
1626                 return;
1627
1628         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1629         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1630         s->hwptr = hwptr;
1631         s->count += diff;
1632         if (s->count >= (signed)s->period_size) {
1633                 s->count %= s->period_size;
1634                 spin_unlock(&chip->reg_lock);
1635                 snd_pcm_period_elapsed(subs);
1636                 spin_lock(&chip->reg_lock);
1637         }
1638 }
1639
1640 static void snd_m3_update_hw_volume(unsigned long private_data)
1641 {
1642         m3_t *chip = (m3_t *) private_data;
1643         int x, val;
1644         unsigned long flags;
1645
1646         /* Figure out which volume control button was pushed,
1647            based on differences from the default register
1648            values. */
1649         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1650
1651         /* Reset the volume control registers. */
1652         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1653         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1654         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1655         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1656
1657         if (!chip->master_switch || !chip->master_volume)
1658                 return;
1659
1660         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1661         spin_lock_irqsave(&chip->ac97_lock, flags);
1662
1663         val = chip->ac97->regs[AC97_MASTER_VOL];
1664         switch (x) {
1665         case 0x88:
1666                 /* mute */
1667                 val ^= 0x8000;
1668                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1669                 outw(val, chip->iobase + CODEC_DATA);
1670                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1671                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1672                                &chip->master_switch->id);
1673                 break;
1674         case 0xaa:
1675                 /* volume up */
1676                 if ((val & 0x7f) > 0)
1677                         val--;
1678                 if ((val & 0x7f00) > 0)
1679                         val -= 0x0100;
1680                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1681                 outw(val, chip->iobase + CODEC_DATA);
1682                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1683                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1684                                &chip->master_volume->id);
1685                 break;
1686         case 0x66:
1687                 /* volume down */
1688                 if ((val & 0x7f) < 0x1f)
1689                         val++;
1690                 if ((val & 0x7f00) < 0x1f00)
1691                         val += 0x0100;
1692                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1693                 outw(val, chip->iobase + CODEC_DATA);
1694                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1695                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1696                                &chip->master_volume->id);
1697                 break;
1698         }
1699         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1700 }
1701
1702 static irqreturn_t
1703 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1704 {
1705         m3_t *chip = dev_id;
1706         u8 status;
1707         int i;
1708
1709         status = inb(chip->iobase + HOST_INT_STATUS);
1710
1711         if (status == 0xff)
1712                 return IRQ_NONE;
1713
1714         if (status & HV_INT_PENDING)
1715                 tasklet_hi_schedule(&chip->hwvol_tq);
1716
1717         /*
1718          * ack an assp int if its running
1719          * and has an int pending
1720          */
1721         if (status & ASSP_INT_PENDING) {
1722                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1723                 if (!(ctl & STOP_ASSP_CLOCK)) {
1724                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1725                         if (ctl & DSP2HOST_REQ_TIMER) {
1726                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1727                                 /* update adc/dac info if it was a timer int */
1728                                 spin_lock(&chip->reg_lock);
1729                                 for (i = 0; i < chip->num_substreams; i++) {
1730                                         m3_dma_t *s = &chip->substreams[i];
1731                                         if (s->running)
1732                                                 snd_m3_update_ptr(chip, s);
1733                                 }
1734                                 spin_unlock(&chip->reg_lock);
1735                         }
1736                 }
1737         }
1738
1739 #if 0 /* TODO: not supported yet */
1740         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1741                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1742 #endif
1743
1744         /* ack ints */
1745         outb(status, chip->iobase + HOST_INT_STATUS);
1746
1747         return IRQ_HANDLED;
1748 }
1749
1750
1751 /*
1752  */
1753
1754 static snd_pcm_hardware_t snd_m3_playback =
1755 {
1756         .info =                 (SNDRV_PCM_INFO_MMAP |
1757                                  SNDRV_PCM_INFO_INTERLEAVED |
1758                                  SNDRV_PCM_INFO_MMAP_VALID |
1759                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1760                                  /*SNDRV_PCM_INFO_PAUSE |*/
1761                                  SNDRV_PCM_INFO_RESUME),
1762         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1763         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1764         .rate_min =             8000,
1765         .rate_max =             48000,
1766         .channels_min =         1,
1767         .channels_max =         2,
1768         .buffer_bytes_max =     (512*1024),
1769         .period_bytes_min =     64,
1770         .period_bytes_max =     (512*1024),
1771         .periods_min =          1,
1772         .periods_max =          1024,
1773 };
1774
1775 static snd_pcm_hardware_t snd_m3_capture =
1776 {
1777         .info =                 (SNDRV_PCM_INFO_MMAP |
1778                                  SNDRV_PCM_INFO_INTERLEAVED |
1779                                  SNDRV_PCM_INFO_MMAP_VALID |
1780                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1781                                  /*SNDRV_PCM_INFO_PAUSE |*/
1782                                  SNDRV_PCM_INFO_RESUME),
1783         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1784         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1785         .rate_min =             8000,
1786         .rate_max =             48000,
1787         .channels_min =         1,
1788         .channels_max =         2,
1789         .buffer_bytes_max =     (512*1024),
1790         .period_bytes_min =     64,
1791         .period_bytes_max =     (512*1024),
1792         .periods_min =          1,
1793         .periods_max =          1024,
1794 };
1795
1796
1797 /*
1798  */
1799
1800 static int
1801 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1802 {
1803         int i;
1804         m3_dma_t *s;
1805
1806         spin_lock_irq(&chip->reg_lock);
1807         for (i = 0; i < chip->num_substreams; i++) {
1808                 s = &chip->substreams[i];
1809                 if (! s->opened)
1810                         goto __found;
1811         }
1812         spin_unlock_irq(&chip->reg_lock);
1813         return -ENOMEM;
1814 __found:
1815         s->opened = 1;
1816         s->running = 0;
1817         spin_unlock_irq(&chip->reg_lock);
1818
1819         subs->runtime->private_data = s;
1820         s->substream = subs;
1821
1822         /* set list owners */
1823         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1824                 s->index_list[0] = &chip->mixer_list;
1825         } else
1826                 s->index_list[0] = &chip->adc1_list;
1827         s->index_list[1] = &chip->msrc_list;
1828         s->index_list[2] = &chip->dma_list;
1829
1830         return 0;
1831 }
1832
1833 static void
1834 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1835 {
1836         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1837
1838         if (s == NULL)
1839                 return; /* not opened properly */
1840
1841         spin_lock_irq(&chip->reg_lock);
1842         if (s->substream && s->running)
1843                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1844         if (s->in_lists) {
1845                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1846                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1847                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1848                 s->in_lists = 0;
1849         }
1850         s->running = 0;
1851         s->opened = 0;
1852         spin_unlock_irq(&chip->reg_lock);
1853 }
1854
1855 static int
1856 snd_m3_playback_open(snd_pcm_substream_t *subs)
1857 {
1858         m3_t *chip = snd_pcm_substream_chip(subs);
1859         snd_pcm_runtime_t *runtime = subs->runtime;
1860         int err;
1861
1862         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1863                 return err;
1864
1865         runtime->hw = snd_m3_playback;
1866         snd_pcm_set_sync(subs);
1867
1868         return 0;
1869 }
1870
1871 static int
1872 snd_m3_playback_close(snd_pcm_substream_t *subs)
1873 {
1874         m3_t *chip = snd_pcm_substream_chip(subs);
1875
1876         snd_m3_substream_close(chip, subs);
1877         return 0;
1878 }
1879
1880 static int
1881 snd_m3_capture_open(snd_pcm_substream_t *subs)
1882 {
1883         m3_t *chip = snd_pcm_substream_chip(subs);
1884         snd_pcm_runtime_t *runtime = subs->runtime;
1885         int err;
1886
1887         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1888                 return err;
1889
1890         runtime->hw = snd_m3_capture;
1891         snd_pcm_set_sync(subs);
1892
1893         return 0;
1894 }
1895
1896 static int
1897 snd_m3_capture_close(snd_pcm_substream_t *subs)
1898 {
1899         m3_t *chip = snd_pcm_substream_chip(subs);
1900
1901         snd_m3_substream_close(chip, subs);
1902         return 0;
1903 }
1904
1905 /*
1906  * create pcm instance
1907  */
1908
1909 static snd_pcm_ops_t snd_m3_playback_ops = {
1910         .open =         snd_m3_playback_open,
1911         .close =        snd_m3_playback_close,
1912         .ioctl =        snd_pcm_lib_ioctl,
1913         .hw_params =    snd_m3_pcm_hw_params,
1914         .hw_free =      snd_m3_pcm_hw_free,
1915         .prepare =      snd_m3_pcm_prepare,
1916         .trigger =      snd_m3_pcm_trigger,
1917         .pointer =      snd_m3_pcm_pointer,
1918 };
1919
1920 static snd_pcm_ops_t snd_m3_capture_ops = {
1921         .open =         snd_m3_capture_open,
1922         .close =        snd_m3_capture_close,
1923         .ioctl =        snd_pcm_lib_ioctl,
1924         .hw_params =    snd_m3_pcm_hw_params,
1925         .hw_free =      snd_m3_pcm_hw_free,
1926         .prepare =      snd_m3_pcm_prepare,
1927         .trigger =      snd_m3_pcm_trigger,
1928         .pointer =      snd_m3_pcm_pointer,
1929 };
1930
1931 static int __devinit
1932 snd_m3_pcm(m3_t * chip, int device)
1933 {
1934         snd_pcm_t *pcm;
1935         int err;
1936
1937         err = snd_pcm_new(chip->card, chip->card->driver, device,
1938                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1939         if (err < 0)
1940                 return err;
1941
1942         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1943         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1944
1945         pcm->private_data = chip;
1946         pcm->info_flags = 0;
1947         strcpy(pcm->name, chip->card->driver);
1948         chip->pcm = pcm;
1949
1950         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1951                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1952
1953         return 0;
1954 }
1955
1956
1957 /*
1958  * ac97 interface
1959  */
1960
1961 /*
1962  * Wait for the ac97 serial bus to be free.
1963  * return nonzero if the bus is still busy.
1964  */
1965 static int snd_m3_ac97_wait(m3_t *chip)
1966 {
1967         int i = 10000;
1968
1969         do {
1970                 if (! (snd_m3_inb(chip, 0x30) & 1))
1971                         return 0;
1972         } while (i-- > 0);
1973
1974         snd_printk("ac97 serial bus busy\n");
1975         return 1;
1976 }
1977
1978 static unsigned short
1979 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1980 {
1981         m3_t *chip = ac97->private_data;
1982         unsigned long flags;
1983         unsigned short data;
1984
1985         if (snd_m3_ac97_wait(chip))
1986                 return 0xffff;
1987         spin_lock_irqsave(&chip->ac97_lock, flags);
1988         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1989         if (snd_m3_ac97_wait(chip))
1990                 return 0xffff;
1991         data = snd_m3_inw(chip, CODEC_DATA);
1992         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1993         return data;
1994 }
1995
1996 static void
1997 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1998 {
1999         m3_t *chip = ac97->private_data;
2000         unsigned long flags;
2001
2002         if (snd_m3_ac97_wait(chip))
2003                 return;
2004         spin_lock_irqsave(&chip->ac97_lock, flags);
2005         snd_m3_outw(chip, val, CODEC_DATA);
2006         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
2007         spin_unlock_irqrestore(&chip->ac97_lock, flags);
2008 }
2009
2010
2011 static void snd_m3_remote_codec_config(int io, int isremote)
2012 {
2013         isremote = isremote ? 1 : 0;
2014
2015         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2016              io + RING_BUS_CTRL_B);
2017         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2018              io + SDO_OUT_DEST_CTRL);
2019         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2020              io + SDO_IN_DEST_CTRL);
2021 }
2022
2023 /*
2024  * hack, returns non zero on err
2025  */
2026 static int snd_m3_try_read_vendor(m3_t *chip)
2027 {
2028         u16 ret;
2029
2030         if (snd_m3_ac97_wait(chip))
2031                 return 1;
2032
2033         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2034
2035         if (snd_m3_ac97_wait(chip))
2036                 return 1;
2037
2038         ret = snd_m3_inw(chip, 0x32);
2039
2040         return (ret == 0) || (ret == 0xffff);
2041 }
2042
2043 static void snd_m3_ac97_reset(m3_t *chip)
2044 {
2045         u16 dir;
2046         int delay1 = 0, delay2 = 0, i;
2047         int io = chip->iobase;
2048
2049         if (chip->allegro_flag) {
2050                 /*
2051                  * the onboard codec on the allegro seems
2052                  * to want to wait a very long time before
2053                  * coming back to life
2054                  */
2055                 delay1 = 50;
2056                 delay2 = 800;
2057         } else {
2058                 /* maestro3 */
2059                 delay1 = 20;
2060                 delay2 = 500;
2061         }
2062
2063         for (i = 0; i < 5; i++) {
2064                 dir = inw(io + GPIO_DIRECTION);
2065                 if (! chip->quirk || ! chip->quirk->irda_workaround)
2066                         dir |= 0x10; /* assuming pci bus master? */
2067
2068                 snd_m3_remote_codec_config(io, 0);
2069
2070                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2071                 udelay(20);
2072
2073                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2074                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2075                 outw(0, io + GPIO_DATA);
2076                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2077
2078                 set_current_state(TASK_UNINTERRUPTIBLE);
2079                 schedule_timeout((delay1 * HZ) / 1000);
2080
2081                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2082                 udelay(5);
2083                 /* ok, bring back the ac-link */
2084                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2085                 outw(~0, io + GPIO_MASK);
2086
2087                 set_current_state(TASK_UNINTERRUPTIBLE);
2088                 schedule_timeout((delay2 * HZ) / 1000);
2089
2090                 if (! snd_m3_try_read_vendor(chip))
2091                         break;
2092
2093                 delay1 += 10;
2094                 delay2 += 100;
2095
2096                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2097                            delay1, delay2);
2098         }
2099
2100 #if 0
2101         /* more gung-ho reset that doesn't
2102          * seem to work anywhere :)
2103          */
2104         tmp = inw(io + RING_BUS_CTRL_A);
2105         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2106         msleep(20);
2107         outw(tmp, io + RING_BUS_CTRL_A);
2108         msleep(50);
2109 #endif
2110 }
2111
2112 static int __devinit snd_m3_mixer(m3_t *chip)
2113 {
2114         ac97_bus_t *pbus;
2115         ac97_template_t ac97;
2116         snd_ctl_elem_id_t id;
2117         int err;
2118         static ac97_bus_ops_t ops = {
2119                 .write = snd_m3_ac97_write,
2120                 .read = snd_m3_ac97_read,
2121         };
2122
2123         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2124                 return err;
2125
2126         memset(&ac97, 0, sizeof(ac97));
2127         ac97.private_data = chip;
2128         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2129                 return err;
2130
2131         /* seems ac97 PCM needs initialization.. hack hack.. */
2132         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2133         set_current_state(TASK_UNINTERRUPTIBLE);
2134         schedule_timeout(HZ / 10);
2135         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2136
2137         memset(&id, 0, sizeof(id));
2138         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2139         strcpy(id.name, "Master Playback Switch");
2140         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2141         memset(&id, 0, sizeof(id));
2142         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2143         strcpy(id.name, "Master Playback Volume");
2144         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2145
2146         return 0;
2147 }
2148
2149
2150 /*
2151  * DSP Code images
2152  */
2153
2154 static u16 assp_kernel_image[] __devinitdata = {
2155     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2156     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2157     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2158     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2159     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2160     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2161     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2162     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2163     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2164     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2165     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2166     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2167     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2168     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2169     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2170     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2171     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2172     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2173     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2174     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2175     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2176     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2177     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2178     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2179     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2180     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2181     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2182     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2183     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2184     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2185     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2186     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2187     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2188     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2189     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2190     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2191     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2192     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2193     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2194     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2195     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2196     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2197     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2198     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2199     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2200     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2201     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2202     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2203     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2204     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2205     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2206     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2207     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2208     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2209     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2210     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2211     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2212     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2213     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2214     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2215     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2216     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2217     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2218     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2219     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2220     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2221     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2222     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2223     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2224     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2225     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2226     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2227     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2228     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2229     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2230     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2231     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2232     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2233     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2234     0xBE3A,
2235 };
2236
2237 /*
2238  * Mini sample rate converter code image
2239  * that is to be loaded at 0x400 on the DSP.
2240  */
2241 static u16 assp_minisrc_image[] __devinitdata = {
2242
2243     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2244     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2245     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2246     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2247     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2248     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2249     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2250     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2251     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2252     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2253     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2254     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2255     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2256     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2257     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2258     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2259     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2260     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2261     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2262     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2263     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2264     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2265     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2266     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2267     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2268     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2269     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2270     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2271     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2272     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2273     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2274     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2275     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2276 };
2277
2278
2279 /*
2280  * initialize ASSP
2281  */
2282
2283 #define MINISRC_LPF_LEN 10
2284 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2285         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2286         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2287 };
2288
2289 static void __devinit snd_m3_assp_init(m3_t *chip)
2290 {
2291         unsigned int i;
2292
2293         /* zero kernel data */
2294         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2295                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2296                                   KDATA_BASE_ADDR + i, 0);
2297
2298         /* zero mixer data? */
2299         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2300                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2301                                   KDATA_BASE_ADDR2 + i, 0);
2302
2303         /* init dma pointer */
2304         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2305                           KDATA_CURRENT_DMA,
2306                           KDATA_DMA_XFER0);
2307
2308         /* write kernel into code memory.. */
2309         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2310                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2311                                   REV_B_CODE_MEMORY_BEGIN + i,
2312                                   assp_kernel_image[i]);
2313         }
2314
2315         /*
2316          * We only have this one client and we know that 0x400
2317          * is free in our kernel's mem map, so lets just
2318          * drop it there.  It seems that the minisrc doesn't
2319          * need vectors, so we won't bother with them..
2320          */
2321         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2322                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2323                                   0x400 + i,
2324                                   assp_minisrc_image[i]);
2325         }
2326
2327         /*
2328          * write the coefficients for the low pass filter?
2329          */
2330         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2331                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2332                                   0x400 + MINISRC_COEF_LOC + i,
2333                                   minisrc_lpf[i]);
2334         }
2335
2336         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2337                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2338                           0x8000);
2339
2340         /*
2341          * the minisrc is the only thing on
2342          * our task list..
2343          */
2344         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2345                           KDATA_TASK0,
2346                           0x400);
2347
2348         /*
2349          * init the mixer number..
2350          */
2351
2352         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2353                           KDATA_MIXER_TASK_NUMBER,0);
2354
2355         /*
2356          * EXTREME KERNEL MASTER VOLUME
2357          */
2358         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2359                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2360         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2361                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2362
2363         chip->mixer_list.curlen = 0;
2364         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2365         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2366         chip->adc1_list.curlen = 0;
2367         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2368         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2369         chip->dma_list.curlen = 0;
2370         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2371         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2372         chip->msrc_list.curlen = 0;
2373         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2374         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2375 }
2376
2377
2378 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2379 {
2380         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2381                                MINISRC_IN_BUFFER_SIZE / 2 +
2382                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2383         int address, i;
2384
2385         /*
2386          * the revb memory map has 0x1100 through 0x1c00
2387          * free.
2388          */
2389
2390         /*
2391          * align instance address to 256 bytes so that it's
2392          * shifted list address is aligned.
2393          * list address = (mem address >> 1) >> 7;
2394          */
2395         data_bytes = (data_bytes + 255) & ~255;
2396         address = 0x1100 + ((data_bytes/2) * index);
2397
2398         if ((address + (data_bytes/2)) >= 0x1c00) {
2399                 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2400                            data_bytes, index, address);
2401                 return -ENOMEM;
2402         }
2403
2404         s->number = index;
2405         s->inst.code = 0x400;
2406         s->inst.data = address;
2407
2408         for (i = data_bytes / 2; i > 0; address++, i--) {
2409                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2410                                   address, 0);
2411         }
2412
2413         return 0;
2414 }
2415
2416
2417 /*
2418  * this works for the reference board, have to find
2419  * out about others
2420  *
2421  * this needs more magic for 4 speaker, but..
2422  */
2423 static void
2424 snd_m3_amp_enable(m3_t *chip, int enable)
2425 {
2426         int io = chip->iobase;
2427         u16 gpo, polarity;
2428
2429         if (! chip->external_amp)
2430                 return;
2431
2432         polarity = enable ? 0 : 1;
2433         polarity = polarity << chip->amp_gpio;
2434         gpo = 1 << chip->amp_gpio;
2435
2436         outw(~gpo, io + GPIO_MASK);
2437
2438         outw(inw(io + GPIO_DIRECTION) | gpo,
2439              io + GPIO_DIRECTION);
2440
2441         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2442              io + GPIO_DATA);
2443
2444         outw(0xffff, io + GPIO_MASK);
2445 }
2446
2447 static int
2448 snd_m3_chip_init(m3_t *chip)
2449 {
2450         struct pci_dev *pcidev = chip->pci;
2451         unsigned long io = chip->iobase;
2452         u32 n;
2453         u16 w;
2454         u8 t; /* makes as much sense as 'n', no? */
2455
2456         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2457         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2458                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2459                DISABLE_LEGACY);
2460         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2461
2462         if (chip->hv_quirk && chip->hv_quirk->is_omnibook) {
2463                 /*
2464                  * Volume buttons on some HP OmniBook laptops don't work
2465                  * correctly. This makes them work for the most part.
2466                  *
2467                  * Volume up and down buttons on the laptop side work.
2468                  * Fn+cursor_up (volme up) works.
2469                  * Fn+cursor_down (volume down) doesn't work.
2470                  * Fn+F7 (mute) works acts as volume up.
2471                  */
2472                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2473                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2474                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2475                 outw(0xffff, io + GPIO_MASK);
2476         }
2477         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2478         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2479         if (chip->hv_quirk)
2480                 n |= chip->hv_quirk->config;
2481         /* For some reason we must always use reduced debounce. */
2482         n |= REDUCED_DEBOUNCE;
2483         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2484         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2485
2486         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2487         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2488         n &= ~INT_CLK_SELECT;
2489         if (!chip->allegro_flag) {
2490                 n &= ~INT_CLK_MULT_ENABLE;
2491                 n |= INT_CLK_SRC_NOT_PCI;
2492         }
2493         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2494         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2495
2496         if (chip->allegro_flag) {
2497                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2498                 n |= IN_CLK_12MHZ_SELECT;
2499                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2500         }
2501
2502         t = inb(chip->iobase + ASSP_CONTROL_A);
2503         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2504         t |= ASSP_CLK_49MHZ_SELECT;
2505         t |= ASSP_0_WS_ENABLE;
2506         outb(t, chip->iobase + ASSP_CONTROL_A);
2507
2508         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2509
2510         outb(0x00, io + HARDWARE_VOL_CTRL);
2511         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2512         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2513         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2514         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2515
2516         return 0;
2517 }
2518
2519 static void
2520 snd_m3_enable_ints(m3_t *chip)
2521 {
2522         unsigned long io = chip->iobase;
2523         unsigned short val;
2524
2525         /* TODO: MPU401 not supported yet */
2526         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2527         if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE))
2528                 val |= HV_INT_ENABLE;
2529         outw(val, io + HOST_INT_CTRL);
2530         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2531              io + ASSP_CONTROL_C);
2532 }
2533
2534
2535 /*
2536  */
2537
2538 static int snd_m3_free(m3_t *chip)
2539 {
2540         m3_dma_t *s;
2541         int i;
2542
2543         if (chip->substreams) {
2544                 spin_lock_irq(&chip->reg_lock);
2545                 for (i = 0; i < chip->num_substreams; i++) {
2546                         s = &chip->substreams[i];
2547                         /* check surviving pcms; this should not happen though.. */
2548                         if (s->substream && s->running)
2549                                 snd_m3_pcm_stop(chip, s, s->substream);
2550                 }
2551                 spin_unlock_irq(&chip->reg_lock);
2552                 kfree(chip->substreams);
2553         }
2554         if (chip->iobase) {
2555                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2556         }
2557
2558 #ifdef CONFIG_PM
2559         vfree(chip->suspend_mem);
2560 #endif
2561
2562         if (chip->irq >= 0) {
2563                 synchronize_irq(chip->irq);
2564                 free_irq(chip->irq, (void *)chip);
2565         }
2566
2567         if (chip->iobase)
2568                 pci_release_regions(chip->pci);
2569
2570         pci_disable_device(chip->pci);
2571         kfree(chip);
2572         return 0;
2573 }
2574
2575
2576 /*
2577  * APM support
2578  */
2579 #ifdef CONFIG_PM
2580 static int m3_suspend(snd_card_t *card, pm_message_t state)
2581 {
2582         m3_t *chip = card->pm_private_data;
2583         int i, index;
2584
2585         if (chip->suspend_mem == NULL)
2586                 return 0;
2587
2588         snd_pcm_suspend_all(chip->pcm);
2589         snd_ac97_suspend(chip->ac97);
2590
2591         msleep(10); /* give the assp a chance to idle.. */
2592
2593         snd_m3_assp_halt(chip);
2594
2595         /* save dsp image */
2596         index = 0;
2597         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2598                 chip->suspend_mem[index++] =
2599                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2600         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2601                 chip->suspend_mem[index++] =
2602                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2603
2604         /* power down apci registers */
2605         snd_m3_outw(chip, 0xffff, 0x54);
2606         snd_m3_outw(chip, 0xffff, 0x56);
2607
2608         pci_disable_device(chip->pci);
2609         return 0;
2610 }
2611
2612 static int m3_resume(snd_card_t *card)
2613 {
2614         m3_t *chip = card->pm_private_data;
2615         int i, index;
2616
2617         if (chip->suspend_mem == NULL)
2618                 return 0;
2619
2620         pci_enable_device(chip->pci);
2621         pci_set_master(chip->pci);
2622
2623         /* first lets just bring everything back. .*/
2624         snd_m3_outw(chip, 0, 0x54);
2625         snd_m3_outw(chip, 0, 0x56);
2626
2627         snd_m3_chip_init(chip);
2628         snd_m3_assp_halt(chip);
2629         snd_m3_ac97_reset(chip);
2630
2631         /* restore dsp image */
2632         index = 0;
2633         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2634                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2635                                   chip->suspend_mem[index++]);
2636         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2637                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2638                                   chip->suspend_mem[index++]);
2639
2640         /* tell the dma engine to restart itself */
2641         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2642                           KDATA_DMA_ACTIVE, 0);
2643
2644         /* restore ac97 registers */
2645         snd_ac97_resume(chip->ac97);
2646
2647         snd_m3_assp_continue(chip);
2648         snd_m3_enable_ints(chip);
2649         snd_m3_amp_enable(chip, 1);
2650
2651         return 0;
2652 }
2653 #endif /* CONFIG_PM */
2654
2655
2656 /*
2657  */
2658
2659 static int snd_m3_dev_free(snd_device_t *device)
2660 {
2661         m3_t *chip = device->device_data;
2662         return snd_m3_free(chip);
2663 }
2664
2665 static int __devinit
2666 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2667               int enable_amp,
2668               int amp_gpio,
2669               m3_t **chip_ret)
2670 {
2671         m3_t *chip;
2672         int i, err;
2673         struct m3_quirk *quirk;
2674         struct m3_hv_quirk *hv_quirk;
2675         static snd_device_ops_t ops = {
2676                 .dev_free =     snd_m3_dev_free,
2677         };
2678
2679         *chip_ret = NULL;
2680
2681         if (pci_enable_device(pci))
2682                 return -EIO;
2683
2684         /* check, if we can restrict PCI DMA transfers to 28 bits */
2685         if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2686             pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2687                 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2688                 pci_disable_device(pci);
2689                 return -ENXIO;
2690         }
2691
2692         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2693         if (chip == NULL) {
2694                 pci_disable_device(pci);
2695                 return -ENOMEM;
2696         }
2697
2698         spin_lock_init(&chip->reg_lock);
2699         spin_lock_init(&chip->ac97_lock);
2700
2701         switch (pci->device) {
2702         case PCI_DEVICE_ID_ESS_ALLEGRO:
2703         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2704         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2705         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2706                 chip->allegro_flag = 1;
2707                 break;
2708         }
2709
2710         chip->card = card;
2711         chip->pci = pci;
2712         chip->irq = -1;
2713
2714         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2715                 if (pci->subsystem_vendor == quirk->vendor &&
2716                     pci->subsystem_device == quirk->device) {
2717                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2718                         chip->quirk = quirk;
2719                         break;
2720                 }
2721         }
2722
2723         for (hv_quirk = m3_hv_quirk_list; hv_quirk->vendor; hv_quirk++) {
2724                 if (pci->vendor == hv_quirk->vendor &&
2725                     pci->device == hv_quirk->device &&
2726                     pci->subsystem_vendor == hv_quirk->subsystem_vendor &&
2727                     pci->subsystem_device == hv_quirk->subsystem_device) {
2728                         chip->hv_quirk = hv_quirk;
2729                         break;
2730                 }
2731         }
2732
2733         chip->external_amp = enable_amp;
2734         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2735                 chip->amp_gpio = amp_gpio;
2736         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2737                 chip->amp_gpio = chip->quirk->amp_gpio;
2738         else if (chip->allegro_flag)
2739                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2740         else /* presumably this is for all 'maestro3's.. */
2741                 chip->amp_gpio = GPO_EXT_AMP_M3;
2742
2743         chip->num_substreams = NR_DSPS;
2744         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2745         if (chip->substreams == NULL) {
2746                 kfree(chip);
2747                 pci_disable_device(pci);
2748                 return -ENOMEM;
2749         }
2750         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2751
2752         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2753                 snd_m3_free(chip);
2754                 return err;
2755         }
2756         chip->iobase = pci_resource_start(pci, 0);
2757
2758         /* just to be sure */
2759         pci_set_master(pci);
2760
2761         snd_m3_chip_init(chip);
2762         snd_m3_assp_halt(chip);
2763
2764         snd_m3_ac97_reset(chip);
2765
2766         snd_m3_assp_init(chip);
2767         snd_m3_amp_enable(chip, 1);
2768
2769         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2770
2771         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2772                         card->driver, (void *)chip)) {
2773                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2774                 snd_m3_free(chip);
2775                 return -ENOMEM;
2776         }
2777         chip->irq = pci->irq;
2778
2779 #ifdef CONFIG_PM
2780         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2781         if (chip->suspend_mem == NULL)
2782                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2783         else
2784                 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2785 #endif
2786
2787         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2788                 snd_m3_free(chip);
2789                 return err;
2790         }
2791
2792         if ((err = snd_m3_mixer(chip)) < 0)
2793                 return err;
2794
2795         for (i = 0; i < chip->num_substreams; i++) {
2796                 m3_dma_t *s = &chip->substreams[i];
2797                 s->chip = chip;
2798                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2799                         return err;
2800         }
2801
2802         if ((err = snd_m3_pcm(chip, 0)) < 0)
2803                 return err;
2804
2805         snd_m3_enable_ints(chip);
2806         snd_m3_assp_continue(chip);
2807
2808         snd_card_set_dev(card, &pci->dev);
2809
2810         *chip_ret = chip;
2811
2812         return 0;
2813 }
2814
2815 /*
2816  */
2817 static int __devinit
2818 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2819 {
2820         static int dev;
2821         snd_card_t *card;
2822         m3_t *chip;
2823         int err;
2824
2825         /* don't pick up modems */
2826         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2827                 return -ENODEV;
2828
2829         if (dev >= SNDRV_CARDS)
2830                 return -ENODEV;
2831         if (!enable[dev]) {
2832                 dev++;
2833                 return -ENOENT;
2834         }
2835
2836         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2837         if (card == NULL)
2838                 return -ENOMEM;
2839
2840         switch (pci->device) {
2841         case PCI_DEVICE_ID_ESS_ALLEGRO:
2842         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2843                 strcpy(card->driver, "Allegro");
2844                 break;
2845         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2846         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2847                 strcpy(card->driver, "Canyon3D-2");
2848                 break;
2849         default:
2850                 strcpy(card->driver, "Maestro3");
2851                 break;
2852         }
2853
2854         if ((err = snd_m3_create(card, pci,
2855                                  external_amp[dev],
2856                                  amp_gpio[dev],
2857                                  &chip)) < 0) {
2858                 snd_card_free(card);
2859                 return err;
2860         }
2861
2862         sprintf(card->shortname, "ESS %s PCI", card->driver);
2863         sprintf(card->longname, "%s at 0x%lx, irq %d",
2864                 card->shortname, chip->iobase, chip->irq);
2865
2866         if ((err = snd_card_register(card)) < 0) {
2867                 snd_card_free(card);
2868                 return err;
2869         }
2870
2871 #if 0 /* TODO: not supported yet */
2872         /* TODO enable midi irq and i/o */
2873         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2874                                   chip->iobase + MPU401_DATA_PORT, 1,
2875                                   chip->irq, 0, &chip->rmidi);
2876         if (err < 0)
2877                 printk(KERN_WARNING "maestro3: no midi support.\n");
2878 #endif
2879
2880         pci_set_drvdata(pci, card);
2881         dev++;
2882         return 0;
2883 }
2884
2885 static void __devexit snd_m3_remove(struct pci_dev *pci)
2886 {
2887         snd_card_free(pci_get_drvdata(pci));
2888         pci_set_drvdata(pci, NULL);
2889 }
2890
2891 static struct pci_driver driver = {
2892         .name = "Maestro3",
2893         .id_table = snd_m3_ids,
2894         .probe = snd_m3_probe,
2895         .remove = __devexit_p(snd_m3_remove),
2896         SND_PCI_PM_CALLBACKS
2897 };
2898
2899 static int __init alsa_card_m3_init(void)
2900 {
2901         return pci_register_driver(&driver);
2902 }
2903
2904 static void __exit alsa_card_m3_exit(void)
2905 {
2906         pci_unregister_driver(&driver);
2907 }
2908
2909 module_init(alsa_card_m3_init)
2910 module_exit(alsa_card_m3_exit)