Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
[pandora-kernel.git] / sound / pci / intel8x0.c
1 /*
2  *   ALSA driver for Intel ICH (i8x0) chipsets
3  *
4  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5  *
6  *
7  *   This code also contains alpha support for SiS 735 chipsets provided
8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9  *   for SiS735, so the code is not fully functional.
10  *
11  *
12  *   This program is free software; you can redistribute it and/or modify
13  *   it under the terms of the GNU General Public License as published by
14  *   the Free Software Foundation; either version 2 of the License, or
15  *   (at your option) any later version.
16  *
17  *   This program is distributed in the hope that it will be useful,
18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *   GNU General Public License for more details.
21  *
22  *   You should have received a copy of the GNU General Public License
23  *   along with this program; if not, write to the Free Software
24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
25
26  *
27  */      
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/pcm.h>
38 #include <sound/ac97_codec.h>
39 #include <sound/info.h>
40 #include <sound/initval.h>
41 /* for 440MX workaround */
42 #include <asm/pgtable.h>
43 #include <asm/cacheflush.h>
44
45 #ifdef CONFIG_KVM_GUEST
46 #include <linux/kvm_para.h>
47 #else
48 #define kvm_para_available() (0)
49 #endif
50
51 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
52 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
53 MODULE_LICENSE("GPL");
54 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
55                 "{Intel,82901AB-ICH0},"
56                 "{Intel,82801BA-ICH2},"
57                 "{Intel,82801CA-ICH3},"
58                 "{Intel,82801DB-ICH4},"
59                 "{Intel,ICH5},"
60                 "{Intel,ICH6},"
61                 "{Intel,ICH7},"
62                 "{Intel,6300ESB},"
63                 "{Intel,ESB2},"
64                 "{Intel,MX440},"
65                 "{SiS,SI7012},"
66                 "{NVidia,nForce Audio},"
67                 "{NVidia,nForce2 Audio},"
68                 "{NVidia,nForce3 Audio},"
69                 "{NVidia,MCP04},"
70                 "{NVidia,MCP501},"
71                 "{NVidia,CK804},"
72                 "{NVidia,CK8},"
73                 "{NVidia,CK8S},"
74                 "{AMD,AMD768},"
75                 "{AMD,AMD8111},"
76                 "{ALI,M5455}}");
77
78 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
79 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
80 static int ac97_clock;
81 static char *ac97_quirk;
82 static int buggy_semaphore;
83 static int buggy_irq = -1; /* auto-check */
84 static int xbox;
85 static int spdif_aclink = -1;
86 static int inside_vm = -1;
87
88 module_param(index, int, 0444);
89 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
90 module_param(id, charp, 0444);
91 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
92 module_param(ac97_clock, int, 0444);
93 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
94 module_param(ac97_quirk, charp, 0444);
95 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
96 module_param(buggy_semaphore, bool, 0444);
97 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
98 module_param(buggy_irq, bool, 0444);
99 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
100 module_param(xbox, bool, 0444);
101 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
102 module_param(spdif_aclink, int, 0444);
103 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
104 module_param(inside_vm, bool, 0444);
105 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
106
107 /* just for backward compatibility */
108 static int enable;
109 module_param(enable, bool, 0444);
110 static int joystick;
111 module_param(joystick, int, 0444);
112
113 /*
114  *  Direct registers
115  */
116 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
117
118 #define ICHREG(x) ICH_REG_##x
119
120 #define DEFINE_REGSET(name,base) \
121 enum { \
122         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
123         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
124         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
125         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
126         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
127         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
128         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
129 };
130
131 /* busmaster blocks */
132 DEFINE_REGSET(OFF, 0);          /* offset */
133 DEFINE_REGSET(PI, 0x00);        /* PCM in */
134 DEFINE_REGSET(PO, 0x10);        /* PCM out */
135 DEFINE_REGSET(MC, 0x20);        /* Mic in */
136
137 /* ICH4 busmaster blocks */
138 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
139 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
140 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
141
142 /* values for each busmaster block */
143
144 /* LVI */
145 #define ICH_REG_LVI_MASK                0x1f
146
147 /* SR */
148 #define ICH_FIFOE                       0x10    /* FIFO error */
149 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
150 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
151 #define ICH_CELV                        0x02    /* current equals last valid */
152 #define ICH_DCH                         0x01    /* DMA controller halted */
153
154 /* PIV */
155 #define ICH_REG_PIV_MASK                0x1f    /* mask */
156
157 /* CR */
158 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
159 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
160 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
161 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
162 #define ICH_STARTBM                     0x01    /* start busmaster operation */
163
164
165 /* global block */
166 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
167 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
168 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
169 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
170 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
171 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
172 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
173 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
174 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
175 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
176 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
177 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
178 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
179 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
180 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
181 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
182 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
183 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
184 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
185 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
186 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
187 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
188 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
189 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
190 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
191 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
192 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
193 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
194 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
195 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
196 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
197 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
198 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
199 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
200 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
201 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
202 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
203 #define   ICH_RCS               0x00008000      /* read completion status */
204 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
205 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
206 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
207 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
208 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
209 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
210 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
211 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
212 #define   ICH_POINT             0x00000040      /* playback interrupt */
213 #define   ICH_PIINT             0x00000020      /* capture interrupt */
214 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
215 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
216 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
217 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
218 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
219 #define   ICH_CAS               0x01            /* codec access semaphore */
220 #define ICH_REG_SDM             0x80
221 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
222 #define   ICH_DI2L_SHIFT        6
223 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
224 #define   ICH_DI1L_SHIFT        4
225 #define   ICH_SE                0x00000008      /* steer enable */
226 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
227
228 #define ICH_MAX_FRAGS           32              /* max hw frags */
229
230
231 /*
232  * registers for Ali5455
233  */
234
235 /* ALi 5455 busmaster blocks */
236 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
237 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
238 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
239 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
240 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
241 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
242 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
243 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
244 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
245 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
246 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
247
248 enum {
249         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
250         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
251         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
252         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
253         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
254         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
255         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
256         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
257         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
258         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
259         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
260         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
261         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
262         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
263         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
264         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
265         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
266         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
267         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
268         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
269         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
270 };
271
272 #define ALI_CAS_SEM_BUSY        0x80000000
273 #define ALI_CPR_ADDR_SECONDARY  0x100
274 #define ALI_CPR_ADDR_READ       0x80
275 #define ALI_CSPSR_CODEC_READY   0x08
276 #define ALI_CSPSR_READ_OK       0x02
277 #define ALI_CSPSR_WRITE_OK      0x01
278
279 /* interrupts for the whole chip by interrupt status register finish */
280  
281 #define ALI_INT_MICIN2          (1<<26)
282 #define ALI_INT_PCMIN2          (1<<25)
283 #define ALI_INT_I2SIN           (1<<24)
284 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
285 #define ALI_INT_SPDIFIN         (1<<22)
286 #define ALI_INT_LFEOUT          (1<<21)
287 #define ALI_INT_CENTEROUT       (1<<20)
288 #define ALI_INT_CODECSPDIFOUT   (1<<19)
289 #define ALI_INT_MICIN           (1<<18)
290 #define ALI_INT_PCMOUT          (1<<17)
291 #define ALI_INT_PCMIN           (1<<16)
292 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
293 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
294 #define ALI_INT_GPIO            (1<<1)
295 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
296                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
297
298 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
299 #define ICH_ALI_SC_AC97_DBL     (1<<30)
300 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
301 #define ICH_ALI_SC_IN_BITS      (3<<18)
302 #define ICH_ALI_SC_OUT_BITS     (3<<16)
303 #define ICH_ALI_SC_6CH_CFG      (3<<14)
304 #define ICH_ALI_SC_PCM_4        (1<<8)
305 #define ICH_ALI_SC_PCM_6        (2<<8)
306 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
307
308 #define ICH_ALI_SS_SEC_ID       (3<<5)
309 #define ICH_ALI_SS_PRI_ID       (3<<3)
310
311 #define ICH_ALI_IF_AC97SP       (1<<21)
312 #define ICH_ALI_IF_MC           (1<<20)
313 #define ICH_ALI_IF_PI           (1<<19)
314 #define ICH_ALI_IF_MC2          (1<<18)
315 #define ICH_ALI_IF_PI2          (1<<17)
316 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
317 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
318 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
319 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
320 #define ICH_ALI_IF_PO_SPDF      (1<<3)
321 #define ICH_ALI_IF_PO           (1<<1)
322
323 /*
324  *  
325  */
326
327 enum {
328         ICHD_PCMIN,
329         ICHD_PCMOUT,
330         ICHD_MIC,
331         ICHD_MIC2,
332         ICHD_PCM2IN,
333         ICHD_SPBAR,
334         ICHD_LAST = ICHD_SPBAR
335 };
336 enum {
337         NVD_PCMIN,
338         NVD_PCMOUT,
339         NVD_MIC,
340         NVD_SPBAR,
341         NVD_LAST = NVD_SPBAR
342 };
343 enum {
344         ALID_PCMIN,
345         ALID_PCMOUT,
346         ALID_MIC,
347         ALID_AC97SPDIFOUT,
348         ALID_SPDIFIN,
349         ALID_SPDIFOUT,
350         ALID_LAST = ALID_SPDIFOUT
351 };
352
353 #define get_ichdev(substream) (substream->runtime->private_data)
354
355 struct ichdev {
356         unsigned int ichd;                      /* ich device number */
357         unsigned long reg_offset;               /* offset to bmaddr */
358         u32 *bdbar;                             /* CPU address (32bit) */
359         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
360         struct snd_pcm_substream *substream;
361         unsigned int physbuf;                   /* physical address (32bit) */
362         unsigned int size;
363         unsigned int fragsize;
364         unsigned int fragsize1;
365         unsigned int position;
366         unsigned int pos_shift;
367         unsigned int last_pos;
368         int frags;
369         int lvi;
370         int lvi_frag;
371         int civ;
372         int ack;
373         int ack_reload;
374         unsigned int ack_bit;
375         unsigned int roff_sr;
376         unsigned int roff_picb;
377         unsigned int int_sta_mask;              /* interrupt status mask */
378         unsigned int ali_slot;                  /* ALI DMA slot */
379         struct ac97_pcm *pcm;
380         int pcm_open_flag;
381         unsigned int page_attr_changed: 1;
382         unsigned int suspended: 1;
383 };
384
385 struct intel8x0 {
386         unsigned int device_type;
387
388         int irq;
389
390         void __iomem *addr;
391         void __iomem *bmaddr;
392
393         struct pci_dev *pci;
394         struct snd_card *card;
395
396         int pcm_devs;
397         struct snd_pcm *pcm[6];
398         struct ichdev ichd[6];
399
400         unsigned multi4: 1,
401                  multi6: 1,
402                  multi8 :1,
403                  dra: 1,
404                  smp20bit: 1;
405         unsigned in_ac97_init: 1,
406                  in_sdin_init: 1;
407         unsigned in_measurement: 1;     /* during ac97 clock measurement */
408         unsigned fix_nocache: 1;        /* workaround for 440MX */
409         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
410         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
411         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
412         unsigned inside_vm: 1;          /* enable VM optimization */
413
414         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
415         unsigned int sdm_saved; /* SDM reg value */
416
417         struct snd_ac97_bus *ac97_bus;
418         struct snd_ac97 *ac97[3];
419         unsigned int ac97_sdin[3];
420         unsigned int max_codecs, ncodecs;
421         unsigned int *codec_bit;
422         unsigned int codec_isr_bits;
423         unsigned int codec_ready_bits;
424
425         spinlock_t reg_lock;
426         
427         u32 bdbars_count;
428         struct snd_dma_buffer bdbars;
429         u32 int_sta_reg;                /* interrupt status register */
430         u32 int_sta_mask;               /* interrupt status mask */
431 };
432
433 static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
434         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
435         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
436         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
437         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
438         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
439         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
440         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
441         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
442         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
443         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
444         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
445         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
446         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
447         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
448         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
449         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
450         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
451         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
452         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
453         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
454         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
455         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
456         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
457         { 0, }
458 };
459
460 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
461
462 /*
463  *  Lowlevel I/O - busmaster
464  */
465
466 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
467 {
468         return ioread8(chip->bmaddr + offset);
469 }
470
471 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
472 {
473         return ioread16(chip->bmaddr + offset);
474 }
475
476 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
477 {
478         return ioread32(chip->bmaddr + offset);
479 }
480
481 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
482 {
483         iowrite8(val, chip->bmaddr + offset);
484 }
485
486 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
487 {
488         iowrite16(val, chip->bmaddr + offset);
489 }
490
491 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
492 {
493         iowrite32(val, chip->bmaddr + offset);
494 }
495
496 /*
497  *  Lowlevel I/O - AC'97 registers
498  */
499
500 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
501 {
502         return ioread16(chip->addr + offset);
503 }
504
505 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
506 {
507         iowrite16(val, chip->addr + offset);
508 }
509
510 /*
511  *  Basic I/O
512  */
513
514 /*
515  * access to AC97 codec via normal i/o (for ICH and SIS7012)
516  */
517
518 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
519 {
520         int time;
521         
522         if (codec > 2)
523                 return -EIO;
524         if (chip->in_sdin_init) {
525                 /* we don't know the ready bit assignment at the moment */
526                 /* so we check any */
527                 codec = chip->codec_isr_bits;
528         } else {
529                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
530         }
531
532         /* codec ready ? */
533         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
534                 return -EIO;
535
536         if (chip->buggy_semaphore)
537                 return 0; /* just ignore ... */
538
539         /* Anyone holding a semaphore for 1 msec should be shot... */
540         time = 100;
541         do {
542                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
543                         return 0;
544                 udelay(10);
545         } while (time--);
546
547         /* access to some forbidden (non existent) ac97 registers will not
548          * reset the semaphore. So even if you don't get the semaphore, still
549          * continue the access. We don't need the semaphore anyway. */
550         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
551                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
552         iagetword(chip, 0);     /* clear semaphore flag */
553         /* I don't care about the semaphore */
554         return -EBUSY;
555 }
556  
557 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
558                                      unsigned short reg,
559                                      unsigned short val)
560 {
561         struct intel8x0 *chip = ac97->private_data;
562         
563         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
564                 if (! chip->in_ac97_init)
565                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
566         }
567         iaputword(chip, reg + ac97->num * 0x80, val);
568 }
569
570 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
571                                               unsigned short reg)
572 {
573         struct intel8x0 *chip = ac97->private_data;
574         unsigned short res;
575         unsigned int tmp;
576
577         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
578                 if (! chip->in_ac97_init)
579                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
580                 res = 0xffff;
581         } else {
582                 res = iagetword(chip, reg + ac97->num * 0x80);
583                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
584                         /* reset RCS and preserve other R/WC bits */
585                         iputdword(chip, ICHREG(GLOB_STA), tmp &
586                                   ~(chip->codec_ready_bits | ICH_GSCI));
587                         if (! chip->in_ac97_init)
588                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
589                         res = 0xffff;
590                 }
591         }
592         return res;
593 }
594
595 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
596                                                    unsigned int codec)
597 {
598         unsigned int tmp;
599
600         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
601                 iagetword(chip, codec * 0x80);
602                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
603                         /* reset RCS and preserve other R/WC bits */
604                         iputdword(chip, ICHREG(GLOB_STA), tmp &
605                                   ~(chip->codec_ready_bits | ICH_GSCI));
606                 }
607         }
608 }
609
610 /*
611  * access to AC97 for Ali5455
612  */
613 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
614 {
615         int count = 0;
616         for (count = 0; count < 0x7f; count++) {
617                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
618                 if (val & mask)
619                         return 0;
620         }
621         if (! chip->in_ac97_init)
622                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
623         return -EBUSY;
624 }
625
626 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
627 {
628         int time = 100;
629         if (chip->buggy_semaphore)
630                 return 0; /* just ignore ... */
631         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
632                 udelay(1);
633         if (! time && ! chip->in_ac97_init)
634                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
635         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
636 }
637
638 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
639 {
640         struct intel8x0 *chip = ac97->private_data;
641         unsigned short data = 0xffff;
642
643         if (snd_intel8x0_ali_codec_semaphore(chip))
644                 goto __err;
645         reg |= ALI_CPR_ADDR_READ;
646         if (ac97->num)
647                 reg |= ALI_CPR_ADDR_SECONDARY;
648         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
649         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
650                 goto __err;
651         data = igetword(chip, ICHREG(ALI_SPR));
652  __err:
653         return data;
654 }
655
656 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
657                                          unsigned short val)
658 {
659         struct intel8x0 *chip = ac97->private_data;
660
661         if (snd_intel8x0_ali_codec_semaphore(chip))
662                 return;
663         iputword(chip, ICHREG(ALI_CPR), val);
664         if (ac97->num)
665                 reg |= ALI_CPR_ADDR_SECONDARY;
666         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
667         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
668 }
669
670
671 /*
672  * DMA I/O
673  */
674 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
675 {
676         int idx;
677         u32 *bdbar = ichdev->bdbar;
678         unsigned long port = ichdev->reg_offset;
679
680         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
681         if (ichdev->size == ichdev->fragsize) {
682                 ichdev->ack_reload = ichdev->ack = 2;
683                 ichdev->fragsize1 = ichdev->fragsize >> 1;
684                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
685                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
686                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
687                                                      ichdev->fragsize1 >> ichdev->pos_shift);
688                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
689                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690                                                      ichdev->fragsize1 >> ichdev->pos_shift);
691                 }
692                 ichdev->frags = 2;
693         } else {
694                 ichdev->ack_reload = ichdev->ack = 1;
695                 ichdev->fragsize1 = ichdev->fragsize;
696                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
697                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
698                                                      (((idx >> 1) * ichdev->fragsize) %
699                                                       ichdev->size));
700                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
701                                                      ichdev->fragsize >> ichdev->pos_shift);
702 #if 0
703                         printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
704                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
705 #endif
706                 }
707                 ichdev->frags = ichdev->size / ichdev->fragsize;
708         }
709         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
710         ichdev->civ = 0;
711         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
712         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
713         ichdev->position = 0;
714 #if 0
715         printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
716                "period_size1 = 0x%x\n",
717                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
718                ichdev->fragsize1);
719 #endif
720         /* clear interrupts */
721         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
722 }
723
724 #ifdef __i386__
725 /*
726  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
727  * which aborts PCI busmaster for audio transfer.  A workaround is to set
728  * the pages as non-cached.  For details, see the errata in
729  *      http://download.intel.com/design/chipsets/specupdt/24505108.pdf
730  */
731 static void fill_nocache(void *buf, int size, int nocache)
732 {
733         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
734         if (nocache)
735                 set_pages_uc(virt_to_page(buf), size);
736         else
737                 set_pages_wb(virt_to_page(buf), size);
738 }
739 #else
740 #define fill_nocache(buf, size, nocache) do { ; } while (0)
741 #endif
742
743 /*
744  *  Interrupt handler
745  */
746
747 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
748 {
749         unsigned long port = ichdev->reg_offset;
750         unsigned long flags;
751         int status, civ, i, step;
752         int ack = 0;
753
754         spin_lock_irqsave(&chip->reg_lock, flags);
755         status = igetbyte(chip, port + ichdev->roff_sr);
756         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
757         if (!(status & ICH_BCIS)) {
758                 step = 0;
759         } else if (civ == ichdev->civ) {
760                 // snd_printd("civ same %d\n", civ);
761                 step = 1;
762                 ichdev->civ++;
763                 ichdev->civ &= ICH_REG_LVI_MASK;
764         } else {
765                 step = civ - ichdev->civ;
766                 if (step < 0)
767                         step += ICH_REG_LVI_MASK + 1;
768                 // if (step != 1)
769                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
770                 ichdev->civ = civ;
771         }
772
773         ichdev->position += step * ichdev->fragsize1;
774         if (! chip->in_measurement)
775                 ichdev->position %= ichdev->size;
776         ichdev->lvi += step;
777         ichdev->lvi &= ICH_REG_LVI_MASK;
778         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
779         for (i = 0; i < step; i++) {
780                 ichdev->lvi_frag++;
781                 ichdev->lvi_frag %= ichdev->frags;
782                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
783 #if 0
784         printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
785                "all = 0x%x, 0x%x\n",
786                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
787                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
788                inl(port + 4), inb(port + ICH_REG_OFF_CR));
789 #endif
790                 if (--ichdev->ack == 0) {
791                         ichdev->ack = ichdev->ack_reload;
792                         ack = 1;
793                 }
794         }
795         spin_unlock_irqrestore(&chip->reg_lock, flags);
796         if (ack && ichdev->substream) {
797                 snd_pcm_period_elapsed(ichdev->substream);
798         }
799         iputbyte(chip, port + ichdev->roff_sr,
800                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
801 }
802
803 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
804 {
805         struct intel8x0 *chip = dev_id;
806         struct ichdev *ichdev;
807         unsigned int status;
808         unsigned int i;
809
810         status = igetdword(chip, chip->int_sta_reg);
811         if (status == 0xffffffff)       /* we are not yet resumed */
812                 return IRQ_NONE;
813
814         if ((status & chip->int_sta_mask) == 0) {
815                 if (status) {
816                         /* ack */
817                         iputdword(chip, chip->int_sta_reg, status);
818                         if (! chip->buggy_irq)
819                                 status = 0;
820                 }
821                 return IRQ_RETVAL(status);
822         }
823
824         for (i = 0; i < chip->bdbars_count; i++) {
825                 ichdev = &chip->ichd[i];
826                 if (status & ichdev->int_sta_mask)
827                         snd_intel8x0_update(chip, ichdev);
828         }
829
830         /* ack them */
831         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
832         
833         return IRQ_HANDLED;
834 }
835
836 /*
837  *  PCM part
838  */
839
840 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
841 {
842         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
843         struct ichdev *ichdev = get_ichdev(substream);
844         unsigned char val = 0;
845         unsigned long port = ichdev->reg_offset;
846
847         switch (cmd) {
848         case SNDRV_PCM_TRIGGER_RESUME:
849                 ichdev->suspended = 0;
850                 /* fallthru */
851         case SNDRV_PCM_TRIGGER_START:
852         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
853                 val = ICH_IOCE | ICH_STARTBM;
854                 ichdev->last_pos = ichdev->position;
855                 break;
856         case SNDRV_PCM_TRIGGER_SUSPEND:
857                 ichdev->suspended = 1;
858                 /* fallthru */
859         case SNDRV_PCM_TRIGGER_STOP:
860                 val = 0;
861                 break;
862         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
863                 val = ICH_IOCE;
864                 break;
865         default:
866                 return -EINVAL;
867         }
868         iputbyte(chip, port + ICH_REG_OFF_CR, val);
869         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
870                 /* wait until DMA stopped */
871                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
872                 /* reset whole DMA things */
873                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
874         }
875         return 0;
876 }
877
878 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
879 {
880         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
881         struct ichdev *ichdev = get_ichdev(substream);
882         unsigned long port = ichdev->reg_offset;
883         static int fiforeg[] = {
884                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
885         };
886         unsigned int val, fifo;
887
888         val = igetdword(chip, ICHREG(ALI_DMACR));
889         switch (cmd) {
890         case SNDRV_PCM_TRIGGER_RESUME:
891                 ichdev->suspended = 0;
892                 /* fallthru */
893         case SNDRV_PCM_TRIGGER_START:
894         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
895                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
896                         /* clear FIFO for synchronization of channels */
897                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
898                         fifo &= ~(0xff << (ichdev->ali_slot % 4));  
899                         fifo |= 0x83 << (ichdev->ali_slot % 4); 
900                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
901                 }
902                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
903                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
904                 /* start DMA */
905                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
906                 break;
907         case SNDRV_PCM_TRIGGER_SUSPEND:
908                 ichdev->suspended = 1;
909                 /* fallthru */
910         case SNDRV_PCM_TRIGGER_STOP:
911         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
912                 /* pause */
913                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
914                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
915                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
916                         ;
917                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
918                         break;
919                 /* reset whole DMA things */
920                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
921                 /* clear interrupts */
922                 iputbyte(chip, port + ICH_REG_OFF_SR,
923                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
924                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
925                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
926                 break;
927         default:
928                 return -EINVAL;
929         }
930         return 0;
931 }
932
933 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
934                                   struct snd_pcm_hw_params *hw_params)
935 {
936         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
937         struct ichdev *ichdev = get_ichdev(substream);
938         struct snd_pcm_runtime *runtime = substream->runtime;
939         int dbl = params_rate(hw_params) > 48000;
940         int err;
941
942         if (chip->fix_nocache && ichdev->page_attr_changed) {
943                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
944                 ichdev->page_attr_changed = 0;
945         }
946         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
947         if (err < 0)
948                 return err;
949         if (chip->fix_nocache) {
950                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
951                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
952                         ichdev->page_attr_changed = 1;
953                 }
954         }
955         if (ichdev->pcm_open_flag) {
956                 snd_ac97_pcm_close(ichdev->pcm);
957                 ichdev->pcm_open_flag = 0;
958         }
959         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
960                                 params_channels(hw_params),
961                                 ichdev->pcm->r[dbl].slots);
962         if (err >= 0) {
963                 ichdev->pcm_open_flag = 1;
964                 /* Force SPDIF setting */
965                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
966                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
967                                           params_rate(hw_params));
968         }
969         return err;
970 }
971
972 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
973 {
974         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
975         struct ichdev *ichdev = get_ichdev(substream);
976
977         if (ichdev->pcm_open_flag) {
978                 snd_ac97_pcm_close(ichdev->pcm);
979                 ichdev->pcm_open_flag = 0;
980         }
981         if (chip->fix_nocache && ichdev->page_attr_changed) {
982                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
983                 ichdev->page_attr_changed = 0;
984         }
985         return snd_pcm_lib_free_pages(substream);
986 }
987
988 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
989                                        struct snd_pcm_runtime *runtime)
990 {
991         unsigned int cnt;
992         int dbl = runtime->rate > 48000;
993
994         spin_lock_irq(&chip->reg_lock);
995         switch (chip->device_type) {
996         case DEVICE_ALI:
997                 cnt = igetdword(chip, ICHREG(ALI_SCR));
998                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
999                 if (runtime->channels == 4 || dbl)
1000                         cnt |= ICH_ALI_SC_PCM_4;
1001                 else if (runtime->channels == 6)
1002                         cnt |= ICH_ALI_SC_PCM_6;
1003                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1004                 break;
1005         case DEVICE_SIS:
1006                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1007                 cnt &= ~ICH_SIS_PCM_246_MASK;
1008                 if (runtime->channels == 4 || dbl)
1009                         cnt |= ICH_SIS_PCM_4;
1010                 else if (runtime->channels == 6)
1011                         cnt |= ICH_SIS_PCM_6;
1012                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1013                 break;
1014         default:
1015                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1016                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1017                 if (runtime->channels == 4 || dbl)
1018                         cnt |= ICH_PCM_4;
1019                 else if (runtime->channels == 6)
1020                         cnt |= ICH_PCM_6;
1021                 else if (runtime->channels == 8)
1022                         cnt |= ICH_PCM_8;
1023                 if (chip->device_type == DEVICE_NFORCE) {
1024                         /* reset to 2ch once to keep the 6 channel data in alignment,
1025                          * to start from Front Left always
1026                          */
1027                         if (cnt & ICH_PCM_246_MASK) {
1028                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1029                                 spin_unlock_irq(&chip->reg_lock);
1030                                 msleep(50); /* grrr... */
1031                                 spin_lock_irq(&chip->reg_lock);
1032                         }
1033                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1034                         if (runtime->sample_bits > 16)
1035                                 cnt |= ICH_PCM_20BIT;
1036                 }
1037                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1038                 break;
1039         }
1040         spin_unlock_irq(&chip->reg_lock);
1041 }
1042
1043 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1044 {
1045         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1046         struct snd_pcm_runtime *runtime = substream->runtime;
1047         struct ichdev *ichdev = get_ichdev(substream);
1048
1049         ichdev->physbuf = runtime->dma_addr;
1050         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1051         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1052         if (ichdev->ichd == ICHD_PCMOUT) {
1053                 snd_intel8x0_setup_pcm_out(chip, runtime);
1054                 if (chip->device_type == DEVICE_INTEL_ICH4)
1055                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1056         }
1057         snd_intel8x0_setup_periods(chip, ichdev);
1058         return 0;
1059 }
1060
1061 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1062 {
1063         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1064         struct ichdev *ichdev = get_ichdev(substream);
1065         size_t ptr1, ptr;
1066         int civ, timeout = 10;
1067         unsigned int position;
1068
1069         spin_lock(&chip->reg_lock);
1070         do {
1071                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1072                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1073                 position = ichdev->position;
1074                 if (ptr1 == 0) {
1075                         udelay(10);
1076                         continue;
1077                 }
1078                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1079                         continue;
1080                 if (chip->inside_vm)
1081                         break;
1082                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1083                         break;
1084         } while (timeout--);
1085         ptr = ichdev->last_pos;
1086         if (ptr1 != 0) {
1087                 ptr1 <<= ichdev->pos_shift;
1088                 ptr = ichdev->fragsize1 - ptr1;
1089                 ptr += position;
1090                 if (ptr < ichdev->last_pos) {
1091                         unsigned int pos_base, last_base;
1092                         pos_base = position / ichdev->fragsize1;
1093                         last_base = ichdev->last_pos / ichdev->fragsize1;
1094                         /* another sanity check; ptr1 can go back to full
1095                          * before the base position is updated
1096                          */
1097                         if (pos_base == last_base)
1098                                 ptr = ichdev->last_pos;
1099                 }
1100         }
1101         ichdev->last_pos = ptr;
1102         spin_unlock(&chip->reg_lock);
1103         if (ptr >= ichdev->size)
1104                 return 0;
1105         return bytes_to_frames(substream->runtime, ptr);
1106 }
1107
1108 static struct snd_pcm_hardware snd_intel8x0_stream =
1109 {
1110         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1111                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1112                                  SNDRV_PCM_INFO_MMAP_VALID |
1113                                  SNDRV_PCM_INFO_PAUSE |
1114                                  SNDRV_PCM_INFO_RESUME),
1115         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1116         .rates =                SNDRV_PCM_RATE_48000,
1117         .rate_min =             48000,
1118         .rate_max =             48000,
1119         .channels_min =         2,
1120         .channels_max =         2,
1121         .buffer_bytes_max =     128 * 1024,
1122         .period_bytes_min =     32,
1123         .period_bytes_max =     128 * 1024,
1124         .periods_min =          1,
1125         .periods_max =          1024,
1126         .fifo_size =            0,
1127 };
1128
1129 static unsigned int channels4[] = {
1130         2, 4,
1131 };
1132
1133 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1134         .count = ARRAY_SIZE(channels4),
1135         .list = channels4,
1136         .mask = 0,
1137 };
1138
1139 static unsigned int channels6[] = {
1140         2, 4, 6,
1141 };
1142
1143 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1144         .count = ARRAY_SIZE(channels6),
1145         .list = channels6,
1146         .mask = 0,
1147 };
1148
1149 static unsigned int channels8[] = {
1150         2, 4, 6, 8,
1151 };
1152
1153 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1154         .count = ARRAY_SIZE(channels8),
1155         .list = channels8,
1156         .mask = 0,
1157 };
1158
1159 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1160 {
1161         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1162         struct snd_pcm_runtime *runtime = substream->runtime;
1163         int err;
1164
1165         ichdev->substream = substream;
1166         runtime->hw = snd_intel8x0_stream;
1167         runtime->hw.rates = ichdev->pcm->rates;
1168         snd_pcm_limit_hw_rates(runtime);
1169         if (chip->device_type == DEVICE_SIS) {
1170                 runtime->hw.buffer_bytes_max = 64*1024;
1171                 runtime->hw.period_bytes_max = 64*1024;
1172         }
1173         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1174                 return err;
1175         runtime->private_data = ichdev;
1176         return 0;
1177 }
1178
1179 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1180 {
1181         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1182         struct snd_pcm_runtime *runtime = substream->runtime;
1183         int err;
1184
1185         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1186         if (err < 0)
1187                 return err;
1188
1189         if (chip->multi8) {
1190                 runtime->hw.channels_max = 8;
1191                 snd_pcm_hw_constraint_list(runtime, 0,
1192                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1193                                                 &hw_constraints_channels8);
1194         } else if (chip->multi6) {
1195                 runtime->hw.channels_max = 6;
1196                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1197                                            &hw_constraints_channels6);
1198         } else if (chip->multi4) {
1199                 runtime->hw.channels_max = 4;
1200                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1201                                            &hw_constraints_channels4);
1202         }
1203         if (chip->dra) {
1204                 snd_ac97_pcm_double_rate_rules(runtime);
1205         }
1206         if (chip->smp20bit) {
1207                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1208                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1209         }
1210         return 0;
1211 }
1212
1213 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1214 {
1215         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1216
1217         chip->ichd[ICHD_PCMOUT].substream = NULL;
1218         return 0;
1219 }
1220
1221 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1222 {
1223         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1224
1225         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1226 }
1227
1228 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1229 {
1230         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1231
1232         chip->ichd[ICHD_PCMIN].substream = NULL;
1233         return 0;
1234 }
1235
1236 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1237 {
1238         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1239
1240         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1241 }
1242
1243 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1244 {
1245         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1246
1247         chip->ichd[ICHD_MIC].substream = NULL;
1248         return 0;
1249 }
1250
1251 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1252 {
1253         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1254
1255         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1256 }
1257
1258 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1259 {
1260         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1261
1262         chip->ichd[ICHD_MIC2].substream = NULL;
1263         return 0;
1264 }
1265
1266 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1267 {
1268         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1269
1270         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1271 }
1272
1273 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1274 {
1275         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1276
1277         chip->ichd[ICHD_PCM2IN].substream = NULL;
1278         return 0;
1279 }
1280
1281 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1282 {
1283         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1284         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1285
1286         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1287 }
1288
1289 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1290 {
1291         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1292         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1293
1294         chip->ichd[idx].substream = NULL;
1295         return 0;
1296 }
1297
1298 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1299 {
1300         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1301         unsigned int val;
1302
1303         spin_lock_irq(&chip->reg_lock);
1304         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1305         val |= ICH_ALI_IF_AC97SP;
1306         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1307         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1308         spin_unlock_irq(&chip->reg_lock);
1309
1310         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1311 }
1312
1313 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1314 {
1315         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1316         unsigned int val;
1317
1318         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1319         spin_lock_irq(&chip->reg_lock);
1320         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1321         val &= ~ICH_ALI_IF_AC97SP;
1322         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1323         spin_unlock_irq(&chip->reg_lock);
1324
1325         return 0;
1326 }
1327
1328 #if 0 // NYI
1329 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1330 {
1331         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1332
1333         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1334 }
1335
1336 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1337 {
1338         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1339
1340         chip->ichd[ALID_SPDIFIN].substream = NULL;
1341         return 0;
1342 }
1343
1344 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1345 {
1346         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1347
1348         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1349 }
1350
1351 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1352 {
1353         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1354
1355         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1356         return 0;
1357 }
1358 #endif
1359
1360 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1361         .open =         snd_intel8x0_playback_open,
1362         .close =        snd_intel8x0_playback_close,
1363         .ioctl =        snd_pcm_lib_ioctl,
1364         .hw_params =    snd_intel8x0_hw_params,
1365         .hw_free =      snd_intel8x0_hw_free,
1366         .prepare =      snd_intel8x0_pcm_prepare,
1367         .trigger =      snd_intel8x0_pcm_trigger,
1368         .pointer =      snd_intel8x0_pcm_pointer,
1369 };
1370
1371 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1372         .open =         snd_intel8x0_capture_open,
1373         .close =        snd_intel8x0_capture_close,
1374         .ioctl =        snd_pcm_lib_ioctl,
1375         .hw_params =    snd_intel8x0_hw_params,
1376         .hw_free =      snd_intel8x0_hw_free,
1377         .prepare =      snd_intel8x0_pcm_prepare,
1378         .trigger =      snd_intel8x0_pcm_trigger,
1379         .pointer =      snd_intel8x0_pcm_pointer,
1380 };
1381
1382 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1383         .open =         snd_intel8x0_mic_open,
1384         .close =        snd_intel8x0_mic_close,
1385         .ioctl =        snd_pcm_lib_ioctl,
1386         .hw_params =    snd_intel8x0_hw_params,
1387         .hw_free =      snd_intel8x0_hw_free,
1388         .prepare =      snd_intel8x0_pcm_prepare,
1389         .trigger =      snd_intel8x0_pcm_trigger,
1390         .pointer =      snd_intel8x0_pcm_pointer,
1391 };
1392
1393 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1394         .open =         snd_intel8x0_mic2_open,
1395         .close =        snd_intel8x0_mic2_close,
1396         .ioctl =        snd_pcm_lib_ioctl,
1397         .hw_params =    snd_intel8x0_hw_params,
1398         .hw_free =      snd_intel8x0_hw_free,
1399         .prepare =      snd_intel8x0_pcm_prepare,
1400         .trigger =      snd_intel8x0_pcm_trigger,
1401         .pointer =      snd_intel8x0_pcm_pointer,
1402 };
1403
1404 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1405         .open =         snd_intel8x0_capture2_open,
1406         .close =        snd_intel8x0_capture2_close,
1407         .ioctl =        snd_pcm_lib_ioctl,
1408         .hw_params =    snd_intel8x0_hw_params,
1409         .hw_free =      snd_intel8x0_hw_free,
1410         .prepare =      snd_intel8x0_pcm_prepare,
1411         .trigger =      snd_intel8x0_pcm_trigger,
1412         .pointer =      snd_intel8x0_pcm_pointer,
1413 };
1414
1415 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1416         .open =         snd_intel8x0_spdif_open,
1417         .close =        snd_intel8x0_spdif_close,
1418         .ioctl =        snd_pcm_lib_ioctl,
1419         .hw_params =    snd_intel8x0_hw_params,
1420         .hw_free =      snd_intel8x0_hw_free,
1421         .prepare =      snd_intel8x0_pcm_prepare,
1422         .trigger =      snd_intel8x0_pcm_trigger,
1423         .pointer =      snd_intel8x0_pcm_pointer,
1424 };
1425
1426 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1427         .open =         snd_intel8x0_playback_open,
1428         .close =        snd_intel8x0_playback_close,
1429         .ioctl =        snd_pcm_lib_ioctl,
1430         .hw_params =    snd_intel8x0_hw_params,
1431         .hw_free =      snd_intel8x0_hw_free,
1432         .prepare =      snd_intel8x0_pcm_prepare,
1433         .trigger =      snd_intel8x0_ali_trigger,
1434         .pointer =      snd_intel8x0_pcm_pointer,
1435 };
1436
1437 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1438         .open =         snd_intel8x0_capture_open,
1439         .close =        snd_intel8x0_capture_close,
1440         .ioctl =        snd_pcm_lib_ioctl,
1441         .hw_params =    snd_intel8x0_hw_params,
1442         .hw_free =      snd_intel8x0_hw_free,
1443         .prepare =      snd_intel8x0_pcm_prepare,
1444         .trigger =      snd_intel8x0_ali_trigger,
1445         .pointer =      snd_intel8x0_pcm_pointer,
1446 };
1447
1448 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1449         .open =         snd_intel8x0_mic_open,
1450         .close =        snd_intel8x0_mic_close,
1451         .ioctl =        snd_pcm_lib_ioctl,
1452         .hw_params =    snd_intel8x0_hw_params,
1453         .hw_free =      snd_intel8x0_hw_free,
1454         .prepare =      snd_intel8x0_pcm_prepare,
1455         .trigger =      snd_intel8x0_ali_trigger,
1456         .pointer =      snd_intel8x0_pcm_pointer,
1457 };
1458
1459 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1460         .open =         snd_intel8x0_ali_ac97spdifout_open,
1461         .close =        snd_intel8x0_ali_ac97spdifout_close,
1462         .ioctl =        snd_pcm_lib_ioctl,
1463         .hw_params =    snd_intel8x0_hw_params,
1464         .hw_free =      snd_intel8x0_hw_free,
1465         .prepare =      snd_intel8x0_pcm_prepare,
1466         .trigger =      snd_intel8x0_ali_trigger,
1467         .pointer =      snd_intel8x0_pcm_pointer,
1468 };
1469
1470 #if 0 // NYI
1471 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1472         .open =         snd_intel8x0_ali_spdifin_open,
1473         .close =        snd_intel8x0_ali_spdifin_close,
1474         .ioctl =        snd_pcm_lib_ioctl,
1475         .hw_params =    snd_intel8x0_hw_params,
1476         .hw_free =      snd_intel8x0_hw_free,
1477         .prepare =      snd_intel8x0_pcm_prepare,
1478         .trigger =      snd_intel8x0_pcm_trigger,
1479         .pointer =      snd_intel8x0_pcm_pointer,
1480 };
1481
1482 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1483         .open =         snd_intel8x0_ali_spdifout_open,
1484         .close =        snd_intel8x0_ali_spdifout_close,
1485         .ioctl =        snd_pcm_lib_ioctl,
1486         .hw_params =    snd_intel8x0_hw_params,
1487         .hw_free =      snd_intel8x0_hw_free,
1488         .prepare =      snd_intel8x0_pcm_prepare,
1489         .trigger =      snd_intel8x0_pcm_trigger,
1490         .pointer =      snd_intel8x0_pcm_pointer,
1491 };
1492 #endif // NYI
1493
1494 struct ich_pcm_table {
1495         char *suffix;
1496         struct snd_pcm_ops *playback_ops;
1497         struct snd_pcm_ops *capture_ops;
1498         size_t prealloc_size;
1499         size_t prealloc_max_size;
1500         int ac97_idx;
1501 };
1502
1503 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1504                                        struct ich_pcm_table *rec)
1505 {
1506         struct snd_pcm *pcm;
1507         int err;
1508         char name[32];
1509
1510         if (rec->suffix)
1511                 sprintf(name, "Intel ICH - %s", rec->suffix);
1512         else
1513                 strcpy(name, "Intel ICH");
1514         err = snd_pcm_new(chip->card, name, device,
1515                           rec->playback_ops ? 1 : 0,
1516                           rec->capture_ops ? 1 : 0, &pcm);
1517         if (err < 0)
1518                 return err;
1519
1520         if (rec->playback_ops)
1521                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1522         if (rec->capture_ops)
1523                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1524
1525         pcm->private_data = chip;
1526         pcm->info_flags = 0;
1527         if (rec->suffix)
1528                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1529         else
1530                 strcpy(pcm->name, chip->card->shortname);
1531         chip->pcm[device] = pcm;
1532
1533         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1534                                               snd_dma_pci_data(chip->pci),
1535                                               rec->prealloc_size, rec->prealloc_max_size);
1536
1537         return 0;
1538 }
1539
1540 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1541         {
1542                 .playback_ops = &snd_intel8x0_playback_ops,
1543                 .capture_ops = &snd_intel8x0_capture_ops,
1544                 .prealloc_size = 64 * 1024,
1545                 .prealloc_max_size = 128 * 1024,
1546         },
1547         {
1548                 .suffix = "MIC ADC",
1549                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1550                 .prealloc_size = 0,
1551                 .prealloc_max_size = 128 * 1024,
1552                 .ac97_idx = ICHD_MIC,
1553         },
1554         {
1555                 .suffix = "MIC2 ADC",
1556                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1557                 .prealloc_size = 0,
1558                 .prealloc_max_size = 128 * 1024,
1559                 .ac97_idx = ICHD_MIC2,
1560         },
1561         {
1562                 .suffix = "ADC2",
1563                 .capture_ops = &snd_intel8x0_capture2_ops,
1564                 .prealloc_size = 0,
1565                 .prealloc_max_size = 128 * 1024,
1566                 .ac97_idx = ICHD_PCM2IN,
1567         },
1568         {
1569                 .suffix = "IEC958",
1570                 .playback_ops = &snd_intel8x0_spdif_ops,
1571                 .prealloc_size = 64 * 1024,
1572                 .prealloc_max_size = 128 * 1024,
1573                 .ac97_idx = ICHD_SPBAR,
1574         },
1575 };
1576
1577 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1578         {
1579                 .playback_ops = &snd_intel8x0_playback_ops,
1580                 .capture_ops = &snd_intel8x0_capture_ops,
1581                 .prealloc_size = 64 * 1024,
1582                 .prealloc_max_size = 128 * 1024,
1583         },
1584         {
1585                 .suffix = "MIC ADC",
1586                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1587                 .prealloc_size = 0,
1588                 .prealloc_max_size = 128 * 1024,
1589                 .ac97_idx = NVD_MIC,
1590         },
1591         {
1592                 .suffix = "IEC958",
1593                 .playback_ops = &snd_intel8x0_spdif_ops,
1594                 .prealloc_size = 64 * 1024,
1595                 .prealloc_max_size = 128 * 1024,
1596                 .ac97_idx = NVD_SPBAR,
1597         },
1598 };
1599
1600 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1601         {
1602                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1603                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1604                 .prealloc_size = 64 * 1024,
1605                 .prealloc_max_size = 128 * 1024,
1606         },
1607         {
1608                 .suffix = "MIC ADC",
1609                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1610                 .prealloc_size = 0,
1611                 .prealloc_max_size = 128 * 1024,
1612                 .ac97_idx = ALID_MIC,
1613         },
1614         {
1615                 .suffix = "IEC958",
1616                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1617                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1618                 .prealloc_size = 64 * 1024,
1619                 .prealloc_max_size = 128 * 1024,
1620                 .ac97_idx = ALID_AC97SPDIFOUT,
1621         },
1622 #if 0 // NYI
1623         {
1624                 .suffix = "HW IEC958",
1625                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1626                 .prealloc_size = 64 * 1024,
1627                 .prealloc_max_size = 128 * 1024,
1628         },
1629 #endif
1630 };
1631
1632 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1633 {
1634         int i, tblsize, device, err;
1635         struct ich_pcm_table *tbl, *rec;
1636
1637         switch (chip->device_type) {
1638         case DEVICE_INTEL_ICH4:
1639                 tbl = intel_pcms;
1640                 tblsize = ARRAY_SIZE(intel_pcms);
1641                 if (spdif_aclink)
1642                         tblsize--;
1643                 break;
1644         case DEVICE_NFORCE:
1645                 tbl = nforce_pcms;
1646                 tblsize = ARRAY_SIZE(nforce_pcms);
1647                 if (spdif_aclink)
1648                         tblsize--;
1649                 break;
1650         case DEVICE_ALI:
1651                 tbl = ali_pcms;
1652                 tblsize = ARRAY_SIZE(ali_pcms);
1653                 break;
1654         default:
1655                 tbl = intel_pcms;
1656                 tblsize = 2;
1657                 break;
1658         }
1659
1660         device = 0;
1661         for (i = 0; i < tblsize; i++) {
1662                 rec = tbl + i;
1663                 if (i > 0 && rec->ac97_idx) {
1664                         /* activate PCM only when associated AC'97 codec */
1665                         if (! chip->ichd[rec->ac97_idx].pcm)
1666                                 continue;
1667                 }
1668                 err = snd_intel8x0_pcm1(chip, device, rec);
1669                 if (err < 0)
1670                         return err;
1671                 device++;
1672         }
1673
1674         chip->pcm_devs = device;
1675         return 0;
1676 }
1677         
1678
1679 /*
1680  *  Mixer part
1681  */
1682
1683 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1684 {
1685         struct intel8x0 *chip = bus->private_data;
1686         chip->ac97_bus = NULL;
1687 }
1688
1689 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1690 {
1691         struct intel8x0 *chip = ac97->private_data;
1692         chip->ac97[ac97->num] = NULL;
1693 }
1694
1695 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1696         /* front PCM */
1697         {
1698                 .exclusive = 1,
1699                 .r = {  {
1700                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1701                                          (1 << AC97_SLOT_PCM_RIGHT) |
1702                                          (1 << AC97_SLOT_PCM_CENTER) |
1703                                          (1 << AC97_SLOT_PCM_SLEFT) |
1704                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1705                                          (1 << AC97_SLOT_LFE)
1706                         },
1707                         {
1708                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1709                                          (1 << AC97_SLOT_PCM_RIGHT) |
1710                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1711                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1712                         }
1713                 }
1714         },
1715         /* PCM IN #1 */
1716         {
1717                 .stream = 1,
1718                 .exclusive = 1,
1719                 .r = {  {
1720                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1721                                          (1 << AC97_SLOT_PCM_RIGHT)
1722                         }
1723                 }
1724         },
1725         /* MIC IN #1 */
1726         {
1727                 .stream = 1,
1728                 .exclusive = 1,
1729                 .r = {  {
1730                                 .slots = (1 << AC97_SLOT_MIC)
1731                         }
1732                 }
1733         },
1734         /* S/PDIF PCM */
1735         {
1736                 .exclusive = 1,
1737                 .spdif = 1,
1738                 .r = {  {
1739                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1740                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1741                         }
1742                 }
1743         },
1744         /* PCM IN #2 */
1745         {
1746                 .stream = 1,
1747                 .exclusive = 1,
1748                 .r = {  {
1749                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1750                                          (1 << AC97_SLOT_PCM_RIGHT)
1751                         }
1752                 }
1753         },
1754         /* MIC IN #2 */
1755         {
1756                 .stream = 1,
1757                 .exclusive = 1,
1758                 .r = {  {
1759                                 .slots = (1 << AC97_SLOT_MIC)
1760                         }
1761                 }
1762         },
1763 };
1764
1765 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1766         {
1767                 .subvendor = 0x0e11,
1768                 .subdevice = 0x000e,
1769                 .name = "Compaq Deskpro EN",    /* AD1885 */
1770                 .type = AC97_TUNE_HP_ONLY
1771         },
1772         {
1773                 .subvendor = 0x0e11,
1774                 .subdevice = 0x008a,
1775                 .name = "Compaq Evo W4000",     /* AD1885 */
1776                 .type = AC97_TUNE_HP_ONLY
1777         },
1778         {
1779                 .subvendor = 0x0e11,
1780                 .subdevice = 0x00b8,
1781                 .name = "Compaq Evo D510C",
1782                 .type = AC97_TUNE_HP_ONLY
1783         },
1784         {
1785                 .subvendor = 0x0e11,
1786                 .subdevice = 0x0860,
1787                 .name = "HP/Compaq nx7010",
1788                 .type = AC97_TUNE_MUTE_LED
1789         },
1790         {
1791                 .subvendor = 0x1014,
1792                 .subdevice = 0x0534,
1793                 .name = "ThinkPad X31",
1794                 .type = AC97_TUNE_INV_EAPD
1795         },
1796         {
1797                 .subvendor = 0x1014,
1798                 .subdevice = 0x1f00,
1799                 .name = "MS-9128",
1800                 .type = AC97_TUNE_ALC_JACK
1801         },
1802         {
1803                 .subvendor = 0x1014,
1804                 .subdevice = 0x0267,
1805                 .name = "IBM NetVista A30p",    /* AD1981B */
1806                 .type = AC97_TUNE_HP_ONLY
1807         },
1808         {
1809                 .subvendor = 0x1025,
1810                 .subdevice = 0x0082,
1811                 .name = "Acer Travelmate 2310",
1812                 .type = AC97_TUNE_HP_ONLY
1813         },
1814         {
1815                 .subvendor = 0x1025,
1816                 .subdevice = 0x0083,
1817                 .name = "Acer Aspire 3003LCi",
1818                 .type = AC97_TUNE_HP_ONLY
1819         },
1820         {
1821                 .subvendor = 0x1028,
1822                 .subdevice = 0x00d8,
1823                 .name = "Dell Precision 530",   /* AD1885 */
1824                 .type = AC97_TUNE_HP_ONLY
1825         },
1826         {
1827                 .subvendor = 0x1028,
1828                 .subdevice = 0x010d,
1829                 .name = "Dell", /* which model?  AD1885 */
1830                 .type = AC97_TUNE_HP_ONLY
1831         },
1832         {
1833                 .subvendor = 0x1028,
1834                 .subdevice = 0x0126,
1835                 .name = "Dell Optiplex GX260",  /* AD1981A */
1836                 .type = AC97_TUNE_HP_ONLY
1837         },
1838         {
1839                 .subvendor = 0x1028,
1840                 .subdevice = 0x012c,
1841                 .name = "Dell Precision 650",   /* AD1981A */
1842                 .type = AC97_TUNE_HP_ONLY
1843         },
1844         {
1845                 .subvendor = 0x1028,
1846                 .subdevice = 0x012d,
1847                 .name = "Dell Precision 450",   /* AD1981B*/
1848                 .type = AC97_TUNE_HP_ONLY
1849         },
1850         {
1851                 .subvendor = 0x1028,
1852                 .subdevice = 0x0147,
1853                 .name = "Dell", /* which model?  AD1981B*/
1854                 .type = AC97_TUNE_HP_ONLY
1855         },
1856         {
1857                 .subvendor = 0x1028,
1858                 .subdevice = 0x0151,
1859                 .name = "Dell Optiplex GX270",  /* AD1981B */
1860                 .type = AC97_TUNE_HP_ONLY
1861         },
1862         {
1863                 .subvendor = 0x1028,
1864                 .subdevice = 0x014e,
1865                 .name = "Dell D800", /* STAC9750/51 */
1866                 .type = AC97_TUNE_HP_ONLY
1867         },
1868         {
1869                 .subvendor = 0x1028,
1870                 .subdevice = 0x0163,
1871                 .name = "Dell Unknown", /* STAC9750/51 */
1872                 .type = AC97_TUNE_HP_ONLY
1873         },
1874         {
1875                 .subvendor = 0x1028,
1876                 .subdevice = 0x016a,
1877                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1878                 .type = AC97_TUNE_HP_ONLY
1879         },
1880         {
1881                 .subvendor = 0x1028,
1882                 .subdevice = 0x0182,
1883                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1884                 .type = AC97_TUNE_HP_ONLY
1885         },
1886         {
1887                 .subvendor = 0x1028,
1888                 .subdevice = 0x0186,
1889                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1890                 .type = AC97_TUNE_HP_MUTE_LED
1891         },
1892         {
1893                 .subvendor = 0x1028,
1894                 .subdevice = 0x0188,
1895                 .name = "Dell Inspiron 6000",
1896                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1897         },
1898         {
1899                 .subvendor = 0x1028,
1900                 .subdevice = 0x0189,
1901                 .name = "Dell Inspiron 9300",
1902                 .type = AC97_TUNE_HP_MUTE_LED
1903         },
1904         {
1905                 .subvendor = 0x1028,
1906                 .subdevice = 0x0191,
1907                 .name = "Dell Inspiron 8600",
1908                 .type = AC97_TUNE_HP_ONLY
1909         },
1910         {
1911                 .subvendor = 0x103c,
1912                 .subdevice = 0x006d,
1913                 .name = "HP zv5000",
1914                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1915         },
1916         {       /* FIXME: which codec? */
1917                 .subvendor = 0x103c,
1918                 .subdevice = 0x00c3,
1919                 .name = "HP xw6000",
1920                 .type = AC97_TUNE_HP_ONLY
1921         },
1922         {
1923                 .subvendor = 0x103c,
1924                 .subdevice = 0x088c,
1925                 .name = "HP nc8000",
1926                 .type = AC97_TUNE_HP_MUTE_LED
1927         },
1928         {
1929                 .subvendor = 0x103c,
1930                 .subdevice = 0x0890,
1931                 .name = "HP nc6000",
1932                 .type = AC97_TUNE_MUTE_LED
1933         },
1934         {
1935                 .subvendor = 0x103c,
1936                 .subdevice = 0x129d,
1937                 .name = "HP xw8000",
1938                 .type = AC97_TUNE_HP_ONLY
1939         },
1940         {
1941                 .subvendor = 0x103c,
1942                 .subdevice = 0x0938,
1943                 .name = "HP nc4200",
1944                 .type = AC97_TUNE_HP_MUTE_LED
1945         },
1946         {
1947                 .subvendor = 0x103c,
1948                 .subdevice = 0x099c,
1949                 .name = "HP nx6110/nc6120",
1950                 .type = AC97_TUNE_HP_MUTE_LED
1951         },
1952         {
1953                 .subvendor = 0x103c,
1954                 .subdevice = 0x0944,
1955                 .name = "HP nc6220",
1956                 .type = AC97_TUNE_HP_MUTE_LED
1957         },
1958         {
1959                 .subvendor = 0x103c,
1960                 .subdevice = 0x0934,
1961                 .name = "HP nc8220",
1962                 .type = AC97_TUNE_HP_MUTE_LED
1963         },
1964         {
1965                 .subvendor = 0x103c,
1966                 .subdevice = 0x12f1,
1967                 .name = "HP xw8200",    /* AD1981B*/
1968                 .type = AC97_TUNE_HP_ONLY
1969         },
1970         {
1971                 .subvendor = 0x103c,
1972                 .subdevice = 0x12f2,
1973                 .name = "HP xw6200",
1974                 .type = AC97_TUNE_HP_ONLY
1975         },
1976         {
1977                 .subvendor = 0x103c,
1978                 .subdevice = 0x3008,
1979                 .name = "HP xw4200",    /* AD1981B*/
1980                 .type = AC97_TUNE_HP_ONLY
1981         },
1982         {
1983                 .subvendor = 0x104d,
1984                 .subdevice = 0x8144,
1985                 .name = "Sony",
1986                 .type = AC97_TUNE_INV_EAPD
1987         },
1988         {
1989                 .subvendor = 0x104d,
1990                 .subdevice = 0x8197,
1991                 .name = "Sony S1XP",
1992                 .type = AC97_TUNE_INV_EAPD
1993         },
1994         {
1995                 .subvendor = 0x104d,
1996                 .subdevice = 0x81c0,
1997                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1998                 .type = AC97_TUNE_INV_EAPD
1999         },
2000         {
2001                 .subvendor = 0x104d,
2002                 .subdevice = 0x81c5,
2003                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2004                 .type = AC97_TUNE_INV_EAPD
2005         },
2006         {
2007                 .subvendor = 0x1043,
2008                 .subdevice = 0x80f3,
2009                 .name = "ASUS ICH5/AD1985",
2010                 .type = AC97_TUNE_AD_SHARING
2011         },
2012         {
2013                 .subvendor = 0x10cf,
2014                 .subdevice = 0x11c3,
2015                 .name = "Fujitsu-Siemens E4010",
2016                 .type = AC97_TUNE_HP_ONLY
2017         },
2018         {
2019                 .subvendor = 0x10cf,
2020                 .subdevice = 0x1225,
2021                 .name = "Fujitsu-Siemens T3010",
2022                 .type = AC97_TUNE_HP_ONLY
2023         },
2024         {
2025                 .subvendor = 0x10cf,
2026                 .subdevice = 0x1253,
2027                 .name = "Fujitsu S6210",        /* STAC9750/51 */
2028                 .type = AC97_TUNE_HP_ONLY
2029         },
2030         {
2031                 .subvendor = 0x10cf,
2032                 .subdevice = 0x127d,
2033                 .name = "Fujitsu Lifebook P7010",
2034                 .type = AC97_TUNE_HP_ONLY
2035         },
2036         {
2037                 .subvendor = 0x10cf,
2038                 .subdevice = 0x127e,
2039                 .name = "Fujitsu Lifebook C1211D",
2040                 .type = AC97_TUNE_HP_ONLY
2041         },
2042         {
2043                 .subvendor = 0x10cf,
2044                 .subdevice = 0x12ec,
2045                 .name = "Fujitsu-Siemens 4010",
2046                 .type = AC97_TUNE_HP_ONLY
2047         },
2048         {
2049                 .subvendor = 0x10cf,
2050                 .subdevice = 0x12f2,
2051                 .name = "Fujitsu-Siemens Celsius H320",
2052                 .type = AC97_TUNE_SWAP_HP
2053         },
2054         {
2055                 .subvendor = 0x10f1,
2056                 .subdevice = 0x2665,
2057                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2058                 .type = AC97_TUNE_HP_ONLY
2059         },
2060         {
2061                 .subvendor = 0x10f1,
2062                 .subdevice = 0x2885,
2063                 .name = "AMD64 Mobo",   /* ALC650 */
2064                 .type = AC97_TUNE_HP_ONLY
2065         },
2066         {
2067                 .subvendor = 0x10f1,
2068                 .subdevice = 0x2895,
2069                 .name = "Tyan Thunder K8WE",
2070                 .type = AC97_TUNE_HP_ONLY
2071         },
2072         {
2073                 .subvendor = 0x10f7,
2074                 .subdevice = 0x834c,
2075                 .name = "Panasonic CF-R4",
2076                 .type = AC97_TUNE_HP_ONLY,
2077         },
2078         {
2079                 .subvendor = 0x110a,
2080                 .subdevice = 0x0056,
2081                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2082                 .type = AC97_TUNE_HP_ONLY
2083         },
2084         {
2085                 .subvendor = 0x11d4,
2086                 .subdevice = 0x5375,
2087                 .name = "ADI AD1985 (discrete)",
2088                 .type = AC97_TUNE_HP_ONLY
2089         },
2090         {
2091                 .subvendor = 0x1462,
2092                 .subdevice = 0x5470,
2093                 .name = "MSI P4 ATX 645 Ultra",
2094                 .type = AC97_TUNE_HP_ONLY
2095         },
2096         {
2097                 .subvendor = 0x161f,
2098                 .subdevice = 0x203a,
2099                 .name = "Gateway 4525GZ",               /* AD1981B */
2100                 .type = AC97_TUNE_INV_EAPD
2101         },
2102         {
2103                 .subvendor = 0x1734,
2104                 .subdevice = 0x0088,
2105                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2106                 .type = AC97_TUNE_HP_ONLY
2107         },
2108         {
2109                 .subvendor = 0x8086,
2110                 .subdevice = 0x2000,
2111                 .mask = 0xfff0,
2112                 .name = "Intel ICH5/AD1985",
2113                 .type = AC97_TUNE_AD_SHARING
2114         },
2115         {
2116                 .subvendor = 0x8086,
2117                 .subdevice = 0x4000,
2118                 .mask = 0xfff0,
2119                 .name = "Intel ICH5/AD1985",
2120                 .type = AC97_TUNE_AD_SHARING
2121         },
2122         {
2123                 .subvendor = 0x8086,
2124                 .subdevice = 0x4856,
2125                 .name = "Intel D845WN (82801BA)",
2126                 .type = AC97_TUNE_SWAP_HP
2127         },
2128         {
2129                 .subvendor = 0x8086,
2130                 .subdevice = 0x4d44,
2131                 .name = "Intel D850EMV2",       /* AD1885 */
2132                 .type = AC97_TUNE_HP_ONLY
2133         },
2134         {
2135                 .subvendor = 0x8086,
2136                 .subdevice = 0x4d56,
2137                 .name = "Intel ICH/AD1885",
2138                 .type = AC97_TUNE_HP_ONLY
2139         },
2140         {
2141                 .subvendor = 0x8086,
2142                 .subdevice = 0x6000,
2143                 .mask = 0xfff0,
2144                 .name = "Intel ICH5/AD1985",
2145                 .type = AC97_TUNE_AD_SHARING
2146         },
2147         {
2148                 .subvendor = 0x8086,
2149                 .subdevice = 0xe000,
2150                 .mask = 0xfff0,
2151                 .name = "Intel ICH5/AD1985",
2152                 .type = AC97_TUNE_AD_SHARING
2153         },
2154 #if 0 /* FIXME: this seems wrong on most boards */
2155         {
2156                 .subvendor = 0x8086,
2157                 .subdevice = 0xa000,
2158                 .mask = 0xfff0,
2159                 .name = "Intel ICH5/AD1985",
2160                 .type = AC97_TUNE_HP_ONLY
2161         },
2162 #endif
2163         { } /* terminator */
2164 };
2165
2166 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2167                                         const char *quirk_override)
2168 {
2169         struct snd_ac97_bus *pbus;
2170         struct snd_ac97_template ac97;
2171         int err;
2172         unsigned int i, codecs;
2173         unsigned int glob_sta = 0;
2174         struct snd_ac97_bus_ops *ops;
2175         static struct snd_ac97_bus_ops standard_bus_ops = {
2176                 .write = snd_intel8x0_codec_write,
2177                 .read = snd_intel8x0_codec_read,
2178         };
2179         static struct snd_ac97_bus_ops ali_bus_ops = {
2180                 .write = snd_intel8x0_ali_codec_write,
2181                 .read = snd_intel8x0_ali_codec_read,
2182         };
2183
2184         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2185         if (!spdif_aclink) {
2186                 switch (chip->device_type) {
2187                 case DEVICE_NFORCE:
2188                         chip->spdif_idx = NVD_SPBAR;
2189                         break;
2190                 case DEVICE_ALI:
2191                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2192                         break;
2193                 case DEVICE_INTEL_ICH4:
2194                         chip->spdif_idx = ICHD_SPBAR;
2195                         break;
2196                 };
2197         }
2198
2199         chip->in_ac97_init = 1;
2200         
2201         memset(&ac97, 0, sizeof(ac97));
2202         ac97.private_data = chip;
2203         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2204         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2205         if (chip->xbox)
2206                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2207         if (chip->device_type != DEVICE_ALI) {
2208                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2209                 ops = &standard_bus_ops;
2210                 chip->in_sdin_init = 1;
2211                 codecs = 0;
2212                 for (i = 0; i < chip->max_codecs; i++) {
2213                         if (! (glob_sta & chip->codec_bit[i]))
2214                                 continue;
2215                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2216                                 snd_intel8x0_codec_read_test(chip, codecs);
2217                                 chip->ac97_sdin[codecs] =
2218                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2219                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2220                                         chip->ac97_sdin[codecs] = 0;
2221                         } else
2222                                 chip->ac97_sdin[codecs] = i;
2223                         codecs++;
2224                 }
2225                 chip->in_sdin_init = 0;
2226                 if (! codecs)
2227                         codecs = 1;
2228         } else {
2229                 ops = &ali_bus_ops;
2230                 codecs = 1;
2231                 /* detect the secondary codec */
2232                 for (i = 0; i < 100; i++) {
2233                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2234                         if (reg & 0x40) {
2235                                 codecs = 2;
2236                                 break;
2237                         }
2238                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2239                         udelay(1);
2240                 }
2241         }
2242         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2243                 goto __err;
2244         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2245         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2246                 pbus->clock = ac97_clock;
2247         /* FIXME: my test board doesn't work well with VRA... */
2248         if (chip->device_type == DEVICE_ALI)
2249                 pbus->no_vra = 1;
2250         else
2251                 pbus->dra = 1;
2252         chip->ac97_bus = pbus;
2253         chip->ncodecs = codecs;
2254
2255         ac97.pci = chip->pci;
2256         for (i = 0; i < codecs; i++) {
2257                 ac97.num = i;
2258                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2259                         if (err != -EACCES)
2260                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2261                         if (i == 0)
2262                                 goto __err;
2263                 }
2264         }
2265         /* tune up the primary codec */
2266         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2267         /* enable separate SDINs for ICH4 */
2268         if (chip->device_type == DEVICE_INTEL_ICH4)
2269                 pbus->isdin = 1;
2270         /* find the available PCM streams */
2271         i = ARRAY_SIZE(ac97_pcm_defs);
2272         if (chip->device_type != DEVICE_INTEL_ICH4)
2273                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2274         if (chip->spdif_idx < 0)
2275                 i--;            /* do not allocate S/PDIF */
2276         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2277         if (err < 0)
2278                 goto __err;
2279         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2280         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2281         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2282         if (chip->spdif_idx >= 0)
2283                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2284         if (chip->device_type == DEVICE_INTEL_ICH4) {
2285                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2286                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2287         }
2288         /* enable separate SDINs for ICH4 */
2289         if (chip->device_type == DEVICE_INTEL_ICH4) {
2290                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2291                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2292                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2293                 if (pcm) {
2294                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2295                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2296                         for (i = 1; i < 4; i++) {
2297                                 if (pcm->r[0].codec[i]) {
2298                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2299                                         break;
2300                                 }
2301                         }
2302                 } else {
2303                         tmp &= ~ICH_SE; /* steer disable */
2304                 }
2305                 iputbyte(chip, ICHREG(SDM), tmp);
2306         }
2307         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2308                 chip->multi4 = 1;
2309                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2310                         chip->multi6 = 1;
2311                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2312                                 chip->multi8 = 1;
2313                 }
2314         }
2315         if (pbus->pcms[0].r[1].rslots[0]) {
2316                 chip->dra = 1;
2317         }
2318         if (chip->device_type == DEVICE_INTEL_ICH4) {
2319                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2320                         chip->smp20bit = 1;
2321         }
2322         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2323                 /* 48kHz only */
2324                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2325         }
2326         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2327                 /* use slot 10/11 for SPDIF */
2328                 u32 val;
2329                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2330                 val |= ICH_PCM_SPDIF_1011;
2331                 iputdword(chip, ICHREG(GLOB_CNT), val);
2332                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2333         }
2334         chip->in_ac97_init = 0;
2335         return 0;
2336
2337  __err:
2338         /* clear the cold-reset bit for the next chance */
2339         if (chip->device_type != DEVICE_ALI)
2340                 iputdword(chip, ICHREG(GLOB_CNT),
2341                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2342         return err;
2343 }
2344
2345
2346 /*
2347  *
2348  */
2349
2350 static void do_ali_reset(struct intel8x0 *chip)
2351 {
2352         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2353         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2354         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2355         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2356         iputdword(chip, ICHREG(ALI_INTERFACECR),
2357                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2358         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2359         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2360 }
2361
2362 #ifdef CONFIG_SND_AC97_POWER_SAVE
2363 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2364         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2365         { } /* end */
2366 };
2367
2368 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2369 {
2370         unsigned int cnt;
2371         /* ACLink on, 2 channels */
2372
2373         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2374                 return -EIO;
2375
2376         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2377         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2378
2379         /* do cold reset - the full ac97 powerdown may leave the controller
2380          * in a warm state but actually it cannot communicate with the codec.
2381          */
2382         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2383         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2384         udelay(10);
2385         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2386         msleep(1);
2387         return 0;
2388 }
2389 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2390         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2391 #else
2392 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2393 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2394 #endif
2395
2396 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2397 {
2398         unsigned long end_time;
2399         unsigned int cnt;
2400         /* ACLink on, 2 channels */
2401         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2402         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2403         /* finish cold or do warm reset */
2404         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2405         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2406         end_time = (jiffies + (HZ / 4)) + 1;
2407         do {
2408                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2409                         return 0;
2410                 schedule_timeout_uninterruptible(1);
2411         } while (time_after_eq(end_time, jiffies));
2412         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2413                    igetdword(chip, ICHREG(GLOB_CNT)));
2414         return -EIO;
2415 }
2416
2417 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2418 {
2419         unsigned long end_time;
2420         unsigned int status, nstatus;
2421         unsigned int cnt;
2422         int err;
2423
2424         /* put logic to right state */
2425         /* first clear status bits */
2426         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2427         if (chip->device_type == DEVICE_NFORCE)
2428                 status |= ICH_NVSPINT;
2429         cnt = igetdword(chip, ICHREG(GLOB_STA));
2430         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2431
2432         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2433                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2434         else
2435                 err = snd_intel8x0_ich_chip_reset(chip);
2436         if (err < 0)
2437                 return err;
2438
2439         if (probing) {
2440                 /* wait for any codec ready status.
2441                  * Once it becomes ready it should remain ready
2442                  * as long as we do not disable the ac97 link.
2443                  */
2444                 end_time = jiffies + HZ;
2445                 do {
2446                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2447                                 chip->codec_isr_bits;
2448                         if (status)
2449                                 break;
2450                         schedule_timeout_uninterruptible(1);
2451                 } while (time_after_eq(end_time, jiffies));
2452                 if (! status) {
2453                         /* no codec is found */
2454                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2455                                    igetdword(chip, ICHREG(GLOB_STA)));
2456                         return -EIO;
2457                 }
2458
2459                 /* wait for other codecs ready status. */
2460                 end_time = jiffies + HZ / 4;
2461                 while (status != chip->codec_isr_bits &&
2462                        time_after_eq(end_time, jiffies)) {
2463                         schedule_timeout_uninterruptible(1);
2464                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2465                                 chip->codec_isr_bits;
2466                 }
2467
2468         } else {
2469                 /* resume phase */
2470                 int i;
2471                 status = 0;
2472                 for (i = 0; i < chip->ncodecs; i++)
2473                         if (chip->ac97[i])
2474                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2475                 /* wait until all the probed codecs are ready */
2476                 end_time = jiffies + HZ;
2477                 do {
2478                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2479                                 chip->codec_isr_bits;
2480                         if (status == nstatus)
2481                                 break;
2482                         schedule_timeout_uninterruptible(1);
2483                 } while (time_after_eq(end_time, jiffies));
2484         }
2485
2486         if (chip->device_type == DEVICE_SIS) {
2487                 /* unmute the output on SIS7012 */
2488                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2489         }
2490         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2491                 /* enable SPDIF interrupt */
2492                 unsigned int val;
2493                 pci_read_config_dword(chip->pci, 0x4c, &val);
2494                 val |= 0x1000000;
2495                 pci_write_config_dword(chip->pci, 0x4c, val);
2496         }
2497         return 0;
2498 }
2499
2500 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2501 {
2502         u32 reg;
2503         int i = 0;
2504
2505         reg = igetdword(chip, ICHREG(ALI_SCR));
2506         if ((reg & 2) == 0)     /* Cold required */
2507                 reg |= 2;
2508         else
2509                 reg |= 1;       /* Warm */
2510         reg &= ~0x80000000;     /* ACLink on */
2511         iputdword(chip, ICHREG(ALI_SCR), reg);
2512
2513         for (i = 0; i < HZ / 2; i++) {
2514                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2515                         goto __ok;
2516                 schedule_timeout_uninterruptible(1);
2517         }
2518         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2519         if (probing)
2520                 return -EIO;
2521
2522  __ok:
2523         for (i = 0; i < HZ / 2; i++) {
2524                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2525                 if (reg & 0x80) /* primary codec */
2526                         break;
2527                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2528                 schedule_timeout_uninterruptible(1);
2529         }
2530
2531         do_ali_reset(chip);
2532         return 0;
2533 }
2534
2535 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2536 {
2537         unsigned int i, timeout;
2538         int err;
2539         
2540         if (chip->device_type != DEVICE_ALI) {
2541                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2542                         return err;
2543                 iagetword(chip, 0);     /* clear semaphore flag */
2544         } else {
2545                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2546                         return err;
2547         }
2548
2549         /* disable interrupts */
2550         for (i = 0; i < chip->bdbars_count; i++)
2551                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2552         /* reset channels */
2553         for (i = 0; i < chip->bdbars_count; i++)
2554                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2555         for (i = 0; i < chip->bdbars_count; i++) {
2556                 timeout = 100000;
2557                 while (--timeout != 0) {
2558                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2559                                 break;
2560                 }
2561                 if (timeout == 0)
2562                         printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2563         }
2564         /* initialize Buffer Descriptor Lists */
2565         for (i = 0; i < chip->bdbars_count; i++)
2566                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2567                           chip->ichd[i].bdbar_addr);
2568         return 0;
2569 }
2570
2571 static int snd_intel8x0_free(struct intel8x0 *chip)
2572 {
2573         unsigned int i;
2574
2575         if (chip->irq < 0)
2576                 goto __hw_end;
2577         /* disable interrupts */
2578         for (i = 0; i < chip->bdbars_count; i++)
2579                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2580         /* reset channels */
2581         for (i = 0; i < chip->bdbars_count; i++)
2582                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2583         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2584                 /* stop the spdif interrupt */
2585                 unsigned int val;
2586                 pci_read_config_dword(chip->pci, 0x4c, &val);
2587                 val &= ~0x1000000;
2588                 pci_write_config_dword(chip->pci, 0x4c, val);
2589         }
2590         /* --- */
2591
2592       __hw_end:
2593         if (chip->irq >= 0)
2594                 free_irq(chip->irq, chip);
2595         if (chip->bdbars.area) {
2596                 if (chip->fix_nocache)
2597                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2598                 snd_dma_free_pages(&chip->bdbars);
2599         }
2600         if (chip->addr)
2601                 pci_iounmap(chip->pci, chip->addr);
2602         if (chip->bmaddr)
2603                 pci_iounmap(chip->pci, chip->bmaddr);
2604         pci_release_regions(chip->pci);
2605         pci_disable_device(chip->pci);
2606         kfree(chip);
2607         return 0;
2608 }
2609
2610 #ifdef CONFIG_PM
2611 /*
2612  * power management
2613  */
2614 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2615 {
2616         struct snd_card *card = pci_get_drvdata(pci);
2617         struct intel8x0 *chip = card->private_data;
2618         int i;
2619
2620         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2621         for (i = 0; i < chip->pcm_devs; i++)
2622                 snd_pcm_suspend_all(chip->pcm[i]);
2623         /* clear nocache */
2624         if (chip->fix_nocache) {
2625                 for (i = 0; i < chip->bdbars_count; i++) {
2626                         struct ichdev *ichdev = &chip->ichd[i];
2627                         if (ichdev->substream && ichdev->page_attr_changed) {
2628                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2629                                 if (runtime->dma_area)
2630                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2631                         }
2632                 }
2633         }
2634         for (i = 0; i < chip->ncodecs; i++)
2635                 snd_ac97_suspend(chip->ac97[i]);
2636         if (chip->device_type == DEVICE_INTEL_ICH4)
2637                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2638
2639         if (chip->irq >= 0) {
2640                 free_irq(chip->irq, chip);
2641                 chip->irq = -1;
2642         }
2643         pci_disable_device(pci);
2644         pci_save_state(pci);
2645         /* The call below may disable built-in speaker on some laptops
2646          * after S2RAM.  So, don't touch it.
2647          */
2648         /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2649         return 0;
2650 }
2651
2652 static int intel8x0_resume(struct pci_dev *pci)
2653 {
2654         struct snd_card *card = pci_get_drvdata(pci);
2655         struct intel8x0 *chip = card->private_data;
2656         int i;
2657
2658         pci_set_power_state(pci, PCI_D0);
2659         pci_restore_state(pci);
2660         if (pci_enable_device(pci) < 0) {
2661                 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2662                        "disabling device\n");
2663                 snd_card_disconnect(card);
2664                 return -EIO;
2665         }
2666         pci_set_master(pci);
2667         snd_intel8x0_chip_init(chip, 0);
2668         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2669                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2670                 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2671                        "disabling device\n", pci->irq);
2672                 snd_card_disconnect(card);
2673                 return -EIO;
2674         }
2675         chip->irq = pci->irq;
2676         synchronize_irq(chip->irq);
2677
2678         /* re-initialize mixer stuff */
2679         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2680                 /* enable separate SDINs for ICH4 */
2681                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2682                 /* use slot 10/11 for SPDIF */
2683                 iputdword(chip, ICHREG(GLOB_CNT),
2684                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2685                           ICH_PCM_SPDIF_1011);
2686         }
2687
2688         /* refill nocache */
2689         if (chip->fix_nocache)
2690                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2691
2692         for (i = 0; i < chip->ncodecs; i++)
2693                 snd_ac97_resume(chip->ac97[i]);
2694
2695         /* refill nocache */
2696         if (chip->fix_nocache) {
2697                 for (i = 0; i < chip->bdbars_count; i++) {
2698                         struct ichdev *ichdev = &chip->ichd[i];
2699                         if (ichdev->substream && ichdev->page_attr_changed) {
2700                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2701                                 if (runtime->dma_area)
2702                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2703                         }
2704                 }
2705         }
2706
2707         /* resume status */
2708         for (i = 0; i < chip->bdbars_count; i++) {
2709                 struct ichdev *ichdev = &chip->ichd[i];
2710                 unsigned long port = ichdev->reg_offset;
2711                 if (! ichdev->substream || ! ichdev->suspended)
2712                         continue;
2713                 if (ichdev->ichd == ICHD_PCMOUT)
2714                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2715                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2716                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2717                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2718                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2719         }
2720
2721         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2722         return 0;
2723 }
2724 #endif /* CONFIG_PM */
2725
2726 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2727
2728 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2729 {
2730         struct snd_pcm_substream *subs;
2731         struct ichdev *ichdev;
2732         unsigned long port;
2733         unsigned long pos, pos1, t;
2734         int civ, timeout = 1000, attempt = 1;
2735         struct timespec start_time, stop_time;
2736
2737         if (chip->ac97_bus->clock != 48000)
2738                 return; /* specified in module option */
2739
2740       __again:
2741         subs = chip->pcm[0]->streams[0].substream;
2742         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2743                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2744                 return;
2745         }
2746         ichdev = &chip->ichd[ICHD_PCMOUT];
2747         ichdev->physbuf = subs->dma_buffer.addr;
2748         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2749         ichdev->substream = NULL; /* don't process interrupts */
2750
2751         /* set rate */
2752         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2753                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2754                 return;
2755         }
2756         snd_intel8x0_setup_periods(chip, ichdev);
2757         port = ichdev->reg_offset;
2758         spin_lock_irq(&chip->reg_lock);
2759         chip->in_measurement = 1;
2760         /* trigger */
2761         if (chip->device_type != DEVICE_ALI)
2762                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2763         else {
2764                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2765                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2766         }
2767         do_posix_clock_monotonic_gettime(&start_time);
2768         spin_unlock_irq(&chip->reg_lock);
2769         msleep(50);
2770         spin_lock_irq(&chip->reg_lock);
2771         /* check the position */
2772         do {
2773                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2774                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2775                 if (pos1 == 0) {
2776                         udelay(10);
2777                         continue;
2778                 }
2779                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2780                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2781                         break;
2782         } while (timeout--);
2783         if (pos1 == 0) {        /* oops, this value is not reliable */
2784                 pos = 0;
2785         } else {
2786                 pos = ichdev->fragsize1;
2787                 pos -= pos1 << ichdev->pos_shift;
2788                 pos += ichdev->position;
2789         }
2790         chip->in_measurement = 0;
2791         do_posix_clock_monotonic_gettime(&stop_time);
2792         /* stop */
2793         if (chip->device_type == DEVICE_ALI) {
2794                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2795                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2796                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2797                         ;
2798         } else {
2799                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2800                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2801                         ;
2802         }
2803         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2804         spin_unlock_irq(&chip->reg_lock);
2805
2806         if (pos == 0) {
2807                 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2808               __retry:
2809                 if (attempt < 3) {
2810                         msleep(300);
2811                         attempt++;
2812                         goto __again;
2813                 }
2814                 goto __end;
2815         }
2816
2817         pos /= 4;
2818         t = stop_time.tv_sec - start_time.tv_sec;
2819         t *= 1000000;
2820         t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2821         printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2822         if (t == 0) {
2823                 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2824                 goto __retry;
2825         }
2826         pos *= 1000;
2827         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2828         if (pos < 40000 || pos >= 60000) {
2829                 /* abnormal value. hw problem? */
2830                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2831                 goto __retry;
2832         } else if (pos > 40500 && pos < 41500)
2833                 /* first exception - 41000Hz reference clock */
2834                 chip->ac97_bus->clock = 41000;
2835         else if (pos > 43600 && pos < 44600)
2836                 /* second exception - 44100HZ reference clock */
2837                 chip->ac97_bus->clock = 44100;
2838         else if (pos < 47500 || pos > 48500)
2839                 /* not 48000Hz, tuning the clock.. */
2840                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2841       __end:
2842         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2843         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2844 }
2845
2846 static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2847         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2848         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2849         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2850         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2851         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2852         { }     /* terminator */
2853 };
2854
2855 static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2856 {
2857         struct pci_dev *pci = chip->pci;
2858         const struct snd_pci_quirk *wl;
2859
2860         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2861         if (!wl)
2862                 return 0;
2863         printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2864                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2865         chip->ac97_bus->clock = wl->value;
2866         return 1;
2867 }
2868
2869 #ifdef CONFIG_PROC_FS
2870 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2871                                    struct snd_info_buffer *buffer)
2872 {
2873         struct intel8x0 *chip = entry->private_data;
2874         unsigned int tmp;
2875
2876         snd_iprintf(buffer, "Intel8x0\n\n");
2877         if (chip->device_type == DEVICE_ALI)
2878                 return;
2879         tmp = igetdword(chip, ICHREG(GLOB_STA));
2880         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2881         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2882         if (chip->device_type == DEVICE_INTEL_ICH4)
2883                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2884         snd_iprintf(buffer, "AC'97 codecs ready    :");
2885         if (tmp & chip->codec_isr_bits) {
2886                 int i;
2887                 static const char *codecs[3] = {
2888                         "primary", "secondary", "tertiary"
2889                 };
2890                 for (i = 0; i < chip->max_codecs; i++)
2891                         if (tmp & chip->codec_bit[i])
2892                                 snd_iprintf(buffer, " %s", codecs[i]);
2893         } else
2894                 snd_iprintf(buffer, " none");
2895         snd_iprintf(buffer, "\n");
2896         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2897             chip->device_type == DEVICE_SIS)
2898                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2899                         chip->ac97_sdin[0],
2900                         chip->ac97_sdin[1],
2901                         chip->ac97_sdin[2]);
2902 }
2903
2904 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2905 {
2906         struct snd_info_entry *entry;
2907
2908         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2909                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2910 }
2911 #else
2912 #define snd_intel8x0_proc_init(x)
2913 #endif
2914
2915 static int snd_intel8x0_dev_free(struct snd_device *device)
2916 {
2917         struct intel8x0 *chip = device->device_data;
2918         return snd_intel8x0_free(chip);
2919 }
2920
2921 struct ich_reg_info {
2922         unsigned int int_sta_mask;
2923         unsigned int offset;
2924 };
2925
2926 static unsigned int ich_codec_bits[3] = {
2927         ICH_PCR, ICH_SCR, ICH_TCR
2928 };
2929 static unsigned int sis_codec_bits[3] = {
2930         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2931 };
2932
2933 static int __devinit snd_intel8x0_create(struct snd_card *card,
2934                                          struct pci_dev *pci,
2935                                          unsigned long device_type,
2936                                          struct intel8x0 ** r_intel8x0)
2937 {
2938         struct intel8x0 *chip;
2939         int err;
2940         unsigned int i;
2941         unsigned int int_sta_masks;
2942         struct ichdev *ichdev;
2943         static struct snd_device_ops ops = {
2944                 .dev_free =     snd_intel8x0_dev_free,
2945         };
2946
2947         static unsigned int bdbars[] = {
2948                 3, /* DEVICE_INTEL */
2949                 6, /* DEVICE_INTEL_ICH4 */
2950                 3, /* DEVICE_SIS */
2951                 6, /* DEVICE_ALI */
2952                 4, /* DEVICE_NFORCE */
2953         };
2954         static struct ich_reg_info intel_regs[6] = {
2955                 { ICH_PIINT, 0 },
2956                 { ICH_POINT, 0x10 },
2957                 { ICH_MCINT, 0x20 },
2958                 { ICH_M2INT, 0x40 },
2959                 { ICH_P2INT, 0x50 },
2960                 { ICH_SPINT, 0x60 },
2961         };
2962         static struct ich_reg_info nforce_regs[4] = {
2963                 { ICH_PIINT, 0 },
2964                 { ICH_POINT, 0x10 },
2965                 { ICH_MCINT, 0x20 },
2966                 { ICH_NVSPINT, 0x70 },
2967         };
2968         static struct ich_reg_info ali_regs[6] = {
2969                 { ALI_INT_PCMIN, 0x40 },
2970                 { ALI_INT_PCMOUT, 0x50 },
2971                 { ALI_INT_MICIN, 0x60 },
2972                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2973                 { ALI_INT_SPDIFIN, 0xa0 },
2974                 { ALI_INT_SPDIFOUT, 0xb0 },
2975         };
2976         struct ich_reg_info *tbl;
2977
2978         *r_intel8x0 = NULL;
2979
2980         if ((err = pci_enable_device(pci)) < 0)
2981                 return err;
2982
2983         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2984         if (chip == NULL) {
2985                 pci_disable_device(pci);
2986                 return -ENOMEM;
2987         }
2988         spin_lock_init(&chip->reg_lock);
2989         chip->device_type = device_type;
2990         chip->card = card;
2991         chip->pci = pci;
2992         chip->irq = -1;
2993
2994         /* module parameters */
2995         chip->buggy_irq = buggy_irq;
2996         chip->buggy_semaphore = buggy_semaphore;
2997         if (xbox)
2998                 chip->xbox = 1;
2999
3000         chip->inside_vm = inside_vm;
3001         if (inside_vm)
3002                 printk(KERN_INFO "intel8x0: enable KVM optimization\n");
3003
3004         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3005             pci->device == PCI_DEVICE_ID_INTEL_440MX)
3006                 chip->fix_nocache = 1; /* enable workaround */
3007
3008         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3009                 kfree(chip);
3010                 pci_disable_device(pci);
3011                 return err;
3012         }
3013
3014         if (device_type == DEVICE_ALI) {
3015                 /* ALI5455 has no ac97 region */
3016                 chip->bmaddr = pci_iomap(pci, 0, 0);
3017                 goto port_inited;
3018         }
3019
3020         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3021                 chip->addr = pci_iomap(pci, 2, 0);
3022         else
3023                 chip->addr = pci_iomap(pci, 0, 0);
3024         if (!chip->addr) {
3025                 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
3026                 snd_intel8x0_free(chip);
3027                 return -EIO;
3028         }
3029         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3030                 chip->bmaddr = pci_iomap(pci, 3, 0);
3031         else
3032                 chip->bmaddr = pci_iomap(pci, 1, 0);
3033         if (!chip->bmaddr) {
3034                 snd_printk(KERN_ERR "Controller space ioremap problem\n");
3035                 snd_intel8x0_free(chip);
3036                 return -EIO;
3037         }
3038
3039  port_inited:
3040         chip->bdbars_count = bdbars[device_type];
3041
3042         /* initialize offsets */
3043         switch (device_type) {
3044         case DEVICE_NFORCE:
3045                 tbl = nforce_regs;
3046                 break;
3047         case DEVICE_ALI:
3048                 tbl = ali_regs;
3049                 break;
3050         default:
3051                 tbl = intel_regs;
3052                 break;
3053         }
3054         for (i = 0; i < chip->bdbars_count; i++) {
3055                 ichdev = &chip->ichd[i];
3056                 ichdev->ichd = i;
3057                 ichdev->reg_offset = tbl[i].offset;
3058                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3059                 if (device_type == DEVICE_SIS) {
3060                         /* SiS 7012 swaps the registers */
3061                         ichdev->roff_sr = ICH_REG_OFF_PICB;
3062                         ichdev->roff_picb = ICH_REG_OFF_SR;
3063                 } else {
3064                         ichdev->roff_sr = ICH_REG_OFF_SR;
3065                         ichdev->roff_picb = ICH_REG_OFF_PICB;
3066                 }
3067                 if (device_type == DEVICE_ALI)
3068                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3069                 /* SIS7012 handles the pcm data in bytes, others are in samples */
3070                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3071         }
3072
3073         /* allocate buffer descriptor lists */
3074         /* the start of each lists must be aligned to 8 bytes */
3075         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3076                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3077                                 &chip->bdbars) < 0) {
3078                 snd_intel8x0_free(chip);
3079                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3080                 return -ENOMEM;
3081         }
3082         /* tables must be aligned to 8 bytes here, but the kernel pages
3083            are much bigger, so we don't care (on i386) */
3084         /* workaround for 440MX */
3085         if (chip->fix_nocache)
3086                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3087         int_sta_masks = 0;
3088         for (i = 0; i < chip->bdbars_count; i++) {
3089                 ichdev = &chip->ichd[i];
3090                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3091                         (i * ICH_MAX_FRAGS * 2);
3092                 ichdev->bdbar_addr = chip->bdbars.addr +
3093                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3094                 int_sta_masks |= ichdev->int_sta_mask;
3095         }
3096         chip->int_sta_reg = device_type == DEVICE_ALI ?
3097                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3098         chip->int_sta_mask = int_sta_masks;
3099
3100         pci_set_master(pci);
3101