sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 /* Power-Management-Code ( CONFIG_PM )
  23  * for ens1371 only ( FIXME )
  24  * derived from cs4281.c, atiixp.c and via82xx.c
  25  * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
  26  * by Kurt J. Bosch
  27  */
  28
  29 #include <asm/io.h>
  30 #include <linux/delay.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/init.h>
  33 #include <linux/pci.h>
  34 #include <linux/slab.h>
  35 #include <linux/gameport.h>
  36 #include <linux/module.h>
  37 #include <linux/mutex.h>
  38
  39 #include <sound/core.h>
  40 #include <sound/control.h>
  41 #include <sound/pcm.h>
  42 #include <sound/rawmidi.h>
  43 #ifdef CHIP1371
  44 #include <sound/ac97_codec.h>
  45 #else
  46 #include <sound/ak4531_codec.h>
  47 #endif
  48 #include <sound/initval.h>
  49 #include <sound/asoundef.h>
  50
  51 #ifndef CHIP1371
  52 #undef CHIP1370
  53 #define CHIP1370
  54 #endif
  55
  56 #ifdef CHIP1370
  57 #define DRIVER_NAME "ENS1370"
  58 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
  59 #else
  60 #define DRIVER_NAME "ENS1371"
  61 #define CHIP_NAME "ES1371"
  62 #endif
  63
  64
  65 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  66 MODULE_LICENSE("GPL");
  67 #ifdef CHIP1370
  68 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  69 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  70                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  71 #endif
  72 #ifdef CHIP1371
  73 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  74 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  75                 "{Ensoniq,AudioPCI ES1373},"
  76                 "{Creative Labs,Ectiva EV1938},"
  77                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  78                 "{Creative Labs,Vibra PCI128},"
  79                 "{Ectiva,EV1938}}");
  80 #endif
  81
  82 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  83 #define SUPPORT_JOYSTICK
  84 #endif
  85
  86 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  87 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  88 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  89 #ifdef SUPPORT_JOYSTICK
  90 #ifdef CHIP1371
  91 static int joystick_port[SNDRV_CARDS];
  92 #else
  93 static bool joystick[SNDRV_CARDS];
  94 #endif
  95 #endif
  96 #ifdef CHIP1371
  97 static int spdif[SNDRV_CARDS];
  98 static int lineio[SNDRV_CARDS];
  99 #endif
 100
 101 module_param_array(index, int, NULL, 0444);
 102 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
 103 module_param_array(id, charp, NULL, 0444);
 104 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
 105 module_param_array(enable, bool, NULL, 0444);
 106 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
 107 #ifdef SUPPORT_JOYSTICK
 108 #ifdef CHIP1371
 109 module_param_array(joystick_port, int, NULL, 0444);
 110 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 111 #else
 112 module_param_array(joystick, bool, NULL, 0444);
 113 MODULE_PARM_DESC(joystick, "Enable joystick.");
 114 #endif
 115 #endif /* SUPPORT_JOYSTICK */
 116 #ifdef CHIP1371
 117 module_param_array(spdif, int, NULL, 0444);
 118 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
 119 module_param_array(lineio, int, NULL, 0444);
 120 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
 121 #endif
 122
 123 /* ES1371 chip ID */
 124 /* This is a little confusing because all ES1371 compatible chips have the
 125    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 126    This is only significant if you want to enable features on the later parts.
 127    Yes, I know it's stupid and why didn't we use the sub IDs?
 128 */
 129 #define ES1371REV_ES1373_A  0x04
 130 #define ES1371REV_ES1373_B  0x06
 131 #define ES1371REV_CT5880_A  0x07
 132 #define CT5880REV_CT5880_C  0x02
 133 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 134 #define CT5880REV_CT5880_E  0x04        /* mw */
 135 #define ES1371REV_ES1371_B  0x09
 136 #define EV1938REV_EV1938_A  0x00
 137 #define ES1371REV_ES1373_8  0x08
 138
 139 /*
 140  * Direct registers
 141  */
 142
 143 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 144
 145 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 146 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 147 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 148 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 149 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 150 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 151 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 152 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 153 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 154 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 155 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 156 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 157 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 158 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 159 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 160 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 161 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 162 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 163 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 164 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 165 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 166 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 167 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 168 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 169 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 170 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 171 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 172 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 173 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 174 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 175 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 176 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 177 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 178 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 179 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 180 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 181 #define   ES_UART_EN            (1<<3)          /* UART enable */
 182 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 183 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 184 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 185 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 186 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 187 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 188 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 189 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 190 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 191 #define   ES_1373_REAR_BIT26    (1<<26)
 192 #define   ES_1373_REAR_BIT24    (1<<24)
 193 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 194 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 195 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 196 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 197 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 198 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 199 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 200 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 201 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 202 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 203 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 204 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 205 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 206 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 207 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 208 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 209 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 210 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 211 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 212 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 213 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 214 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 215 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 216 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 217 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 218 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 219 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 220 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 221 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 222 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 223 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 224 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 225 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 226 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 227 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 228 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 229 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 230 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 231 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 232 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 233 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 234 #define   EV_1938_CODEC_MAGIC      (1<<26)
 235 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 236 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 237 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 238 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 239
 240 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 241 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 242 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 243 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 244 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 245 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 246 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 247 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 248 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 249 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 250 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 251 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 252 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 253
 254 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 255 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 256 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 257 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 258 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 259 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 260 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 261 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 262 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 263 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 264 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 265 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 266 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 267 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 268 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 269 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 270 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 271 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 272 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 273 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 274 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 275 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 276 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 277
 278 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 279
 280 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 281 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 282 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 283 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 284 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 285 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 286 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 287 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 288 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 289 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 290 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 291 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 292 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 293 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 294 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 295 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 296 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 297 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 298 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 299 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 300 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 301 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 302 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 303 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 304 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 305 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 306 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 307
 308 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 309 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 310 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 311 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 312 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 313 #define   ES_REG_COUNTM         (0xffff<<0)
 314 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 315
 316 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 317 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 318 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 319 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 320 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 321 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 322 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 323 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 324 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 325 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 326 #define   ES_REG_FSIZEM          (0xffff<<0)
 327 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 328 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 329 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 330
 331 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 332 #define   ES_REG_UF_VALID        (1<<8)
 333 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 334 #define   ES_REG_UF_BYTEM        (0xff<<0)
 335 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 336
 337
 338 /*
 339  *  Pages
 340  */
 341
 342 #define ES_PAGE_DAC     0x0c
 343 #define ES_PAGE_ADC     0x0d
 344 #define ES_PAGE_UART    0x0e
 345 #define ES_PAGE_UART1   0x0f
 346
 347 /*
 348  *  Sample rate converter addresses
 349  */
 350
 351 #define ES_SMPREG_DAC1          0x70
 352 #define ES_SMPREG_DAC2          0x74
 353 #define ES_SMPREG_ADC           0x78
 354 #define ES_SMPREG_VOL_ADC       0x6c
 355 #define ES_SMPREG_VOL_DAC1      0x7c
 356 #define ES_SMPREG_VOL_DAC2      0x7e
 357 #define ES_SMPREG_TRUNC_N       0x00
 358 #define ES_SMPREG_INT_REGS      0x01
 359 #define ES_SMPREG_ACCUM_FRAC    0x02
 360 #define ES_SMPREG_VFREQ_FRAC    0x03
 361
 362 /*
 363  *  Some contants
 364  */
 365
 366 #define ES_1370_SRCLOCK    1411200
 367 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 368
 369 /*
 370  *  Open modes
 371  */
 372
 373 #define ES_MODE_PLAY1   0x0001
 374 #define ES_MODE_PLAY2   0x0002
 375 #define ES_MODE_CAPTURE 0x0004
 376
 377 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 378 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 379
 380 /*
 381
 382  */
 383
 384 struct ensoniq {
 385         spinlock_t reg_lock;
 386         struct mutex src_mutex;
 387
 388         int irq;
 389
 390         unsigned long playback1size;
 391         unsigned long playback2size;
 392         unsigned long capture3size;
 393
 394         unsigned long port;
 395         unsigned int mode;
 396         unsigned int uartm;     /* UART mode */
 397
 398         unsigned int ctrl;      /* control register */
 399         unsigned int sctrl;     /* serial control register */
 400         unsigned int cssr;      /* control status register */
 401         unsigned int uartc;     /* uart control register */
 402         unsigned int rev;       /* chip revision */
 403
 404         union {
 405 #ifdef CHIP1371
 406                 struct {
 407                         struct snd_ac97 *ac97;
 408                 } es1371;
 409 #else
 410                 struct {
 411                         int pclkdiv_lock;
 412                         struct snd_ak4531 *ak4531;
 413                 } es1370;
 414 #endif
 415         } u;
 416
 417         struct pci_dev *pci;
 418         struct snd_card *card;
 419         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
 420         struct snd_pcm *pcm2;   /* DAC2 PCM */
 421         struct snd_pcm_substream *playback1_substream;
 422         struct snd_pcm_substream *playback2_substream;
 423         struct snd_pcm_substream *capture_substream;
 424         unsigned int p1_dma_size;
 425         unsigned int p2_dma_size;
 426         unsigned int c_dma_size;
 427         unsigned int p1_period_size;
 428         unsigned int p2_period_size;
 429         unsigned int c_period_size;
 430         struct snd_rawmidi *rmidi;
 431         struct snd_rawmidi_substream *midi_input;
 432         struct snd_rawmidi_substream *midi_output;
 433
 434         unsigned int spdif;
 435         unsigned int spdif_default;
 436         unsigned int spdif_stream;
 437
 438 #ifdef CHIP1370
 439         struct snd_dma_buffer dma_bug;
 440 #endif
 441
 442 #ifdef SUPPORT_JOYSTICK
 443         struct gameport *gameport;
 444 #endif
 445 };
 446
 447 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
 448
 449 static DEFINE_PCI_DEVICE_TABLE(snd_audiopci_ids) = {
 450 #ifdef CHIP1370
 451         { PCI_VDEVICE(ENSONIQ, 0x5000), 0, },   /* ES1370 */
 452 #endif
 453 #ifdef CHIP1371
 454         { PCI_VDEVICE(ENSONIQ, 0x1371), 0, },   /* ES1371 */
 455         { PCI_VDEVICE(ENSONIQ, 0x5880), 0, },   /* ES1373 - CT5880 */
 456         { PCI_VDEVICE(ECTIVA, 0x8938), 0, },    /* Ectiva EV1938 */
 457 #endif
 458         { 0, }
 459 };
 460
 461 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 462
 463 /*
 464  *  constants
 465  */
 466
 467 #define POLL_COUNT      0xa000
 468
 469 #ifdef CHIP1370
 470 static unsigned int snd_es1370_fixed_rates[] =
 471         {5512, 11025, 22050, 44100};
 472 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
 473         .count = 4,
 474         .list = snd_es1370_fixed_rates,
 475         .mask = 0,
 476 };
 477 static struct snd_ratnum es1370_clock = {
 478         .num = ES_1370_SRCLOCK,
 479         .den_min = 29,
 480         .den_max = 353,
 481         .den_step = 1,
 482 };
 483 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
 484         .nrats = 1,
 485         .rats = &es1370_clock,
 486 };
 487 #else
 488 static struct snd_ratden es1371_dac_clock = {
 489         .num_min = 3000 * (1 << 15),
 490         .num_max = 48000 * (1 << 15),
 491         .num_step = 3000,
 492         .den = 1 << 15,
 493 };
 494 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
 495         .nrats = 1,
 496         .rats = &es1371_dac_clock,
 497 };
 498 static struct snd_ratnum es1371_adc_clock = {
 499         .num = 48000 << 15,
 500         .den_min = 32768,
 501         .den_max = 393216,
 502         .den_step = 1,
 503 };
 504 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
 505         .nrats = 1,
 506         .rats = &es1371_adc_clock,
 507 };
 508 #endif
 509 static const unsigned int snd_ensoniq_sample_shift[] =
 510         {0, 1, 1, 2};
 511
 512 /*
 513  *  common I/O routines
 514  */
 515
 516 #ifdef CHIP1371
 517
 518 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
 519 {
 520         unsigned int t, r = 0;
 521
 522         for (t = 0; t < POLL_COUNT; t++) {
 523                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 524                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 525                         return r;
 526                 cond_resched();
 527         }
 528         snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n",
 529                    ES_REG(ensoniq, 1371_SMPRATE), r);
 530         return 0;
 531 }
 532
 533 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
 534 {
 535         unsigned int temp, i, orig, r;
 536
 537         /* wait for ready */
 538         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 539
 540         /* expose the SRC state bits */
 541         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 542                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 543         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 544         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 545
 546         /* now, wait for busy and the correct time to read */
 547         temp = snd_es1371_wait_src_ready(ensoniq);
 548
 549         if ((temp & 0x00870000) != 0x00010000) {
 550                 /* wait for the right state */
 551                 for (i = 0; i < POLL_COUNT; i++) {
 552                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 553                         if ((temp & 0x00870000) == 0x00010000)
 554                                 break;
 555                 }
 556         }
 557
 558         /* hide the state bits */
 559         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 560                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 561         r |= ES_1371_SRC_RAM_ADDRO(reg);
 562         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 563
 564         return temp;
 565 }
 566
 567 static void snd_es1371_src_write(struct ensoniq * ensoniq,
 568                                  unsigned short reg, unsigned short data)
 569 {
 570         unsigned int r;
 571
 572         r = snd_es1371_wait_src_ready(ensoniq) &
 573             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 574              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 575         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 576         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 577 }
 578
 579 #endif /* CHIP1371 */
 580
 581 #ifdef CHIP1370
 582
 583 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
 584                                    unsigned short reg, unsigned short val)
 585 {
 586         struct ensoniq *ensoniq = ak4531->private_data;
 587         unsigned long end_time = jiffies + HZ / 10;
 588
 589 #if 0
 590         printk(KERN_DEBUG
 591                "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
 592                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 593 #endif
 594         do {
 595                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 596                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 597                         return;
 598                 }
 599                 schedule_timeout_uninterruptible(1);
 600         } while (time_after(end_time, jiffies));
 601         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
 602                    inl(ES_REG(ensoniq, STATUS)));
 603 }
 604
 605 #endif /* CHIP1370 */
 606
 607 #ifdef CHIP1371
 608
 609 static inline bool is_ev1938(struct ensoniq *ensoniq)
 610 {
 611         return ensoniq->pci->device == 0x8938;
 612 }
 613
 614 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
 615                                    unsigned short reg, unsigned short val)
 616 {
 617         struct ensoniq *ensoniq = ac97->private_data;
 618         unsigned int t, x, flag;
 619
 620         flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
 621         mutex_lock(&ensoniq->src_mutex);
 622         for (t = 0; t < POLL_COUNT; t++) {
 623                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 624                         /* save the current state for latter */
 625                         x = snd_es1371_wait_src_ready(ensoniq);
 626                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 627                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 628                              ES_REG(ensoniq, 1371_SMPRATE));
 629                         /* wait for not busy (state 0) first to avoid
 630                            transition states */
 631                         for (t = 0; t < POLL_COUNT; t++) {
 632                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 633                                     0x00000000)
 634                                         break;
 635                         }
 636                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 637                         for (t = 0; t < POLL_COUNT; t++) {
 638                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 639                                     0x00010000)
 640                                         break;
 641                         }
 642                         outl(ES_1371_CODEC_WRITE(reg, val) | flag,
 643                              ES_REG(ensoniq, 1371_CODEC));
 644                         /* restore SRC reg */
 645                         snd_es1371_wait_src_ready(ensoniq);
 646                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 647                         mutex_unlock(&ensoniq->src_mutex);
 648                         return;
 649                 }
 650         }
 651         mutex_unlock(&ensoniq->src_mutex);
 652         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
 653                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 654 }
 655
 656 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
 657                                             unsigned short reg)
 658 {
 659         struct ensoniq *ensoniq = ac97->private_data;
 660         unsigned int t, x, flag, fail = 0;
 661
 662         flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
 663       __again:
 664         mutex_lock(&ensoniq->src_mutex);
 665         for (t = 0; t < POLL_COUNT; t++) {
 666                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 667                         /* save the current state for latter */
 668                         x = snd_es1371_wait_src_ready(ensoniq);
 669                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 670                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 671                              ES_REG(ensoniq, 1371_SMPRATE));
 672                         /* wait for not busy (state 0) first to avoid
 673                            transition states */
 674                         for (t = 0; t < POLL_COUNT; t++) {
 675                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 676                                     0x00000000)
 677                                         break;
 678                         }
 679                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 680                         for (t = 0; t < POLL_COUNT; t++) {
 681                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 682                                     0x00010000)
 683                                         break;
 684                         }
 685                         outl(ES_1371_CODEC_READS(reg) | flag,
 686                              ES_REG(ensoniq, 1371_CODEC));
 687                         /* restore SRC reg */
 688                         snd_es1371_wait_src_ready(ensoniq);
 689                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 690                         /* wait for WIP again */
 691                         for (t = 0; t < POLL_COUNT; t++) {
 692                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 693                                         break;
 694                         }
 695                         /* now wait for the stinkin' data (RDY) */
 696                         for (t = 0; t < POLL_COUNT; t++) {
 697                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 698                                         if (is_ev1938(ensoniq)) {
 699                                                 for (t = 0; t < 100; t++)
 700                                                         inl(ES_REG(ensoniq, CONTROL));
 701                                                 x = inl(ES_REG(ensoniq, 1371_CODEC));
 702                                         }
 703                                         mutex_unlock(&ensoniq->src_mutex);
 704                                         return ES_1371_CODEC_READ(x);
 705                                 }
 706                         }
 707                         mutex_unlock(&ensoniq->src_mutex);
 708                         if (++fail > 10) {
 709                                 snd_printk(KERN_ERR "codec read timeout (final) "
 710                                            "at 0x%lx, reg = 0x%x [0x%x]\n",
 711                                            ES_REG(ensoniq, 1371_CODEC), reg,
 712                                            inl(ES_REG(ensoniq, 1371_CODEC)));
 713                                 return 0;
 714                         }
 715                         goto __again;
 716                 }
 717         }
 718         mutex_unlock(&ensoniq->src_mutex);
 719         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
 720                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 721         return 0;
 722 }
 723
 724 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
 725 {
 726         msleep(750);
 727         snd_es1371_codec_read(ac97, AC97_RESET);
 728         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
 729         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
 730         msleep(50);
 731 }
 732
 733 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
 734 {
 735         unsigned int n, truncm, freq, result;
 736
 737         mutex_lock(&ensoniq->src_mutex);
 738         n = rate / 3000;
 739         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 740                 n--;
 741         truncm = (21 * n - 1) | 1;
 742         freq = ((48000UL << 15) / rate) * n;
 743         result = (48000UL << 15) / (freq / n);
 744         if (rate >= 24000) {
 745                 if (truncm > 239)
 746                         truncm = 239;
 747                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 748                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 749         } else {
 750                 if (truncm > 119)
 751                         truncm = 119;
 752                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 753                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 754         }
 755         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 756                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
 757                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 758                              ((freq >> 5) & 0xfc00));
 759         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 760         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 761         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 762         mutex_unlock(&ensoniq->src_mutex);
 763 }
 764
 765 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
 766 {
 767         unsigned int freq, r;
 768
 769         mutex_lock(&ensoniq->src_mutex);
 770         freq = ((rate << 15) + 1500) / 3000;
 771         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 772                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
 773                 ES_1371_DIS_P1;
 774         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 775         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 776                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
 777                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 778                              ((freq >> 5) & 0xfc00));
 779         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 780         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 781                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
 782         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 783         mutex_unlock(&ensoniq->src_mutex);
 784 }
 785
 786 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
 787 {
 788         unsigned int freq, r;
 789
 790         mutex_lock(&ensoniq->src_mutex);
 791         freq = ((rate << 15) + 1500) / 3000;
 792         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 793                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
 794                 ES_1371_DIS_P2;
 795         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 796         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 797                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
 798                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 799                              ((freq >> 5) & 0xfc00));
 800         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
 801                              freq & 0x7fff);
 802         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 803                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
 804         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 805         mutex_unlock(&ensoniq->src_mutex);
 806 }
 807
 808 #endif /* CHIP1371 */
 809
 810 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
 811 {
 812         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 813         switch (cmd) {
 814         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 815         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 816         {
 817                 unsigned int what = 0;
 818                 struct snd_pcm_substream *s;
 819                 snd_pcm_group_for_each_entry(s, substream) {
 820                         if (s == ensoniq->playback1_substream) {
 821                                 what |= ES_P1_PAUSE;
 822                                 snd_pcm_trigger_done(s, substream);
 823                         } else if (s == ensoniq->playback2_substream) {
 824                                 what |= ES_P2_PAUSE;
 825                                 snd_pcm_trigger_done(s, substream);
 826                         } else if (s == ensoniq->capture_substream)
 827                                 return -EINVAL;
 828                 }
 829                 spin_lock(&ensoniq->reg_lock);
 830                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 831                         ensoniq->sctrl |= what;
 832                 else
 833                         ensoniq->sctrl &= ~what;
 834                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 835                 spin_unlock(&ensoniq->reg_lock);
 836                 break;
 837         }
 838         case SNDRV_PCM_TRIGGER_START:
 839         case SNDRV_PCM_TRIGGER_STOP:
 840         {
 841                 unsigned int what = 0;
 842                 struct snd_pcm_substream *s;
 843                 snd_pcm_group_for_each_entry(s, substream) {
 844                         if (s == ensoniq->playback1_substream) {
 845                                 what |= ES_DAC1_EN;
 846                                 snd_pcm_trigger_done(s, substream);
 847                         } else if (s == ensoniq->playback2_substream) {
 848                                 what |= ES_DAC2_EN;
 849                                 snd_pcm_trigger_done(s, substream);
 850                         } else if (s == ensoniq->capture_substream) {
 851                                 what |= ES_ADC_EN;
 852                                 snd_pcm_trigger_done(s, substream);
 853                         }
 854                 }
 855                 spin_lock(&ensoniq->reg_lock);
 856                 if (cmd == SNDRV_PCM_TRIGGER_START)
 857                         ensoniq->ctrl |= what;
 858                 else
 859                         ensoniq->ctrl &= ~what;
 860                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 861                 spin_unlock(&ensoniq->reg_lock);
 862                 break;
 863         }
 864         default:
 865                 return -EINVAL;
 866         }
 867         return 0;
 868 }
 869
 870 /*
 871  *  PCM part
 872  */
 873
 874 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
 875                                  struct snd_pcm_hw_params *hw_params)
 876 {
 877         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 878 }
 879
 880 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
 881 {
 882         return snd_pcm_lib_free_pages(substream);
 883 }
 884
 885 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
 886 {
 887         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 888         struct snd_pcm_runtime *runtime = substream->runtime;
 889         unsigned int mode = 0;
 890
 891         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 892         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 893         if (snd_pcm_format_width(runtime->format) == 16)
 894                 mode |= 0x02;
 895         if (runtime->channels > 1)
 896                 mode |= 0x01;
 897         spin_lock_irq(&ensoniq->reg_lock);
 898         ensoniq->ctrl &= ~ES_DAC1_EN;
 899 #ifdef CHIP1371
 900         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 901         if (runtime->rate == 48000)
 902                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 903         else
 904                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 905 #endif
 906         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 907         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 908         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 909         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 910         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 911         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 912         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 913         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 914              ES_REG(ensoniq, DAC1_COUNT));
 915 #ifdef CHIP1370
 916         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 917         switch (runtime->rate) {
 918         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 919         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 920         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 921         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 922         default: snd_BUG();
 923         }
 924 #endif
 925         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 926         spin_unlock_irq(&ensoniq->reg_lock);
 927 #ifndef CHIP1370
 928         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 929 #endif
 930         return 0;
 931 }
 932
 933 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
 934 {
 935         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 936         struct snd_pcm_runtime *runtime = substream->runtime;
 937         unsigned int mode = 0;
 938
 939         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 940         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 941         if (snd_pcm_format_width(runtime->format) == 16)
 942                 mode |= 0x02;
 943         if (runtime->channels > 1)
 944                 mode |= 0x01;
 945         spin_lock_irq(&ensoniq->reg_lock);
 946         ensoniq->ctrl &= ~ES_DAC2_EN;
 947         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 948         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 949         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 950         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 951         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 952                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 953         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 954                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 955         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 956         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 957              ES_REG(ensoniq, DAC2_COUNT));
 958 #ifdef CHIP1370
 959         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 960                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 961                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 962                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 963         }
 964 #endif
 965         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 966         spin_unlock_irq(&ensoniq->reg_lock);
 967 #ifndef CHIP1370
 968         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 969 #endif
 970         return 0;
 971 }
 972
 973 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
 974 {
 975         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 976         struct snd_pcm_runtime *runtime = substream->runtime;
 977         unsigned int mode = 0;
 978
 979         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 980         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 981         if (snd_pcm_format_width(runtime->format) == 16)
 982                 mode |= 0x02;
 983         if (runtime->channels > 1)
 984                 mode |= 0x01;
 985         spin_lock_irq(&ensoniq->reg_lock);
 986         ensoniq->ctrl &= ~ES_ADC_EN;
 987         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 988         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 989         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 990         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 991         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 992         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 993         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 994         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 995              ES_REG(ensoniq, ADC_COUNT));
 996 #ifdef CHIP1370
 997         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 998                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 999                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
1000                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
1001         }
1002 #endif
1003         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1004         spin_unlock_irq(&ensoniq->reg_lock);
1005 #ifndef CHIP1370
1006         snd_es1371_adc_rate(ensoniq, runtime->rate);
1007 #endif
1008         return 0;
1009 }
1010
1011 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1012 {
1013         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1014         size_t ptr;
1015
1016         spin_lock(&ensoniq->reg_lock);
1017         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1018                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1019                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1020                 ptr = bytes_to_frames(substream->runtime, ptr);
1021         } else {
1022                 ptr = 0;
1023         }
1024         spin_unlock(&ensoniq->reg_lock);
1025         return ptr;
1026 }
1027
1028 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1029 {
1030         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1031         size_t ptr;
1032
1033         spin_lock(&ensoniq->reg_lock);
1034         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1035                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1036                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1037                 ptr = bytes_to_frames(substream->runtime, ptr);
1038         } else {
1039                 ptr = 0;
1040         }
1041         spin_unlock(&ensoniq->reg_lock);
1042         return ptr;
1043 }
1044
1045 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1046 {
1047         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1048         size_t ptr;
1049
1050         spin_lock(&ensoniq->reg_lock);
1051         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1052                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1053                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1054                 ptr = bytes_to_frames(substream->runtime, ptr);
1055         } else {
1056                 ptr = 0;
1057         }
1058         spin_unlock(&ensoniq->reg_lock);
1059         return ptr;
1060 }
1061
1062 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1063 {
1064         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1065                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1066                                  SNDRV_PCM_INFO_MMAP_VALID |
1067                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1068         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1069         .rates =
1070 #ifndef CHIP1370
1071                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1072 #else
1073                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1074                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1075                                  SNDRV_PCM_RATE_44100),
1076 #endif
1077         .rate_min =             4000,
1078         .rate_max =             48000,
1079         .channels_min =         1,
1080         .channels_max =         2,
1081         .buffer_bytes_max =     (128*1024),
1082         .period_bytes_min =     64,
1083         .period_bytes_max =     (128*1024),
1084         .periods_min =          1,
1085         .periods_max =          1024,
1086         .fifo_size =            0,
1087 };
1088
1089 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1090 {
1091         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1092                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1093                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1094                                  SNDRV_PCM_INFO_SYNC_START),
1095         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1096         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1097         .rate_min =             4000,
1098         .rate_max =             48000,
1099         .channels_min =         1,
1100         .channels_max =         2,
1101         .buffer_bytes_max =     (128*1024),
1102         .period_bytes_min =     64,
1103         .period_bytes_max =     (128*1024),
1104         .periods_min =          1,
1105         .periods_max =          1024,
1106         .fifo_size =            0,
1107 };
1108
1109 static struct snd_pcm_hardware snd_ensoniq_capture =
1110 {
1111         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1112                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1113                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1114         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1115         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1116         .rate_min =             4000,
1117         .rate_max =             48000,
1118         .channels_min =         1,
1119         .channels_max =         2,
1120         .buffer_bytes_max =     (128*1024),
1121         .period_bytes_min =     64,
1122         .period_bytes_max =     (128*1024),
1123         .periods_min =          1,
1124         .periods_max =          1024,
1125         .fifo_size =            0,
1126 };
1127
1128 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1129 {
1130         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1131         struct snd_pcm_runtime *runtime = substream->runtime;
1132
1133         ensoniq->mode |= ES_MODE_PLAY1;
1134         ensoniq->playback1_substream = substream;
1135         runtime->hw = snd_ensoniq_playback1;
1136         snd_pcm_set_sync(substream);
1137         spin_lock_irq(&ensoniq->reg_lock);
1138         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1139                 ensoniq->spdif_stream = ensoniq->spdif_default;
1140         spin_unlock_irq(&ensoniq->reg_lock);
1141 #ifdef CHIP1370
1142         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1143                                    &snd_es1370_hw_constraints_rates);
1144 #else
1145         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1146                                       &snd_es1371_hw_constraints_dac_clock);
1147 #endif
1148         return 0;
1149 }
1150
1151 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1152 {
1153         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1154         struct snd_pcm_runtime *runtime = substream->runtime;
1155
1156         ensoniq->mode |= ES_MODE_PLAY2;
1157         ensoniq->playback2_substream = substream;
1158         runtime->hw = snd_ensoniq_playback2;
1159         snd_pcm_set_sync(substream);
1160         spin_lock_irq(&ensoniq->reg_lock);
1161         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1162                 ensoniq->spdif_stream = ensoniq->spdif_default;
1163         spin_unlock_irq(&ensoniq->reg_lock);
1164 #ifdef CHIP1370
1165         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1166                                       &snd_es1370_hw_constraints_clock);
1167 #else
1168         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1169                                       &snd_es1371_hw_constraints_dac_clock);
1170 #endif
1171         return 0;
1172 }
1173
1174 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1175 {
1176         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1177         struct snd_pcm_runtime *runtime = substream->runtime;
1178
1179         ensoniq->mode |= ES_MODE_CAPTURE;
1180         ensoniq->capture_substream = substream;
1181         runtime->hw = snd_ensoniq_capture;
1182         snd_pcm_set_sync(substream);
1183 #ifdef CHIP1370
1184         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1185                                       &snd_es1370_hw_constraints_clock);
1186 #else
1187         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1188                                       &snd_es1371_hw_constraints_adc_clock);
1189 #endif
1190         return 0;
1191 }
1192
1193 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1194 {
1195         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1196
1197         ensoniq->playback1_substream = NULL;
1198         ensoniq->mode &= ~ES_MODE_PLAY1;
1199         return 0;
1200 }
1201
1202 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1203 {
1204         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1205
1206         ensoniq->playback2_substream = NULL;
1207         spin_lock_irq(&ensoniq->reg_lock);
1208 #ifdef CHIP1370
1209         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1210 #endif
1211         ensoniq->mode &= ~ES_MODE_PLAY2;
1212         spin_unlock_irq(&ensoniq->reg_lock);
1213         return 0;
1214 }
1215
1216 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1217 {
1218         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1219
1220         ensoniq->capture_substream = NULL;
1221         spin_lock_irq(&ensoniq->reg_lock);
1222 #ifdef CHIP1370
1223         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1224 #endif
1225         ensoniq->mode &= ~ES_MODE_CAPTURE;
1226         spin_unlock_irq(&ensoniq->reg_lock);
1227         return 0;
1228 }
1229
1230 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1231         .open =         snd_ensoniq_playback1_open,
1232         .close =        snd_ensoniq_playback1_close,
1233         .ioctl =        snd_pcm_lib_ioctl,
1234         .hw_params =    snd_ensoniq_hw_params,
1235         .hw_free =      snd_ensoniq_hw_free,
1236         .prepare =      snd_ensoniq_playback1_prepare,
1237         .trigger =      snd_ensoniq_trigger,
1238         .pointer =      snd_ensoniq_playback1_pointer,
1239 };
1240
1241 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1242         .open =         snd_ensoniq_playback2_open,
1243         .close =        snd_ensoniq_playback2_close,
1244         .ioctl =        snd_pcm_lib_ioctl,
1245         .hw_params =    snd_ensoniq_hw_params,
1246         .hw_free =      snd_ensoniq_hw_free,
1247         .prepare =      snd_ensoniq_playback2_prepare,
1248         .trigger =      snd_ensoniq_trigger,
1249         .pointer =      snd_ensoniq_playback2_pointer,
1250 };
1251
1252 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1253         .open =         snd_ensoniq_capture_open,
1254         .close =        snd_ensoniq_capture_close,
1255         .ioctl =        snd_pcm_lib_ioctl,
1256         .hw_params =    snd_ensoniq_hw_params,
1257         .hw_free =      snd_ensoniq_hw_free,
1258         .prepare =      snd_ensoniq_capture_prepare,
1259         .trigger =      snd_ensoniq_trigger,
1260         .pointer =      snd_ensoniq_capture_pointer,
1261 };
1262
1263 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1264                                      struct snd_pcm ** rpcm)
1265 {
1266         struct snd_pcm *pcm;
1267         int err;
1268
1269         if (rpcm)
1270                 *rpcm = NULL;
1271         err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1272         if (err < 0)
1273                 return err;
1274
1275 #ifdef CHIP1370
1276         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1277 #else
1278         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1279 #endif
1280         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1281
1282         pcm->private_data = ensoniq;
1283         pcm->info_flags = 0;
1284         strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1285         ensoniq->pcm1 = pcm;
1286
1287         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1288                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1289
1290         if (rpcm)
1291                 *rpcm = pcm;
1292         return 0;
1293 }
1294
1295 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1296                                       struct snd_pcm ** rpcm)
1297 {
1298         struct snd_pcm *pcm;
1299         int err;
1300
1301         if (rpcm)
1302                 *rpcm = NULL;
1303         err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1304         if (err < 0)
1305                 return err;
1306
1307 #ifdef CHIP1370
1308         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1309 #else
1310         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1311 #endif
1312         pcm->private_data = ensoniq;
1313         pcm->info_flags = 0;
1314         strcpy(pcm->name, CHIP_NAME " DAC1");
1315         ensoniq->pcm2 = pcm;
1316
1317         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1318                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1319
1320         if (rpcm)
1321                 *rpcm = pcm;
1322         return 0;
1323 }
1324
1325 /*
1326  *  Mixer section
1327  */
1328
1329 /*
1330  * ENS1371 mixer (including SPDIF interface)
1331  */
1332 #ifdef CHIP1371
1333 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1334                                   struct snd_ctl_elem_info *uinfo)
1335 {
1336         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1337         uinfo->count = 1;
1338         return 0;
1339 }
1340
1341 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1342                                          struct snd_ctl_elem_value *ucontrol)
1343 {
1344         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1345         spin_lock_irq(&ensoniq->reg_lock);
1346         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1347         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1348         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1349         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1350         spin_unlock_irq(&ensoniq->reg_lock);
1351         return 0;
1352 }
1353
1354 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1355                                          struct snd_ctl_elem_value *ucontrol)
1356 {
1357         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1358         unsigned int val;
1359         int change;
1360
1361         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1362               ((u32)ucontrol->value.iec958.status[1] << 8) |
1363               ((u32)ucontrol->value.iec958.status[2] << 16) |
1364               ((u32)ucontrol->value.iec958.status[3] << 24);
1365         spin_lock_irq(&ensoniq->reg_lock);
1366         change = ensoniq->spdif_default != val;
1367         ensoniq->spdif_default = val;
1368         if (change && ensoniq->playback1_substream == NULL &&
1369             ensoniq->playback2_substream == NULL)
1370                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1371         spin_unlock_irq(&ensoniq->reg_lock);
1372         return change;
1373 }
1374
1375 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1376                                       struct snd_ctl_elem_value *ucontrol)
1377 {
1378         ucontrol->value.iec958.status[0] = 0xff;
1379         ucontrol->value.iec958.status[1] = 0xff;
1380         ucontrol->value.iec958.status[2] = 0xff;
1381         ucontrol->value.iec958.status[3] = 0xff;
1382         return 0;
1383 }
1384
1385 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1386                                         struct snd_ctl_elem_value *ucontrol)
1387 {
1388         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1389         spin_lock_irq(&ensoniq->reg_lock);
1390         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1391         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1392         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1393         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1394         spin_unlock_irq(&ensoniq->reg_lock);
1395         return 0;
1396 }
1397
1398 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1399                                         struct snd_ctl_elem_value *ucontrol)
1400 {
1401         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1402         unsigned int val;
1403         int change;
1404
1405         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1406               ((u32)ucontrol->value.iec958.status[1] << 8) |
1407               ((u32)ucontrol->value.iec958.status[2] << 16) |
1408               ((u32)ucontrol->value.iec958.status[3] << 24);
1409         spin_lock_irq(&ensoniq->reg_lock);
1410         change = ensoniq->spdif_stream != val;
1411         ensoniq->spdif_stream = val;
1412         if (change && (ensoniq->playback1_substream != NULL ||
1413                        ensoniq->playback2_substream != NULL))
1414                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1415         spin_unlock_irq(&ensoniq->reg_lock);
1416         return change;
1417 }
1418
1419 #define ES1371_SPDIF(xname) \
1420 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1421   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1422
1423 #define snd_es1371_spdif_info           snd_ctl_boolean_mono_info
1424
1425 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1426                                 struct snd_ctl_elem_value *ucontrol)
1427 {
1428         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1429
1430         spin_lock_irq(&ensoniq->reg_lock);
1431         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1432         spin_unlock_irq(&ensoniq->reg_lock);
1433         return 0;
1434 }
1435
1436 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1437                                 struct snd_ctl_elem_value *ucontrol)
1438 {
1439         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1440         unsigned int nval1, nval2;
1441         int change;
1442
1443         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1444         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1445         spin_lock_irq(&ensoniq->reg_lock);
1446         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1447         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1448         ensoniq->ctrl |= nval1;
1449         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1450         ensoniq->cssr |= nval2;
1451         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1452         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1453         spin_unlock_irq(&ensoniq->reg_lock);
1454         return change;
1455 }
1456
1457
1458 /* spdif controls */
1459 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1460         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1461         {
1462                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1463                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1464                 .info =         snd_ens1373_spdif_info,
1465                 .get =          snd_ens1373_spdif_default_get,
1466                 .put =          snd_ens1373_spdif_default_put,
1467         },
1468         {
1469                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1470                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1471                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1472                 .info =         snd_ens1373_spdif_info,
1473                 .get =          snd_ens1373_spdif_mask_get
1474         },
1475         {
1476                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1477                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1478                 .info =         snd_ens1373_spdif_info,
1479                 .get =          snd_ens1373_spdif_stream_get,
1480                 .put =          snd_ens1373_spdif_stream_put
1481         },
1482 };
1483
1484
1485 #define snd_es1373_rear_info            snd_ctl_boolean_mono_info
1486
1487 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1488                                struct snd_ctl_elem_value *ucontrol)
1489 {
1490         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1491         int val = 0;
1492
1493         spin_lock_irq(&ensoniq->reg_lock);
1494         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1495                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1496                 val = 1;
1497         ucontrol->value.integer.value[0] = val;
1498         spin_unlock_irq(&ensoniq->reg_lock);
1499         return 0;
1500 }
1501
1502 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1503                                struct snd_ctl_elem_value *ucontrol)
1504 {
1505         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1506         unsigned int nval1;
1507         int change;
1508
1509         nval1 = ucontrol->value.integer.value[0] ?
1510                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1511         spin_lock_irq(&ensoniq->reg_lock);
1512         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1513                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1514         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1515         ensoniq->cssr |= nval1;
1516         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1517         spin_unlock_irq(&ensoniq->reg_lock);
1518         return change;
1519 }
1520
1521 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1522 {
1523         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1524         .name =         "AC97 2ch->4ch Copy Switch",
1525         .info =         snd_es1373_rear_info,
1526         .get =          snd_es1373_rear_get,
1527         .put =          snd_es1373_rear_put,
1528 };
1529
1530 #define snd_es1373_line_info            snd_ctl_boolean_mono_info
1531
1532 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1533                                struct snd_ctl_elem_value *ucontrol)
1534 {
1535         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1536         int val = 0;
1537
1538         spin_lock_irq(&ensoniq->reg_lock);
1539         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1540                 val = 1;
1541         ucontrol->value.integer.value[0] = val;
1542         spin_unlock_irq(&ensoniq->reg_lock);
1543         return 0;
1544 }
1545
1546 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1547                                struct snd_ctl_elem_value *ucontrol)
1548 {
1549         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1550         int changed;
1551         unsigned int ctrl;
1552
1553         spin_lock_irq(&ensoniq->reg_lock);
1554         ctrl = ensoniq->ctrl;
1555         if (ucontrol->value.integer.value[0])
1556                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1557         else
1558                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1559         changed = (ctrl != ensoniq->ctrl);
1560         if (changed)
1561                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1562         spin_unlock_irq(&ensoniq->reg_lock);
1563         return changed;
1564 }
1565
1566 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1567 {
1568         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1569         .name =         "Line In->Rear Out Switch",
1570         .info =         snd_es1373_line_info,
1571         .get =          snd_es1373_line_get,
1572         .put =          snd_es1373_line_put,
1573 };
1574
1575 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1576 {
1577         struct ensoniq *ensoniq = ac97->private_data;
1578         ensoniq->u.es1371.ac97 = NULL;
1579 }
1580
1581 struct es1371_quirk {
1582         unsigned short vid;             /* vendor ID */
1583         unsigned short did;             /* device ID */
1584         unsigned char rev;              /* revision */
1585 };
1586
1587 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1588                                 struct es1371_quirk *list)
1589 {
1590         while (list->vid != (unsigned short)PCI_ANY_ID) {
1591                 if (ensoniq->pci->vendor == list->vid &&
1592                     ensoniq->pci->device == list->did &&
1593                     ensoniq->rev == list->rev)
1594                         return 1;
1595                 list++;
1596         }
1597         return 0;
1598 }
1599
1600 static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1601         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1602         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1603         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1604         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1605         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1606         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1607 };
1608
1609 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1610         SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1611         SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1612         { } /* end */
1613 };
1614
1615 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1616                                             int has_spdif, int has_line)
1617 {
1618         struct snd_card *card = ensoniq->card;
1619         struct snd_ac97_bus *pbus;
1620         struct snd_ac97_template ac97;
1621         int err;
1622         static struct snd_ac97_bus_ops ops = {
1623                 .write = snd_es1371_codec_write,
1624                 .read = snd_es1371_codec_read,
1625                 .wait = snd_es1371_codec_wait,
1626         };
1627
1628         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1629                 return err;
1630
1631         memset(&ac97, 0, sizeof(ac97));
1632         ac97.private_data = ensoniq;
1633         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1634         ac97.pci = ensoniq->pci;
1635         ac97.scaps = AC97_SCAP_AUDIO;
1636         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1637                 return err;
1638         if (has_spdif > 0 ||
1639             (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1640                 struct snd_kcontrol *kctl;
1641                 int i, is_spdif = 0;
1642
1643                 ensoniq->spdif_default = ensoniq->spdif_stream =
1644                         SNDRV_PCM_DEFAULT_CON_SPDIF;
1645                 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1646
1647                 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1648                         is_spdif++;
1649
1650                 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1651                         kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1652                         if (!kctl)
1653                                 return -ENOMEM;
1654                         kctl->id.index = is_spdif;
1655                         err = snd_ctl_add(card, kctl);
1656                         if (err < 0)
1657                                 return err;
1658                 }
1659         }
1660         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1661                 /* mirror rear to front speakers */
1662                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1663                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1664                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1665                 if (err < 0)
1666                         return err;
1667         }
1668         if (has_line > 0 ||
1669             snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1670                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1671                                                       ensoniq));
1672                  if (err < 0)
1673                          return err;
1674         }
1675
1676         return 0;
1677 }
1678
1679 #endif /* CHIP1371 */
1680
1681 /* generic control callbacks for ens1370 */
1682 #ifdef CHIP1370
1683 #define ENSONIQ_CONTROL(xname, mask) \
1684 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1685   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1686   .private_value = mask }
1687
1688 #define snd_ensoniq_control_info        snd_ctl_boolean_mono_info
1689
1690 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1691                                    struct snd_ctl_elem_value *ucontrol)
1692 {
1693         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1694         int mask = kcontrol->private_value;
1695
1696         spin_lock_irq(&ensoniq->reg_lock);
1697         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1698         spin_unlock_irq(&ensoniq->reg_lock);
1699         return 0;
1700 }
1701
1702 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1703                                    struct snd_ctl_elem_value *ucontrol)
1704 {
1705         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1706         int mask = kcontrol->private_value;
1707         unsigned int nval;
1708         int change;
1709
1710         nval = ucontrol->value.integer.value[0] ? mask : 0;
1711         spin_lock_irq(&ensoniq->reg_lock);
1712         change = (ensoniq->ctrl & mask) != nval;
1713         ensoniq->ctrl &= ~mask;
1714         ensoniq->ctrl |= nval;
1715         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1716         spin_unlock_irq(&ensoniq->reg_lock);
1717         return change;
1718 }
1719
1720 /*
1721  * ENS1370 mixer
1722  */
1723
1724 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1725 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1726 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1727 };
1728
1729 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1730
1731 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1732 {
1733         struct ensoniq *ensoniq = ak4531->private_data;
1734         ensoniq->u.es1370.ak4531 = NULL;
1735 }
1736
1737 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1738 {
1739         struct snd_card *card = ensoniq->card;
1740         struct snd_ak4531 ak4531;
1741         unsigned int idx;
1742         int err;
1743
1744         /* try reset AK4531 */
1745         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1746         inw(ES_REG(ensoniq, 1370_CODEC));
1747         udelay(100);
1748         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1749         inw(ES_REG(ensoniq, 1370_CODEC));
1750         udelay(100);
1751
1752         memset(&ak4531, 0, sizeof(ak4531));
1753         ak4531.write = snd_es1370_codec_write;
1754         ak4531.private_data = ensoniq;
1755         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1756         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1757                 return err;
1758         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1759                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1760                 if (err < 0)
1761                         return err;
1762         }
1763         return 0;
1764 }
1765
1766 #endif /* CHIP1370 */
1767
1768 #ifdef SUPPORT_JOYSTICK
1769
1770 #ifdef CHIP1371
1771 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1772 {
1773         switch (joystick_port[dev]) {
1774         case 0: /* disabled */
1775         case 1: /* auto-detect */
1776         case 0x200:
1777         case 0x208:
1778         case 0x210:
1779         case 0x218:
1780                 return joystick_port[dev];
1781
1782         default:
1783                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1784                 return 0;
1785         }
1786 }
1787 #else
1788 static inline int snd_ensoniq_get_joystick_port(int dev)
1789 {
1790         return joystick[dev] ? 0x200 : 0;
1791 }
1792 #endif
1793
1794 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1795 {
1796         struct gameport *gp;
1797         int io_port;
1798
1799         io_port = snd_ensoniq_get_joystick_port(dev);
1800
1801         switch (io_port) {
1802         case 0:
1803                 return -ENOSYS;
1804
1805         case 1: /* auto_detect */
1806                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1807                         if (request_region(io_port, 8, "ens137x: gameport"))
1808                                 break;
1809                 if (io_port > 0x218) {
1810                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1811                         return -EBUSY;
1812                 }
1813                 break;
1814
1815         default:
1816                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1817                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1818                                io_port);
1819                         return -EBUSY;
1820                 }
1821                 break;
1822         }
1823
1824         ensoniq->gameport = gp = gameport_allocate_port();
1825         if (!gp) {
1826                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1827                 release_region(io_port, 8);
1828                 return -ENOMEM;
1829         }
1830
1831         gameport_set_name(gp, "ES137x");
1832         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1833         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1834         gp->io = io_port;
1835
1836         ensoniq->ctrl |= ES_JYSTK_EN;
1837 #ifdef CHIP1371
1838         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1839         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1840 #endif
1841         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1842
1843         gameport_register_port(ensoniq->gameport);
1844
1845         return 0;
1846 }
1847
1848 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1849 {
1850         if (ensoniq->gameport) {
1851                 int port = ensoniq->gameport->io;
1852
1853                 gameport_unregister_port(ensoniq->gameport);
1854                 ensoniq->gameport = NULL;
1855                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1856                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1857                 release_region(port, 8);
1858         }
1859 }
1860 #else
1861 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1862 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1863 #endif /* SUPPORT_JOYSTICK */
1864
1865 /*
1866
1867  */
1868
1869 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1870                                   struct snd_info_buffer *buffer)
1871 {
1872         struct ensoniq *ensoniq = entry->private_data;
1873
1874         snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1875         snd_iprintf(buffer, "Joystick enable  : %s\n",
1876                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1877 #ifdef CHIP1370
1878         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1879                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1880         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1881                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1882 #else
1883         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1884                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1885 #endif
1886 }
1887
1888 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1889 {
1890         struct snd_info_entry *entry;
1891
1892         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1893                 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1894 }
1895
1896 /*
1897
1898  */
1899
1900 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1901 {
1902         snd_ensoniq_free_gameport(ensoniq);
1903         if (ensoniq->irq < 0)
1904                 goto __hw_end;
1905 #ifdef CHIP1370
1906         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1907         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1908 #else
1909         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1910         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1911 #endif
1912         if (ensoniq->irq >= 0)
1913                 synchronize_irq(ensoniq->irq);
1914         pci_set_power_state(ensoniq->pci, 3);
1915       __hw_end:
1916 #ifdef CHIP1370
1917         if (ensoniq->dma_bug.area)
1918                 snd_dma_free_pages(&ensoniq->dma_bug);
1919 #endif
1920         if (ensoniq->irq >= 0)
1921                 free_irq(ensoniq->irq, ensoniq);
1922         pci_release_regions(ensoniq->pci);
1923         pci_disable_device(ensoniq->pci);
1924         kfree(ensoniq);
1925         return 0;
1926 }
1927
1928 static int snd_ensoniq_dev_free(struct snd_device *device)
1929 {
1930         struct ensoniq *ensoniq = device->device_data;
1931         return snd_ensoniq_free(ensoniq);
1932 }
1933
1934 #ifdef CHIP1371
1935 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1936         SND_PCI_QUIRK_ID(0x107b, 0x2150),       /* Gateway Solo 2150 */
1937         SND_PCI_QUIRK_ID(0x13bd, 0x100c),       /* EV1938 on Mebius PC-MJ100V */
1938         SND_PCI_QUIRK_ID(0x1102, 0x5938),       /* Targa Xtender300 */
1939         SND_PCI_QUIRK_ID(0x1102, 0x8938),       /* IPC Topnote G notebook */
1940         { } /* end */
1941 };
1942
1943 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1944         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1945         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1946         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1947         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1948         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1949         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1950 };
1951 #endif
1952
1953 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1954 {
1955 #ifdef CHIP1371
1956         int idx;
1957 #endif
1958         /* this code was part of snd_ensoniq_create before intruduction
1959           * of suspend/resume
1960           */
1961 #ifdef CHIP1370
1962         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1963         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1964         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1965         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1966         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1967 #else
1968         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1969         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1970         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1971         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1972             outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1973             /* need to delay around 20ms(bleech) to give
1974                some CODECs enough time to wakeup */
1975             msleep(20);
1976         }
1977         /* AC'97 warm reset to start the bitclk */
1978         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1979         inl(ES_REG(ensoniq, CONTROL));
1980         udelay(20);
1981         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1982         /* Init the sample rate converter */
1983         snd_es1371_wait_src_ready(ensoniq);
1984         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1985         for (idx = 0; idx < 0x80; idx++)
1986                 snd_es1371_src_write(ensoniq, idx, 0);
1987         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1988         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1989         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1990         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1991         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1992         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1993         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1994         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1995         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1996         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1997         snd_es1371_adc_rate(ensoniq, 22050);
1998         snd_es1371_dac1_rate(ensoniq, 22050);
1999         snd_es1371_dac2_rate(ensoniq, 22050);
2000         /* WARNING:
2001          * enabling the sample rate converter without properly programming
2002          * its parameters causes the chip to lock up (the SRC busy bit will
2003          * be stuck high, and I've found no way to rectify this other than
2004          * power cycle) - Thomas Sailer
2005          */
2006         snd_es1371_wait_src_ready(ensoniq);
2007         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2008         /* try reset codec directly */
2009         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2010 #endif
2011         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2012         outb(0x00, ES_REG(ensoniq, UART_RES));
2013         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2014         synchronize_irq(ensoniq->irq);
2015 }
2016
2017 #ifdef CONFIG_PM_SLEEP
2018 static int snd_ensoniq_suspend(struct device *dev)
2019 {
2020         struct pci_dev *pci = to_pci_dev(dev);
2021         struct snd_card *card = dev_get_drvdata(dev);
2022         struct ensoniq *ensoniq = card->private_data;
2023
2024         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2025
2026         snd_pcm_suspend_all(ensoniq->pcm1);
2027         snd_pcm_suspend_all(ensoniq->pcm2);
2028
2029 #ifdef CHIP1371
2030         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2031 #else
2032         /* try to reset AK4531 */
2033         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2034         inw(ES_REG(ensoniq, 1370_CODEC));
2035         udelay(100);
2036         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2037         inw(ES_REG(ensoniq, 1370_CODEC));
2038         udelay(100);
2039         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2040 #endif
2041
2042         pci_disable_device(pci);
2043         pci_save_state(pci);
2044         pci_set_power_state(pci, PCI_D3hot);
2045         return 0;
2046 }
2047
2048 static int snd_ensoniq_resume(struct device *dev)
2049 {
2050         struct pci_dev *pci = to_pci_dev(dev);
2051         struct snd_card *card = dev_get_drvdata(dev);
2052         struct ensoniq *ensoniq = card->private_data;
2053
2054         pci_set_power_state(pci, PCI_D0);
2055         pci_restore_state(pci);
2056         if (pci_enable_device(pci) < 0) {
2057                 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2058                        "disabling device\n");
2059                 snd_card_disconnect(card);
2060                 return -EIO;
2061         }
2062         pci_set_master(pci);
2063
2064         snd_ensoniq_chip_init(ensoniq);
2065
2066 #ifdef CHIP1371
2067         snd_ac97_resume(ensoniq->u.es1371.ac97);
2068 #else
2069         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2070 #endif
2071         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2072         return 0;
2073 }
2074
2075 static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2076 #define SND_ENSONIQ_PM_OPS      &snd_ensoniq_pm
2077 #else
2078 #define SND_ENSONIQ_PM_OPS      NULL
2079 #endif /* CONFIG_PM_SLEEP */
2080
2081 static int __devinit snd_ensoniq_create(struct snd_card *card,
2082                                      struct pci_dev *pci,
2083                                      struct ensoniq ** rensoniq)
2084 {
2085         struct ensoniq *ensoniq;
2086         int err;
2087         static struct snd_device_ops ops = {
2088                 .dev_free =     snd_ensoniq_dev_free,
2089         };
2090
2091         *rensoniq = NULL;
2092         if ((err = pci_enable_device(pci)) < 0)
2093                 return err;
2094         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2095         if (ensoniq == NULL) {
2096                 pci_disable_device(pci);
2097                 return -ENOMEM;
2098         }
2099         spin_lock_init(&ensoniq->reg_lock);
2100         mutex_init(&ensoniq->src_mutex);
2101         ensoniq->card = card;
2102         ensoniq->pci = pci;
2103         ensoniq->irq = -1;
2104         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2105                 kfree(ensoniq);
2106                 pci_disable_device(pci);
2107                 return err;
2108         }
2109         ensoniq->port = pci_resource_start(pci, 0);
2110         if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2111                         KBUILD_MODNAME, ensoniq)) {
2112                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2113                 snd_ensoniq_free(ensoniq);
2114                 return -EBUSY;
2115         }
2116         ensoniq->irq = pci->irq;
2117 #ifdef CHIP1370
2118         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2119                                 16, &ensoniq->dma_bug) < 0) {
2120                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2121                 snd_ensoniq_free(ensoniq);
2122                 return -EBUSY;
2123         }
2124 #endif
2125         pci_set_master(pci);
2126         ensoniq->rev = pci->revision;
2127 #ifdef CHIP1370
2128 #if 0
2129         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2130                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2131 #else   /* get microphone working */
2132         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2133 #endif
2134         ensoniq->sctrl = 0;
2135 #else
2136         ensoniq->ctrl = 0;
2137         ensoniq->sctrl = 0;
2138         ensoniq->cssr = 0;
2139         if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2140                 ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2141
2142         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2143                 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2144 #endif
2145
2146         snd_ensoniq_chip_init(ensoniq);
2147
2148         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2149                 snd_ensoniq_free(ensoniq);
2150                 return err;
2151         }
2152
2153         snd_ensoniq_proc_init(ensoniq);
2154
2155         snd_card_set_dev(card, &pci->dev);
2156
2157         *rensoniq = ensoniq;
2158         return 0;
2159 }
2160
2161 /*
2162  *  MIDI section
2163  */
2164
2165 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2166 {
2167         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2168         unsigned char status, mask, byte;
2169
2170         if (rmidi == NULL)
2171                 return;
2172         /* do Rx at first */
2173         spin_lock(&ensoniq->reg_lock);
2174         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2175         while (mask) {
2176                 status = inb(ES_REG(ensoniq, UART_STATUS));
2177                 if ((status & mask) == 0)
2178                         break;
2179                 byte = inb(ES_REG(ensoniq, UART_DATA));
2180                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2181         }
2182         spin_unlock(&ensoniq->reg_lock);
2183
2184         /* do Tx at second */
2185         spin_lock(&ensoniq->reg_lock);
2186         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2187         while (mask) {
2188                 status = inb(ES_REG(ensoniq, UART_STATUS));
2189                 if ((status & mask) == 0)
2190                         break;
2191                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2192                         ensoniq->uartc &= ~ES_TXINTENM;
2193                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2194                         mask &= ~ES_TXRDY;
2195                 } else {
2196                         outb(byte, ES_REG(ensoniq, UART_DATA));
2197                 }
2198         }
2199         spin_unlock(&ensoniq->reg_lock);
2200 }
2201
2202 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2203 {
2204         struct ensoniq *ensoniq = substream->rmidi->private_data;
2205
2206         spin_lock_irq(&ensoniq->reg_lock);
2207         ensoniq->uartm |= ES_MODE_INPUT;
2208         ensoniq->midi_input = substream;
2209         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2210                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2211                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2212                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2213         }
2214         spin_unlock_irq(&ensoniq->reg_lock);
2215         return 0;
2216 }
2217
2218 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2219 {
2220         struct ensoniq *ensoniq = substream->rmidi->private_data;
2221
2222         spin_lock_irq(&ensoniq->reg_lock);
2223         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2224                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2225                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2226         } else {
2227                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2228         }
2229         ensoniq->midi_input = NULL;
2230         ensoniq->uartm &= ~ES_MODE_INPUT;
2231         spin_unlock_irq(&ensoniq->reg_lock);
2232         return 0;
2233 }
2234
2235 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2236 {
2237         struct ensoniq *ensoniq = substream->rmidi->private_data;
2238
2239         spin_lock_irq(&ensoniq->reg_lock);
2240         ensoniq->uartm |= ES_MODE_OUTPUT;
2241         ensoniq->midi_output = substream;
2242         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2243                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2244                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2245                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2246         }
2247         spin_unlock_irq(&ensoniq->reg_lock);
2248         return 0;
2249 }
2250
2251 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2252 {
2253         struct ensoniq *ensoniq = substream->rmidi->private_data;
2254
2255         spin_lock_irq(&ensoniq->reg_lock);
2256         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2257                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2258                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2259         } else {
2260                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2261         }
2262         ensoniq->midi_output = NULL;
2263         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2264         spin_unlock_irq(&ensoniq->reg_lock);
2265         return 0;
2266 }
2267
2268 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2269 {
2270         unsigned long flags;
2271         struct ensoniq *ensoniq = substream->rmidi->private_data;
2272         int idx;
2273
2274         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2275         if (up) {
2276                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2277                         /* empty input FIFO */
2278                         for (idx = 0; idx < 32; idx++)
2279                                 inb(ES_REG(ensoniq, UART_DATA));
2280                         ensoniq->uartc |= ES_RXINTEN;
2281                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2282                 }
2283         } else {
2284                 if (ensoniq->uartc & ES_RXINTEN) {
2285                         ensoniq->uartc &= ~ES_RXINTEN;
2286                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2287                 }
2288         }
2289         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2290 }
2291
2292 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2293 {
2294         unsigned long flags;
2295         struct ensoniq *ensoniq = substream->rmidi->private_data;
2296         unsigned char byte;
2297
2298         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2299         if (up) {
2300                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2301                         ensoniq->uartc |= ES_TXINTENO(1);
2302                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2303                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2304                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2305                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2306                                         ensoniq->uartc &= ~ES_TXINTENM;
2307                                 } else {
2308                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2309                                 }
2310                         }
2311                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2312                 }
2313         } else {
2314                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2315                         ensoniq->uartc &= ~ES_TXINTENM;
2316                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2317                 }
2318         }
2319         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2320 }
2321
2322 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2323 {
2324         .open =         snd_ensoniq_midi_output_open,
2325         .close =        snd_ensoniq_midi_output_close,
2326         .trigger =      snd_ensoniq_midi_output_trigger,
2327 };
2328
2329 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2330 {
2331         .open =         snd_ensoniq_midi_input_open,
2332         .close =        snd_ensoniq_midi_input_close,
2333         .trigger =      snd_ensoniq_midi_input_trigger,
2334 };
2335
2336 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2337                                       struct snd_rawmidi **rrawmidi)
2338 {
2339         struct snd_rawmidi *rmidi;
2340         int err;
2341
2342         if (rrawmidi)
2343                 *rrawmidi = NULL;
2344         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2345                 return err;
2346         strcpy(rmidi->name, CHIP_NAME);
2347         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2348         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2349         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2350                 SNDRV_RAWMIDI_INFO_DUPLEX;
2351         rmidi->private_data = ensoniq;
2352         ensoniq->rmidi = rmidi;
2353         if (rrawmidi)
2354                 *rrawmidi = rmidi;
2355         return 0;
2356 }
2357
2358 /*
2359  *  Interrupt handler
2360  */
2361
2362 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2363 {
2364         struct ensoniq *ensoniq = dev_id;
2365         unsigned int status, sctrl;
2366
2367         if (ensoniq == NULL)
2368                 return IRQ_NONE;
2369
2370         status = inl(ES_REG(ensoniq, STATUS));
2371         if (!(status & ES_INTR))
2372                 return IRQ_NONE;
2373
2374         spin_lock(&ensoniq->reg_lock);
2375         sctrl = ensoniq->sctrl;
2376         if (status & ES_DAC1)
2377                 sctrl &= ~ES_P1_INT_EN;
2378         if (status & ES_DAC2)
2379                 sctrl &= ~ES_P2_INT_EN;
2380         if (status & ES_ADC)
2381                 sctrl &= ~ES_R1_INT_EN;
2382         outl(sctrl, ES_REG(ensoniq, SERIAL));
2383         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2384         spin_unlock(&ensoniq->reg_lock);
2385
2386         if (status & ES_UART)
2387                 snd_ensoniq_midi_interrupt(ensoniq);
2388         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2389                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2390         if ((status & ES_ADC) && ensoniq->capture_substream)
2391                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2392         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2393                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2394         return IRQ_HANDLED;
2395 }
2396
2397 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2398                                         const struct pci_device_id *pci_id)
2399 {
2400         static int dev;
2401         struct snd_card *card;
2402         struct ensoniq *ensoniq;
2403         int err, pcm_devs[2];
2404
2405         if (dev >= SNDRV_CARDS)
2406                 return -ENODEV;
2407         if (!enable[dev]) {
2408                 dev++;
2409                 return -ENOENT;
2410         }
2411
2412         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2413         if (err < 0)
2414                 return err;
2415
2416         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2417                 snd_card_free(card);
2418                 return err;
2419         }
2420         card->private_data = ensoniq;
2421
2422         pcm_devs[0] = 0; pcm_devs[1] = 1;
2423 #ifdef CHIP1370
2424         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2425                 snd_card_free(card);
2426                 return err;
2427         }
2428 #endif
2429 #ifdef CHIP1371
2430         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2431                 snd_card_free(card);
2432                 return err;
2433         }
2434 #endif
2435         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2436                 snd_card_free(card);
2437                 return err;
2438         }
2439         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2440                 snd_card_free(card);
2441                 return err;
2442         }
2443         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2444                 snd_card_free(card);
2445                 return err;
2446         }
2447
2448         snd_ensoniq_create_gameport(ensoniq, dev);
2449
2450         strcpy(card->driver, DRIVER_NAME);
2451
2452         strcpy(card->shortname, "Ensoniq AudioPCI");
2453         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2454                 card->shortname,
2455                 card->driver,
2456                 ensoniq->port,
2457                 ensoniq->irq);
2458
2459         if ((err = snd_card_register(card)) < 0) {
2460                 snd_card_free(card);
2461                 return err;
2462         }
2463
2464         pci_set_drvdata(pci, card);
2465         dev++;
2466         return 0;
2467 }
2468
2469 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2470 {
2471         snd_card_free(pci_get_drvdata(pci));
2472         pci_set_drvdata(pci, NULL);
2473 }
2474
2475 static struct pci_driver ens137x_driver = {
2476         .name = KBUILD_MODNAME,
2477         .id_table = snd_audiopci_ids,
2478         .probe = snd_audiopci_probe,
2479         .remove = __devexit_p(snd_audiopci_remove),
2480         .driver = {
2481                 .pm = SND_ENSONIQ_PM_OPS,
2482         },
2483 };
2484
2485 module_pci_driver(ens137x_driver);