1 /****************************************************************************
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
7 This file is part of Echo Digital Audio's generic driver library.
9 Echo Digital Audio's generic driver library is free software;
10 you can redistribute it and/or modify it under the terms of
11 the GNU General Public License as published by the Free Software
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
24 *************************************************************************
26 Translation from C++ and adaptation for use in ALSA-Driver
27 were made by Giuliano Pochini <pochini@shiny.it>
29 ****************************************************************************/
32 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
34 static int set_professional_spdif(struct echoaudio *chip, char prof);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
36 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
37 static int check_asic_status(struct echoaudio *chip);
40 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
44 DE_INIT(("init_hw() - Mona\n"));
45 if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA))
48 if ((err = init_dsp_comm_page(chip))) {
49 DE_INIT(("init_hw - could not initialize DSP comm page\n"));
53 chip->device_id = device_id;
54 chip->subdevice_id = subdevice_id;
55 chip->bad_board = TRUE;
56 chip->input_clock_types =
57 ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
58 ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
60 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
61 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
62 ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
64 /* Mona comes in both '301 and '361 flavors */
65 if (chip->device_id == DEVICE_ID_56361)
66 chip->dsp_code_to_load = FW_MONA_361_DSP;
68 chip->dsp_code_to_load = FW_MONA_301_DSP;
70 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
71 chip->professional_spdif = FALSE;
72 chip->digital_in_automute = TRUE;
74 if ((err = load_firmware(chip)) < 0)
76 chip->bad_board = FALSE;
78 if ((err = init_line_levels(chip)) < 0)
81 err = set_digital_mode(chip, DIGITAL_MODE_SPDIF_RCA);
84 err = set_professional_spdif(chip, TRUE);
86 DE_INIT(("init_hw done\n"));
92 static u32 detect_input_clocks(const struct echoaudio *chip)
94 u32 clocks_from_dsp, clock_bits;
96 /* Map the DSP clock detect bits to the generic driver clock
98 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
100 clock_bits = ECHO_CLOCK_BIT_INTERNAL;
102 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
103 clock_bits |= ECHO_CLOCK_BIT_SPDIF;
105 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
106 clock_bits |= ECHO_CLOCK_BIT_ADAT;
108 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
109 clock_bits |= ECHO_CLOCK_BIT_WORD;
116 /* Mona has an ASIC on the PCI card and another ASIC in the external box;
117 both need to be loaded. */
118 static int load_asic(struct echoaudio *chip)
124 if (chip->asic_loaded)
129 if (chip->device_id == DEVICE_ID_56361)
130 asic = FW_MONA_361_1_ASIC48;
132 asic = FW_MONA_301_1_ASIC48;
134 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
138 chip->asic_code = asic;
141 /* Do the external one */
142 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
148 err = check_asic_status(chip);
150 /* Set up the control register if the load succeeded -
151 48 kHz, internal clock, S/PDIF RCA mode */
153 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
154 err = write_control_reg(chip, control_reg, TRUE);
162 /* Depending on what digital mode you want, Mona needs different ASICs
163 loaded. This function checks the ASIC needed for the new mode and sees
164 if it matches the one already loaded. */
165 static int switch_asic(struct echoaudio *chip, char double_speed)
170 /* Check the clock detect bits to see if this is
171 a single-speed clock or a double-speed clock; load
172 a new ASIC if necessary. */
173 if (chip->device_id == DEVICE_ID_56361) {
175 asic = FW_MONA_361_1_ASIC96;
177 asic = FW_MONA_361_1_ASIC48;
180 asic = FW_MONA_301_1_ASIC96;
182 asic = FW_MONA_301_1_ASIC48;
185 if (asic != chip->asic_code) {
186 /* Load the desired ASIC */
187 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
191 chip->asic_code = asic;
199 static int set_sample_rate(struct echoaudio *chip, u32 rate)
201 u32 control_reg, clock;
205 /* Only set the clock for internal mode. */
206 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
207 DE_ACT(("set_sample_rate: Cannot set sample rate - "
208 "clock not set to CLK_CLOCKININTERNAL\n"));
209 /* Save the rate anyhow */
210 chip->comm_page->sample_rate = cpu_to_le32(rate);
211 chip->sample_rate = rate;
215 /* Now, check to see if the required ASIC is loaded */
217 if (chip->digital_mode == DIGITAL_MODE_ADAT)
219 if (chip->device_id == DEVICE_ID_56361)
220 asic = FW_MONA_361_1_ASIC96;
222 asic = FW_MONA_301_1_ASIC96;
224 if (chip->device_id == DEVICE_ID_56361)
225 asic = FW_MONA_361_1_ASIC48;
227 asic = FW_MONA_301_1_ASIC48;
231 if (asic != chip->asic_code) {
233 /* Load the desired ASIC (load_asic_generic() can sleep) */
234 spin_unlock_irq(&chip->lock);
235 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
237 spin_lock_irq(&chip->lock);
241 chip->asic_code = asic;
245 /* Compute the new control register value */
247 control_reg = le32_to_cpu(chip->comm_page->control_register);
248 control_reg &= GML_CLOCK_CLEAR_MASK;
249 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
259 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
263 /* Professional mode */
264 if (control_reg & GML_SPDIF_PRO_MODE)
265 clock |= GML_SPDIF_SAMPLE_RATE0;
268 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
269 GML_SPDIF_SAMPLE_RATE1;
284 DE_ACT(("set_sample_rate: %d invalid!\n", rate));
288 control_reg |= clock;
290 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
291 chip->sample_rate = rate;
292 DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
294 return write_control_reg(chip, control_reg, force_write);
299 static int set_input_clock(struct echoaudio *chip, u16 clock)
301 u32 control_reg, clocks_from_dsp;
304 DE_ACT(("set_input_clock:\n"));
306 /* Prevent two simultaneous calls to switch_asic() */
307 if (atomic_read(&chip->opencount))
310 /* Mask off the clock select bits */
311 control_reg = le32_to_cpu(chip->comm_page->control_register) &
312 GML_CLOCK_CLEAR_MASK;
313 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
316 case ECHO_CLOCK_INTERNAL:
317 DE_ACT(("Set Mona clock to INTERNAL\n"));
318 chip->input_clock = ECHO_CLOCK_INTERNAL;
319 return set_sample_rate(chip, chip->sample_rate);
320 case ECHO_CLOCK_SPDIF:
321 if (chip->digital_mode == DIGITAL_MODE_ADAT)
323 spin_unlock_irq(&chip->lock);
324 err = switch_asic(chip, clocks_from_dsp &
325 GML_CLOCK_DETECT_BIT_SPDIF96);
326 spin_lock_irq(&chip->lock);
329 DE_ACT(("Set Mona clock to SPDIF\n"));
330 control_reg |= GML_SPDIF_CLOCK;
331 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
332 control_reg |= GML_DOUBLE_SPEED_MODE;
334 control_reg &= ~GML_DOUBLE_SPEED_MODE;
336 case ECHO_CLOCK_WORD:
337 DE_ACT(("Set Mona clock to WORD\n"));
338 spin_unlock_irq(&chip->lock);
339 err = switch_asic(chip, clocks_from_dsp &
340 GML_CLOCK_DETECT_BIT_WORD96);
341 spin_lock_irq(&chip->lock);
344 control_reg |= GML_WORD_CLOCK;
345 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
346 control_reg |= GML_DOUBLE_SPEED_MODE;
348 control_reg &= ~GML_DOUBLE_SPEED_MODE;
350 case ECHO_CLOCK_ADAT:
351 DE_ACT(("Set Mona clock to ADAT\n"));
352 if (chip->digital_mode != DIGITAL_MODE_ADAT)
354 control_reg |= GML_ADAT_CLOCK;
355 control_reg &= ~GML_DOUBLE_SPEED_MODE;
358 DE_ACT(("Input clock 0x%x not supported for Mona\n", clock));
362 chip->input_clock = clock;
363 return write_control_reg(chip, control_reg, TRUE);
368 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
371 int err, incompatible_clock;
373 /* Set clock to "internal" if it's not compatible with the new mode */
374 incompatible_clock = FALSE;
376 case DIGITAL_MODE_SPDIF_OPTICAL:
377 case DIGITAL_MODE_SPDIF_RCA:
378 if (chip->input_clock == ECHO_CLOCK_ADAT)
379 incompatible_clock = TRUE;
381 case DIGITAL_MODE_ADAT:
382 if (chip->input_clock == ECHO_CLOCK_SPDIF)
383 incompatible_clock = TRUE;
386 DE_ACT(("Digital mode not supported: %d\n", mode));
390 spin_lock_irq(&chip->lock);
392 if (incompatible_clock) { /* Switch to 48KHz, internal */
393 chip->sample_rate = 48000;
394 set_input_clock(chip, ECHO_CLOCK_INTERNAL);
397 /* Clear the current digital mode */
398 control_reg = le32_to_cpu(chip->comm_page->control_register);
399 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
401 /* Tweak the control reg */
403 case DIGITAL_MODE_SPDIF_OPTICAL:
404 control_reg |= GML_SPDIF_OPTICAL_MODE;
406 case DIGITAL_MODE_SPDIF_RCA:
407 /* GML_SPDIF_OPTICAL_MODE bit cleared */
409 case DIGITAL_MODE_ADAT:
410 /* If the current ASIC is the 96KHz ASIC, switch the ASIC
412 if (chip->asic_code == FW_MONA_361_1_ASIC96 ||
413 chip->asic_code == FW_MONA_301_1_ASIC96) {
414 set_sample_rate(chip, 48000);
416 control_reg |= GML_ADAT_MODE;
417 control_reg &= ~GML_DOUBLE_SPEED_MODE;
421 err = write_control_reg(chip, control_reg, FALSE);
422 spin_unlock_irq(&chip->lock);
425 chip->digital_mode = mode;
427 DE_ACT(("set_digital_mode to %d\n", mode));
428 return incompatible_clock;