2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
11 * This file contains the implementation of hardware access methord for 20k1.
18 #include <linux/types.h>
19 #include <linux/slab.h>
20 #include <linux/pci.h>
22 #include <linux/string.h>
23 #include <linux/spinlock.h>
24 #include <linux/kernel.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
28 #include "ct20k1reg.h"
32 spinlock_t reg_20k1_lock;
33 spinlock_t reg_pci_lock;
36 static u32 hw_read_20kx(struct hw *hw, u32 reg);
37 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
38 static u32 hw_read_pci(struct hw *hw, u32 reg);
39 static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
42 * Type definition block.
43 * The layout of control structures can be directly applied on 20k2 chip.
47 * SRC control block definitions.
50 /* SRC resource control block */
51 #define SRCCTL_STATE 0x00000007
52 #define SRCCTL_BM 0x00000008
53 #define SRCCTL_RSR 0x00000030
54 #define SRCCTL_SF 0x000001C0
55 #define SRCCTL_WR 0x00000200
56 #define SRCCTL_PM 0x00000400
57 #define SRCCTL_ROM 0x00001800
58 #define SRCCTL_VO 0x00002000
59 #define SRCCTL_ST 0x00004000
60 #define SRCCTL_IE 0x00008000
61 #define SRCCTL_ILSZ 0x000F0000
62 #define SRCCTL_BP 0x00100000
64 #define SRCCCR_CISZ 0x000007FF
65 #define SRCCCR_CWA 0x001FF800
66 #define SRCCCR_D 0x00200000
67 #define SRCCCR_RS 0x01C00000
68 #define SRCCCR_NAL 0x3E000000
69 #define SRCCCR_RA 0xC0000000
71 #define SRCCA_CA 0x03FFFFFF
72 #define SRCCA_RS 0x1C000000
73 #define SRCCA_NAL 0xE0000000
75 #define SRCSA_SA 0x03FFFFFF
77 #define SRCLA_LA 0x03FFFFFF
79 /* Mixer Parameter Ring ram Low and Hight register.
80 * Fixed-point value in 8.24 format for parameter channel */
81 #define MPRLH_PITCH 0xFFFFFFFF
83 /* SRC resource register dirty flags */
92 u16 czbfs:1; /* Clear Z-Buffers */
98 struct src_rsc_ctrl_blk {
105 union src_dirty dirty;
108 /* SRC manager control block */
109 union src_mgr_dirty {
125 struct src_mgr_ctrl_blk {
128 union src_mgr_dirty dirty;
131 /* SRCIMP manager control block */
132 #define SRCAIM_ARC 0x00000FFF
133 #define SRCAIM_NXT 0x00FF0000
134 #define SRCAIM_SRC 0xFF000000
141 /* SRCIMP manager register dirty flags */
142 union srcimp_mgr_dirty {
150 struct srcimp_mgr_ctrl_blk {
151 struct srcimap srcimap;
152 union srcimp_mgr_dirty dirty;
156 * Function implementation block.
159 static int src_get_rsc_ctrl_blk(void **rblk)
161 struct src_rsc_ctrl_blk *blk;
164 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
173 static int src_put_rsc_ctrl_blk(void *blk)
175 kfree((struct src_rsc_ctrl_blk *)blk);
180 static int src_set_state(void *blk, unsigned int state)
182 struct src_rsc_ctrl_blk *ctl = blk;
184 set_field(&ctl->ctl, SRCCTL_STATE, state);
185 ctl->dirty.bf.ctl = 1;
189 static int src_set_bm(void *blk, unsigned int bm)
191 struct src_rsc_ctrl_blk *ctl = blk;
193 set_field(&ctl->ctl, SRCCTL_BM, bm);
194 ctl->dirty.bf.ctl = 1;
198 static int src_set_rsr(void *blk, unsigned int rsr)
200 struct src_rsc_ctrl_blk *ctl = blk;
202 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
203 ctl->dirty.bf.ctl = 1;
207 static int src_set_sf(void *blk, unsigned int sf)
209 struct src_rsc_ctrl_blk *ctl = blk;
211 set_field(&ctl->ctl, SRCCTL_SF, sf);
212 ctl->dirty.bf.ctl = 1;
216 static int src_set_wr(void *blk, unsigned int wr)
218 struct src_rsc_ctrl_blk *ctl = blk;
220 set_field(&ctl->ctl, SRCCTL_WR, wr);
221 ctl->dirty.bf.ctl = 1;
225 static int src_set_pm(void *blk, unsigned int pm)
227 struct src_rsc_ctrl_blk *ctl = blk;
229 set_field(&ctl->ctl, SRCCTL_PM, pm);
230 ctl->dirty.bf.ctl = 1;
234 static int src_set_rom(void *blk, unsigned int rom)
236 struct src_rsc_ctrl_blk *ctl = blk;
238 set_field(&ctl->ctl, SRCCTL_ROM, rom);
239 ctl->dirty.bf.ctl = 1;
243 static int src_set_vo(void *blk, unsigned int vo)
245 struct src_rsc_ctrl_blk *ctl = blk;
247 set_field(&ctl->ctl, SRCCTL_VO, vo);
248 ctl->dirty.bf.ctl = 1;
252 static int src_set_st(void *blk, unsigned int st)
254 struct src_rsc_ctrl_blk *ctl = blk;
256 set_field(&ctl->ctl, SRCCTL_ST, st);
257 ctl->dirty.bf.ctl = 1;
261 static int src_set_ie(void *blk, unsigned int ie)
263 struct src_rsc_ctrl_blk *ctl = blk;
265 set_field(&ctl->ctl, SRCCTL_IE, ie);
266 ctl->dirty.bf.ctl = 1;
270 static int src_set_ilsz(void *blk, unsigned int ilsz)
272 struct src_rsc_ctrl_blk *ctl = blk;
274 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
275 ctl->dirty.bf.ctl = 1;
279 static int src_set_bp(void *blk, unsigned int bp)
281 struct src_rsc_ctrl_blk *ctl = blk;
283 set_field(&ctl->ctl, SRCCTL_BP, bp);
284 ctl->dirty.bf.ctl = 1;
288 static int src_set_cisz(void *blk, unsigned int cisz)
290 struct src_rsc_ctrl_blk *ctl = blk;
292 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
293 ctl->dirty.bf.ccr = 1;
297 static int src_set_ca(void *blk, unsigned int ca)
299 struct src_rsc_ctrl_blk *ctl = blk;
301 set_field(&ctl->ca, SRCCA_CA, ca);
302 ctl->dirty.bf.ca = 1;
306 static int src_set_sa(void *blk, unsigned int sa)
308 struct src_rsc_ctrl_blk *ctl = blk;
310 set_field(&ctl->sa, SRCSA_SA, sa);
311 ctl->dirty.bf.sa = 1;
315 static int src_set_la(void *blk, unsigned int la)
317 struct src_rsc_ctrl_blk *ctl = blk;
319 set_field(&ctl->la, SRCLA_LA, la);
320 ctl->dirty.bf.la = 1;
324 static int src_set_pitch(void *blk, unsigned int pitch)
326 struct src_rsc_ctrl_blk *ctl = blk;
328 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
329 ctl->dirty.bf.mpr = 1;
333 static int src_set_clear_zbufs(void *blk, unsigned int clear)
335 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
339 static int src_set_dirty(void *blk, unsigned int flags)
341 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
345 static int src_set_dirty_all(void *blk)
347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
351 #define AR_SLOT_SIZE 4096
352 #define AR_SLOT_BLOCK_SIZE 16
353 #define AR_PTS_PITCH 6
354 #define AR_PARAM_SRC_OFFSET 0x60
356 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
358 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
359 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
363 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
365 struct src_rsc_ctrl_blk *ctl = blk;
368 if (ctl->dirty.bf.czbfs) {
369 /* Clear Z-Buffer registers */
370 for (i = 0; i < 8; i++)
371 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
373 for (i = 0; i < 4; i++)
374 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
376 for (i = 0; i < 8; i++)
377 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
379 ctl->dirty.bf.czbfs = 0;
381 if (ctl->dirty.bf.mpr) {
382 /* Take the parameter mixer resource in the same group as that
383 * the idx src is in for simplicity. Unlike src, all conjugate
384 * parameter mixer resources must be programmed for
385 * corresponding conjugate src resources. */
386 unsigned int pm_idx = src_param_pitch_mixer(idx);
387 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
388 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
389 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
390 ctl->dirty.bf.mpr = 0;
392 if (ctl->dirty.bf.sa) {
393 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
394 ctl->dirty.bf.sa = 0;
396 if (ctl->dirty.bf.la) {
397 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
398 ctl->dirty.bf.la = 0;
400 if (ctl->dirty.bf.ca) {
401 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
402 ctl->dirty.bf.ca = 0;
405 /* Write srccf register */
406 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
408 if (ctl->dirty.bf.ccr) {
409 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
410 ctl->dirty.bf.ccr = 0;
412 if (ctl->dirty.bf.ctl) {
413 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
414 ctl->dirty.bf.ctl = 0;
420 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
422 struct src_rsc_ctrl_blk *ctl = blk;
424 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
425 ctl->dirty.bf.ca = 0;
427 return get_field(ctl->ca, SRCCA_CA);
430 static unsigned int src_get_dirty(void *blk)
432 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
435 static unsigned int src_dirty_conj_mask(void)
440 static int src_mgr_enbs_src(void *blk, unsigned int idx)
442 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
443 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
444 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
448 static int src_mgr_enb_src(void *blk, unsigned int idx)
450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
451 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
455 static int src_mgr_dsb_src(void *blk, unsigned int idx)
457 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
458 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
462 static int src_mgr_commit_write(struct hw *hw, void *blk)
464 struct src_mgr_ctrl_blk *ctl = blk;
468 if (ctl->dirty.bf.enbsa) {
470 ret = hw_read_20kx(hw, SRCENBSTAT);
472 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
473 ctl->dirty.bf.enbsa = 0;
475 for (i = 0; i < 8; i++) {
476 if ((ctl->dirty.data & (0x1 << i))) {
477 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
478 ctl->dirty.data &= ~(0x1 << i);
485 static int src_mgr_get_ctrl_blk(void **rblk)
487 struct src_mgr_ctrl_blk *blk;
490 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
499 static int src_mgr_put_ctrl_blk(void *blk)
501 kfree((struct src_mgr_ctrl_blk *)blk);
506 static int srcimp_mgr_get_ctrl_blk(void **rblk)
508 struct srcimp_mgr_ctrl_blk *blk;
511 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
520 static int srcimp_mgr_put_ctrl_blk(void *blk)
522 kfree((struct srcimp_mgr_ctrl_blk *)blk);
527 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
529 struct srcimp_mgr_ctrl_blk *ctl = blk;
531 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
532 ctl->dirty.bf.srcimap = 1;
536 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
538 struct srcimp_mgr_ctrl_blk *ctl = blk;
540 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
541 ctl->dirty.bf.srcimap = 1;
545 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
547 struct srcimp_mgr_ctrl_blk *ctl = blk;
549 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
550 ctl->dirty.bf.srcimap = 1;
554 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
556 struct srcimp_mgr_ctrl_blk *ctl = blk;
558 ctl->srcimap.idx = addr;
559 ctl->dirty.bf.srcimap = 1;
563 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
565 struct srcimp_mgr_ctrl_blk *ctl = blk;
567 if (ctl->dirty.bf.srcimap) {
568 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
569 ctl->srcimap.srcaim);
570 ctl->dirty.bf.srcimap = 0;
577 * AMIXER control block definitions.
580 #define AMOPLO_M 0x00000003
581 #define AMOPLO_X 0x0003FFF0
582 #define AMOPLO_Y 0xFFFC0000
584 #define AMOPHI_SADR 0x000000FF
585 #define AMOPHI_SE 0x80000000
587 /* AMIXER resource register dirty flags */
597 /* AMIXER resource control block */
598 struct amixer_rsc_ctrl_blk {
601 union amixer_dirty dirty;
604 static int amixer_set_mode(void *blk, unsigned int mode)
606 struct amixer_rsc_ctrl_blk *ctl = blk;
608 set_field(&ctl->amoplo, AMOPLO_M, mode);
609 ctl->dirty.bf.amoplo = 1;
613 static int amixer_set_iv(void *blk, unsigned int iv)
615 /* 20k1 amixer does not have this field */
619 static int amixer_set_x(void *blk, unsigned int x)
621 struct amixer_rsc_ctrl_blk *ctl = blk;
623 set_field(&ctl->amoplo, AMOPLO_X, x);
624 ctl->dirty.bf.amoplo = 1;
628 static int amixer_set_y(void *blk, unsigned int y)
630 struct amixer_rsc_ctrl_blk *ctl = blk;
632 set_field(&ctl->amoplo, AMOPLO_Y, y);
633 ctl->dirty.bf.amoplo = 1;
637 static int amixer_set_sadr(void *blk, unsigned int sadr)
639 struct amixer_rsc_ctrl_blk *ctl = blk;
641 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
642 ctl->dirty.bf.amophi = 1;
646 static int amixer_set_se(void *blk, unsigned int se)
648 struct amixer_rsc_ctrl_blk *ctl = blk;
650 set_field(&ctl->amophi, AMOPHI_SE, se);
651 ctl->dirty.bf.amophi = 1;
655 static int amixer_set_dirty(void *blk, unsigned int flags)
657 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
661 static int amixer_set_dirty_all(void *blk)
663 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
667 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
669 struct amixer_rsc_ctrl_blk *ctl = blk;
671 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
672 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
673 ctl->dirty.bf.amoplo = 0;
674 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
675 ctl->dirty.bf.amophi = 0;
681 static int amixer_get_y(void *blk)
683 struct amixer_rsc_ctrl_blk *ctl = blk;
685 return get_field(ctl->amoplo, AMOPLO_Y);
688 static unsigned int amixer_get_dirty(void *blk)
690 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
693 static int amixer_rsc_get_ctrl_blk(void **rblk)
695 struct amixer_rsc_ctrl_blk *blk;
698 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
707 static int amixer_rsc_put_ctrl_blk(void *blk)
709 kfree((struct amixer_rsc_ctrl_blk *)blk);
714 static int amixer_mgr_get_ctrl_blk(void **rblk)
716 /*amixer_mgr_ctrl_blk_t *blk;*/
719 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
728 static int amixer_mgr_put_ctrl_blk(void *blk)
730 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
736 * DAIO control block definitions.
739 /* Receiver Sample Rate Tracker Control register */
740 #define SRTCTL_SRCR 0x000000FF
741 #define SRTCTL_SRCL 0x0000FF00
742 #define SRTCTL_RSR 0x00030000
743 #define SRTCTL_DRAT 0x000C0000
744 #define SRTCTL_RLE 0x10000000
745 #define SRTCTL_RLP 0x20000000
746 #define SRTCTL_EC 0x40000000
747 #define SRTCTL_ET 0x80000000
749 /* DAIO Receiver register dirty flags */
758 /* DAIO Receiver control block */
759 struct dai_ctrl_blk {
761 union dai_dirty dirty;
764 /* S/PDIF Transmitter register dirty flags */
773 /* S/PDIF Transmitter control block */
774 struct dao_ctrl_blk {
775 unsigned int spos; /* S/PDIF Output Channel Status Register */
776 union dao_dirty dirty;
779 /* Audio Input Mapper RAM */
780 #define AIM_ARC 0x00000FFF
781 #define AIM_NXT 0x007F0000
788 /* I2S Transmitter/Receiver Control register */
789 #define I2SCTL_EA 0x00000004
790 #define I2SCTL_EI 0x00000010
792 /* S/PDIF Transmitter Control register */
793 #define SPOCTL_OE 0x00000001
794 #define SPOCTL_OS 0x0000000E
795 #define SPOCTL_RIV 0x00000010
796 #define SPOCTL_LIV 0x00000020
797 #define SPOCTL_SR 0x000000C0
799 /* S/PDIF Receiver Control register */
800 #define SPICTL_EN 0x00000001
801 #define SPICTL_I24 0x00000002
802 #define SPICTL_IB 0x00000004
803 #define SPICTL_SM 0x00000008
804 #define SPICTL_VM 0x00000010
806 /* DAIO manager register dirty flags */
807 union daio_mgr_dirty {
819 /* DAIO manager control block */
820 struct daio_mgr_ctrl_blk {
824 struct daoimap daoimap;
825 union daio_mgr_dirty dirty;
828 static int dai_srt_set_srcr(void *blk, unsigned int src)
830 struct dai_ctrl_blk *ctl = blk;
832 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
833 ctl->dirty.bf.srtctl = 1;
837 static int dai_srt_set_srcl(void *blk, unsigned int src)
839 struct dai_ctrl_blk *ctl = blk;
841 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
842 ctl->dirty.bf.srtctl = 1;
846 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
848 struct dai_ctrl_blk *ctl = blk;
850 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
851 ctl->dirty.bf.srtctl = 1;
855 static int dai_srt_set_drat(void *blk, unsigned int drat)
857 struct dai_ctrl_blk *ctl = blk;
859 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
860 ctl->dirty.bf.srtctl = 1;
864 static int dai_srt_set_ec(void *blk, unsigned int ec)
866 struct dai_ctrl_blk *ctl = blk;
868 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
869 ctl->dirty.bf.srtctl = 1;
873 static int dai_srt_set_et(void *blk, unsigned int et)
875 struct dai_ctrl_blk *ctl = blk;
877 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
878 ctl->dirty.bf.srtctl = 1;
882 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
884 struct dai_ctrl_blk *ctl = blk;
886 if (ctl->dirty.bf.srtctl) {
889 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
892 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
894 ctl->dirty.bf.srtctl = 0;
900 static int dai_get_ctrl_blk(void **rblk)
902 struct dai_ctrl_blk *blk;
905 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
914 static int dai_put_ctrl_blk(void *blk)
916 kfree((struct dai_ctrl_blk *)blk);
921 static int dao_set_spos(void *blk, unsigned int spos)
923 ((struct dao_ctrl_blk *)blk)->spos = spos;
924 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
928 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
930 struct dao_ctrl_blk *ctl = blk;
932 if (ctl->dirty.bf.spos) {
935 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
937 ctl->dirty.bf.spos = 0;
943 static int dao_get_spos(void *blk, unsigned int *spos)
945 *spos = ((struct dao_ctrl_blk *)blk)->spos;
949 static int dao_get_ctrl_blk(void **rblk)
951 struct dao_ctrl_blk *blk;
954 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
963 static int dao_put_ctrl_blk(void *blk)
965 kfree((struct dao_ctrl_blk *)blk);
970 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
972 struct daio_mgr_ctrl_blk *ctl = blk;
976 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
977 ctl->dirty.bf.spictl |= (0x1 << idx);
981 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
982 ctl->dirty.bf.i2sictl |= (0x1 << idx);
987 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
989 struct daio_mgr_ctrl_blk *ctl = blk;
993 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
994 ctl->dirty.bf.spictl |= (0x1 << idx);
998 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
999 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1004 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1006 struct daio_mgr_ctrl_blk *ctl = blk;
1010 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1011 ctl->dirty.bf.spoctl |= (0x1 << idx);
1015 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1016 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1021 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1023 struct daio_mgr_ctrl_blk *ctl = blk;
1027 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1028 ctl->dirty.bf.spoctl |= (0x1 << idx);
1032 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1033 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1038 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1040 struct daio_mgr_ctrl_blk *ctl = blk;
1044 switch ((conf & 0x7)) {
1046 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1049 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1052 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1055 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1060 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1061 (conf >> 4) & 0x1); /* Non-audio */
1062 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1063 (conf >> 4) & 0x1); /* Non-audio */
1064 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1065 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1067 ctl->dirty.bf.spoctl |= (0x1 << idx);
1075 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1077 struct daio_mgr_ctrl_blk *ctl = blk;
1079 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1080 ctl->dirty.bf.daoimap = 1;
1084 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1086 struct daio_mgr_ctrl_blk *ctl = blk;
1088 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1089 ctl->dirty.bf.daoimap = 1;
1093 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1095 struct daio_mgr_ctrl_blk *ctl = blk;
1097 ctl->daoimap.idx = addr;
1098 ctl->dirty.bf.daoimap = 1;
1102 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1104 struct daio_mgr_ctrl_blk *ctl = blk;
1107 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1108 for (i = 0; i < 4; i++) {
1109 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1110 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1112 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1113 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1115 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1118 if (ctl->dirty.bf.spoctl) {
1119 for (i = 0; i < 4; i++) {
1120 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1121 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1123 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1126 if (ctl->dirty.bf.spictl) {
1127 for (i = 0; i < 4; i++) {
1128 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1129 ctl->dirty.bf.spictl &= ~(0x1 << i);
1131 hw_write_20kx(hw, SPICTL, ctl->spictl);
1134 if (ctl->dirty.bf.daoimap) {
1135 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1137 ctl->dirty.bf.daoimap = 0;
1143 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1145 struct daio_mgr_ctrl_blk *blk;
1148 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1152 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1153 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1154 blk->spictl = hw_read_20kx(hw, SPICTL);
1161 static int daio_mgr_put_ctrl_blk(void *blk)
1163 kfree((struct daio_mgr_ctrl_blk *)blk);
1168 /* Timer interrupt */
1169 static int set_timer_irq(struct hw *hw, int enable)
1171 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1175 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1178 ticks |= TIMR_IE | TIMR_IP;
1179 hw_write_20kx(hw, TIMR, ticks);
1183 static unsigned int get_wc(struct hw *hw)
1185 return hw_read_20kx(hw, WC);
1188 /* Card hardware initialization block */
1190 unsigned int msr; /* master sample rate in rsrs */
1194 unsigned int msr; /* master sample rate in rsrs */
1195 unsigned char input; /* the input source of ADC */
1196 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1200 unsigned int msr; /* master sample rate in rsrs */
1204 unsigned long vm_pgt_phys;
1207 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1212 /* Read I2S CTL. Keep original value. */
1213 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1214 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1215 /* Program I2S with proper master sample rate and enable
1216 * the correct I2S channel. */
1217 i2sorg &= 0xfffffffc;
1219 /* Enable S/PDIF-out-A in fixed 24-bit data
1220 * format and default to 48kHz. */
1221 /* Disable all before doing any changes. */
1222 hw_write_20kx(hw, SPOCTL, 0x0);
1225 switch (info->msr) {
1228 spdorg |= (0x0 << 6);
1232 spdorg |= (0x1 << 6);
1236 spdorg |= (0x2 << 6);
1243 hw_write_20kx(hw, I2SCTL, i2sorg);
1244 hw_write_20kx(hw, SPOCTL, spdorg);
1246 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1247 /* Disable all before doing any changes. */
1248 hw_write_20kx(hw, SPICTL, 0x0);
1250 spdorg = 0x0a0a0a0a;
1251 hw_write_20kx(hw, SPICTL, spdorg);
1257 /* TRANSPORT operations */
1258 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1261 u32 ptp_phys_low, ptp_phys_high;
1263 /* Set up device page table */
1264 if ((~0UL) == info->vm_pgt_phys) {
1265 printk(KERN_ERR "Wrong device page table page address!\n");
1269 trnctl = 0x13; /* 32-bit, 4k-size page */
1270 ptp_phys_low = (u32)info->vm_pgt_phys;
1271 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1272 if (sizeof(void *) == 8) /* 64bit address */
1274 #if 0 /* Only 4k h/w pages for simplicitiy */
1275 #if PAGE_SIZE == 8192
1279 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1280 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1281 hw_write_20kx(hw, TRNCTL, trnctl);
1282 hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */
1287 /* Card initialization */
1288 #define GCTL_EAC 0x00000001
1289 #define GCTL_EAI 0x00000002
1290 #define GCTL_BEP 0x00000004
1291 #define GCTL_BES 0x00000008
1292 #define GCTL_DSP 0x00000010
1293 #define GCTL_DBP 0x00000020
1294 #define GCTL_ABP 0x00000040
1295 #define GCTL_TBP 0x00000080
1296 #define GCTL_SBP 0x00000100
1297 #define GCTL_FBP 0x00000200
1298 #define GCTL_XA 0x00000400
1299 #define GCTL_ET 0x00000800
1300 #define GCTL_PR 0x00001000
1301 #define GCTL_MRL 0x00002000
1302 #define GCTL_SDE 0x00004000
1303 #define GCTL_SDI 0x00008000
1304 #define GCTL_SM 0x00010000
1305 #define GCTL_SR 0x00020000
1306 #define GCTL_SD 0x00040000
1307 #define GCTL_SE 0x00080000
1308 #define GCTL_AID 0x00100000
1310 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1312 unsigned int pllctl;
1315 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1316 for (i = 0; i < 3; i++) {
1317 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1320 hw_write_20kx(hw, PLLCTL, pllctl);
1324 printk(KERN_ALERT "PLL initialization failed!!!\n");
1331 static int hw_auto_init(struct hw *hw)
1336 gctl = hw_read_20kx(hw, GCTL);
1337 set_field(&gctl, GCTL_EAI, 0);
1338 hw_write_20kx(hw, GCTL, gctl);
1339 set_field(&gctl, GCTL_EAI, 1);
1340 hw_write_20kx(hw, GCTL, gctl);
1342 for (i = 0; i < 400000; i++) {
1343 gctl = hw_read_20kx(hw, GCTL);
1344 if (get_field(gctl, GCTL_AID))
1347 if (!get_field(gctl, GCTL_AID)) {
1348 printk(KERN_ALERT "Card Auto-init failed!!!\n");
1355 static int i2c_unlock(struct hw *hw)
1357 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1360 hw_write_pci(hw, 0xcc, 0x8c);
1361 hw_write_pci(hw, 0xcc, 0x0e);
1362 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1365 hw_write_pci(hw, 0xcc, 0xee);
1366 hw_write_pci(hw, 0xcc, 0xaa);
1367 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1373 static void i2c_lock(struct hw *hw)
1375 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1376 hw_write_pci(hw, 0xcc, 0x00);
1379 static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1384 ret = hw_read_pci(hw, 0xEC);
1385 } while (!(ret & 0x800000));
1386 hw_write_pci(hw, 0xE0, device);
1387 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1390 /* DAC operations */
1392 static int hw_reset_dac(struct hw *hw)
1402 ret = hw_read_pci(hw, 0xEC);
1403 } while (!(ret & 0x800000));
1404 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1406 /* To be effective, need to reset the DAC twice. */
1407 for (i = 0; i < 2; i++) {
1410 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1412 hw_write_20kx(hw, GPIO, gpioorg);
1414 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1417 i2c_write(hw, 0x00180080, 0x01, 0x80);
1418 i2c_write(hw, 0x00180080, 0x02, 0x10);
1425 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1431 if (hw->model == CTSB055X) {
1432 /* SB055x, unmute outputs */
1433 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1434 gpioorg &= 0xffbf; /* set GPIO6 to low */
1435 gpioorg |= 2; /* set GPIO1 to high */
1436 hw_write_20kx(hw, GPIO, gpioorg);
1441 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1443 hw_write_20kx(hw, GPIO, gpioorg);
1450 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1452 ret = hw_read_pci(hw, 0xEC);
1453 } while (!(ret & 0x800000));
1455 switch (info->msr) {
1470 i2c_write(hw, 0x00180080, 0x06, data);
1471 i2c_write(hw, 0x00180080, 0x09, data);
1472 i2c_write(hw, 0x00180080, 0x0c, data);
1473 i2c_write(hw, 0x00180080, 0x0f, data);
1477 /* unmute outputs */
1478 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1479 gpioorg = gpioorg | 0x40;
1480 hw_write_20kx(hw, GPIO, gpioorg);
1485 /* ADC operations */
1487 static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1492 static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1496 data = hw_read_20kx(hw, GPIO);
1499 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1502 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1504 case ADC_NONE: /* Digital I/O */
1505 data = (!(data & (0x1<<8)));
1513 static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1517 data = hw_read_20kx(hw, GPIO);
1520 data = (data & (0x1 << 7)) ? 1 : 0;
1523 data = (data & (0x1 << 7)) ? 0 : 1;
1531 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1533 switch (hw->model) {
1535 return is_adc_input_selected_SB055x(hw, type);
1537 return is_adc_input_selected_hendrix(hw, type);
1539 return is_adc_input_selected_hendrix(hw, type);
1541 return is_adc_input_selected_SBx(hw, type);
1546 adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1551 * check and set the following GPIO bits accordingly
1554 * Mic_Pwr_on = GPIO7
1555 * Digital_IO_Sel = GPIO8
1557 * Aux/MicLine_Sw = GPIO12
1559 data = hw_read_20kx(hw, GPIO);
1563 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1564 data |= boost ? (0x1<<2) : 0;
1570 data |= (0x1<<8) | (0x1<<12);
1573 data |= (0x1<<12); /* set to digital */
1579 hw_write_20kx(hw, GPIO, data);
1586 adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1596 ret = hw_read_pci(hw, 0xEC);
1597 } while (!(ret & 0x800000)); /* i2c ready poll */
1598 /* set i2c access mode as Direct Control */
1599 hw_write_pci(hw, 0xEC, 0x05);
1601 data = hw_read_20kx(hw, GPIO);
1604 data |= ((0x1 << 7) | (0x1 << 8));
1605 i2c_data = 0x1; /* Mic-in */
1608 data &= ~(0x1 << 7);
1610 i2c_data = 0x2; /* Line-in */
1613 data &= ~(0x1 << 8);
1614 i2c_data = 0x0; /* set to Digital */
1620 hw_write_20kx(hw, GPIO, data);
1621 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1623 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1624 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1626 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1627 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1636 adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1646 ret = hw_read_pci(hw, 0xEC);
1647 } while (!(ret & 0x800000)); /* i2c ready poll */
1648 /* set i2c access mode as Direct Control */
1649 hw_write_pci(hw, 0xEC, 0x05);
1651 data = hw_read_20kx(hw, GPIO);
1655 i2c_data = 0x1; /* Mic-in */
1658 data &= ~(0x1 << 7);
1659 i2c_data = 0x2; /* Line-in */
1665 hw_write_20kx(hw, GPIO, data);
1666 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1668 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1669 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1671 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1672 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1680 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1682 int state = type == ADC_MICIN;
1684 switch (hw->model) {
1686 return adc_input_select_SB055x(hw, type, state);
1688 return adc_input_select_hendrix(hw, type, state);
1690 return adc_input_select_hendrix(hw, type, state);
1692 return adc_input_select_SBx(hw, type, state);
1696 static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1698 return adc_input_select_SB055x(hw, input, mic20db);
1701 static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1708 input_source = 0x100; /* default to analog */
1712 input_source = 0x180; /* set GPIO7 to select Mic */
1725 input_source = 0x0; /* set to Digital */
1736 ret = hw_read_pci(hw, 0xEC);
1737 } while (!(ret & 0x800000)); /* i2c ready poll */
1738 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1740 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1741 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1742 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1743 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1746 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1747 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1749 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1750 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1753 if (!(hw_read_20kx(hw, ID0) & 0x100))
1754 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1758 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1760 gpioorg |= input_source;
1761 hw_write_20kx(hw, GPIO, gpioorg);
1766 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1768 if (hw->model == CTSB055X)
1769 return adc_init_SB055x(hw, info->input, info->mic20db);
1771 return adc_init_SBx(hw, info->input, info->mic20db);
1774 static struct capabilities hw_capabilities(struct hw *hw)
1776 struct capabilities cap;
1778 /* SB073x and Vista compatible cards have no digit IO switch */
1779 cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
1780 cap.dedicated_mic = 0;
1781 cap.output_switch = 0;
1782 cap.mic_source_switch = 0;
1787 #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1789 #define UAA_CFG_PWRSTATUS 0x44
1790 #define UAA_CFG_SPACE_FLAG 0xA0
1791 #define UAA_CORE_CHANGE 0x3FFC
1792 static int uaa_to_xfi(struct pci_dev *pci)
1794 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1795 unsigned int cmd, irq, cl_size, l_timer, pwr;
1796 unsigned int is_uaa;
1797 unsigned int data[4] = {0};
1798 unsigned int io_base;
1801 const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
1802 const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1803 const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
1804 const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
1805 const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
1806 const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
1807 const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
1809 /* By default, Hendrix card UAA Bar0 should be using memory... */
1810 io_base = pci_resource_start(pci, 0);
1811 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1815 /* Read current mode from Mode Change Register */
1816 for (i = 0; i < 4; i++)
1817 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1819 /* Determine current mode... */
1820 if (data[0] == CTLA) {
1821 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1822 && data[3] == CTLA) || (data[1] == CTLA
1823 && data[2] == CTLZ && data[3] == CTLL));
1824 } else if (data[0] == CTLZ) {
1825 is_uaa = (data[1] == CTLL
1826 && data[2] == CTLA && data[3] == CTLA);
1827 } else if (data[0] == CTLL) {
1828 is_uaa = (data[1] == CTLA
1829 && data[2] == CTLA && data[3] == CTLZ);
1835 /* Not in UAA mode currently. Return directly. */
1840 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1841 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1842 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1843 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1844 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1845 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1846 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1847 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1848 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1849 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1850 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1852 /* Set up X-Fi core PCI configuration space. */
1853 /* Switch to X-Fi config space with BAR0 exposed. */
1854 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1855 /* Copy UAA's BAR5 into X-Fi BAR0 */
1856 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1857 /* Switch to X-Fi config space without BAR0 exposed. */
1858 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1859 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1861 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1862 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1863 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1864 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1865 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1866 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1867 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1869 /* Switch to X-Fi mode */
1870 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1871 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1872 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1873 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1880 static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
1882 struct hw *hw = dev_id;
1883 unsigned int status;
1885 status = hw_read_20kx(hw, GIP);
1889 if (hw->irq_callback)
1890 hw->irq_callback(hw->irq_callback_data, status);
1892 hw_write_20kx(hw, GIP, status);
1896 static int hw_card_start(struct hw *hw)
1899 struct pci_dev *pci = hw->pci;
1900 const unsigned int dma_bits = BITS_PER_LONG;
1902 err = pci_enable_device(pci);
1906 /* Set DMA transfer mask */
1907 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1908 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1910 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1911 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1915 err = pci_request_regions(pci, "XFi");
1919 if (hw->model == CTUAA)
1920 hw->io_base = pci_resource_start(pci, 5);
1922 hw->io_base = pci_resource_start(pci, 0);
1926 /* Switch to X-Fi mode from UAA mode if neeeded */
1927 if (hw->model == CTUAA) {
1928 err = uaa_to_xfi(pci);
1935 err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1936 KBUILD_MODNAME, hw);
1938 printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq);
1944 pci_set_master(pci);
1949 pci_release_regions(pci);
1952 pci_disable_device(pci);
1956 static int hw_card_stop(struct hw *hw)
1960 /* disable transport bus master and queueing of request */
1961 hw_write_20kx(hw, TRNCTL, 0x00);
1964 data = hw_read_20kx(hw, PLLCTL);
1965 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
1967 /* TODO: Disable interrupt and so on... */
1969 synchronize_irq(hw->irq);
1973 static int hw_card_shutdown(struct hw *hw)
1976 free_irq(hw->irq, hw);
1981 iounmap((void *)hw->mem_base);
1983 hw->mem_base = (unsigned long)NULL;
1986 pci_release_regions(hw->pci);
1990 pci_disable_device(hw->pci);
1995 static int hw_card_init(struct hw *hw, struct card_conf *info)
2000 struct dac_conf dac_info = {0};
2001 struct adc_conf adc_info = {0};
2002 struct daio_conf daio_info = {0};
2003 struct trn_conf trn_info = {0};
2005 /* Get PCI io port base address and do Hendrix switch if needed. */
2006 err = hw_card_start(hw);
2011 err = hw_pll_init(hw, info->rsr);
2015 /* kick off auto-init */
2016 err = hw_auto_init(hw);
2020 /* Enable audio ring */
2021 gctl = hw_read_20kx(hw, GCTL);
2022 set_field(&gctl, GCTL_EAC, 1);
2023 set_field(&gctl, GCTL_DBP, 1);
2024 set_field(&gctl, GCTL_TBP, 1);
2025 set_field(&gctl, GCTL_FBP, 1);
2026 set_field(&gctl, GCTL_ET, 1);
2027 hw_write_20kx(hw, GCTL, gctl);
2030 /* Reset all global pending interrupts */
2031 hw_write_20kx(hw, GIE, 0);
2032 /* Reset all SRC pending interrupts */
2033 hw_write_20kx(hw, SRCIP, 0);
2036 /* Detect the card ID and configure GPIO accordingly. */
2037 switch (hw->model) {
2039 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2042 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2045 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2048 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2052 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2053 err = hw_trn_init(hw, &trn_info);
2057 daio_info.msr = info->msr;
2058 err = hw_daio_init(hw, &daio_info);
2062 dac_info.msr = info->msr;
2063 err = hw_dac_init(hw, &dac_info);
2067 adc_info.msr = info->msr;
2068 adc_info.input = ADC_LINEIN;
2069 adc_info.mic20db = 0;
2070 err = hw_adc_init(hw, &adc_info);
2074 data = hw_read_20kx(hw, SRCMCTL);
2075 data |= 0x1; /* Enables input from the audio ring */
2076 hw_write_20kx(hw, SRCMCTL, data);
2082 static int hw_suspend(struct hw *hw, pm_message_t state)
2084 struct pci_dev *pci = hw->pci;
2088 if (hw->model == CTUAA) {
2089 /* Switch to UAA config space. */
2090 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
2093 pci_disable_device(pci);
2094 pci_save_state(pci);
2095 pci_set_power_state(pci, pci_choose_state(pci, state));
2100 static int hw_resume(struct hw *hw, struct card_conf *info)
2102 struct pci_dev *pci = hw->pci;
2104 pci_set_power_state(pci, PCI_D0);
2105 pci_restore_state(pci);
2107 /* Re-initialize card hardware. */
2108 return hw_card_init(hw, info);
2112 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2115 unsigned long flags;
2118 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2119 outl(reg, hw->io_base + 0x0);
2120 value = inl(hw->io_base + 0x4);
2121 spin_unlock_irqrestore(
2122 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2127 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2129 unsigned long flags;
2132 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2133 outl(reg, hw->io_base + 0x0);
2134 outl(data, hw->io_base + 0x4);
2135 spin_unlock_irqrestore(
2136 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2140 static u32 hw_read_pci(struct hw *hw, u32 reg)
2143 unsigned long flags;
2146 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2147 outl(reg, hw->io_base + 0x10);
2148 value = inl(hw->io_base + 0x14);
2149 spin_unlock_irqrestore(
2150 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2155 static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2157 unsigned long flags;
2160 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2161 outl(reg, hw->io_base + 0x10);
2162 outl(data, hw->io_base + 0x14);
2163 spin_unlock_irqrestore(
2164 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2167 static struct hw ct20k1_preset __devinitdata = {
2170 .card_init = hw_card_init,
2171 .card_stop = hw_card_stop,
2172 .pll_init = hw_pll_init,
2173 .is_adc_source_selected = hw_is_adc_input_selected,
2174 .select_adc_source = hw_adc_input_select,
2175 .capabilities = hw_capabilities,
2177 .suspend = hw_suspend,
2178 .resume = hw_resume,
2181 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2182 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2183 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2184 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2185 .src_set_state = src_set_state,
2186 .src_set_bm = src_set_bm,
2187 .src_set_rsr = src_set_rsr,
2188 .src_set_sf = src_set_sf,
2189 .src_set_wr = src_set_wr,
2190 .src_set_pm = src_set_pm,
2191 .src_set_rom = src_set_rom,
2192 .src_set_vo = src_set_vo,
2193 .src_set_st = src_set_st,
2194 .src_set_ie = src_set_ie,
2195 .src_set_ilsz = src_set_ilsz,
2196 .src_set_bp = src_set_bp,
2197 .src_set_cisz = src_set_cisz,
2198 .src_set_ca = src_set_ca,
2199 .src_set_sa = src_set_sa,
2200 .src_set_la = src_set_la,
2201 .src_set_pitch = src_set_pitch,
2202 .src_set_dirty = src_set_dirty,
2203 .src_set_clear_zbufs = src_set_clear_zbufs,
2204 .src_set_dirty_all = src_set_dirty_all,
2205 .src_commit_write = src_commit_write,
2206 .src_get_ca = src_get_ca,
2207 .src_get_dirty = src_get_dirty,
2208 .src_dirty_conj_mask = src_dirty_conj_mask,
2209 .src_mgr_enbs_src = src_mgr_enbs_src,
2210 .src_mgr_enb_src = src_mgr_enb_src,
2211 .src_mgr_dsb_src = src_mgr_dsb_src,
2212 .src_mgr_commit_write = src_mgr_commit_write,
2214 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2215 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2216 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2217 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2218 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2219 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2220 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2222 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2223 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2224 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2225 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2226 .amixer_set_mode = amixer_set_mode,
2227 .amixer_set_iv = amixer_set_iv,
2228 .amixer_set_x = amixer_set_x,
2229 .amixer_set_y = amixer_set_y,
2230 .amixer_set_sadr = amixer_set_sadr,
2231 .amixer_set_se = amixer_set_se,
2232 .amixer_set_dirty = amixer_set_dirty,
2233 .amixer_set_dirty_all = amixer_set_dirty_all,
2234 .amixer_commit_write = amixer_commit_write,
2235 .amixer_get_y = amixer_get_y,
2236 .amixer_get_dirty = amixer_get_dirty,
2238 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2239 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2240 .dai_srt_set_srco = dai_srt_set_srcr,
2241 .dai_srt_set_srcm = dai_srt_set_srcl,
2242 .dai_srt_set_rsr = dai_srt_set_rsr,
2243 .dai_srt_set_drat = dai_srt_set_drat,
2244 .dai_srt_set_ec = dai_srt_set_ec,
2245 .dai_srt_set_et = dai_srt_set_et,
2246 .dai_commit_write = dai_commit_write,
2248 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2249 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2250 .dao_set_spos = dao_set_spos,
2251 .dao_commit_write = dao_commit_write,
2252 .dao_get_spos = dao_get_spos,
2254 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2255 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2256 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2257 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2258 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2259 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2260 .daio_mgr_dao_init = daio_mgr_dao_init,
2261 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2262 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2263 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2264 .daio_mgr_commit_write = daio_mgr_commit_write,
2266 .set_timer_irq = set_timer_irq,
2267 .set_timer_tick = set_timer_tick,
2271 int __devinit create_20k1_hw_obj(struct hw **rhw)
2273 struct hw20k1 *hw20k1;
2276 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2280 spin_lock_init(&hw20k1->reg_20k1_lock);
2281 spin_lock_init(&hw20k1->reg_pci_lock);
2283 hw20k1->hw = ct20k1_preset;
2290 int destroy_20k1_hw_obj(struct hw *hw)
2293 hw_card_shutdown(hw);
2295 kfree(container_of(hw, struct hw20k1, hw));