sound/oss/i810_audio.c

   1 /*
   2  *      Intel i810 and friends ICH driver for Linux
   3  *      Alan Cox <alan@redhat.com>
   4  *
   5  *  Built from:
   6  *      Low level code:  Zach Brown (original nonworking i810 OSS driver)
   7  *                       Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
   8  *
   9  *      Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
  10  *      Extended by: Zach Brown <zab@redhat.com>
  11  *                      and others..
  12  *
  13  *  Hardware Provided By:
  14  *      Analog Devices (A major AC97 codec maker)
  15  *      Intel Corp  (you've probably heard of them already)
  16  *
  17  *  AC97 clues and assistance provided by
  18  *      Analog Devices
  19  *      Zach 'Fufu' Brown
  20  *      Jeff Garzik
  21  *
  22  *      This program is free software; you can redistribute it and/or modify
  23  *      it under the terms of the GNU General Public License as published by
  24  *      the Free Software Foundation; either version 2 of the License, or
  25  *      (at your option) any later version.
  26  *
  27  *      This program is distributed in the hope that it will be useful,
  28  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  *      GNU General Public License for more details.
  31  *
  32  *      You should have received a copy of the GNU General Public License
  33  *      along with this program; if not, write to the Free Software
  34  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35  *
  36  *
  37  *      Intel 810 theory of operation
  38  *
  39  *      The chipset provides three DMA channels that talk to an AC97
  40  *      CODEC (AC97 is a digital/analog mixer standard). At its simplest
  41  *      you get 48Khz audio with basic volume and mixer controls. At the
  42  *      best you get rate adaption in the codec. We set the card up so
  43  *      that we never take completion interrupts but instead keep the card
  44  *      chasing its tail around a ring buffer. This is needed for mmap
  45  *      mode audio and happens to work rather well for non-mmap modes too.
  46  *
  47  *      The board has one output channel for PCM audio (supported) and
  48  *      a stereo line in and mono microphone input. Again these are normally
  49  *      locked to 48Khz only. Right now recording is not finished.
  50  *
  51  *      There is no midi support, no synth support. Use timidity. To get
  52  *      esd working you need to use esd -r 48000 as it won't probe 48KHz
  53  *      by default. mpg123 can't handle 48Khz only audio so use xmms.
  54  *
  55  *      Fix The Sound On Dell
  56  *
  57  *      Not everyone uses 48KHz. We know of no way to detect this reliably
  58  *      and certainly not to get the right data. If your i810 audio sounds
  59  *      stupid you may need to investigate other speeds. According to Analog
  60  *      they tend to use a 14.318MHz clock which gives you a base rate of
  61  *      41194Hz.
  62  *
  63  *      This is available via the 'ftsodell=1' option.
  64  *
  65  *      If you need to force a specific rate set the clocking= option
  66  *
  67  *      This driver is cursed. (Ben LaHaise)
  68  *
  69  *  ICH 3 caveats
  70  *      Intel errata #7 for ICH3 IO. We need to disable SMI stuff
  71  *      when codec probing. [Not Yet Done]
  72  *
  73  *  ICH 4 caveats
  74  *
  75  *      The ICH4 has the feature, that the codec ID doesn't have to be
  76  *      congruent with the IO connection.
  77  *
  78  *      Therefore, from driver version 0.23 on, there is a "codec ID" <->
  79  *      "IO register base offset" mapping (card->ac97_id_map) field.
  80  *
  81  *      Juergen "George" Sawinski (jsaw)
  82  */
  83
  84 #include <linux/module.h>
  85 #include <linux/string.h>
  86 #include <linux/ctype.h>
  87 #include <linux/ioport.h>
  88 #include <linux/sched.h>
  89 #include <linux/delay.h>
  90 #include <linux/sound.h>
  91 #include <linux/slab.h>
  92 #include <linux/soundcard.h>
  93 #include <linux/pci.h>
  94 #include <linux/interrupt.h>
  95 #include <asm/io.h>
  96 #include <asm/dma.h>
  97 #include <linux/init.h>
  98 #include <linux/poll.h>
  99 #include <linux/spinlock.h>
 100 #include <linux/smp_lock.h>
 101 #include <linux/ac97_codec.h>
 102 #include <linux/bitops.h>
 103 #include <asm/uaccess.h>
 104
 105 #define DRIVER_VERSION "1.01"
 106
 107 #define MODULOP2(a, b) ((a) & ((b) - 1))
 108 #define MASKP2(a, b) ((a) & ~((b) - 1))
 109
 110 static int ftsodell;
 111 static int strict_clocking;
 112 static unsigned int clocking;
 113 static int spdif_locked;
 114 static int ac97_quirk = AC97_TUNE_DEFAULT;
 115
 116 //#define DEBUG
 117 //#define DEBUG2
 118 //#define DEBUG_INTERRUPTS
 119 //#define DEBUG_MMAP
 120 //#define DEBUG_MMIO
 121
 122 #define ADC_RUNNING     1
 123 #define DAC_RUNNING     2
 124
 125 #define I810_FMT_16BIT  1
 126 #define I810_FMT_STEREO 2
 127 #define I810_FMT_MASK   3
 128
 129 #define SPDIF_ON        0x0004
 130 #define SURR_ON         0x0010
 131 #define CENTER_LFE_ON   0x0020
 132 #define VOL_MUTED       0x8000
 133
 134 /* the 810's array of pointers to data buffers */
 135
 136 struct sg_item {
 137 #define BUSADDR_MASK    0xFFFFFFFE
 138         u32 busaddr;
 139 #define CON_IOC         0x80000000 /* interrupt on completion */
 140 #define CON_BUFPAD      0x40000000 /* pad underrun with last sample, else 0 */
 141 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
 142         u32 control;
 143 };
 144
 145 /* an instance of the i810 channel */
 146 #define SG_LEN 32
 147 struct i810_channel
 148 {
 149         /* these sg guys should probably be allocated
 150            separately as nocache. Must be 8 byte aligned */
 151         struct sg_item sg[SG_LEN];      /* 32*8 */
 152         u32 offset;                     /* 4 */
 153         u32 port;                       /* 4 */
 154         u32 used;
 155         u32 num;
 156 };
 157
 158 /*
 159  * we have 3 separate dma engines.  pcm in, pcm out, and mic.
 160  * each dma engine has controlling registers.  These goofy
 161  * names are from the datasheet, but make it easy to write
 162  * code while leafing through it.
 163  *
 164  * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2,
 165  * mic in 2, s/pdif.   Of special interest is the fact that
 166  * the upper 3 DMA engines on the ICH4 *must* be accessed
 167  * via mmio access instead of pio access.
 168  */
 169
 170 #define ENUM_ENGINE(PRE,DIG)                                                                    \
 171 enum {                                                                                          \
 172         PRE##_BASE =    0x##DIG##0,             /* Base Address */                              \
 173         PRE##_BDBAR =   0x##DIG##0,             /* Buffer Descriptor list Base Address */       \
 174         PRE##_CIV =     0x##DIG##4,             /* Current Index Value */                       \
 175         PRE##_LVI =     0x##DIG##5,             /* Last Valid Index */                          \
 176         PRE##_SR =      0x##DIG##6,             /* Status Register */                           \
 177         PRE##_PICB =    0x##DIG##8,             /* Position In Current Buffer */                \
 178         PRE##_PIV =     0x##DIG##a,             /* Prefetched Index Value */                    \
 179         PRE##_CR =      0x##DIG##b              /* Control Register */                          \
 180 }
 181
 182 ENUM_ENGINE(OFF,0);     /* Offsets */
 183 ENUM_ENGINE(PI,0);      /* PCM In */
 184 ENUM_ENGINE(PO,1);      /* PCM Out */
 185 ENUM_ENGINE(MC,2);      /* Mic In */
 186
 187 enum {
 188         GLOB_CNT =      0x2c,                   /* Global Control */
 189         GLOB_STA =      0x30,                   /* Global Status */
 190         CAS      =      0x34                    /* Codec Write Semaphore Register */
 191 };
 192
 193 ENUM_ENGINE(MC2,4);     /* Mic In 2 */
 194 ENUM_ENGINE(PI2,5);     /* PCM In 2 */
 195 ENUM_ENGINE(SP,6);      /* S/PDIF */
 196
 197 enum {
 198         SDM =           0x80                    /* SDATA_IN Map Register */
 199 };
 200
 201 /* interrupts for a dma engine */
 202 #define DMA_INT_FIFO            (1<<4)  /* fifo under/over flow */
 203 #define DMA_INT_COMPLETE        (1<<3)  /* buffer read/write complete and ioc set */
 204 #define DMA_INT_LVI             (1<<2)  /* last valid done */
 205 #define DMA_INT_CELV            (1<<1)  /* last valid is current */
 206 #define DMA_INT_DCH             (1)     /* DMA Controller Halted (happens on LVI interrupts) */
 207 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
 208
 209 /* interrupts for the whole chip */
 210 #define INT_SEC         (1<<11)
 211 #define INT_PRI         (1<<10)
 212 #define INT_MC          (1<<7)
 213 #define INT_PO          (1<<6)
 214 #define INT_PI          (1<<5)
 215 #define INT_MO          (1<<2)
 216 #define INT_NI          (1<<1)
 217 #define INT_GPI         (1<<0)
 218 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
 219
 220 /* magic numbers to protect our data structures */
 221 #define I810_CARD_MAGIC         0x5072696E /* "Prin" */
 222 #define I810_STATE_MAGIC        0x63657373 /* "cess" */
 223 #define I810_DMA_MASK           0xffffffff /* DMA buffer mask for pci_alloc_consist */
 224 #define NR_HW_CH                3
 225
 226 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
 227 #define NR_AC97                 4
 228
 229 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
 230 /* stream at a minimum for this card to be happy */
 231 static const unsigned sample_size[] = { 1, 2, 2, 4 };
 232 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
 233 /* values are one less than might be expected */
 234 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
 235
 236 enum {
 237         ICH82801AA = 0,
 238         ICH82901AB,
 239         INTEL440MX,
 240         INTELICH2,
 241         INTELICH3,
 242         INTELICH4,
 243         INTELICH5,
 244         SI7012,
 245         NVIDIA_NFORCE,
 246         AMD768,
 247         AMD8111
 248 };
 249
 250 static char * card_names[] = {
 251         "Intel ICH 82801AA",
 252         "Intel ICH 82901AB",
 253         "Intel 440MX",
 254         "Intel ICH2",
 255         "Intel ICH3",
 256         "Intel ICH4",
 257         "Intel ICH5",
 258         "SiS 7012",
 259         "NVIDIA nForce Audio",
 260         "AMD 768",
 261         "AMD-8111 IOHub"
 262 };
 263
 264 /* These are capabilities (and bugs) the chipsets _can_ have */
 265 static struct {
 266         int16_t      nr_ac97;
 267 #define CAP_MMIO                 0x0001
 268 #define CAP_20BIT_AUDIO_SUPPORT  0x0002
 269         u_int16_t flags;
 270 } card_cap[] = {
 271         {  1, 0x0000 }, /* ICH82801AA */
 272         {  1, 0x0000 }, /* ICH82901AB */
 273         {  1, 0x0000 }, /* INTEL440MX */
 274         {  1, 0x0000 }, /* INTELICH2 */
 275         {  2, 0x0000 }, /* INTELICH3 */
 276         {  3, 0x0003 }, /* INTELICH4 */
 277         {  3, 0x0003 }, /* INTELICH5 */
 278         /*@FIXME to be verified*/       {  2, 0x0000 }, /* SI7012 */
 279         /*@FIXME to be verified*/       {  2, 0x0000 }, /* NVIDIA_NFORCE */
 280         /*@FIXME to be verified*/       {  2, 0x0000 }, /* AMD768 */
 281         /*@FIXME to be verified*/       {  3, 0x0001 }, /* AMD8111 */
 282 };
 283
 284 static struct pci_device_id i810_pci_tbl [] = {
 285         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_5,
 286          PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
 287         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_5,
 288          PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
 289         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
 290          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
 291         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_4,
 292          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
 293         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_5,
 294          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
 295         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_5,
 296          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
 297         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_5,
 298          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH5},
 299         {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012,
 300          PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012},
 301         {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO,
 302          PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
 303         {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO,
 304          PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
 305         {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO,
 306          PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
 307         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7445,
 308          PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768},
 309         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AUDIO,
 310          PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111},
 311         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_5,
 312          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
 313         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_18,
 314          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
 315
 316         {0,}
 317 };
 318
 319 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
 320
 321 #ifdef CONFIG_PM
 322 #define PM_SUSPENDED(card) (card->pm_suspended)
 323 #else
 324 #define PM_SUSPENDED(card) (0)
 325 #endif
 326
 327 /* "software" or virtual channel, an instance of opened /dev/dsp */
 328 struct i810_state {
 329         unsigned int magic;
 330         struct i810_card *card; /* Card info */
 331
 332         /* single open lock mechanism, only used for recording */
 333         struct semaphore open_sem;
 334         wait_queue_head_t open_wait;
 335
 336         /* file mode */
 337         mode_t open_mode;
 338
 339         /* virtual channel number */
 340         int virt;
 341
 342 #ifdef CONFIG_PM
 343         unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
 344 #endif
 345         struct dmabuf {
 346                 /* wave sample stuff */
 347                 unsigned int rate;
 348                 unsigned char fmt, enable, trigger;
 349
 350                 /* hardware channel */
 351                 struct i810_channel *read_channel;
 352                 struct i810_channel *write_channel;
 353
 354                 /* OSS buffer management stuff */
 355                 void *rawbuf;
 356                 dma_addr_t dma_handle;
 357                 unsigned buforder;
 358                 unsigned numfrag;
 359                 unsigned fragshift;
 360
 361                 /* our buffer acts like a circular ring */
 362                 unsigned hwptr;         /* where dma last started, updated by update_ptr */
 363                 unsigned swptr;         /* where driver last clear/filled, updated by read/write */
 364                 int count;              /* bytes to be consumed or been generated by dma machine */
 365                 unsigned total_bytes;   /* total bytes dmaed by hardware */
 366
 367                 unsigned error;         /* number of over/underruns */
 368                 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
 369
 370                 /* redundant, but makes calculations easier */
 371                 /* what the hardware uses */
 372                 unsigned dmasize;
 373                 unsigned fragsize;
 374                 unsigned fragsamples;
 375
 376                 /* what we tell the user to expect */
 377                 unsigned userfrags;
 378                 unsigned userfragsize;
 379
 380                 /* OSS stuff */
 381                 unsigned mapped:1;
 382                 unsigned ready:1;
 383                 unsigned update_flag;
 384                 unsigned ossfragsize;
 385                 unsigned ossmaxfrags;
 386                 unsigned subdivision;
 387         } dmabuf;
 388 };
 389
 390
 391 struct i810_card {
 392         unsigned int magic;
 393
 394         /* We keep i810 cards in a linked list */
 395         struct i810_card *next;
 396
 397         /* The i810 has a certain amount of cross channel interaction
 398            so we use a single per card lock */
 399         spinlock_t lock;
 400
 401         /* Control AC97 access serialization */
 402         spinlock_t ac97_lock;
 403
 404         /* PCI device stuff */
 405         struct pci_dev * pci_dev;
 406         u16 pci_id;
 407         u16 pci_id_internal; /* used to access card_cap[] */
 408 #ifdef CONFIG_PM
 409         u16 pm_suspended;
 410         int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
 411 #endif
 412         /* soundcore stuff */
 413         int dev_audio;
 414
 415         /* structures for abstraction of hardware facilities, codecs, banks and channels*/
 416         u16    ac97_id_map[NR_AC97];
 417         struct ac97_codec *ac97_codec[NR_AC97];
 418         struct i810_state *states[NR_HW_CH];
 419         struct i810_channel *channel;   /* 1:1 to states[] but diff. lifetime */
 420         dma_addr_t chandma;
 421
 422         u16 ac97_features;
 423         u16 ac97_status;
 424         u16 channels;
 425
 426         /* hardware resources */
 427         unsigned long ac97base;
 428         unsigned long iobase;
 429         u32 irq;
 430
 431         unsigned long ac97base_mmio_phys;
 432         unsigned long iobase_mmio_phys;
 433         u_int8_t __iomem *ac97base_mmio;
 434         u_int8_t __iomem *iobase_mmio;
 435
 436         int           use_mmio;
 437
 438         /* Function support */
 439         struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
 440         struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
 441         struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
 442         void (*free_pcm_channel)(struct i810_card *, int chan);
 443
 444         /* We have a *very* long init time possibly, so use this to block */
 445         /* attempts to open our devices before we are ready (stops oops'es) */
 446         int initializing;
 447 };
 448
 449 /* extract register offset from codec struct */
 450 #define IO_REG_OFF(codec) (((struct i810_card *) codec->private_data)->ac97_id_map[codec->id])
 451
 452 #define I810_IOREAD(size, type, card, off)                              \
 453 ({                                                                      \
 454         type val;                                                       \
 455         if (card->use_mmio)                                             \
 456                 val=read##size(card->iobase_mmio+off);                  \
 457         else                                                            \
 458                 val=in##size(card->iobase+off);                         \
 459         val;                                                            \
 460 })
 461
 462 #define I810_IOREADL(card, off)         I810_IOREAD(l, u32, card, off)
 463 #define I810_IOREADW(card, off)         I810_IOREAD(w, u16, card, off)
 464 #define I810_IOREADB(card, off)         I810_IOREAD(b, u8,  card, off)
 465
 466 #define I810_IOWRITE(size, val, card, off)                              \
 467 ({                                                                      \
 468         if (card->use_mmio)                                             \
 469                 write##size(val, card->iobase_mmio+off);                \
 470         else                                                            \
 471                 out##size(val, card->iobase+off);                       \
 472 })
 473
 474 #define I810_IOWRITEL(val, card, off)   I810_IOWRITE(l, val, card, off)
 475 #define I810_IOWRITEW(val, card, off)   I810_IOWRITE(w, val, card, off)
 476 #define I810_IOWRITEB(val, card, off)   I810_IOWRITE(b, val, card, off)
 477
 478 #define GET_CIV(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_CIV), SG_LEN)
 479 #define GET_LVI(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_LVI), SG_LEN)
 480
 481 /* set LVI from CIV */
 482 #define CIV_TO_LVI(card, port, off) \
 483         I810_IOWRITEB(MODULOP2(GET_CIV((card), (port)) + (off), SG_LEN), (card), (port) + OFF_LVI)
 484
 485 static struct ac97_quirk ac97_quirks[] __devinitdata = {
 486         {
 487                 .vendor = 0x0e11,
 488                 .device = 0x00b8,
 489                 .name = "Compaq Evo D510C",
 490                 .type = AC97_TUNE_HP_ONLY
 491         },
 492         {
 493                 .vendor = 0x1028,
 494                 .device = 0x00d8,
 495                 .name = "Dell Precision 530",   /* AD1885 */
 496                 .type = AC97_TUNE_HP_ONLY
 497         },
 498         {
 499                 .vendor = 0x1028,
 500                 .device = 0x0126,
 501                 .name = "Dell Optiplex GX260",  /* AD1981A */
 502                 .type = AC97_TUNE_HP_ONLY
 503         },
 504         {
 505                 .vendor = 0x1028,
 506                 .device = 0x012d,
 507                 .name = "Dell Precision 450",   /* AD1981B*/
 508                 .type = AC97_TUNE_HP_ONLY
 509         },
 510         {       /* FIXME: which codec? */
 511                 .vendor = 0x103c,
 512                 .device = 0x00c3,
 513                 .name = "Hewlett-Packard onboard",
 514                 .type = AC97_TUNE_HP_ONLY
 515         },
 516         {
 517                 .vendor = 0x103c,
 518                 .device = 0x12f1,
 519                 .name = "HP xw8200",    /* AD1981B*/
 520                 .type = AC97_TUNE_HP_ONLY
 521         },
 522         {
 523                 .vendor = 0x103c,
 524                 .device = 0x3008,
 525                 .name = "HP xw4200",    /* AD1981B*/
 526                 .type = AC97_TUNE_HP_ONLY
 527         },
 528         {
 529                 .vendor = 0x10f1,
 530                 .device = 0x2665,
 531                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
 532                 .type = AC97_TUNE_HP_ONLY
 533         },
 534         {
 535                 .vendor = 0x10f1,
 536                 .device = 0x2885,
 537                 .name = "AMD64 Mobo",   /* ALC650 */
 538                 .type = AC97_TUNE_HP_ONLY
 539         },
 540         {
 541                 .vendor = 0x110a,
 542                 .device = 0x0056,
 543                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
 544                 .type = AC97_TUNE_HP_ONLY
 545         },
 546         {
 547                 .vendor = 0x11d4,
 548                 .device = 0x5375,
 549                 .name = "ADI AD1985 (discrete)",
 550                 .type = AC97_TUNE_HP_ONLY
 551         },
 552         {
 553                 .vendor = 0x1462,
 554                 .device = 0x5470,
 555                 .name = "MSI P4 ATX 645 Ultra",
 556                 .type = AC97_TUNE_HP_ONLY
 557         },
 558         {
 559                 .vendor = 0x1734,
 560                 .device = 0x0088,
 561                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
 562                 .type = AC97_TUNE_HP_ONLY
 563         },
 564         {
 565                 .vendor = 0x8086,
 566                 .device = 0x4856,
 567                 .name = "Intel D845WN (82801BA)",
 568                 .type = AC97_TUNE_SWAP_HP
 569         },
 570         {
 571                 .vendor = 0x8086,
 572                 .device = 0x4d44,
 573                 .name = "Intel D850EMV2",       /* AD1885 */
 574                 .type = AC97_TUNE_HP_ONLY
 575         },
 576         {
 577                 .vendor = 0x8086,
 578                 .device = 0x4d56,
 579                 .name = "Intel ICH/AD1885",
 580                 .type = AC97_TUNE_HP_ONLY
 581         },
 582         {
 583                 .vendor = 0x1028,
 584                 .device = 0x012d,
 585                 .name = "Dell Precision 450",   /* AD1981B*/
 586                 .type = AC97_TUNE_HP_ONLY
 587         },
 588         {
 589                 .vendor = 0x103c,
 590                 .device = 0x3008,
 591                 .name = "HP xw4200",    /* AD1981B*/
 592                 .type = AC97_TUNE_HP_ONLY
 593         },
 594         {
 595                 .vendor = 0x103c,
 596                 .device = 0x12f1,
 597                 .name = "HP xw8200",    /* AD1981B*/
 598                 .type = AC97_TUNE_HP_ONLY
 599         },
 600         { } /* terminator */
 601 };
 602
 603 static struct i810_card *devs = NULL;
 604
 605 static int i810_open_mixdev(struct inode *inode, struct file *file);
 606 static int i810_ioctl_mixdev(struct inode *inode, struct file *file,
 607                              unsigned int cmd, unsigned long arg);
 608 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
 609 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
 610 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg);
 611 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data);
 612 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg);
 613 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data);
 614
 615 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
 616 {
 617         if(card->channel[1].used==1)
 618                 return NULL;
 619         card->channel[1].used=1;
 620         return &card->channel[1];
 621 }
 622
 623 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
 624 {
 625         if(card->channel[0].used==1)
 626                 return NULL;
 627         card->channel[0].used=1;
 628         return &card->channel[0];
 629 }
 630
 631 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
 632 {
 633         if(card->channel[2].used==1)
 634                 return NULL;
 635         card->channel[2].used=1;
 636         return &card->channel[2];
 637 }
 638
 639 static void i810_free_pcm_channel(struct i810_card *card, int channel)
 640 {
 641         card->channel[channel].used=0;
 642 }
 643
 644 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
 645 {
 646         unsigned long id = 0L;
 647
 648         id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
 649         id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
 650 #ifdef DEBUG
 651         printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
 652 #endif
 653         switch ( id ) {
 654                 case 0x41445361: /* AD1886 */
 655                         if (rate == 48000) {
 656                                 return 1;
 657                         }
 658                         break;
 659                 default: /* all other codecs, until we know otherwiae */
 660                         if (rate == 48000 || rate == 44100 || rate == 32000) {
 661                                 return 1;
 662                         }
 663                         break;
 664         }
 665         return (0);
 666 }
 667
 668 /* i810_set_spdif_output
 669  *
 670  *  Configure the S/PDIF output transmitter. When we turn on
 671  *  S/PDIF, we turn off the analog output. This may not be
 672  *  the right thing to do.
 673  *
 674  *  Assumptions:
 675  *     The DSP sample rate must already be set to a supported
 676  *     S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
 677  */
 678 static int i810_set_spdif_output(struct i810_state *state, int slots, int rate)
 679 {
 680         int     vol;
 681         int     aud_reg;
 682         int     r = 0;
 683         struct ac97_codec *codec = state->card->ac97_codec[0];
 684
 685         if(!codec->codec_ops->digital) {
 686                 state->card->ac97_status &= ~SPDIF_ON;
 687         } else {
 688                 if ( slots == -1 ) { /* Turn off S/PDIF */
 689                         codec->codec_ops->digital(codec, 0, 0, 0);
 690                         /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
 691                         if ( !(state->card->ac97_status & VOL_MUTED) ) {
 692                                 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
 693                                 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
 694                         }
 695                         state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
 696                         return 0;
 697                 }
 698
 699                 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
 700                 state->card->ac97_status = vol & VOL_MUTED;
 701
 702                 r = codec->codec_ops->digital(codec, slots, rate, 0);
 703
 704                 if(r)
 705                         state->card->ac97_status |= SPDIF_ON;
 706                 else
 707                         state->card->ac97_status &= ~SPDIF_ON;
 708
 709                 /* Mute the analog output */
 710                 /* Should this only mute the PCM volume??? */
 711                 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
 712         }
 713         return r;
 714 }
 715
 716 /* i810_set_dac_channels
 717  *
 718  *  Configure the codec's multi-channel DACs
 719  *
 720  *  The logic is backwards. Setting the bit to 1 turns off the DAC.
 721  *
 722  *  What about the ICH? We currently configure it using the
 723  *  SNDCTL_DSP_CHANNELS ioctl.  If we're turnning on the DAC,
 724  *  does that imply that we want the ICH set to support
 725  *  these channels?
 726  *
 727  *  TODO:
 728  *    vailidate that the codec really supports these DACs
 729  *    before turning them on.
 730  */
 731 static void i810_set_dac_channels(struct i810_state *state, int channel)
 732 {
 733         int     aud_reg;
 734         struct ac97_codec *codec = state->card->ac97_codec[0];
 735
 736         /* No codec, no setup */
 737
 738         if(codec == NULL)
 739                 return;
 740
 741         aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
 742         aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
 743         state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
 744
 745         switch ( channel ) {
 746                 case 2: /* always enabled */
 747                         break;
 748                 case 4:
 749                         aud_reg &= ~AC97_EA_PRJ;
 750                         state->card->ac97_status |= SURR_ON;
 751                         break;
 752                 case 6:
 753                         aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
 754                         state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
 755                         break;
 756                 default:
 757                         break;
 758         }
 759         i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
 760
 761 }
 762
 763
 764 /* set playback sample rate */
 765 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
 766 {
 767         struct dmabuf *dmabuf = &state->dmabuf;
 768         u32 new_rate;
 769         struct ac97_codec *codec=state->card->ac97_codec[0];
 770
 771         if(!(state->card->ac97_features&0x0001))
 772         {
 773                 dmabuf->rate = clocking;
 774 #ifdef DEBUG
 775                 printk("Asked for %d Hz, but ac97_features says we only do %dHz.  Sorry!\n",
 776                        rate,clocking);
 777 #endif
 778                 return clocking;
 779         }
 780
 781         if (rate > 48000)
 782                 rate = 48000;
 783         if (rate < 8000)
 784                 rate = 8000;
 785         dmabuf->rate = rate;
 786
 787         /*
 788          *      Adjust for misclocked crap
 789          */
 790         rate = ( rate * clocking)/48000;
 791         if(strict_clocking && rate < 8000) {
 792                 rate = 8000;
 793                 dmabuf->rate = (rate * 48000)/clocking;
 794         }
 795
 796         new_rate=ac97_set_dac_rate(codec, rate);
 797         if(new_rate != rate) {
 798                 dmabuf->rate = (new_rate * 48000)/clocking;
 799         }
 800 #ifdef DEBUG
 801         printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
 802 #endif
 803         rate = new_rate;
 804         return dmabuf->rate;
 805 }
 806
 807 /* set recording sample rate */
 808 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
 809 {
 810         struct dmabuf *dmabuf = &state->dmabuf;
 811         u32 new_rate;
 812         struct ac97_codec *codec=state->card->ac97_codec[0];
 813
 814         if(!(state->card->ac97_features&0x0001))
 815         {
 816                 dmabuf->rate = clocking;
 817                 return clocking;
 818         }
 819
 820         if (rate > 48000)
 821                 rate = 48000;
 822         if (rate < 8000)
 823                 rate = 8000;
 824         dmabuf->rate = rate;
 825
 826         /*
 827          *      Adjust for misclocked crap
 828          */
 829
 830         rate = ( rate * clocking)/48000;
 831         if(strict_clocking && rate < 8000) {
 832                 rate = 8000;
 833                 dmabuf->rate = (rate * 48000)/clocking;
 834         }
 835
 836         new_rate = ac97_set_adc_rate(codec, rate);
 837
 838         if(new_rate != rate) {
 839                 dmabuf->rate = (new_rate * 48000)/clocking;
 840                 rate = new_rate;
 841         }
 842 #ifdef DEBUG
 843         printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
 844 #endif
 845         return dmabuf->rate;
 846 }
 847
 848 /* get current playback/recording dma buffer pointer (byte offset from LBA),
 849    called with spinlock held! */
 850
 851 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
 852 {
 853         struct dmabuf *dmabuf = &state->dmabuf;
 854         unsigned int civ, offset, port, port_picb, bytes = 2;
 855
 856         if (!dmabuf->enable)
 857                 return 0;
 858
 859         if (rec)
 860                 port = dmabuf->read_channel->port;
 861         else
 862                 port = dmabuf->write_channel->port;
 863
 864         if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) {
 865                 port_picb = port + OFF_SR;
 866                 bytes = 1;
 867         } else
 868                 port_picb = port + OFF_PICB;
 869
 870         do {
 871                 civ = GET_CIV(state->card, port);
 872                 offset = I810_IOREADW(state->card, port_picb);
 873                 /* Must have a delay here! */
 874                 if(offset == 0)
 875                         udelay(1);
 876                 /* Reread both registers and make sure that that total
 877                  * offset from the first reading to the second is 0.
 878                  * There is an issue with SiS hardware where it will count
 879                  * picb down to 0, then update civ to the next value,
 880                  * then set the new picb to fragsize bytes.  We can catch
 881                  * it between the civ update and the picb update, making
 882                  * it look as though we are 1 fragsize ahead of where we
 883                  * are.  The next to we get the address though, it will
 884                  * be back in the right place, and we will suddenly think
 885                  * we just went forward dmasize - fragsize bytes, causing
 886                  * totally stupid *huge* dma overrun messages.  We are
 887                  * assuming that the 1us delay is more than long enough
 888                  * that we won't have to worry about the chip still being
 889                  * out of sync with reality ;-)
 890                  */
 891         } while (civ != GET_CIV(state->card, port) || offset != I810_IOREADW(state->card, port_picb));
 892
 893         return (((civ + 1) * dmabuf->fragsize - (bytes * offset))
 894                 % dmabuf->dmasize);
 895 }
 896
 897 /* Stop recording (lock held) */
 898 static inline void __stop_adc(struct i810_state *state)
 899 {
 900         struct dmabuf *dmabuf = &state->dmabuf;
 901         struct i810_card *card = state->card;
 902
 903         dmabuf->enable &= ~ADC_RUNNING;
 904         I810_IOWRITEB(0, card, PI_CR);
 905         // wait for the card to acknowledge shutdown
 906         while( I810_IOREADB(card, PI_CR) != 0 ) ;
 907         // now clear any latent interrupt bits (like the halt bit)
 908         if(card->pci_id == PCI_DEVICE_ID_SI_7012)
 909                 I810_IOWRITEB( I810_IOREADB(card, PI_PICB), card, PI_PICB );
 910         else
 911                 I810_IOWRITEB( I810_IOREADB(card, PI_SR), card, PI_SR );
 912         I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PI, card, GLOB_STA);
 913 }
 914
 915 static void stop_adc(struct i810_state *state)
 916 {
 917         struct i810_card *card = state->card;
 918         unsigned long flags;
 919
 920         spin_lock_irqsave(&card->lock, flags);
 921         __stop_adc(state);
 922         spin_unlock_irqrestore(&card->lock, flags);
 923 }
 924
 925 static inline void __start_adc(struct i810_state *state)
 926 {
 927         struct dmabuf *dmabuf = &state->dmabuf;
 928
 929         if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
 930             (dmabuf->trigger & PCM_ENABLE_INPUT)) {
 931                 dmabuf->enable |= ADC_RUNNING;
 932                 // Interrupt enable, LVI enable, DMA enable
 933                 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PI_CR);
 934         }
 935 }
 936
 937 static void start_adc(struct i810_state *state)
 938 {
 939         struct i810_card *card = state->card;
 940         unsigned long flags;
 941
 942         spin_lock_irqsave(&card->lock, flags);
 943         __start_adc(state);
 944         spin_unlock_irqrestore(&card->lock, flags);
 945 }
 946
 947 /* stop playback (lock held) */
 948 static inline void __stop_dac(struct i810_state *state)
 949 {
 950         struct dmabuf *dmabuf = &state->dmabuf;
 951         struct i810_card *card = state->card;
 952
 953         dmabuf->enable &= ~DAC_RUNNING;
 954         I810_IOWRITEB(0, card, PO_CR);
 955         // wait for the card to acknowledge shutdown
 956         while( I810_IOREADB(card, PO_CR) != 0 ) ;
 957         // now clear any latent interrupt bits (like the halt bit)
 958         if(card->pci_id == PCI_DEVICE_ID_SI_7012)
 959                 I810_IOWRITEB( I810_IOREADB(card, PO_PICB), card, PO_PICB );
 960         else
 961                 I810_IOWRITEB( I810_IOREADB(card, PO_SR), card, PO_SR );
 962         I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PO, card, GLOB_STA);
 963 }
 964
 965 static void stop_dac(struct i810_state *state)
 966 {
 967         struct i810_card *card = state->card;
 968         unsigned long flags;
 969
 970         spin_lock_irqsave(&card->lock, flags);
 971         __stop_dac(state);
 972         spin_unlock_irqrestore(&card->lock, flags);
 973 }
 974
 975 static inline void __start_dac(struct i810_state *state)
 976 {
 977         struct dmabuf *dmabuf = &state->dmabuf;
 978
 979         if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
 980             (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
 981                 dmabuf->enable |= DAC_RUNNING;
 982                 // Interrupt enable, LVI enable, DMA enable
 983                 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PO_CR);
 984         }
 985 }
 986 static void start_dac(struct i810_state *state)
 987 {
 988         struct i810_card *card = state->card;
 989         unsigned long flags;
 990
 991         spin_lock_irqsave(&card->lock, flags);
 992         __start_dac(state);
 993         spin_unlock_irqrestore(&card->lock, flags);
 994 }
 995
 996 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
 997 #define DMABUF_MINORDER 1
 998
 999 /* allocate DMA buffer, playback and recording buffer should be allocated separately */
1000 static int alloc_dmabuf(struct i810_state *state)
1001 {
1002         struct dmabuf *dmabuf = &state->dmabuf;
1003         void *rawbuf= NULL;
1004         int order, size;
1005         struct page *page, *pend;
1006
1007         /* If we don't have any oss frag params, then use our default ones */
1008         if(dmabuf->ossmaxfrags == 0)
1009                 dmabuf->ossmaxfrags = 4;
1010         if(dmabuf->ossfragsize == 0)
1011                 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
1012         size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
1013
1014         if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size)
1015                 return 0;
1016         /* alloc enough to satisfy the oss params */
1017         for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
1018                 if ( (PAGE_SIZE<<order) > size )
1019                         continue;
1020                 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
1021                                                    PAGE_SIZE << order,
1022                                                    &dmabuf->dma_handle)))
1023                         break;
1024         }
1025         if (!rawbuf)
1026                 return -ENOMEM;
1027
1028
1029 #ifdef DEBUG
1030         printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
1031                PAGE_SIZE << order, order, rawbuf);
1032 #endif
1033
1034         dmabuf->ready  = dmabuf->mapped = 0;
1035         dmabuf->rawbuf = rawbuf;
1036         dmabuf->buforder = order;
1037
1038         /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
1039         pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
1040         for (page = virt_to_page(rawbuf); page <= pend; page++)
1041                 SetPageReserved(page);
1042
1043         return 0;
1044 }
1045
1046 /* free DMA buffer */
1047 static void dealloc_dmabuf(struct i810_state *state)
1048 {
1049         struct dmabuf *dmabuf = &state->dmabuf;
1050         struct page *page, *pend;
1051
1052         if (dmabuf->rawbuf) {
1053                 /* undo marking the pages as reserved */
1054                 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
1055                 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
1056                         ClearPageReserved(page);
1057                 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
1058                                     dmabuf->rawbuf, dmabuf->dma_handle);
1059         }
1060         dmabuf->rawbuf = NULL;
1061         dmabuf->mapped = dmabuf->ready = 0;
1062 }
1063
1064 static int prog_dmabuf(struct i810_state *state, unsigned rec)
1065 {
1066         struct dmabuf *dmabuf = &state->dmabuf;
1067         struct i810_channel *c;
1068         struct sg_item *sg;
1069         unsigned long flags;
1070         int ret;
1071         unsigned fragint;
1072         int i;
1073
1074         spin_lock_irqsave(&state->card->lock, flags);
1075         if(dmabuf->enable & DAC_RUNNING)
1076                 __stop_dac(state);
1077         if(dmabuf->enable & ADC_RUNNING)
1078                 __stop_adc(state);
1079         dmabuf->total_bytes = 0;
1080         dmabuf->count = dmabuf->error = 0;
1081         dmabuf->swptr = dmabuf->hwptr = 0;
1082         spin_unlock_irqrestore(&state->card->lock, flags);
1083
1084         /* allocate DMA buffer, let alloc_dmabuf determine if we are already
1085          * allocated well enough or if we should replace the current buffer
1086          * (assuming one is already allocated, if it isn't, then allocate it).
1087          */
1088         if ((ret = alloc_dmabuf(state)))
1089                 return ret;
1090
1091         /* FIXME: figure out all this OSS fragment stuff */
1092         /* I did, it now does what it should according to the OSS API.  DL */
1093         /* We may not have realloced our dmabuf, but the fragment size to
1094          * fragment number ratio may have changed, so go ahead and reprogram
1095          * things
1096          */
1097         dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
1098         dmabuf->numfrag = SG_LEN;
1099         dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
1100         dmabuf->fragsamples = dmabuf->fragsize >> 1;
1101         dmabuf->fragshift = ffs(dmabuf->fragsize) - 1;
1102         dmabuf->userfragsize = dmabuf->ossfragsize;
1103         dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
1104
1105         memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
1106
1107         if(dmabuf->ossmaxfrags == 4) {
1108                 fragint = 8;
1109         } else if (dmabuf->ossmaxfrags == 8) {
1110                 fragint = 4;
1111         } else if (dmabuf->ossmaxfrags == 16) {
1112                 fragint = 2;
1113         } else {
1114                 fragint = 1;
1115         }
1116         /*
1117          *      Now set up the ring
1118          */
1119         if(dmabuf->read_channel)
1120                 c = dmabuf->read_channel;
1121         else
1122                 c = dmabuf->write_channel;
1123         while(c != NULL) {
1124                 sg=&c->sg[0];
1125                 /*
1126                  *      Load up 32 sg entries and take an interrupt at half
1127                  *      way (we might want more interrupts later..)
1128                  */
1129
1130                 for(i=0;i<dmabuf->numfrag;i++)
1131                 {
1132                         sg->busaddr=(u32)dmabuf->dma_handle+dmabuf->fragsize*i;
1133                         // the card will always be doing 16bit stereo
1134                         sg->control=dmabuf->fragsamples;
1135                         if(state->card->pci_id == PCI_DEVICE_ID_SI_7012)
1136                                 sg->control <<= 1;
1137                         sg->control|=CON_BUFPAD;
1138                         // set us up to get IOC interrupts as often as needed to
1139                         // satisfy numfrag requirements, no more
1140                         if( ((i+1) % fragint) == 0) {
1141                                 sg->control|=CON_IOC;
1142                         }
1143                         sg++;
1144                 }
1145                 spin_lock_irqsave(&state->card->lock, flags);
1146                 I810_IOWRITEB(2, state->card, c->port+OFF_CR);   /* reset DMA machine */
1147                 while( I810_IOREADB(state->card, c->port+OFF_CR) & 0x02 ) ;
1148                 I810_IOWRITEL((u32)state->card->chandma +
1149                     c->num*sizeof(struct i810_channel),
1150                     state->card, c->port+OFF_BDBAR);
1151                 CIV_TO_LVI(state->card, c->port, 0);
1152
1153                 spin_unlock_irqrestore(&state->card->lock, flags);
1154
1155                 if(c != dmabuf->write_channel)
1156                         c = dmabuf->write_channel;
1157                 else
1158                         c = NULL;
1159         }
1160
1161         /* set the ready flag for the dma buffer */
1162         dmabuf->ready = 1;
1163
1164 #ifdef DEBUG
1165         printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
1166                "fragsize = %d dmasize = %d\n",
1167                dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
1168                dmabuf->fragsize, dmabuf->dmasize);
1169 #endif
1170
1171         return 0;
1172 }
1173
1174 static void __i810_update_lvi(struct i810_state *state, int rec)
1175 {
1176         struct dmabuf *dmabuf = &state->dmabuf;
1177         int x, port;
1178         int trigger;
1179         int count, fragsize;
1180         void (*start)(struct i810_state *);
1181
1182         count = dmabuf->count;
1183         if (rec) {
1184                 port = dmabuf->read_channel->port;
1185                 trigger = PCM_ENABLE_INPUT;
1186                 start = __start_adc;
1187                 count = dmabuf->dmasize - count;
1188         } else {
1189                 port = dmabuf->write_channel->port;
1190                 trigger = PCM_ENABLE_OUTPUT;
1191                 start = __start_dac;
1192         }
1193
1194         /* Do not process partial fragments. */
1195         fragsize = dmabuf->fragsize;
1196         if (count < fragsize)
1197                 return;
1198
1199         /* if we are currently stopped, then our CIV is actually set to our
1200          * *last* sg segment and we are ready to wrap to the next.  However,
1201          * if we set our LVI to the last sg segment, then it won't wrap to
1202          * the next sg segment, it won't even get a start.  So, instead, when
1203          * we are stopped, we set both the LVI value and also we increment
1204          * the CIV value to the next sg segment to be played so that when
1205          * we call start, things will operate properly.  Since the CIV can't
1206          * be written to directly for this purpose, we set the LVI to CIV + 1
1207          * temporarily.  Once the engine has started we set the LVI to its
1208          * final value.
1209          */
1210         if (!dmabuf->enable && dmabuf->ready) {
1211                 if (!(dmabuf->trigger & trigger))
1212                         return;
1213
1214                 CIV_TO_LVI(state->card, port, 1);
1215
1216                 start(state);
1217                 while (!(I810_IOREADB(state->card, port + OFF_CR) & ((1<<4) | (1<<2))))
1218                         ;
1219         }
1220
1221         /* MASKP2(swptr, fragsize) - 1 is the tail of our transfer */
1222         x = MODULOP2(MASKP2(dmabuf->swptr, fragsize) - 1, dmabuf->dmasize);
1223         x >>= dmabuf->fragshift;
1224         I810_IOWRITEB(x, state->card, port + OFF_LVI);
1225 }
1226
1227 static void i810_update_lvi(struct i810_state *state, int rec)
1228 {
1229         struct dmabuf *dmabuf = &state->dmabuf;
1230         unsigned long flags;
1231
1232         if(!dmabuf->ready)
1233                 return;
1234         spin_lock_irqsave(&state->card->lock, flags);
1235         __i810_update_lvi(state, rec);
1236         spin_unlock_irqrestore(&state->card->lock, flags);
1237 }
1238
1239 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
1240 static void i810_update_ptr(struct i810_state *state)
1241 {
1242         struct dmabuf *dmabuf = &state->dmabuf;
1243         unsigned hwptr;
1244         unsigned fragmask, dmamask;
1245         int diff;
1246
1247         fragmask = MASKP2(~0, dmabuf->fragsize);
1248         dmamask = MODULOP2(~0, dmabuf->dmasize);
1249
1250         /* error handling and process wake up for ADC */
1251         if (dmabuf->enable == ADC_RUNNING) {
1252                 /* update hardware pointer */
1253                 hwptr = i810_get_dma_addr(state, 1) & fragmask;
1254                 diff = (hwptr - dmabuf->hwptr) & dmamask;
1255 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1256                 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1257 #endif
1258                 dmabuf->hwptr = hwptr;
1259                 dmabuf->total_bytes += diff;
1260                 dmabuf->count += diff;
1261                 if (dmabuf->count > dmabuf->dmasize) {
1262                         /* buffer underrun or buffer overrun */
1263                         /* this is normal for the end of a read */
1264                         /* only give an error if we went past the */
1265                         /* last valid sg entry */
1266                         if (GET_CIV(state->card, PI_BASE) !=
1267                             GET_LVI(state->card, PI_BASE)) {
1268                                 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1269                                 dmabuf->error++;
1270                         }
1271                 }
1272                 if (diff)
1273                         wake_up(&dmabuf->wait);
1274         }
1275         /* error handling and process wake up for DAC */
1276         if (dmabuf->enable == DAC_RUNNING) {
1277                 /* update hardware pointer */
1278                 hwptr = i810_get_dma_addr(state, 0) & fragmask;
1279                 diff = (hwptr - dmabuf->hwptr) & dmamask;
1280 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1281                 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1282 #endif
1283                 dmabuf->hwptr = hwptr;
1284                 dmabuf->total_bytes += diff;
1285                 dmabuf->count -= diff;
1286                 if (dmabuf->count < 0) {
1287                         /* buffer underrun or buffer overrun */
1288                         /* this is normal for the end of a write */
1289                         /* only give an error if we went past the */
1290                         /* last valid sg entry */
1291                         if (GET_CIV(state->card, PO_BASE) !=
1292                             GET_LVI(state->card, PO_BASE)) {
1293                                 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1294                                 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1295                                         "count %d\n",
1296                                         GET_CIV(state->card, PO_BASE),
1297                                         GET_LVI(state->card, PO_BASE),
1298                                         dmabuf->hwptr, dmabuf->count);
1299                                 dmabuf->error++;
1300                         }
1301                 }
1302                 if (diff)
1303                         wake_up(&dmabuf->wait);
1304         }
1305 }
1306
1307 static inline int i810_get_free_write_space(struct i810_state *state)
1308 {
1309         struct dmabuf *dmabuf = &state->dmabuf;
1310         int free;
1311
1312         i810_update_ptr(state);
1313         // catch underruns during playback
1314         if (dmabuf->count < 0) {
1315                 dmabuf->count = 0;
1316                 dmabuf->swptr = dmabuf->hwptr;
1317         }
1318         free = dmabuf->dmasize - dmabuf->count;
1319         if(free < 0)
1320                 return(0);
1321         return(free);
1322 }
1323
1324 static inline int i810_get_available_read_data(struct i810_state *state)
1325 {
1326         struct dmabuf *dmabuf = &state->dmabuf;
1327         int avail;
1328
1329         i810_update_ptr(state);
1330         // catch overruns during record
1331         if (dmabuf->count > dmabuf->dmasize) {
1332                 dmabuf->count = dmabuf->dmasize;
1333                 dmabuf->swptr = dmabuf->hwptr;
1334         }
1335         avail = dmabuf->count;
1336         if(avail < 0)
1337                 return(0);
1338         return(avail);
1339 }
1340
1341 static inline void fill_partial_frag(struct dmabuf *dmabuf)
1342 {
1343         unsigned fragsize;
1344         unsigned swptr, len;
1345
1346         fragsize = dmabuf->fragsize;
1347         swptr = dmabuf->swptr;
1348         len = fragsize - MODULOP2(dmabuf->swptr, fragsize);
1349         if (len == fragsize)
1350                 return;
1351
1352         memset(dmabuf->rawbuf + swptr, '\0', len);
1353         dmabuf->swptr = MODULOP2(swptr + len, dmabuf->dmasize);
1354         dmabuf->count += len;
1355 }
1356
1357 static int drain_dac(struct i810_state *state, int signals_allowed)
1358 {
1359         DECLARE_WAITQUEUE(wait, current);
1360         struct dmabuf *dmabuf = &state->dmabuf;
1361         unsigned long flags;
1362         unsigned long tmo;
1363         int count;
1364
1365         if (!dmabuf->ready)
1366                 return 0;
1367         if(dmabuf->mapped) {
1368                 stop_dac(state);
1369                 return 0;
1370         }
1371
1372         spin_lock_irqsave(&state->card->lock, flags);
1373
1374         fill_partial_frag(dmabuf);
1375
1376         /*
1377          * This will make sure that our LVI is correct, that our
1378          * pointer is updated, and that the DAC is running.  We
1379          * have to force the setting of dmabuf->trigger to avoid
1380          * any possible deadlocks.
1381          */
1382         dmabuf->trigger = PCM_ENABLE_OUTPUT;
1383         __i810_update_lvi(state, 0);
1384
1385         spin_unlock_irqrestore(&state->card->lock, flags);
1386
1387         add_wait_queue(&dmabuf->wait, &wait);
1388         for (;;) {
1389
1390                 spin_lock_irqsave(&state->card->lock, flags);
1391                 i810_update_ptr(state);
1392                 count = dmabuf->count;
1393
1394                 /* It seems that we have to set the current state to
1395                  * TASK_INTERRUPTIBLE every time to make the process
1396                  * really go to sleep.  This also has to be *after* the
1397                  * update_ptr() call because update_ptr is likely to
1398                  * do a wake_up() which will unset this before we ever
1399                  * try to sleep, resuling in a tight loop in this code
1400                  * instead of actually sleeping and waiting for an
1401                  * interrupt to wake us up!
1402                  */
1403                 __set_current_state(signals_allowed ?
1404                                     TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1405                 spin_unlock_irqrestore(&state->card->lock, flags);
1406
1407                 if (count <= 0)
1408                         break;
1409
1410                 if (signal_pending(current) && signals_allowed) {
1411                         break;
1412                 }
1413
1414                 /*
1415                  * set the timeout to significantly longer than it *should*
1416                  * take for the DAC to drain the DMA buffer
1417                  */
1418                 tmo = (count * HZ) / (dmabuf->rate);
1419                 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){
1420                         printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1421                         count = 0;
1422                         break;
1423                 }
1424         }
1425         set_current_state(TASK_RUNNING);
1426         remove_wait_queue(&dmabuf->wait, &wait);
1427         if(count > 0 && signal_pending(current) && signals_allowed)
1428                 return -ERESTARTSYS;
1429         stop_dac(state);
1430         return 0;
1431 }
1432
1433 static void i810_channel_interrupt(struct i810_card *card)
1434 {
1435         int i, count;
1436
1437 #ifdef DEBUG_INTERRUPTS
1438         printk("CHANNEL ");
1439 #endif
1440         for(i=0;i<NR_HW_CH;i++)
1441         {
1442                 struct i810_state *state = card->states[i];
1443                 struct i810_channel *c;
1444                 struct dmabuf *dmabuf;
1445                 unsigned long port;
1446                 u16 status;
1447
1448                 if(!state)
1449                         continue;
1450                 if(!state->dmabuf.ready)
1451                         continue;
1452                 dmabuf = &state->dmabuf;
1453                 if(dmabuf->enable & DAC_RUNNING) {
1454                         c=dmabuf->write_channel;
1455                 } else if(dmabuf->enable & ADC_RUNNING) {
1456                         c=dmabuf->read_channel;
1457                 } else  /* This can occur going from R/W to close */
1458                         continue;
1459
1460                 port = c->port;
1461
1462                 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1463                         status = I810_IOREADW(card, port + OFF_PICB);
1464                 else
1465                         status = I810_IOREADW(card, port + OFF_SR);
1466
1467 #ifdef DEBUG_INTERRUPTS
1468                 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1469 #endif
1470                 if(status & DMA_INT_COMPLETE)
1471                 {
1472                         /* only wake_up() waiters if this interrupt signals
1473                          * us being beyond a userfragsize of data open or
1474                          * available, and i810_update_ptr() does that for
1475                          * us
1476                          */
1477                         i810_update_ptr(state);
1478 #ifdef DEBUG_INTERRUPTS
1479                         printk("COMP %d ", dmabuf->hwptr /
1480                                         dmabuf->fragsize);
1481 #endif
1482                 }
1483                 if(status & (DMA_INT_LVI | DMA_INT_DCH))
1484                 {
1485                         /* wake_up() unconditionally on LVI and DCH */
1486                         i810_update_ptr(state);
1487                         wake_up(&dmabuf->wait);
1488 #ifdef DEBUG_INTERRUPTS
1489                         if(status & DMA_INT_LVI)
1490                                 printk("LVI ");
1491                         if(status & DMA_INT_DCH)
1492                                 printk("DCH -");
1493 #endif
1494                         count = dmabuf->count;
1495                         if(dmabuf->enable & ADC_RUNNING)
1496                                 count = dmabuf->dmasize - count;
1497                         if (count >= (int)dmabuf->fragsize) {
1498                                 I810_IOWRITEB(I810_IOREADB(card, port+OFF_CR) | 1, card, port+OFF_CR);
1499 #ifdef DEBUG_INTERRUPTS
1500                                 printk(" CONTINUE ");
1501 #endif
1502                         } else {
1503                                 if (dmabuf->enable & DAC_RUNNING)
1504                                         __stop_dac(state);
1505                                 if (dmabuf->enable & ADC_RUNNING)
1506                                         __stop_adc(state);
1507                                 dmabuf->enable = 0;
1508 #ifdef DEBUG_INTERRUPTS
1509                                 printk(" STOP ");
1510 #endif
1511                         }
1512                 }
1513                 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1514                         I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_PICB);
1515                 else
1516                         I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_SR);
1517         }
1518 #ifdef DEBUG_INTERRUPTS
1519         printk(")\n");
1520 #endif
1521 }
1522
1523 static irqreturn_t i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1524 {
1525         struct i810_card *card = (struct i810_card *)dev_id;
1526         u32 status;
1527
1528         spin_lock(&card->lock);
1529
1530         status = I810_IOREADL(card, GLOB_STA);
1531
1532         if(!(status & INT_MASK))
1533         {
1534                 spin_unlock(&card->lock);
1535                 return IRQ_NONE;  /* not for us */
1536         }
1537
1538         if(status & (INT_PO|INT_PI|INT_MC))
1539                 i810_channel_interrupt(card);
1540
1541         /* clear 'em */
1542         I810_IOWRITEL(status & INT_MASK, card, GLOB_STA);
1543         spin_unlock(&card->lock);
1544         return IRQ_HANDLED;
1545 }
1546
1547 /* in this loop, dmabuf.count signifies the amount of data that is
1548    waiting to be copied to the user's buffer.  It is filled by the dma
1549    machine and drained by this loop. */
1550
1551 static ssize_t i810_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1552 {
1553         struct i810_state *state = (struct i810_state *)file->private_data;
1554         struct i810_card *card=state ? state->card : NULL;
1555         struct dmabuf *dmabuf = &state->dmabuf;
1556         ssize_t ret;
1557         unsigned long flags;
1558         unsigned int swptr;
1559         int cnt;
1560         int pending;
1561         DECLARE_WAITQUEUE(waita, current);
1562
1563 #ifdef DEBUG2
1564         printk("i810_audio: i810_read called, count = %d\n", count);
1565 #endif
1566
1567         if (dmabuf->mapped)
1568                 return -ENXIO;
1569         if (dmabuf->enable & DAC_RUNNING)
1570                 return -ENODEV;
1571         if (!dmabuf->read_channel) {
1572                 dmabuf->ready = 0;
1573                 dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
1574                 if (!dmabuf->read_channel) {
1575                         return -EBUSY;
1576                 }
1577         }
1578         if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1579                 return ret;
1580         if (!access_ok(VERIFY_WRITE, buffer, count))
1581                 return -EFAULT;
1582         ret = 0;
1583
1584         pending = 0;
1585
1586         add_wait_queue(&dmabuf->wait, &waita);
1587         while (count > 0) {
1588                 set_current_state(TASK_INTERRUPTIBLE);
1589                 spin_lock_irqsave(&card->lock, flags);
1590                 if (PM_SUSPENDED(card)) {
1591                         spin_unlock_irqrestore(&card->lock, flags);
1592                         schedule();
1593                         if (signal_pending(current)) {
1594                                 if (!ret) ret = -EAGAIN;
1595                                 break;
1596                         }
1597                         continue;
1598                 }
1599                 cnt = i810_get_available_read_data(state);
1600                 swptr = dmabuf->swptr;
1601                 // this is to make the copy_to_user simpler below
1602                 if(cnt > (dmabuf->dmasize - swptr))
1603                         cnt = dmabuf->dmasize - swptr;
1604                 spin_unlock_irqrestore(&card->lock, flags);
1605
1606                 if (cnt > count)
1607                         cnt = count;
1608                 if (cnt <= 0) {
1609                         unsigned long tmo;
1610                         /*
1611                          * Don't let us deadlock.  The ADC won't start if
1612                          * dmabuf->trigger isn't set.  A call to SETTRIGGER
1613                          * could have turned it off after we set it to on
1614                          * previously.
1615                          */
1616                         dmabuf->trigger = PCM_ENABLE_INPUT;
1617                         /*
1618                          * This does three things.  Updates LVI to be correct,
1619                          * makes sure the ADC is running, and updates the
1620                          * hwptr.
1621                          */
1622                         i810_update_lvi(state,1);
1623                         if (file->f_flags & O_NONBLOCK) {
1624                                 if (!ret) ret = -EAGAIN;
1625                                 goto done;
1626                         }
1627                         /* Set the timeout to how long it would take to fill
1628                          * two of our buffers.  If we haven't been woke up
1629                          * by then, then we know something is wrong.
1630                          */
1631                         tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1632                         /* There are two situations when sleep_on_timeout returns, one is when
1633                            the interrupt is serviced correctly and the process is waked up by
1634                            ISR ON TIME. Another is when timeout is expired, which means that
1635                            either interrupt is NOT serviced correctly (pending interrupt) or it
1636                            is TOO LATE for the process to be scheduled to run (scheduler latency)
1637                            which results in a (potential) buffer overrun. And worse, there is
1638                            NOTHING we can do to prevent it. */
1639                         if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1640 #ifdef DEBUG
1641                                 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1642                                        "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1643                                        dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1644                                        dmabuf->hwptr, dmabuf->swptr);
1645 #endif
1646                                 /* a buffer overrun, we delay the recovery until next time the
1647                                    while loop begin and we REALLY have space to record */
1648                         }
1649                         if (signal_pending(current)) {
1650                                 ret = ret ? ret : -ERESTARTSYS;
1651                                 goto done;
1652                         }
1653                         continue;
1654                 }
1655
1656                 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1657                         if (!ret) ret = -EFAULT;
1658                         goto done;
1659                 }
1660
1661                 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1662
1663                 spin_lock_irqsave(&card->lock, flags);
1664
1665                 if (PM_SUSPENDED(card)) {
1666                         spin_unlock_irqrestore(&card->lock, flags);
1667                         continue;
1668                 }
1669                 dmabuf->swptr = swptr;
1670                 pending = dmabuf->count -= cnt;
1671                 spin_unlock_irqrestore(&card->lock, flags);
1672
1673                 count -= cnt;
1674                 buffer += cnt;
1675                 ret += cnt;
1676         }
1677  done:
1678         pending = dmabuf->dmasize - pending;
1679         if (dmabuf->enable || pending >= dmabuf->userfragsize)
1680                 i810_update_lvi(state, 1);
1681         set_current_state(TASK_RUNNING);
1682         remove_wait_queue(&dmabuf->wait, &waita);
1683
1684         return ret;
1685 }
1686
1687 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1688    the soundcard.  it is drained by the dma machine and filled by this loop. */
1689 static ssize_t i810_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1690 {
1691         struct i810_state *state = (struct i810_state *)file->private_data;
1692         struct i810_card *card=state ? state->card : NULL;
1693         struct dmabuf *dmabuf = &state->dmabuf;
1694         ssize_t ret;
1695         unsigned long flags;
1696         unsigned int swptr = 0;
1697         int pending;
1698         int cnt;
1699         DECLARE_WAITQUEUE(waita, current);
1700
1701 #ifdef DEBUG2
1702         printk("i810_audio: i810_write called, count = %d\n", count);
1703 #endif
1704
1705         if (dmabuf->mapped)
1706                 return -ENXIO;
1707         if (dmabuf->enable & ADC_RUNNING)
1708                 return -ENODEV;
1709         if (!dmabuf->write_channel) {
1710                 dmabuf->ready = 0;
1711                 dmabuf->write_channel = card->alloc_pcm_channel(card);
1712                 if(!dmabuf->write_channel)
1713                         return -EBUSY;
1714         }
1715         if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1716                 return ret;
1717         if (!access_ok(VERIFY_READ, buffer, count))
1718                 return -EFAULT;
1719         ret = 0;
1720
1721         pending = 0;
1722
1723         add_wait_queue(&dmabuf->wait, &waita);
1724         while (count > 0) {
1725                 set_current_state(TASK_INTERRUPTIBLE);
1726                 spin_lock_irqsave(&state->card->lock, flags);
1727                 if (PM_SUSPENDED(card)) {
1728                         spin_unlock_irqrestore(&card->lock, flags);
1729                         schedule();
1730                         if (signal_pending(current)) {
1731                                 if (!ret) ret = -EAGAIN;
1732                                 break;
1733                         }
1734                         continue;
1735                 }
1736
1737                 cnt = i810_get_free_write_space(state);
1738                 swptr = dmabuf->swptr;
1739                 /* Bound the maximum size to how much we can copy to the
1740                  * dma buffer before we hit the end.  If we have more to
1741                  * copy then it will get done in a second pass of this
1742                  * loop starting from the beginning of the buffer.
1743                  */
1744                 if(cnt > (dmabuf->dmasize - swptr))
1745                         cnt = dmabuf->dmasize - swptr;
1746                 spin_unlock_irqrestore(&state->card->lock, flags);
1747
1748 #ifdef DEBUG2
1749                 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1750 #endif
1751                 if (cnt > count)
1752                         cnt = count;
1753                 if (cnt <= 0) {
1754                         unsigned long tmo;
1755                         // There is data waiting to be played
1756                         /*
1757                          * Force the trigger setting since we would
1758                          * deadlock with it set any other way
1759                          */
1760                         dmabuf->trigger = PCM_ENABLE_OUTPUT;
1761                         i810_update_lvi(state,0);
1762                         if (file->f_flags & O_NONBLOCK) {
1763                                 if (!ret) ret = -EAGAIN;
1764                                 goto ret;
1765                         }
1766                         /* Not strictly correct but works */
1767                         tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1768                         /* There are two situations when sleep_on_timeout returns, one is when
1769                            the interrupt is serviced correctly and the process is waked up by
1770                            ISR ON TIME. Another is when timeout is expired, which means that
1771                            either interrupt is NOT serviced correctly (pending interrupt) or it
1772                            is TOO LATE for the process to be scheduled to run (scheduler latency)
1773                            which results in a (potential) buffer underrun. And worse, there is
1774                            NOTHING we can do to prevent it. */
1775                         if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1776 #ifdef DEBUG
1777                                 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1778                                        "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1779                                        dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1780                                        dmabuf->hwptr, dmabuf->swptr);
1781 #endif
1782                                 /* a buffer underrun, we delay the recovery until next time the
1783                                    while loop begin and we REALLY have data to play */
1784                                 //return ret;
1785                         }
1786                         if (signal_pending(current)) {
1787                                 if (!ret) ret = -ERESTARTSYS;
1788                                 goto ret;
1789                         }
1790                         continue;
1791                 }
1792                 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1793                         if (!ret) ret = -EFAULT;
1794                         goto ret;
1795                 }
1796
1797                 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1798
1799                 spin_lock_irqsave(&state->card->lock, flags);
1800                 if (PM_SUSPENDED(card)) {
1801                         spin_unlock_irqrestore(&card->lock, flags);
1802                         continue;
1803                 }
1804
1805                 dmabuf->swptr = swptr;
1806                 pending = dmabuf->count += cnt;
1807
1808                 count -= cnt;
1809                 buffer += cnt;
1810                 ret += cnt;
1811                 spin_unlock_irqrestore(&state->card->lock, flags);
1812         }
1813 ret:
1814         if (dmabuf->enable || pending >= dmabuf->userfragsize)
1815                 i810_update_lvi(state, 0);
1816         set_current_state(TASK_RUNNING);
1817         remove_wait_queue(&dmabuf->wait, &waita);
1818
1819         return ret;
1820 }
1821
1822 /* No kernel lock - we have our own spinlock */
1823 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1824 {
1825         struct i810_state *state = (struct i810_state *)file->private_data;
1826         struct dmabuf *dmabuf = &state->dmabuf;
1827         unsigned long flags;
1828         unsigned int mask = 0;
1829
1830         if(!dmabuf->ready)
1831                 return 0;
1832         poll_wait(file, &dmabuf->wait, wait);
1833         spin_lock_irqsave(&state->card->lock, flags);
1834         if (dmabuf->enable & ADC_RUNNING ||
1835             dmabuf->trigger & PCM_ENABLE_INPUT) {
1836                 if (i810_get_available_read_data(state) >=
1837                     (signed)dmabuf->userfragsize)
1838                         mask |= POLLIN | POLLRDNORM;
1839         }
1840         if (dmabuf->enable & DAC_RUNNING ||
1841             dmabuf->trigger & PCM_ENABLE_OUTPUT) {
1842                 if (i810_get_free_write_space(state) >=
1843                     (signed)dmabuf->userfragsize)
1844                         mask |= POLLOUT | POLLWRNORM;
1845         }
1846         spin_unlock_irqrestore(&state->card->lock, flags);
1847         return mask;
1848 }
1849
1850 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1851 {
1852         struct i810_state *state = (struct i810_state *)file->private_data;
1853         struct dmabuf *dmabuf = &state->dmabuf;
1854         int ret = -EINVAL;
1855         unsigned long size;
1856
1857         lock_kernel();
1858         if (vma->vm_flags & VM_WRITE) {
1859                 if (!dmabuf->write_channel &&
1860                     (dmabuf->write_channel =
1861                      state->card->alloc_pcm_channel(state->card)) == NULL) {
1862                         ret = -EBUSY;
1863                         goto out;
1864                 }
1865         }
1866         if (vma->vm_flags & VM_READ) {
1867                 if (!dmabuf->read_channel &&
1868                     (dmabuf->read_channel =
1869                      state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1870                         ret = -EBUSY;
1871                         goto out;
1872                 }
1873         }
1874         if ((ret = prog_dmabuf(state, 0)) != 0)
1875                 goto out;
1876
1877         ret = -EINVAL;
1878         if (vma->vm_pgoff != 0)
1879                 goto out;
1880         size = vma->vm_end - vma->vm_start;
1881         if (size > (PAGE_SIZE << dmabuf->buforder))
1882                 goto out;
1883         ret = -EAGAIN;
1884         if (remap_pfn_range(vma, vma->vm_start,
1885                              virt_to_phys(dmabuf->rawbuf) >> PAGE_SHIFT,
1886                              size, vma->vm_page_prot))
1887                 goto out;
1888         dmabuf->mapped = 1;
1889         dmabuf->trigger = 0;
1890         ret = 0;
1891 #ifdef DEBUG_MMAP
1892         printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1893 #endif
1894 out:
1895         unlock_kernel();
1896         return ret;
1897 }
1898
1899 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1900 {
1901         struct i810_state *state = (struct i810_state *)file->private_data;
1902         struct i810_channel *c = NULL;
1903         struct dmabuf *dmabuf = &state->dmabuf;
1904         unsigned long flags;
1905         audio_buf_info abinfo;
1906         count_info cinfo;
1907         unsigned int i_glob_cnt;
1908         int val = 0, ret;
1909         struct ac97_codec *codec = state->card->ac97_codec[0];
1910         void __user *argp = (void __user *)arg;
1911         int __user *p = argp;
1912
1913 #ifdef DEBUG
1914         printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *p : 0);
1915 #endif
1916
1917         switch (cmd)
1918         {
1919         case OSS_GETVERSION:
1920 #ifdef DEBUG
1921                 printk("OSS_GETVERSION\n");
1922 #endif
1923                 return put_user(SOUND_VERSION, p);
1924
1925         case SNDCTL_DSP_RESET:
1926 #ifdef DEBUG
1927                 printk("SNDCTL_DSP_RESET\n");
1928 #endif
1929                 spin_lock_irqsave(&state->card->lock, flags);
1930                 if (dmabuf->enable == DAC_RUNNING) {
1931                         c = dmabuf->write_channel;
1932                         __stop_dac(state);
1933                 }
1934                 if (dmabuf->enable == ADC_RUNNING) {
1935                         c = dmabuf->read_channel;
1936                         __stop_adc(state);
1937                 }
1938                 if (c != NULL) {
1939                         I810_IOWRITEB(2, state->card, c->port+OFF_CR);   /* reset DMA machine */
1940                         while ( I810_IOREADB(state->card, c->port+OFF_CR) & 2 )
1941                                 cpu_relax();
1942                         I810_IOWRITEL((u32)state->card->chandma +
1943                             c->num*sizeof(struct i810_channel),
1944                             state->card, c->port+OFF_BDBAR);
1945                         CIV_TO_LVI(state->card, c->port, 0);
1946                 }
1947
1948                 spin_unlock_irqrestore(&state->card->lock, flags);
1949                 synchronize_irq(state->card->pci_dev->irq);
1950                 dmabuf->ready = 0;
1951                 dmabuf->swptr = dmabuf->hwptr = 0;
1952                 dmabuf->count = dmabuf->total_bytes = 0;
1953                 return 0;
1954
1955         case SNDCTL_DSP_SYNC:
1956 #ifdef DEBUG
1957                 printk("SNDCTL_DSP_SYNC\n");
1958 #endif
1959                 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1960                         return 0;
1961                 if((val = drain_dac(state, 1)))
1962                         return val;
1963                 dmabuf->total_bytes = 0;
1964                 return 0;
1965
1966         case SNDCTL_DSP_SPEED: /* set smaple rate */
1967 #ifdef DEBUG
1968                 printk("SNDCTL_DSP_SPEED\n");
1969 #endif
1970                 if (get_user(val, p))
1971                         return -EFAULT;
1972                 if (val >= 0) {
1973                         if (file->f_mode & FMODE_WRITE) {
1974                                 if ( (state->card->ac97_status & SPDIF_ON) ) {  /* S/PDIF Enabled */
1975                                         /* AD1886 only supports 48000, need to check that */
1976                                         if ( i810_valid_spdif_rate ( codec, val ) ) {
1977                                                 /* Set DAC rate */
1978                                                 i810_set_spdif_output ( state, -1, 0 );
1979                                                 stop_dac(state);
1980                                                 dmabuf->ready = 0;
1981                                                 spin_lock_irqsave(&state->card->lock, flags);
1982                                                 i810_set_dac_rate(state, val);
1983                                                 spin_unlock_irqrestore(&state->card->lock, flags);
1984                                                 /* Set S/PDIF transmitter rate. */
1985                                                 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1986                                                 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1987                                                         val = dmabuf->rate;
1988                                                 }
1989                                         } else { /* Not a valid rate for S/PDIF, ignore it */
1990                                                 val = dmabuf->rate;
1991                                         }
1992                                 } else {
1993                                         stop_dac(state);
1994                                         dmabuf->ready = 0;
1995                                         spin_lock_irqsave(&state->card->lock, flags);
1996                                         i810_set_dac_rate(state, val);
1997                                         spin_unlock_irqrestore(&state->card->lock, flags);
1998                                 }
1999                         }
2000                         if (file->f_mode & FMODE_READ) {
2001                                 stop_adc(state);
2002                                 dmabuf->ready = 0;
2003                                 spin_lock_irqsave(&state->card->lock, flags);
2004                                 i810_set_adc_rate(state, val);
2005                                 spin_unlock_irqrestore(&state->card->lock, flags);
2006                         }
2007                 }
2008                 return put_user(dmabuf->rate, p);
2009
2010         case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
2011 #ifdef DEBUG
2012                 printk("SNDCTL_DSP_STEREO\n");
2013 #endif
2014                 if (dmabuf->enable & DAC_RUNNING) {
2015                         stop_dac(state);
2016                 }
2017                 if (dmabuf->enable & ADC_RUNNING) {
2018                         stop_adc(state);
2019                 }
2020                 return put_user(1, p);
2021
2022         case SNDCTL_DSP_GETBLKSIZE:
2023                 if (file->f_mode & FMODE_WRITE) {
2024                         if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
2025                                 return val;
2026                 }
2027                 if (file->f_mode & FMODE_READ) {
2028                         if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
2029                                 return val;
2030                 }
2031 #ifdef DEBUG
2032                 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
2033 #endif
2034                 return put_user(dmabuf->userfragsize, p);
2035
2036         case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
2037 #ifdef DEBUG
2038                 printk("SNDCTL_DSP_GETFMTS\n");
2039 #endif
2040                 return put_user(AFMT_S16_LE, p);
2041
2042         case SNDCTL_DSP_SETFMT: /* Select sample format */
2043 #ifdef DEBUG
2044                 printk("SNDCTL_DSP_SETFMT\n");
2045 #endif
2046                 return put_user(AFMT_S16_LE, p);
2047
2048         case SNDCTL_DSP_CHANNELS:
2049 #ifdef DEBUG
2050                 printk("SNDCTL_DSP_CHANNELS\n");
2051 #endif
2052                 if (get_user(val, p))
2053                         return -EFAULT;
2054
2055                 if (val > 0) {
2056                         if (dmabuf->enable & DAC_RUNNING) {
2057                                 stop_dac(state);
2058                         }
2059                         if (dmabuf->enable & ADC_RUNNING) {
2060                                 stop_adc(state);
2061                         }
2062                 } else {
2063                         return put_user(state->card->channels, p);
2064                 }
2065
2066                 /* ICH and ICH0 only support 2 channels */
2067                 if ( state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AA_5
2068                      || state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AB_5)
2069                         return put_user(2, p);
2070
2071                 /* Multi-channel support was added with ICH2. Bits in */
2072                 /* Global Status and Global Control register are now  */
2073                 /* used to indicate this.                             */
2074
2075                 i_glob_cnt = I810_IOREADL(state->card, GLOB_CNT);
2076
2077                 /* Current # of channels enabled */
2078                 if ( i_glob_cnt & 0x0100000 )
2079                         ret = 4;
2080                 else if ( i_glob_cnt & 0x0200000 )
2081                         ret = 6;
2082                 else
2083                         ret = 2;
2084
2085                 switch ( val ) {
2086                         case 2: /* 2 channels is always supported */
2087                                 I810_IOWRITEL(i_glob_cnt & 0xffcfffff,
2088                                      state->card, GLOB_CNT);
2089                                 /* Do we need to change mixer settings????  */
2090                                 break;
2091                         case 4: /* Supported on some chipsets, better check first */
2092                                 if ( state->card->channels >= 4 ) {
2093                                         I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x100000,
2094                                               state->card, GLOB_CNT);
2095                                         /* Do we need to change mixer settings??? */
2096                                 } else {
2097                                         val = ret;
2098                                 }
2099                                 break;
2100                         case 6: /* Supported on some chipsets, better check first */
2101                                 if ( state->card->channels >= 6 ) {
2102                                         I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x200000,
2103                                               state->card, GLOB_CNT);
2104                                         /* Do we need to change mixer settings??? */
2105                                 } else {
2106                                         val = ret;
2107                                 }
2108                                 break;
2109                         default: /* nothing else is ever supported by the chipset */
2110                                 val = ret;
2111                                 break;
2112                 }
2113
2114                 return put_user(val, p);
2115
2116         case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
2117                 /* we update the swptr to the end of the last sg segment then return */
2118 #ifdef DEBUG
2119                 printk("SNDCTL_DSP_POST\n");
2120 #endif
2121                 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
2122                         return 0;
2123                 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
2124                         val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
2125                         dmabuf->swptr += val;
2126                         dmabuf->count += val;
2127                 }
2128                 return 0;
2129
2130         case SNDCTL_DSP_SUBDIVIDE:
2131                 if (dmabuf->subdivision)
2132                         return -EINVAL;
2133                 if (get_user(val, p))
2134                         return -EFAULT;
2135                 if (val != 1 && val != 2 && val != 4)
2136                         return -EINVAL;
2137 #ifdef DEBUG
2138                 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
2139 #endif
2140                 dmabuf->subdivision = val;
2141                 dmabuf->ready = 0;
2142                 return 0;
2143
2144         case SNDCTL_DSP_SETFRAGMENT:
2145                 if (get_user(val, p))
2146                         return -EFAULT;
2147
2148                 dmabuf->ossfragsize = 1<<(val & 0xffff);
2149                 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
2150                 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags)
2151                         return -EINVAL;
2152                 /*
2153                  * Bound the frag size into our allowed range of 256 - 4096
2154                  */
2155                 if (dmabuf->ossfragsize < 256)
2156                         dmabuf->ossfragsize = 256;
2157                 else if (dmabuf->ossfragsize > 4096)
2158                         dmabuf->ossfragsize = 4096;
2159                 /*
2160                  * The numfrags could be something reasonable, or it could
2161                  * be 0xffff meaning "Give me as much as possible".  So,
2162                  * we check the numfrags * fragsize doesn't exceed our
2163                  * 64k buffer limit, nor is it less than our 8k minimum.
2164                  * If it fails either one of these checks, then adjust the
2165                  * number of fragments, not the size of them.  It's OK if
2166                  * our number of fragments doesn't equal 32 or anything
2167                  * like our hardware based number now since we are using
2168                  * a different frag count for the hardware.  Before we get
2169                  * into this though, bound the maxfrags to avoid overflow
2170                  * issues.  A reasonable bound would be 64k / 256 since our
2171                  * maximum buffer size is 64k and our minimum frag size is
2172                  * 256.  On the other end, our minimum buffer size is 8k and
2173                  * our maximum frag size is 4k, so the lower bound should
2174                  * be 2.
2175                  */
2176
2177                 if(dmabuf->ossmaxfrags > 256)
2178                         dmabuf->ossmaxfrags = 256;
2179                 else if (dmabuf->ossmaxfrags < 2)
2180                         dmabuf->ossmaxfrags = 2;
2181
2182                 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
2183                 while (val < 8192) {
2184                     val <<= 1;
2185                     dmabuf->ossmaxfrags <<= 1;
2186                 }
2187                 while (val > 65536) {
2188                     val >>= 1;
2189                     dmabuf->ossmaxfrags >>= 1;
2190                 }
2191                 dmabuf->ready = 0;
2192 #ifdef DEBUG
2193                 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
2194                         dmabuf->ossfragsize, dmabuf->ossmaxfrags);
2195 #endif
2196
2197                 return 0;
2198
2199         case SNDCTL_DSP_GETOSPACE:
2200                 if (!(file->f_mode & FMODE_WRITE))
2201                         return -EINVAL;
2202                 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2203                         return val;
2204                 spin_lock_irqsave(&state->card->lock, flags);
2205                 i810_update_ptr(state);
2206                 abinfo.fragsize = dmabuf->userfragsize;
2207                 abinfo.fragstotal = dmabuf->userfrags;
2208                 if (dmabuf->mapped)
2209                         abinfo.bytes = dmabuf->dmasize;
2210                 else
2211                         abinfo.bytes = i810_get_free_write_space(state);
2212                 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2213                 spin_unlock_irqrestore(&state->card->lock, flags);
2214 #if defined(DEBUG) || defined(DEBUG_MMAP)
2215                 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
2216                         abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2217 #endif
2218                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2219
2220         case SNDCTL_DSP_GETOPTR:
2221                 if (!(file->f_mode & FMODE_WRITE))
2222                         return -EINVAL;
2223                 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2224                         return val;
2225                 spin_lock_irqsave(&state->card->lock, flags);
2226                 val = i810_get_free_write_space(state);
2227                 cinfo.bytes = dmabuf->total_bytes;
2228                 cinfo.ptr = dmabuf->hwptr;
2229                 cinfo.blocks = val/dmabuf->userfragsize;
2230                 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
2231                         dmabuf->count += val;
2232                         dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2233                         __i810_update_lvi(state, 0);
2234                 }
2235                 spin_unlock_irqrestore(&state->card->lock, flags);
2236 #if defined(DEBUG) || defined(DEBUG_MMAP)
2237                 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
2238                         cinfo.blocks, cinfo.ptr, dmabuf->count);
2239 #endif
2240                 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2241
2242         case SNDCTL_DSP_GETISPACE:
2243                 if (!(file->f_mode & FMODE_READ))
2244                         return -EINVAL;
2245                 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
2246                         return val;
2247                 spin_lock_irqsave(&state->card->lock, flags);
2248                 abinfo.bytes = i810_get_available_read_data(state);
2249                 abinfo.fragsize = dmabuf->userfragsize;
2250                 abinfo.fragstotal = dmabuf->userfrags;
2251                 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2252                 spin_unlock_irqrestore(&state->card->lock, flags);
2253 #if defined(DEBUG) || defined(DEBUG_MMAP)
2254                 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
2255                         abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2256 #endif
2257                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2258
2259         case SNDCTL_DSP_GETIPTR:
2260                 if (!(file->f_mode & FMODE_READ))
2261                         return -EINVAL;
2262                 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2263                         return val;
2264                 spin_lock_irqsave(&state->card->lock, flags);
2265                 val = i810_get_available_read_data(state);
2266                 cinfo.bytes = dmabuf->total_bytes;
2267                 cinfo.blocks = val/dmabuf->userfragsize;
2268                 cinfo.ptr = dmabuf->hwptr;
2269                 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) {
2270                         dmabuf->count -= val;
2271                         dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2272                         __i810_update_lvi(state, 1);
2273                 }
2274                 spin_unlock_irqrestore(&state->card->lock, flags);
2275 #if defined(DEBUG) || defined(DEBUG_MMAP)
2276                 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
2277                         cinfo.blocks, cinfo.ptr, dmabuf->count);
2278 #endif
2279                 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2280
2281         case SNDCTL_DSP_NONBLOCK:
2282 #ifdef DEBUG
2283                 printk("SNDCTL_DSP_NONBLOCK\n");
2284 #endif
2285                 file->f_flags |= O_NONBLOCK;
2286                 return 0;
2287
2288         case SNDCTL_DSP_GETCAPS:
2289 #ifdef DEBUG
2290                 printk("SNDCTL_DSP_GETCAPS\n");
2291 #endif
2292             return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
2293                             p);
2294
2295         case SNDCTL_DSP_GETTRIGGER:
2296                 val = 0;
2297 #ifdef DEBUG
2298                 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
2299 #endif
2300                 return put_user(dmabuf->trigger, p);
2301
2302         case SNDCTL_DSP_SETTRIGGER:
2303                 if (get_user(val, p))
2304                         return -EFAULT;
2305 #if defined(DEBUG) || defined(DEBUG_MMAP)
2306                 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
2307 #endif
2308                 /* silently ignore invalid PCM_ENABLE_xxx bits,
2309                  * like the other drivers do
2310                  */
2311                 if (!(file->f_mode & FMODE_READ ))
2312                         val &= ~PCM_ENABLE_INPUT;
2313                 if (!(file->f_mode & FMODE_WRITE ))
2314                         val &= ~PCM_ENABLE_OUTPUT;
2315                 if((file->f_mode & FMODE_READ) && !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
2316                         stop_adc(state);
2317                 }
2318                 if((file->f_mode & FMODE_WRITE) && !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
2319                         stop_dac(state);
2320                 }
2321                 dmabuf->trigger = val;
2322                 if((val & PCM_ENABLE_OUTPUT) && !(dmabuf->enable & DAC_RUNNING)) {
2323                         if (!dmabuf->write_channel) {
2324                                 dmabuf->ready = 0;
2325                                 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
2326                                 if (!dmabuf->write_channel)
2327                                         return -EBUSY;
2328                         }
2329                         if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
2330                                 return ret;
2331                         if (dmabuf->mapped) {
2332                                 spin_lock_irqsave(&state->card->lock, flags);
2333                                 i810_update_ptr(state);
2334                                 dmabuf->count = 0;
2335                                 dmabuf->swptr = dmabuf->hwptr;
2336                                 dmabuf->count = i810_get_free_write_space(state);
2337                                 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize;
2338                                 spin_unlock_irqrestore(&state->card->lock, flags);
2339                         }
2340                         i810_update_lvi(state, 0);
2341                         start_dac(state);
2342                 }
2343                 if((val & PCM_ENABLE_INPUT) && !(dmabuf->enable & ADC_RUNNING)) {
2344                         if (!dmabuf->read_channel) {
2345                                 dmabuf->ready = 0;
2346                                 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
2347                                 if (!dmabuf->read_channel)
2348                                         return -EBUSY;
2349                         }
2350                         if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
2351                                 return ret;
2352                         if (dmabuf->mapped) {
2353                                 spin_lock_irqsave(&state->card->lock, flags);
2354                                 i810_update_ptr(state);
2355                                 dmabuf->swptr = dmabuf->hwptr;
2356                                 dmabuf->count = 0;
2357                                 spin_unlock_irqrestore(&state->card->lock, flags);
2358                         }
2359                         i810_update_lvi(state, 1);
2360                         start_adc(state);
2361                 }
2362                 return 0;
2363
2364         case SNDCTL_DSP_SETDUPLEX:
2365 #ifdef DEBUG
2366                 printk("SNDCTL_DSP_SETDUPLEX\n");
2367 #endif
2368                 return -EINVAL;
2369
2370         case SNDCTL_DSP_GETODELAY:
2371                 if (!(file->f_mode & FMODE_WRITE))
2372                         return -EINVAL;
2373                 spin_lock_irqsave(&state->card->lock, flags);
2374                 i810_update_ptr(state);
2375                 val = dmabuf->count;
2376                 spin_unlock_irqrestore(&state->card->lock, flags);
2377 #ifdef DEBUG
2378                 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
2379 #endif
2380                 return put_user(val, p);
2381
2382         case SOUND_PCM_READ_RATE:
2383 #ifdef DEBUG
2384                 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
2385 #endif
2386                 return put_user(dmabuf->rate, p);
2387
2388         case SOUND_PCM_READ_CHANNELS:
2389 #ifdef DEBUG
2390                 printk("SOUND_PCM_READ_CHANNELS\n");
2391 #endif
2392                 return put_user(2, p);
2393
2394         case SOUND_PCM_READ_BITS:
2395 #ifdef DEBUG
2396                 printk("SOUND_PCM_READ_BITS\n");
2397 #endif
2398                 return put_user(AFMT_S16_LE, p);
2399
2400         case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
2401 #ifdef DEBUG
2402                 printk("SNDCTL_DSP_SETSPDIF\n");
2403 #endif
2404                 if (get_user(val, p))
2405                         return -EFAULT;
2406
2407                 /* Check to make sure the codec supports S/PDIF transmitter */
2408
2409                 if((state->card->ac97_features & 4)) {
2410                         /* mask out the transmitter speed bits so the user can't set them */
2411                         val &= ~0x3000;
2412
2413                         /* Add the current transmitter speed bits to the passed value */
2414                         ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2415                         val |= (ret & 0x3000);
2416
2417                         i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
2418                         if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
2419                                 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
2420                                 return -EFAULT;
2421                         }
2422                 }
2423 #ifdef DEBUG
2424                 else
2425                         printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2426 #endif
2427                 return put_user(val, p);
2428
2429         case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2430 #ifdef DEBUG
2431                 printk("SNDCTL_DSP_GETSPDIF\n");
2432 #endif
2433                 if (get_user(val, p))
2434                         return -EFAULT;
2435
2436                 /* Check to make sure the codec supports S/PDIF transmitter */
2437
2438                 if(!(state->card->ac97_features & 4)) {
2439 #ifdef DEBUG
2440                         printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2441 #endif
2442                         val = 0;
2443                 } else {
2444                         val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2445                 }
2446                 //return put_user((val & 0xcfff), p);
2447                 return put_user(val, p);
2448
2449         case SNDCTL_DSP_GETCHANNELMASK:
2450 #ifdef DEBUG
2451                 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2452 #endif
2453                 if (get_user(val, p))
2454                         return -EFAULT;
2455
2456                 /* Based on AC'97 DAC support, not ICH hardware */
2457                 val = DSP_BIND_FRONT;
2458                 if ( state->card->ac97_features & 0x0004 )
2459                         val |= DSP_BIND_SPDIF;
2460
2461                 if ( state->card->ac97_features & 0x0080 )
2462                         val |= DSP_BIND_SURR;
2463                 if ( state->card->ac97_features & 0x0140 )
2464                         val |= DSP_BIND_CENTER_LFE;
2465
2466                 return put_user(val, p);
2467
2468         case SNDCTL_DSP_BIND_CHANNEL:
2469 #ifdef DEBUG
2470                 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2471 #endif
2472                 if (get_user(val, p))
2473                         return -EFAULT;
2474                 if ( val == DSP_BIND_QUERY ) {
2475                         val = DSP_BIND_FRONT; /* Always report this as being enabled */
2476                         if ( state->card->ac97_status & SPDIF_ON )
2477                                 val |= DSP_BIND_SPDIF;
2478                         else {
2479                                 if ( state->card->ac97_status & SURR_ON )
2480                                         val |= DSP_BIND_SURR;
2481                                 if ( state->card->ac97_status & CENTER_LFE_ON )
2482                                         val |= DSP_BIND_CENTER_LFE;
2483                         }
2484                 } else {  /* Not a query, set it */
2485                         if (!(file->f_mode & FMODE_WRITE))
2486                                 return -EINVAL;
2487                         if ( dmabuf->enable == DAC_RUNNING ) {
2488                                 stop_dac(state);
2489                         }
2490                         if ( val & DSP_BIND_SPDIF ) {  /* Turn on SPDIF */
2491                                 /*  Ok, this should probably define what slots
2492                                  *  to use. For now, we'll only set it to the
2493                                  *  defaults:
2494                                  *
2495                                  *   non multichannel codec maps to slots 3&4
2496                                  *   2 channel codec maps to slots 7&8
2497                                  *   4 channel codec maps to slots 6&9
2498                                  *   6 channel codec maps to slots 10&11
2499                                  *
2500                                  *  there should be some way for the app to
2501                                  *  select the slot assignment.
2502                                  */
2503
2504                                 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2505                                 if ( !(state->card->ac97_status & SPDIF_ON) )
2506                                         val &= ~DSP_BIND_SPDIF;
2507                         } else {
2508                                 int mask;
2509                                 int channels;
2510
2511                                 /* Turn off S/PDIF if it was on */
2512                                 if ( state->card->ac97_status & SPDIF_ON )
2513                                         i810_set_spdif_output ( state, -1, 0 );
2514
2515                                 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2516                                 switch (mask) {
2517                                         case DSP_BIND_FRONT:
2518                                                 channels = 2;
2519                                                 break;
2520                                         case DSP_BIND_FRONT|DSP_BIND_SURR:
2521                                                 channels = 4;
2522                                                 break;
2523                                         case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2524                                                 channels = 6;
2525                                                 break;
2526                                         default:
2527                                                 val = DSP_BIND_FRONT;
2528                                                 channels = 2;
2529                                                 break;
2530                                 }
2531                                 i810_set_dac_channels ( state, channels );
2532
2533                                 /* check that they really got turned on */
2534                                 if (!(state->card->ac97_status & SURR_ON))
2535                                         val &= ~DSP_BIND_SURR;
2536                                 if (!(state->card->ac97_status & CENTER_LFE_ON))
2537                                         val &= ~DSP_BIND_CENTER_LFE;
2538                         }
2539                 }
2540                 return put_user(val, p);
2541
2542         case SNDCTL_DSP_MAPINBUF:
2543         case SNDCTL_DSP_MAPOUTBUF:
2544         case SNDCTL_DSP_SETSYNCRO:
2545         case SOUND_PCM_WRITE_FILTER:
2546         case SOUND_PCM_READ_FILTER:
2547 #ifdef DEBUG
2548                 printk("SNDCTL_* -EINVAL\n");
2549 #endif
2550                 return -EINVAL;
2551         }
2552         return -EINVAL;
2553 }
2554
2555 static int i810_open(struct inode *inode, struct file *file)
2556 {
2557         int i = 0;
2558         struct i810_card *card = devs;
2559         struct i810_state *state = NULL;
2560         struct dmabuf *dmabuf = NULL;
2561
2562         /* find an avaiable virtual channel (instance of /dev/dsp) */
2563         while (card != NULL) {
2564                 /*
2565                  * If we are initializing and then fail, card could go
2566                  * away unuexpectedly while we are in the for() loop.
2567                  * So, check for card on each iteration before we check
2568                  * for card->initializing to avoid a possible oops.
2569                  * This usually only matters for times when the driver is
2570                  * autoloaded by kmod.
2571                  */
2572                 for (i = 0; i < 50 && card && card->initializing; i++) {
2573                         set_current_state(TASK_UNINTERRUPTIBLE);
2574                         schedule_timeout(HZ/20);
2575                 }
2576                 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) {
2577                         if (card->states[i] == NULL) {
2578                                 state = card->states[i] = (struct i810_state *)
2579                                         kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2580                                 if (state == NULL)
2581                                         return -ENOMEM;
2582                                 memset(state, 0, sizeof(struct i810_state));
2583                                 dmabuf = &state->dmabuf;
2584                                 goto found_virt;
2585                         }
2586                 }
2587                 card = card->next;
2588         }
2589         /* no more virtual channel avaiable */
2590         if (!state)
2591                 return -ENODEV;
2592
2593 found_virt:
2594         /* initialize the virtual channel */
2595         state->virt = i;
2596         state->card = card;
2597         state->magic = I810_STATE_MAGIC;
2598         init_waitqueue_head(&dmabuf->wait);
2599         init_MUTEX(&state->open_sem);
2600         file->private_data = state;
2601         dmabuf->trigger = 0;
2602
2603         /* allocate hardware channels */
2604         if(file->f_mode & FMODE_READ) {
2605                 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2606                         kfree (card->states[i]);
2607                         card->states[i] = NULL;
2608                         return -EBUSY;
2609                 }
2610                 dmabuf->trigger |= PCM_ENABLE_INPUT;
2611                 i810_set_adc_rate(state, 8000);
2612         }
2613         if(file->f_mode & FMODE_WRITE) {
2614                 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2615                         /* make sure we free the record channel allocated above */
2616                         if(file->f_mode & FMODE_READ)
2617                                 card->free_pcm_channel(card,dmabuf->read_channel->num);
2618                         kfree (card->states[i]);
2619                         card->states[i] = NULL;
2620                         return -EBUSY;
2621                 }
2622                 /* Initialize to 8kHz?  What if we don't support 8kHz? */
2623                 /*  Let's change this to check for S/PDIF stuff */
2624
2625                 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2626                 if ( spdif_locked ) {
2627                         i810_set_dac_rate(state, spdif_locked);
2628                         i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2629                 } else {
2630                         i810_set_dac_rate(state, 8000);
2631                         /* Put the ACLink in 2 channel mode by default */
2632                         i = I810_IOREADL(card, GLOB_CNT);
2633                         I810_IOWRITEL(i & 0xffcfffff, card, GLOB_CNT);
2634                 }
2635         }
2636
2637         /* set default sample format. According to OSS Programmer's Guide  /dev/dsp
2638            should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2639            /dev/dspW will accept 16-bits sample, but we don't support those so we
2640            set it immediately to stereo and 16bit, which is all we do support */
2641         dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2642         dmabuf->ossfragsize = 0;
2643         dmabuf->ossmaxfrags  = 0;
2644         dmabuf->subdivision  = 0;
2645
2646         state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2647
2648         return nonseekable_open(inode, file);
2649 }
2650
2651 static int i810_release(struct inode *inode, struct file *file)
2652 {
2653         struct i810_state *state = (struct i810_state *)file->private_data;
2654         struct i810_card *card = state->card;
2655         struct dmabuf *dmabuf = &state->dmabuf;
2656         unsigned long flags;
2657
2658         lock_kernel();
2659
2660         /* stop DMA state machine and free DMA buffers/channels */
2661         if(dmabuf->trigger & PCM_ENABLE_OUTPUT) {
2662                 drain_dac(state, 0);
2663         }
2664         if(dmabuf->trigger & PCM_ENABLE_INPUT) {
2665                 stop_adc(state);
2666         }
2667         spin_lock_irqsave(&card->lock, flags);
2668         dealloc_dmabuf(state);
2669         if (file->f_mode & FMODE_WRITE) {
2670                 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2671         }
2672         if (file->f_mode & FMODE_READ) {
2673                 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2674         }
2675
2676         state->card->states[state->virt] = NULL;
2677         kfree(state);
2678         spin_unlock_irqrestore(&card->lock, flags);
2679         unlock_kernel();
2680
2681         return 0;
2682 }
2683
2684 static /*const*/ struct file_operations i810_audio_fops = {
2685         .owner          = THIS_MODULE,
2686         .llseek         = no_llseek,
2687         .read           = i810_read,
2688         .write          = i810_write,
2689         .poll           = i810_poll,
2690         .ioctl          = i810_ioctl,
2691         .mmap           = i810_mmap,
2692         .open           = i810_open,
2693         .release        = i810_release,
2694 };
2695
2696 /* Write AC97 codec registers */
2697
2698 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg)
2699 {
2700         struct i810_card *card = dev->private_data;
2701         int count = 100;
2702         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2703
2704         while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2705                 udelay(1);
2706
2707 #ifdef DEBUG_MMIO
2708         {
2709                 u16 ans = readw(card->ac97base_mmio + reg_set);
2710                 printk(KERN_DEBUG "i810_audio: ac97_get_mmio(%d) -> 0x%04X\n", ((int) reg_set) & 0xffff, (u32) ans);
2711                 return ans;
2712         }
2713 #else
2714         return readw(card->ac97base_mmio + reg_set);
2715 #endif
2716 }
2717
2718 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg)
2719 {
2720         struct i810_card *card = dev->private_data;
2721         int count = 100;
2722         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2723
2724         while(count-- && (I810_IOREADB(card, CAS) & 1))
2725                 udelay(1);
2726
2727         return inw(card->ac97base + reg_set);
2728 }
2729
2730 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data)
2731 {
2732         struct i810_card *card = dev->private_data;
2733         int count = 100;
2734         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2735
2736         while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2737                 udelay(1);
2738
2739         writew(data, card->ac97base_mmio + reg_set);
2740
2741 #ifdef DEBUG_MMIO
2742         printk(KERN_DEBUG "i810_audio: ac97_set_mmio(0x%04X, %d)\n", (u32) data, ((int) reg_set) & 0xffff);
2743 #endif
2744 }
2745
2746 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data)
2747 {
2748         struct i810_card *card = dev->private_data;
2749         int count = 100;
2750         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2751
2752         while(count-- && (I810_IOREADB(card, CAS) & 1))
2753                 udelay(1);
2754
2755         outw(data, card->ac97base + reg_set);
2756 }
2757
2758 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2759 {
2760         struct i810_card *card = dev->private_data;
2761         u16 ret;
2762
2763         spin_lock(&card->ac97_lock);
2764         if (card->use_mmio) {
2765                 ret = i810_ac97_get_mmio(dev, reg);
2766         }
2767         else {
2768                 ret = i810_ac97_get_io(dev, reg);
2769         }
2770         spin_unlock(&card->ac97_lock);
2771
2772         return ret;
2773 }
2774
2775 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2776 {
2777         struct i810_card *card = dev->private_data;
2778
2779         spin_lock(&card->ac97_lock);
2780         if (card->use_mmio) {
2781                 i810_ac97_set_mmio(dev, reg, data);
2782         }
2783         else {
2784                 i810_ac97_set_io(dev, reg, data);
2785         }
2786         spin_unlock(&card->ac97_lock);
2787 }
2788
2789
2790 /* OSS /dev/mixer file operation methods */
2791
2792 static int i810_open_mixdev(struct inode *inode, struct file *file)
2793 {
2794         int i;
2795         int minor = iminor(inode);
2796         struct i810_card *card = devs;
2797
2798         for (card = devs; card != NULL; card = card->next) {
2799                 /*
2800                  * If we are initializing and then fail, card could go
2801                  * away unuexpectedly while we are in the for() loop.
2802                  * So, check for card on each iteration before we check
2803                  * for card->initializing to avoid a possible oops.
2804                  * This usually only matters for times when the driver is
2805                  * autoloaded by kmod.
2806                  */
2807                 for (i = 0; i < 50 && card && card->initializing; i++) {
2808                         set_current_state(TASK_UNINTERRUPTIBLE);
2809                         schedule_timeout(HZ/20);
2810                 }
2811                 for (i = 0; i < NR_AC97 && card && !card->initializing; i++)
2812                         if (card->ac97_codec[i] != NULL &&
2813                             card->ac97_codec[i]->dev_mixer == minor) {
2814                                 file->private_data = card->ac97_codec[i];
2815                                 return nonseekable_open(inode, file);
2816                         }
2817         }
2818         return -ENODEV;
2819 }
2820
2821 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2822                                 unsigned long arg)
2823 {
2824         struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2825
2826         return codec->mixer_ioctl(codec, cmd, arg);
2827 }
2828
2829 static /*const*/ struct file_operations i810_mixer_fops = {
2830         .owner          = THIS_MODULE,
2831         .llseek         = no_llseek,
2832         .ioctl          = i810_ioctl_mixdev,
2833         .open           = i810_open_mixdev,
2834 };
2835
2836 /* AC97 codec initialisation.  These small functions exist so we don't
2837    duplicate code between module init and apm resume */
2838
2839 static inline int i810_ac97_exists(struct i810_card *card, int ac97_number)
2840 {
2841         u32 reg = I810_IOREADL(card, GLOB_STA);
2842         switch (ac97_number) {
2843         case 0:
2844                 return reg & (1<<8);
2845         case 1:
2846                 return reg & (1<<9);
2847         case 2:
2848                 return reg & (1<<28);
2849         }
2850         return 0;
2851 }
2852
2853 static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
2854 {
2855         i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2856         i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2857                       i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2858
2859         return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
2860 }
2861
2862
2863 static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
2864 {
2865         /* Returns 0 on failure */
2866         int i;
2867
2868         if (ac97_probe_codec(codec) == 0) return 0;
2869
2870         /* power it all up */
2871         i810_ac97_set(codec, AC97_POWER_CONTROL,
2872                       i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2873
2874         /* wait for analog ready */
2875         for (i=100; i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); i--)
2876         {
2877                 set_current_state(TASK_UNINTERRUPTIBLE);
2878                 schedule_timeout(HZ/20);
2879         }
2880         return i;
2881 }
2882
2883 static int is_new_ich(u16 pci_id)
2884 {
2885         switch (pci_id) {
2886         case PCI_DEVICE_ID_INTEL_82801DB_5:
2887         case PCI_DEVICE_ID_INTEL_82801EB_5:
2888         case PCI_DEVICE_ID_INTEL_ESB_5:
2889         case PCI_DEVICE_ID_INTEL_ICH6_18:
2890                 return 1;
2891         default:
2892                 break;
2893         }
2894
2895         return 0;
2896 }
2897
2898 static inline int ich_use_mmio(struct i810_card *card)
2899 {
2900         return is_new_ich(card->pci_id) && card->use_mmio;
2901 }
2902
2903 /**
2904  *      i810_ac97_power_up_bus  -       bring up AC97 link
2905  *      @card : ICH audio device to power up
2906  *
2907  *      Bring up the ACLink AC97 codec bus
2908  */
2909
2910 static int i810_ac97_power_up_bus(struct i810_card *card)
2911 {
2912         u32 reg = I810_IOREADL(card, GLOB_CNT);
2913         int i;
2914         int primary_codec_id = 0;
2915
2916         if((reg&2)==0)  /* Cold required */
2917                 reg|=2;
2918         else
2919                 reg|=4; /* Warm */
2920
2921         reg&=~8;        /* ACLink on */
2922
2923         /* At this point we deassert AC_RESET # */
2924         I810_IOWRITEL(reg , card, GLOB_CNT);
2925
2926         /* We must now allow time for the Codec initialisation.
2927            600mS is the specified time */
2928
2929         for(i=0;i<10;i++)
2930         {
2931                 if((I810_IOREADL(card, GLOB_CNT)&4)==0)
2932                         break;
2933
2934                 set_current_state(TASK_UNINTERRUPTIBLE);
2935                 schedule_timeout(HZ/20);
2936         }
2937         if(i==10)
2938         {
2939                 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2940                 return 0;
2941         }
2942
2943         set_current_state(TASK_UNINTERRUPTIBLE);
2944         schedule_timeout(HZ/2);
2945
2946         /*
2947          *      See if the primary codec comes ready. This must happen
2948          *      before we start doing DMA stuff
2949          */
2950         /* see i810_ac97_init for the next 10 lines (jsaw) */
2951         if (card->use_mmio)
2952                 readw(card->ac97base_mmio);
2953         else
2954                 inw(card->ac97base);
2955         if (ich_use_mmio(card)) {
2956                 primary_codec_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2957                 printk(KERN_INFO "i810_audio: Primary codec has ID %d\n",
2958                        primary_codec_id);
2959         }
2960
2961         if(! i810_ac97_exists(card, primary_codec_id))
2962         {
2963                 printk(KERN_INFO "i810_audio: Codec not ready.. wait.. ");
2964                 set_current_state(TASK_UNINTERRUPTIBLE);
2965                 schedule_timeout(HZ);   /* actually 600mS by the spec */
2966
2967                 if(i810_ac97_exists(card, primary_codec_id))
2968                         printk("OK\n");
2969                 else
2970                         printk("no response.\n");
2971         }
2972         if (card->use_mmio)
2973                 readw(card->ac97base_mmio);
2974         else
2975                 inw(card->ac97base);
2976         return 1;
2977 }
2978
2979 static int __devinit i810_ac97_init(struct i810_card *card)
2980 {
2981         int num_ac97 = 0;
2982         int ac97_id;
2983         int total_channels = 0;
2984         int nr_ac97_max = card_cap[card->pci_id_internal].nr_ac97;
2985         struct ac97_codec *codec;
2986         u16 eid;
2987         u32 reg;
2988
2989         if(!i810_ac97_power_up_bus(card)) return 0;
2990
2991         /* Number of channels supported */
2992         /* What about the codec?  Just because the ICH supports */
2993         /* multiple channels doesn't mean the codec does.       */
2994         /* we'll have to modify this in the codec section below */
2995         /* to reflect what the codec has.                       */
2996         /* ICH and ICH0 only support 2 channels so don't bother */
2997         /* to check....                                         */
2998
2999         card->channels = 2;
3000         reg = I810_IOREADL(card, GLOB_STA);
3001         if ( reg & 0x0200000 )
3002                 card->channels = 6;
3003         else if ( reg & 0x0100000 )
3004                 card->channels = 4;
3005         printk(KERN_INFO "i810_audio: Audio Controller supports %d channels.\n", card->channels);
3006         printk(KERN_INFO "i810_audio: Defaulting to base 2 channel mode.\n");
3007         reg = I810_IOREADL(card, GLOB_CNT);
3008         I810_IOWRITEL(reg & 0xffcfffff, card, GLOB_CNT);
3009
3010         for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++)
3011                 card->ac97_codec[num_ac97] = NULL;
3012
3013         /*@FIXME I don't know, if I'm playing to safe here... (jsaw) */
3014         if ((nr_ac97_max > 2) && !card->use_mmio) nr_ac97_max = 2;
3015
3016         for (num_ac97 = 0; num_ac97 < nr_ac97_max; num_ac97++) {
3017                 /* codec reset */
3018                 printk(KERN_INFO "i810_audio: Resetting connection %d\n", num_ac97);
3019                 if (card->use_mmio)
3020                         readw(card->ac97base_mmio + 0x80*num_ac97);
3021                 else
3022                         inw(card->ac97base + 0x80*num_ac97);
3023
3024                 /* If we have the SDATA_IN Map Register, as on ICH4, we
3025                    do not loop thru all possible codec IDs but thru all
3026                    possible IO channels. Bit 0:1 of SDM then holds the
3027                    last codec ID spoken to.
3028                 */
3029                 if (ich_use_mmio(card)) {
3030                         ac97_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
3031                         printk(KERN_INFO "i810_audio: Connection %d with codec id %d\n",
3032                                num_ac97, ac97_id);
3033                 }
3034                 else {
3035                         ac97_id = num_ac97;
3036                 }
3037
3038                 /* The ICH programmer's reference says you should   */
3039                 /* check the ready status before probing. So we chk */
3040                 /*   What do we do if it's not ready?  Wait and try */
3041                 /*   again, or abort?                               */
3042                 if (!i810_ac97_exists(card, ac97_id)) {
3043                         if(num_ac97 == 0)
3044                                 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
3045                 }
3046
3047                 if ((codec = ac97_alloc_codec()) == NULL)
3048                         return -ENOMEM;
3049
3050                 /* initialize some basic codec information, other fields will be filled
3051                    in ac97_probe_codec */
3052                 codec->private_data = card;
3053                 codec->id = ac97_id;
3054                 card->ac97_id_map[ac97_id] = num_ac97 * 0x80;
3055
3056                 if (card->use_mmio) {
3057                         codec->codec_read = i810_ac97_get_mmio;
3058                         codec->codec_write = i810_ac97_set_mmio;
3059                 }
3060                 else {
3061                         codec->codec_read = i810_ac97_get_io;
3062                         codec->codec_write = i810_ac97_set_io;
3063                 }
3064
3065                 if(!i810_ac97_probe_and_powerup(card,codec)) {
3066                         printk(KERN_ERR "i810_audio: timed out waiting for codec %d analog ready.\n", ac97_id);
3067                         ac97_release_codec(codec);
3068                         break;  /* it didn't work */
3069                 }
3070                 /* Store state information about S/PDIF transmitter */
3071                 card->ac97_status = 0;
3072
3073                 /* Don't attempt to get eid until powerup is complete */
3074                 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
3075
3076                 if(eid==0xFFFF)
3077                 {
3078                         printk(KERN_WARNING "i810_audio: no codec attached ?\n");
3079                         ac97_release_codec(codec);
3080                         break;
3081                 }
3082
3083                 /* Check for an AC97 1.0 soft modem (ID1) */
3084
3085                 if(codec->modem)
3086                 {
3087                         printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", ac97_id);
3088                         ac97_release_codec(codec);
3089                         continue;
3090                 }
3091
3092                 card->ac97_features = eid;
3093
3094                 /* Now check the codec for useful features to make up for
3095                    the dumbness of the 810 hardware engine */
3096
3097                 if(!(eid&0x0001))
3098                         printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
3099                 else
3100                 {
3101                         if(!i810_ac97_enable_variable_rate(codec)) {
3102                                 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
3103                                 card->ac97_features&=~1;
3104                         }
3105                 }
3106
3107                 /* Turn on the amplifier */
3108
3109                 codec->codec_write(codec, AC97_POWER_CONTROL,
3110                          codec->codec_read(codec, AC97_POWER_CONTROL) & ~0x8000);
3111
3112                 /* Determine how many channels the codec(s) support   */
3113                 /*   - The primary codec always supports 2            */
3114                 /*   - If the codec supports AMAP, surround DACs will */
3115                 /*     automaticlly get assigned to slots.            */
3116                 /*     * Check for surround DACs and increment if     */
3117                 /*       found.                                       */
3118                 /*   - Else check if the codec is revision 2.2        */
3119                 /*     * If surround DACs exist, assign them to slots */
3120                 /*       and increment channel count.                 */
3121
3122                 /* All of this only applies to ICH2 and above. ICH    */
3123                 /* and ICH0 only support 2 channels.  ICH2 will only  */
3124                 /* support multiple codecs in a "split audio" config. */
3125                 /* as described above.                                */
3126
3127                 /* TODO: Remove all the debugging messages!           */
3128
3129                 if((eid & 0xc000) == 0) /* primary codec */
3130                         total_channels += 2;
3131
3132                 if(eid & 0x200) { /* GOOD, AMAP support */
3133                         if (eid & 0x0080) /* L/R Surround channels */
3134                                 total_channels += 2;
3135                         if (eid & 0x0140) /* LFE and Center channels */
3136                                 total_channels += 2;
3137                         printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", ac97_id, total_channels);
3138                 } else if (eid & 0x0400) {  /* this only works on 2.2 compliant codecs */
3139                         eid &= 0xffcf;
3140                         if((eid & 0xc000) != 0) {
3141                                 switch ( total_channels ) {
3142                                         case 2:
3143                                                 /* Set dsa1, dsa0 to 01 */
3144                                                 eid |= 0x0010;
3145                                                 break;
3146                                         case 4:
3147                                                 /* Set dsa1, dsa0 to 10 */
3148                                                 eid |= 0x0020;
3149                                                 break;
3150                                         case 6:
3151                                                 /* Set dsa1, dsa0 to 11 */
3152                                                 eid |= 0x0030;
3153                                                 break;
3154                                 }
3155                                 total_channels += 2;
3156                         }
3157                         i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
3158                         eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
3159                         printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", ac97_id, eid);
3160                         if (eid & 0x0080) /* L/R Surround channels */
3161                                 total_channels += 2;
3162                         if (eid & 0x0140) /* LFE and Center channels */
3163                                 total_channels += 2;
3164                         printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", ac97_id, total_channels);
3165                 } else {
3166                         printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", ac97_id, total_channels);
3167                 }
3168
3169                 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
3170                         printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
3171                         ac97_release_codec(codec);
3172                         break;
3173                 }
3174
3175                 card->ac97_codec[num_ac97] = codec;
3176         }
3177
3178         /* tune up the primary codec */
3179         ac97_tune_hardware(card->pci_dev, ac97_quirks, ac97_quirk);
3180
3181         /* pick the minimum of channels supported by ICHx or codec(s) */
3182         card->channels = (card->channels > total_channels)?total_channels:card->channels;
3183
3184         return num_ac97;
3185 }
3186
3187 static void __devinit i810_configure_clocking (void)
3188 {
3189         struct i810_card *card;
3190         struct i810_state *state;
3191         struct dmabuf *dmabuf;
3192         unsigned int i, offset, new_offset;
3193         unsigned long flags;
3194
3195         card = devs;
3196         /* We could try to set the clocking for multiple cards, but can you even have
3197          * more than one i810 in a machine?  Besides, clocking is global, so unless
3198          * someone actually thinks more than one i810 in a machine is possible and
3199          * decides to rewrite that little bit, setting the rate for more than one card
3200          * is a waste of time.
3201          */
3202         if(card != NULL) {
3203                 state = card->states[0] = (struct i810_state *)
3204                                         kmalloc(sizeof(struct i810_state), GFP_KERNEL);
3205                 if (state == NULL)
3206                         return;
3207                 memset(state, 0, sizeof(struct i810_state));
3208                 dmabuf = &state->dmabuf;
3209
3210                 dmabuf->write_channel = card->alloc_pcm_channel(card);
3211                 state->virt = 0;
3212                 state->card = card;
3213                 state->magic = I810_STATE_MAGIC;
3214                 init_waitqueue_head(&dmabuf->wait);
3215                 init_MUTEX(&state->open_sem);
3216                 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
3217                 dmabuf->trigger = PCM_ENABLE_OUTPUT;
3218                 i810_set_spdif_output(state, -1, 0);
3219                 i810_set_dac_channels(state, 2);
3220                 i810_set_dac_rate(state, 48000);
3221                 if(prog_dmabuf(state, 0) != 0) {
3222                         goto config_out_nodmabuf;
3223                 }
3224                 if(dmabuf->dmasize < 16384) {
3225                         goto config_out;
3226                 }
3227                 dmabuf->count = dmabuf->dmasize;
3228                 CIV_TO_LVI(card, dmabuf->write_channel->port, -1);
3229                 local_irq_save(flags);
3230                 start_dac(state);
3231                 offset = i810_get_dma_addr(state, 0);
3232                 mdelay(50);
3233                 new_offset = i810_get_dma_addr(state, 0);
3234                 stop_dac(state);
3235                 local_irq_restore(flags);
3236                 i = new_offset - offset;
3237 #ifdef DEBUG_INTERRUPTS
3238                 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
3239 #endif
3240                 if(i == 0)
3241                         goto config_out;
3242                 i = i / 4 * 20;
3243                 if (i > 48500 || i < 47500) {
3244                         clocking = clocking * clocking / i;
3245                         printk("i810_audio: setting clocking to %d\n", clocking);
3246                 }
3247 config_out:
3248                 dealloc_dmabuf(state);
3249 config_out_nodmabuf:
3250                 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
3251                 kfree(state);
3252                 card->states[0] = NULL;
3253         }
3254 }
3255
3256 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
3257    until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
3258
3259 static int __devinit i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
3260 {
3261         struct i810_card *card;
3262
3263         if (pci_enable_device(pci_dev))
3264                 return -EIO;
3265
3266         if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
3267                 printk(KERN_ERR "i810_audio: architecture does not support"
3268                        " 32bit PCI busmaster DMA\n");
3269                 return -ENODEV;
3270         }
3271
3272         if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
3273                 printk(KERN_ERR "i810_audio: out of memory\n");
3274                 return -ENOMEM;
3275         }
3276         memset(card, 0, sizeof(*card));
3277
3278         card->initializing = 1;
3279         card->pci_dev = pci_dev;
3280         card->pci_id = pci_id->device;
3281         card->ac97base = pci_resource_start (pci_dev, 0);
3282         card->iobase = pci_resource_start (pci_dev, 1);
3283
3284         if (!(card->ac97base) || !(card->iobase)) {
3285                 card->ac97base = 0;
3286                 card->iobase = 0;
3287         }
3288
3289         /* if chipset could have mmio capability, check it */
3290         if (card_cap[pci_id->driver_data].flags & CAP_MMIO) {
3291                 card->ac97base_mmio_phys = pci_resource_start (pci_dev, 2);
3292                 card->iobase_mmio_phys = pci_resource_start (pci_dev, 3);
3293
3294                 if ((card->ac97base_mmio_phys) && (card->iobase_mmio_phys)) {
3295                         card->use_mmio = 1;
3296                 }
3297                 else {
3298                         card->ac97base_mmio_phys = 0;
3299                         card->iobase_mmio_phys = 0;
3300                 }
3301         }
3302
3303         if (!(card->use_mmio) && (!(card->iobase) || !(card->ac97base))) {
3304                 printk(KERN_ERR "i810_audio: No I/O resources available.\n");
3305                 goto out_mem;
3306         }
3307
3308         card->irq = pci_dev->irq;
3309         card->next = devs;
3310         card->magic = I810_CARD_MAGIC;
3311 #ifdef CONFIG_PM
3312         card->pm_suspended=0;
3313 #endif
3314         spin_lock_init(&card->lock);
3315         spin_lock_init(&card->ac97_lock);
3316         devs = card;
3317
3318         pci_set_master(pci_dev);
3319
3320         printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, "
3321                "MEM 0x%04lx and 0x%04lx, IRQ %d\n",
3322                card_names[pci_id->driver_data],
3323                card->iobase, card->ac97base,
3324                card->ac97base_mmio_phys, card->iobase_mmio_phys,
3325                card->irq);
3326
3327         card->alloc_pcm_channel = i810_alloc_pcm_channel;
3328         card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
3329         card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
3330         card->free_pcm_channel = i810_free_pcm_channel;
3331
3332         if ((card->channel = pci_alloc_consistent(pci_dev,
3333             sizeof(struct i810_channel)*NR_HW_CH, &card->chandma)) == NULL) {
3334                 printk(KERN_ERR "i810: cannot allocate channel DMA memory\n");
3335                 goto out_mem;
3336         }
3337
3338         { /* We may dispose of this altogether some time soon, so... */
3339                 struct i810_channel *cp = card->channel;
3340
3341                 cp[0].offset = 0;
3342                 cp[0].port = 0x00;
3343                 cp[0].num = 0;
3344                 cp[1].offset = 0;
3345                 cp[1].port = 0x10;
3346                 cp[1].num = 1;
3347                 cp[2].offset = 0;
3348                 cp[2].port = 0x20;
3349                 cp[2].num = 2;
3350         }
3351
3352         /* claim our iospace and irq */
3353         if (!request_region(card->iobase, 64, card_names[pci_id->driver_data])) {
3354                 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->iobase);
3355                 goto out_region1;
3356         }
3357         if (!request_region(card->ac97base, 256, card_names[pci_id->driver_data])) {
3358                 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->ac97base);
3359                 goto out_region2;
3360         }
3361
3362         if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
3363                         card_names[pci_id->driver_data], card)) {
3364                 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
3365                 goto out_pio;
3366         }
3367
3368         if (card->use_mmio) {
3369                 if (request_mem_region(card->ac97base_mmio_phys, 512, "ich_audio MMBAR")) {
3370                         if ((card->ac97base_mmio = ioremap(card->ac97base_mmio_phys, 512))) { /*@FIXME can ioremap fail? don't know (jsaw) */
3371                                 if (request_mem_region(card->iobase_mmio_phys, 256, "ich_audio MBBAR")) {
3372                                         if ((card->iobase_mmio = ioremap(card->iobase_mmio_phys, 256))) {
3373                                                 printk(KERN_INFO "i810: %s mmio at 0x%04lx and 0x%04lx\n",
3374                                                        card_names[pci_id->driver_data],
3375                                                        (unsigned long) card->ac97base_mmio,
3376                                                        (unsigned long) card->iobase_mmio);
3377                                         }
3378                                         else {
3379                                                 iounmap(card->ac97base_mmio);
3380                                                 release_mem_region(card->ac97base_mmio_phys, 512);
3381                                                 release_mem_region(card->iobase_mmio_phys, 512);
3382                                                 card->use_mmio = 0;
3383                                         }
3384                                 }
3385                                 else {
3386                                         iounmap(card->ac97base_mmio);
3387                                         release_mem_region(card->ac97base_mmio_phys, 512);
3388                                         card->use_mmio = 0;
3389                                 }
3390                         }
3391                 }
3392                 else {
3393                         card->use_mmio = 0;
3394                 }
3395         }
3396
3397         /* initialize AC97 codec and register /dev/mixer */
3398         if (i810_ac97_init(card) <= 0) {
3399                 free_irq(card->irq, card);
3400                 goto out_iospace;
3401         }
3402         pci_set_drvdata(pci_dev, card);
3403
3404         if(clocking == 0) {
3405                 clocking = 48000;
3406                 i810_configure_clocking();
3407         }
3408
3409         /* register /dev/dsp */
3410         if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
3411                 int i;
3412                 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
3413                 free_irq(card->irq, card);
3414                 for (i = 0; i < NR_AC97; i++)
3415                 if (card->ac97_codec[i] != NULL) {
3416                         unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3417                         ac97_release_codec(card->ac97_codec[i]);
3418                 }
3419                 goto out_iospace;
3420         }
3421
3422         card->initializing = 0;
3423         return 0;
3424
3425 out_iospace:
3426         if (card->use_mmio) {
3427                 iounmap(card->ac97base_mmio);
3428                 iounmap(card->iobase_mmio);
3429                 release_mem_region(card->ac97base_mmio_phys, 512);
3430                 release_mem_region(card->iobase_mmio_phys, 256);
3431         }
3432 out_pio:
3433         release_region(card->iobase, 64);
3434 out_region2:
3435         release_region(card->ac97base, 256);
3436 out_region1:
3437         pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3438             card->channel, card->chandma);
3439 out_mem:
3440         kfree(card);
3441         return -ENODEV;
3442 }
3443
3444 static void __devexit i810_remove(struct pci_dev *pci_dev)
3445 {
3446         int i;
3447         struct i810_card *card = pci_get_drvdata(pci_dev);
3448         /* free hardware resources */
3449         free_irq(card->irq, devs);
3450         release_region(card->iobase, 64);
3451         release_region(card->ac97base, 256);
3452         pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3453                             card->channel, card->chandma);
3454         if (card->use_mmio) {
3455                 iounmap(card->ac97base_mmio);
3456                 iounmap(card->iobase_mmio);
3457                 release_mem_region(card->ac97base_mmio_phys, 512);
3458                 release_mem_region(card->iobase_mmio_phys, 256);
3459         }
3460
3461         /* unregister audio devices */
3462         for (i = 0; i < NR_AC97; i++)
3463                 if (card->ac97_codec[i] != NULL) {
3464                         unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3465                         ac97_release_codec(card->ac97_codec[i]);
3466                         card->ac97_codec[i] = NULL;
3467                 }
3468         unregister_sound_dsp(card->dev_audio);
3469         kfree(card);
3470 }
3471
3472 #ifdef CONFIG_PM
3473 static int i810_pm_suspend(struct pci_dev *dev, pm_message_t pm_state)
3474 {
3475         struct i810_card *card = pci_get_drvdata(dev);
3476         struct i810_state *state;
3477         unsigned long flags;
3478         struct dmabuf *dmabuf;
3479         int i,num_ac97;
3480 #ifdef DEBUG
3481         printk("i810_audio: i810_pm_suspend called\n");
3482 #endif
3483         if(!card) return 0;
3484         spin_lock_irqsave(&card->lock, flags);
3485         card->pm_suspended=1;
3486         for(i=0;i<NR_HW_CH;i++) {
3487                 state = card->states[i];
3488                 if(!state) continue;
3489                 /* this happens only if there are open files */
3490                 dmabuf = &state->dmabuf;
3491                 if(dmabuf->enable & DAC_RUNNING ||
3492                    (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
3493                         state->pm_saved_dac_rate=dmabuf->rate;
3494                         stop_dac(state);
3495                 } else {
3496                         state->pm_saved_dac_rate=0;
3497                 }
3498                 if(dmabuf->enable & ADC_RUNNING) {
3499                         state->pm_saved_adc_rate=dmabuf->rate;
3500                         stop_adc(state);
3501                 } else {
3502                         state->pm_saved_adc_rate=0;
3503                 }
3504                 dmabuf->ready = 0;
3505                 dmabuf->swptr = dmabuf->hwptr = 0;
3506                 dmabuf->count = dmabuf->total_bytes = 0;
3507         }
3508
3509         spin_unlock_irqrestore(&card->lock, flags);
3510
3511         /* save mixer settings */
3512         for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3513                 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3514                 if(!codec) continue;
3515                 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3516                         if((supported_mixer(codec,i)) &&
3517                            (codec->read_mixer)) {
3518                                 card->pm_saved_mixer_settings[i][num_ac97]=
3519                                         codec->read_mixer(codec,i);
3520                         }
3521                 }
3522         }
3523         pci_save_state(dev); /* XXX do we need this? */
3524         pci_disable_device(dev); /* disable busmastering */
3525         pci_set_power_state(dev,3); /* Zzz. */
3526
3527         return 0;
3528 }
3529
3530
3531 static int i810_pm_resume(struct pci_dev *dev)
3532 {
3533         int num_ac97,i=0;
3534         struct i810_card *card=pci_get_drvdata(dev);
3535         pci_enable_device(dev);
3536         pci_restore_state (dev);
3537
3538         /* observation of a toshiba portege 3440ct suggests that the
3539            hardware has to be more or less completely reinitialized from
3540            scratch after an apm suspend.  Works For Me.   -dan */
3541
3542         i810_ac97_power_up_bus(card);
3543
3544         for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3545                 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3546                 /* check they haven't stolen the hardware while we were
3547                    away */
3548                 if(!codec || !i810_ac97_exists(card,num_ac97)) {
3549                         if(num_ac97) continue;
3550                         else BUG();
3551                 }
3552                 if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
3553
3554                 if((card->ac97_features&0x0001)) {
3555                         /* at probe time we found we could do variable
3556                            rates, but APM suspend has made it forget
3557                            its magical powers */
3558                         if(!i810_ac97_enable_variable_rate(codec)) BUG();
3559                 }
3560                 /* we lost our mixer settings, so restore them */
3561                 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3562                         if(supported_mixer(codec,i)){
3563                                 int val=card->
3564                                         pm_saved_mixer_settings[i][num_ac97];
3565                                 codec->mixer_state[i]=val;
3566                                 codec->write_mixer(codec,i,
3567                                                    (val  & 0xff) ,
3568                                                    ((val >> 8)  & 0xff) );
3569                         }
3570                 }
3571         }
3572
3573         /* we need to restore the sample rate from whatever it was */
3574         for(i=0;i<NR_HW_CH;i++) {
3575                 struct i810_state * state=card->states[i];
3576                 if(state) {
3577                         if(state->pm_saved_adc_rate)
3578                                 i810_set_adc_rate(state,state->pm_saved_adc_rate);
3579                         if(state->pm_saved_dac_rate)
3580                                 i810_set_dac_rate(state,state->pm_saved_dac_rate);
3581                 }
3582         }
3583
3584
3585         card->pm_suspended = 0;
3586
3587         /* any processes that were reading/writing during the suspend
3588            probably ended up here */
3589         for(i=0;i<NR_HW_CH;i++) {
3590                 struct i810_state *state = card->states[i];
3591                 if(state) wake_up(&state->dmabuf.wait);
3592         }
3593
3594         return 0;
3595 }
3596 #endif /* CONFIG_PM */
3597
3598 MODULE_AUTHOR("The Linux kernel team");
3599 MODULE_DESCRIPTION("Intel 810 audio support");
3600 MODULE_LICENSE("GPL");
3601 module_param(ftsodell, int, 0444);
3602 module_param(clocking, uint, 0444);
3603 module_param(strict_clocking, int, 0444);
3604 module_param(spdif_locked, int, 0444);
3605
3606 #define I810_MODULE_NAME "i810_audio"
3607
3608 static struct pci_driver i810_pci_driver = {
3609         .name           = I810_MODULE_NAME,
3610         .id_table       = i810_pci_tbl,
3611         .probe          = i810_probe,
3612         .remove         = __devexit_p(i810_remove),
3613 #ifdef CONFIG_PM
3614         .suspend        = i810_pm_suspend,
3615         .resume         = i810_pm_resume,
3616 #endif /* CONFIG_PM */
3617 };
3618
3619
3620 static int __init i810_init_module (void)
3621 {
3622         int retval;
3623
3624         printk(KERN_INFO "Intel 810 + AC97 Audio, version "
3625                DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
3626
3627         retval = pci_register_driver(&i810_pci_driver);
3628         if (retval)
3629                 return retval;
3630
3631         if(ftsodell != 0) {
3632                 printk("i810_audio: ftsodell is now a deprecated option.\n");
3633         }
3634         if(spdif_locked > 0 ) {
3635                 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
3636                         printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
3637                 } else {
3638                         printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n");
3639                         spdif_locked = 0;
3640                 }
3641         }
3642
3643         return 0;
3644 }
3645
3646 static void __exit i810_cleanup_module (void)
3647 {
3648         pci_unregister_driver(&i810_pci_driver);
3649 }
3650
3651 module_init(i810_init_module);
3652 module_exit(i810_cleanup_module);
3653
3654 /*
3655 Local Variables:
3656 c-basic-offset: 8
3657 End:
3658 */