sound/oss/cmpci.c

   1 /*
   2  *      cmpci.c  --  C-Media PCI audio driver.
   3  *
   4  *      Copyright (C) 1999  C-media support (support@cmedia.com.tw)
   5  *
   6  *      Based on the PCI drivers by Thomas Sailer (sailer@ife.ee.ethz.ch)
   7  *
   8  *      For update, visit:
   9  *              http://www.cmedia.com.tw
  10  *
  11  *      This program is free software; you can redistribute it and/or modify
  12  *      it under the terms of the GNU General Public License as published by
  13  *      the Free Software Foundation; either version 2 of the License, or
  14  *      (at your option) any later version.
  15  *
  16  *      This program is distributed in the hope that it will be useful,
  17  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *      GNU General Public License for more details.
  20  *
  21  *      You should have received a copy of the GNU General Public License
  22  *      along with this program; if not, write to the Free Software
  23  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  * Special thanks to David C. Niemi, Jan Pfeifer
  26  *
  27  *
  28  * Module command line parameters:
  29  *   none so far
  30  *
  31  *
  32  *  Supported devices:
  33  *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  34  *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  35  *  /dev/midi   simple MIDI UART interface, no ioctl
  36  *
  37  *  The card has both an FM and a Wavetable synth, but I have to figure
  38  *  out first how to drive them...
  39  *
  40  *  Revision history
  41  *    06.05.98   0.1   Initial release
  42  *    10.05.98   0.2   Fixed many bugs, esp. ADC rate calculation
  43  *                     First stab at a simple midi interface (no bells&whistles)
  44  *    13.05.98   0.3   Fix stupid cut&paste error: set_adc_rate was called instead of
  45  *                     set_dac_rate in the FMODE_WRITE case in cm_open
  46  *                     Fix hwptr out of bounds (now mpg123 works)
  47  *    14.05.98   0.4   Don't allow excessive interrupt rates
  48  *    08.06.98   0.5   First release using Alan Cox' soundcore instead of miscdevice
  49  *    03.08.98   0.6   Do not include modversions.h
  50  *                     Now mixer behaviour can basically be selected between
  51  *                     "OSS documented" and "OSS actual" behaviour
  52  *    31.08.98   0.7   Fix realplayer problems - dac.count issues
  53  *    10.12.98   0.8   Fix drain_dac trying to wait on not yet initialized DMA
  54  *    16.12.98   0.9   Fix a few f_file & FMODE_ bugs
  55  *    06.01.99   0.10  remove the silly SA_INTERRUPT flag.
  56  *                     hopefully killed the egcs section type conflict
  57  *    12.03.99   0.11  cinfo.blocks should be reset after GETxPTR ioctl.
  58  *                     reported by Johan Maes <joma@telindus.be>
  59  *    22.03.99   0.12  return EAGAIN instead of EBUSY when O_NONBLOCK
  60  *                     read/write cannot be executed
  61  *    18.08.99   1.5   Only deallocate DMA buffer when unloading.
  62  *    02.09.99   1.6   Enable SPDIF LOOP
  63  *                     Change the mixer read back
  64  *    21.09.99   2.33  Use RCS version as driver version.
  65  *                     Add support for modem, S/PDIF loop and 4 channels.
  66  *                     (8738 only)
  67  *                     Fix bug cause x11amp cannot play.
  68  *
  69  *    Fixes:
  70  *    Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  71  *    18/05/2001 - .bss nitpicks, fix a bug in set_dac_channels where it
  72  *                 was calling prog_dmabuf with s->lock held, call missing
  73  *                 unlock_kernel in cm_midi_release
  74  *    08/10/2001 - use set_current_state in some more places
  75  *
  76  *      Carlos Eduardo Gorges <carlos@techlinux.com.br>
  77  *      Fri May 25 2001
  78  *      - SMP support ( spin[un]lock* revision )
  79  *      - speaker mixer support
  80  *      Mon Aug 13 2001
  81  *      - optimizations and cleanups
  82  *
  83  *    03/01/2003 - open_mode fixes from Georg Acher <acher@in.tum.de>
  84  *      Simon Braunschmidt <brasimon@web.de>
  85  *     Sat Jan 31 2004
  86  *      - provide support for opl3 FM by releasing IO range after initialization
  87  *
  88  *    ChenLi Tien <cltien@cmedia.com.tw>
  89  *    Mar 9 2004
  90  *      - Fix S/PDIF out if spdif_loop enabled
  91  *      - Load opl3 driver if enabled (fmio in proper range)
  92  *      - Load mpu401 if enabled (mpuio in proper range)
  93  *    Apr 5 2004
  94  *      - Fix DUAL_DAC dma synchronization bug
  95  *      - Check exist FM/MPU401 I/O before activate.
  96  *      - Add AFTM_S16_BE format support, so MPlayer/Xine can play AC3/mutlichannel
  97  *        on Mac
  98  *      - Change to support kernel 2.6 so only small patch needed
  99  *      - All parameters default to 0
 100  *      - Add spdif_out to send PCM through S/PDIF out jack
 101  *      - Add hw_copy to get 4-spaker output for general PCM/analog output
 102  *
 103  *    Stefan Thater <stefan.thaeter@gmx.de>
 104  *    Apr 5 2004
 105  *      - Fix mute single channel for CD/Line-in/AUX-in
 106  */
 107 /*****************************************************************************/
 108
 109 #include <linux/config.h>
 110 #include <linux/module.h>
 111 #include <linux/string.h>
 112 #include <linux/interrupt.h>
 113 #include <linux/ioport.h>
 114 #include <linux/sched.h>
 115 #include <linux/delay.h>
 116 #include <linux/sound.h>
 117 #include <linux/slab.h>
 118 #include <linux/soundcard.h>
 119 #include <linux/pci.h>
 120 #include <linux/init.h>
 121 #include <linux/poll.h>
 122 #include <linux/spinlock.h>
 123 #include <linux/smp_lock.h>
 124 #include <linux/bitops.h>
 125 #include <linux/wait.h>
 126 #include <linux/dma-mapping.h>
 127
 128 #include <asm/io.h>
 129 #include <asm/page.h>
 130 #include <asm/uaccess.h>
 131
 132 #ifdef CONFIG_SOUND_CMPCI_MIDI
 133 #include "sound_config.h"
 134 #include "mpu401.h"
 135 #endif
 136 #ifdef CONFIG_SOUND_CMPCI_FM
 137 #include "opl3.h"
 138 #endif
 139 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
 140 #include <linux/gameport.h>
 141 #endif
 142
 143 /* --------------------------------------------------------------------- */
 144 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 145 #undef DMABYTEIO
 146 #define DBG(x) {}
 147 /* --------------------------------------------------------------------- */
 148
 149 #define CM_MAGIC  ((PCI_VENDOR_ID_CMEDIA<<16)|PCI_DEVICE_ID_CMEDIA_CM8338A)
 150
 151 /* CM8338 registers definition ****************/
 152
 153 #define CODEC_CMI_FUNCTRL0              (0x00)
 154 #define CODEC_CMI_FUNCTRL1              (0x04)
 155 #define CODEC_CMI_CHFORMAT              (0x08)
 156 #define CODEC_CMI_INT_HLDCLR            (0x0C)
 157 #define CODEC_CMI_INT_STATUS            (0x10)
 158 #define CODEC_CMI_LEGACY_CTRL           (0x14)
 159 #define CODEC_CMI_MISC_CTRL             (0x18)
 160 #define CODEC_CMI_TDMA_POS              (0x1C)
 161 #define CODEC_CMI_MIXER                 (0x20)
 162 #define CODEC_SB16_DATA                 (0x22)
 163 #define CODEC_SB16_ADDR                 (0x23)
 164 #define CODEC_CMI_MIXER1                (0x24)
 165 #define CODEC_CMI_MIXER2                (0x25)
 166 #define CODEC_CMI_AUX_VOL               (0x26)
 167 #define CODEC_CMI_MISC                  (0x27)
 168 #define CODEC_CMI_AC97                  (0x28)
 169
 170 #define CODEC_CMI_CH0_FRAME1            (0x80)
 171 #define CODEC_CMI_CH0_FRAME2            (0x84)
 172 #define CODEC_CMI_CH1_FRAME1            (0x88)
 173 #define CODEC_CMI_CH1_FRAME2            (0x8C)
 174
 175 #define CODEC_CMI_SPDIF_CTRL            (0x90)
 176 #define CODEC_CMI_MISC_CTRL2            (0x92)
 177
 178 #define CODEC_CMI_EXT_REG               (0xF0)
 179
 180 /*  Mixer registers for SB16 ******************/
 181
 182 #define DSP_MIX_DATARESETIDX            ((unsigned char)(0x00))
 183
 184 #define DSP_MIX_MASTERVOLIDX_L          ((unsigned char)(0x30))
 185 #define DSP_MIX_MASTERVOLIDX_R          ((unsigned char)(0x31))
 186 #define DSP_MIX_VOICEVOLIDX_L           ((unsigned char)(0x32))
 187 #define DSP_MIX_VOICEVOLIDX_R           ((unsigned char)(0x33))
 188 #define DSP_MIX_FMVOLIDX_L              ((unsigned char)(0x34))
 189 #define DSP_MIX_FMVOLIDX_R              ((unsigned char)(0x35))
 190 #define DSP_MIX_CDVOLIDX_L              ((unsigned char)(0x36))
 191 #define DSP_MIX_CDVOLIDX_R              ((unsigned char)(0x37))
 192 #define DSP_MIX_LINEVOLIDX_L            ((unsigned char)(0x38))
 193 #define DSP_MIX_LINEVOLIDX_R            ((unsigned char)(0x39))
 194
 195 #define DSP_MIX_MICVOLIDX               ((unsigned char)(0x3A))
 196 #define DSP_MIX_SPKRVOLIDX              ((unsigned char)(0x3B))
 197
 198 #define DSP_MIX_OUTMIXIDX               ((unsigned char)(0x3C))
 199
 200 #define DSP_MIX_ADCMIXIDX_L             ((unsigned char)(0x3D))
 201 #define DSP_MIX_ADCMIXIDX_R             ((unsigned char)(0x3E))
 202
 203 #define DSP_MIX_INGAINIDX_L             ((unsigned char)(0x3F))
 204 #define DSP_MIX_INGAINIDX_R             ((unsigned char)(0x40))
 205 #define DSP_MIX_OUTGAINIDX_L            ((unsigned char)(0x41))
 206 #define DSP_MIX_OUTGAINIDX_R            ((unsigned char)(0x42))
 207
 208 #define DSP_MIX_AGCIDX                  ((unsigned char)(0x43))
 209
 210 #define DSP_MIX_TREBLEIDX_L             ((unsigned char)(0x44))
 211 #define DSP_MIX_TREBLEIDX_R             ((unsigned char)(0x45))
 212 #define DSP_MIX_BASSIDX_L               ((unsigned char)(0x46))
 213 #define DSP_MIX_BASSIDX_R               ((unsigned char)(0x47))
 214 #define DSP_MIX_EXTENSION               ((unsigned char)(0xf0))
 215 // pseudo register for AUX
 216 #define DSP_MIX_AUXVOL_L                ((unsigned char)(0x50))
 217 #define DSP_MIX_AUXVOL_R                ((unsigned char)(0x51))
 218
 219 // I/O length
 220 #define CM_EXTENT_CODEC   0x100
 221 #define CM_EXTENT_MIDI    0x2
 222 #define CM_EXTENT_SYNTH   0x4
 223 #define CM_EXTENT_GAME    0x8
 224
 225 // Function Control Register 0 (00h)
 226 #define CHADC0          0x01
 227 #define CHADC1          0x02
 228 #define PAUSE0          0x04
 229 #define PAUSE1          0x08
 230
 231 // Function Control Register 0+2 (02h)
 232 #define CHEN0           0x01
 233 #define CHEN1           0x02
 234 #define RST_CH0         0x04
 235 #define RST_CH1         0x08
 236
 237 // Function Control Register 1 (04h)
 238 #define JYSTK_EN        0x02
 239 #define UART_EN         0x04
 240 #define SPDO2DAC        0x40
 241 #define SPDFLOOP        0x80
 242
 243 // Function Control Register 1+1 (05h)
 244 #define SPDF_0          0x01
 245 #define SPDF_1          0x02
 246 #define ASFC            0x1c
 247 #define DSFC            0xe0
 248 #define SPDIF2DAC       (SPDF_1 << 8 | SPDO2DAC)
 249
 250 // Channel Format Register (08h)
 251 #define CM_CFMT_STEREO  0x01
 252 #define CM_CFMT_16BIT   0x02
 253 #define CM_CFMT_MASK    0x03
 254 #define POLVALID        0x20
 255 #define INVSPDIFI       0x80
 256
 257 // Channel Format Register+2 (0ah)
 258 #define SPD24SEL        0x20
 259
 260 // Channel Format Register+3 (0bh)
 261 #define CHB3D           0x20
 262 #define CHB3D5C         0x80
 263
 264 // Interrupt Hold/Clear Register+2 (0eh)
 265 #define CH0_INT_EN      0x01
 266 #define CH1_INT_EN      0x02
 267
 268 // Interrupt Register (10h)
 269 #define CHINT0          0x01
 270 #define CHINT1          0x02
 271 #define CH0BUSY         0x04
 272 #define CH1BUSY         0x08
 273
 274 // Legacy Control/Status Register+1 (15h)
 275 #define EXBASEN         0x10
 276 #define BASE2LIN        0x20
 277 #define CENTR2LIN       0x40
 278 #define CB2LIN          (BASE2LIN | CENTR2LIN)
 279 #define CHB3D6C         0x80
 280
 281 // Legacy Control/Status Register+2 (16h)
 282 #define DAC2SPDO        0x20
 283 #define SPDCOPYRHT      0x40
 284 #define ENSPDOUT        0x80
 285
 286 // Legacy Control/Status Register+3 (17h)
 287 #define FMSEL           0x03
 288 #define VSBSEL          0x0c
 289 #define VMPU            0x60
 290 #define NXCHG           0x80
 291
 292 // Miscellaneous Control Register (18h)
 293 #define REAR2LIN        0x20
 294 #define MUTECH1         0x40
 295 #define ENCENTER        0x80
 296
 297 // Miscellaneous Control Register+1 (19h)
 298 #define SELSPDIFI2      0x01
 299 #define SPDF_AC97       0x80
 300
 301 // Miscellaneous Control Register+2 (1ah)
 302 #define AC3_EN          0x04
 303 #define FM_EN           0x08
 304 #define SPD32SEL        0x20
 305 #define XCHGDAC         0x40
 306 #define ENDBDAC         0x80
 307
 308 // Miscellaneous Control Register+3 (1bh)
 309 #define SPDIFI48K       0x01
 310 #define SPDO5V          0x02
 311 #define N4SPK3D         0x04
 312 #define RESET           0x40
 313 #define PWD             0x80
 314 #define SPDIF48K        (SPDIFI48K << 24 | SPDF_AC97 << 8)
 315
 316 // Mixer1 (24h)
 317 #define CDPLAY          0x01
 318 #define X3DEN           0x02
 319 #define REAR2FRONT      0x10
 320 #define SPK4            0x20
 321 #define WSMUTE          0x40
 322 #define FMMUTE          0x80
 323
 324 // Miscellaneous Register (27h)
 325 #define SPDVALID        0x02
 326 #define CENTR2MIC       0x04
 327
 328 // Miscellaneous Register2 (92h)
 329 #define SPD32KFMT       0x10
 330
 331 #define CM_CFMT_DACSHIFT   2
 332 #define CM_CFMT_ADCSHIFT   0
 333 #define CM_FREQ_DACSHIFT   5
 334 #define CM_FREQ_ADCSHIFT   2
 335 #define RSTDAC  RST_CH1
 336 #define RSTADC  RST_CH0
 337 #define ENDAC   CHEN1
 338 #define ENADC   CHEN0
 339 #define PAUSEDAC        PAUSE1
 340 #define PAUSEADC        PAUSE0
 341 #define CODEC_CMI_ADC_FRAME1    CODEC_CMI_CH0_FRAME1
 342 #define CODEC_CMI_ADC_FRAME2    CODEC_CMI_CH0_FRAME2
 343 #define CODEC_CMI_DAC_FRAME1    CODEC_CMI_CH1_FRAME1
 344 #define CODEC_CMI_DAC_FRAME2    CODEC_CMI_CH1_FRAME2
 345 #define DACINT  CHINT1
 346 #define ADCINT  CHINT0
 347 #define DACBUSY CH1BUSY
 348 #define ADCBUSY CH0BUSY
 349 #define ENDACINT        CH1_INT_EN
 350 #define ENADCINT        CH0_INT_EN
 351
 352 static const unsigned sample_size[] = { 1, 2, 2, 4 };
 353 static const unsigned sample_shift[]    = { 0, 1, 1, 2 };
 354
 355 #define SND_DEV_DSP16   5
 356
 357 #define NR_DEVICE 3             /* maximum number of devices */
 358
 359 #define set_dac1_rate   set_adc_rate
 360 #define set_dac1_rate_unlocked  set_adc_rate_unlocked
 361 #define stop_dac1       stop_adc
 362 #define stop_dac1_unlocked      stop_adc_unlocked
 363 #define get_dmadac1     get_dmaadc
 364
 365 static unsigned int devindex = 0;
 366
 367 //*********************************************/
 368
 369 struct cm_state {
 370         /* magic */
 371         unsigned int magic;
 372
 373         /* list of cmedia devices */
 374         struct list_head devs;
 375
 376         /* the corresponding pci_dev structure */
 377         struct pci_dev *dev;
 378
 379         int dev_audio;                  /* soundcore stuff */
 380         int dev_mixer;
 381
 382         unsigned int iosb, iobase, iosynth,
 383                          iomidi, iogame, irq;   /* hardware resources */
 384         unsigned short deviceid;                /* pci_id */
 385
 386         struct {                                /* mixer stuff */
 387                 unsigned int modcnt;
 388                 unsigned short vol[13];
 389         } mix;
 390
 391         unsigned int rateadc, ratedac;          /* wave stuff */
 392         unsigned char fmt, enable;
 393
 394         spinlock_t lock;
 395         struct semaphore open_sem;
 396         mode_t open_mode;
 397         wait_queue_head_t open_wait;
 398
 399         struct dmabuf {
 400                 void *rawbuf;
 401                 dma_addr_t dmaaddr;
 402                 unsigned buforder;
 403                 unsigned numfrag;
 404                 unsigned fragshift;
 405                 unsigned hwptr, swptr;
 406                 unsigned total_bytes;
 407                 int count;
 408                 unsigned error;         /* over/underrun */
 409                 wait_queue_head_t wait;
 410
 411                 unsigned fragsize;      /* redundant, but makes calculations easier */
 412                 unsigned dmasize;
 413                 unsigned fragsamples;
 414                 unsigned dmasamples;
 415
 416                 unsigned mapped:1;      /* OSS stuff */
 417                 unsigned ready:1;
 418                 unsigned endcleared:1;
 419                 unsigned enabled:1;
 420                 unsigned ossfragshift;
 421                 int ossmaxfrags;
 422                 unsigned subdivision;
 423         } dma_dac, dma_adc;
 424
 425 #ifdef CONFIG_SOUND_CMPCI_MIDI
 426         int midi_devc;
 427         struct address_info mpu_data;
 428 #endif
 429 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
 430         struct gameport *gameport;
 431 #endif
 432
 433         int     chip_version;
 434         int     max_channels;
 435         int     curr_channels;
 436         int     capability;             /* HW capability, various for chip versions */
 437
 438         int     status;                 /* HW or SW state */
 439
 440         int     spdif_counter;          /* spdif frame counter */
 441 };
 442
 443 /* flags used for capability */
 444 #define CAN_AC3_HW              0x00000001              /* 037 or later */
 445 #define CAN_AC3_SW              0x00000002              /* 033 or later */
 446 #define CAN_AC3                 (CAN_AC3_HW | CAN_AC3_SW)
 447 #define CAN_DUAL_DAC            0x00000004              /* 033 or later */
 448 #define CAN_MULTI_CH_HW         0x00000008              /* 039 or later */
 449 #define CAN_MULTI_CH            (CAN_MULTI_CH_HW | CAN_DUAL_DAC)
 450 #define CAN_LINE_AS_REAR        0x00000010              /* 033 or later */
 451 #define CAN_LINE_AS_BASS        0x00000020              /* 039 or later */
 452 #define CAN_MIC_AS_BASS         0x00000040              /* 039 or later */
 453
 454 /* flags used for status */
 455 #define DO_AC3_HW               0x00000001
 456 #define DO_AC3_SW               0x00000002
 457 #define DO_AC3                  (DO_AC3_HW | DO_AC3_SW)
 458 #define DO_DUAL_DAC             0x00000004
 459 #define DO_MULTI_CH_HW          0x00000008
 460 #define DO_MULTI_CH             (DO_MULTI_CH_HW | DO_DUAL_DAC)
 461 #define DO_LINE_AS_REAR         0x00000010              /* 033 or later */
 462 #define DO_LINE_AS_BASS         0x00000020              /* 039 or later */
 463 #define DO_MIC_AS_BASS          0x00000040              /* 039 or later */
 464 #define DO_SPDIF_OUT            0x00000100
 465 #define DO_SPDIF_IN             0x00000200
 466 #define DO_SPDIF_LOOP           0x00000400
 467 #define DO_BIGENDIAN_W          0x00001000              /* used in PowerPC */
 468 #define DO_BIGENDIAN_R          0x00002000              /* used in PowerPC */
 469
 470 static LIST_HEAD(devs);
 471
 472 static  int     mpuio;
 473 static  int     fmio;
 474 static  int     joystick;
 475 static  int     spdif_inverse;
 476 static  int     spdif_loop;
 477 static  int     spdif_out;
 478 static  int     use_line_as_rear;
 479 static  int     use_line_as_bass;
 480 static  int     use_mic_as_bass;
 481 static  int     mic_boost;
 482 static  int     hw_copy;
 483 module_param(mpuio, int, 0);
 484 module_param(fmio, int, 0);
 485 module_param(joystick, bool, 0);
 486 module_param(spdif_inverse, bool, 0);
 487 module_param(spdif_loop, bool, 0);
 488 module_param(spdif_out, bool, 0);
 489 module_param(use_line_as_rear, bool, 0);
 490 module_param(use_line_as_bass, bool, 0);
 491 module_param(use_mic_as_bass, bool, 0);
 492 module_param(mic_boost, bool, 0);
 493 module_param(hw_copy, bool, 0);
 494 MODULE_PARM_DESC(mpuio, "(0x330, 0x320, 0x310, 0x300) Base of MPU-401, 0 to disable");
 495 MODULE_PARM_DESC(fmio, "(0x388, 0x3C8, 0x3E0) Base of OPL3, 0 to disable");
 496 MODULE_PARM_DESC(joystick, "(1/0) Enable joystick interface, still need joystick driver");
 497 MODULE_PARM_DESC(spdif_inverse, "(1/0) Invert S/PDIF-in signal");
 498 MODULE_PARM_DESC(spdif_loop, "(1/0) Route S/PDIF-in to S/PDIF-out directly");
 499 MODULE_PARM_DESC(spdif_out, "(1/0) Send PCM to S/PDIF-out (PCM volume will not function)");
 500 MODULE_PARM_DESC(use_line_as_rear, "(1/0) Use line-in jack as rear-out");
 501 MODULE_PARM_DESC(use_line_as_bass, "(1/0) Use line-in jack as bass/center");
 502 MODULE_PARM_DESC(use_mic_as_bass, "(1/0) Use mic-in jack as bass/center");
 503 MODULE_PARM_DESC(mic_boost, "(1/0) Enable microphone boost");
 504 MODULE_PARM_DESC(hw_copy, "Copy front channel to surround channel");
 505
 506 /* --------------------------------------------------------------------- */
 507
 508 static inline unsigned ld2(unsigned int x)
 509 {
 510         unsigned exp=16,l=5,r=0;
 511         static const unsigned num[]={0x2,0x4,0x10,0x100,0x10000};
 512
 513         /* num: 2, 4, 16, 256, 65536 */
 514         /* exp: 1, 2,  4,   8,    16 */
 515
 516         while(l--) {
 517                 if( x >= num[l] ) {
 518                         if(num[l]>2) x >>= exp;
 519                         r+=exp;
 520                 }
 521                 exp>>=1;
 522         }
 523
 524         return r;
 525 }
 526
 527 /* --------------------------------------------------------------------- */
 528
 529 static void maskb(unsigned int addr, unsigned int mask, unsigned int value)
 530 {
 531         outb((inb(addr) & mask) | value, addr);
 532 }
 533
 534 static void maskw(unsigned int addr, unsigned int mask, unsigned int value)
 535 {
 536         outw((inw(addr) & mask) | value, addr);
 537 }
 538
 539 static void maskl(unsigned int addr, unsigned int mask, unsigned int value)
 540 {
 541         outl((inl(addr) & mask) | value, addr);
 542 }
 543
 544 static void set_dmadac1(struct cm_state *s, unsigned int addr, unsigned int count)
 545 {
 546         if (addr)
 547             outl(addr, s->iobase + CODEC_CMI_ADC_FRAME1);
 548         outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2);
 549         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC0, 0);
 550 }
 551
 552 static void set_dmaadc(struct cm_state *s, unsigned int addr, unsigned int count)
 553 {
 554         outl(addr, s->iobase + CODEC_CMI_ADC_FRAME1);
 555         outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2);
 556         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, CHADC0);
 557 }
 558
 559 static void set_dmadac(struct cm_state *s, unsigned int addr, unsigned int count)
 560 {
 561         outl(addr, s->iobase + CODEC_CMI_DAC_FRAME1);
 562         outw(count - 1, s->iobase + CODEC_CMI_DAC_FRAME2);
 563         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC1, 0);
 564         if (s->status & DO_DUAL_DAC)
 565                 set_dmadac1(s, 0, count);
 566 }
 567
 568 static void set_countadc(struct cm_state *s, unsigned count)
 569 {
 570         outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2 + 2);
 571 }
 572
 573 static void set_countdac(struct cm_state *s, unsigned count)
 574 {
 575         outw(count - 1, s->iobase + CODEC_CMI_DAC_FRAME2 + 2);
 576         if (s->status & DO_DUAL_DAC)
 577             set_countadc(s, count);
 578 }
 579
 580 static unsigned get_dmadac(struct cm_state *s)
 581 {
 582         unsigned int curr_addr;
 583
 584         curr_addr = inw(s->iobase + CODEC_CMI_DAC_FRAME2) + 1;
 585         curr_addr <<= sample_shift[(s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK];
 586         curr_addr = s->dma_dac.dmasize - curr_addr;
 587
 588         return curr_addr;
 589 }
 590
 591 static unsigned get_dmaadc(struct cm_state *s)
 592 {
 593         unsigned int curr_addr;
 594
 595         curr_addr = inw(s->iobase + CODEC_CMI_ADC_FRAME2) + 1;
 596         curr_addr <<= sample_shift[(s->fmt >> CM_CFMT_ADCSHIFT) & CM_CFMT_MASK];
 597         curr_addr = s->dma_adc.dmasize - curr_addr;
 598
 599         return curr_addr;
 600 }
 601
 602 static void wrmixer(struct cm_state *s, unsigned char idx, unsigned char data)
 603 {
 604         unsigned char regval, pseudo;
 605
 606         // pseudo register
 607         if (idx == DSP_MIX_AUXVOL_L) {
 608                 data >>= 4;
 609                 data &= 0x0f;
 610                 regval = inb(s->iobase + CODEC_CMI_AUX_VOL) & ~0x0f;
 611                 outb(regval | data, s->iobase + CODEC_CMI_AUX_VOL);
 612                 return;
 613         }
 614         if (idx == DSP_MIX_AUXVOL_R) {
 615                 data &= 0xf0;
 616                 regval = inb(s->iobase + CODEC_CMI_AUX_VOL) & ~0xf0;
 617                 outb(regval | data, s->iobase + CODEC_CMI_AUX_VOL);
 618                 return;
 619         }
 620         outb(idx, s->iobase + CODEC_SB16_ADDR);
 621         udelay(10);
 622         // pseudo bits
 623         if (idx == DSP_MIX_OUTMIXIDX) {
 624                 pseudo = data & ~0x1f;
 625                 pseudo >>= 1;
 626                 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x30;
 627                 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
 628         }
 629         if (idx == DSP_MIX_ADCMIXIDX_L) {
 630                 pseudo = data & 0x80;
 631                 pseudo >>= 1;
 632                 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x40;
 633                 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
 634         }
 635         if (idx == DSP_MIX_ADCMIXIDX_R) {
 636                 pseudo = data & 0x80;
 637                 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x80;
 638                 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
 639         }
 640         outb(data, s->iobase + CODEC_SB16_DATA);
 641         udelay(10);
 642 }
 643
 644 static unsigned char rdmixer(struct cm_state *s, unsigned char idx)
 645 {
 646         unsigned char v, pseudo;
 647
 648         // pseudo register
 649         if (idx == DSP_MIX_AUXVOL_L) {
 650                 v = inb(s->iobase + CODEC_CMI_AUX_VOL) & 0x0f;
 651                 v <<= 4;
 652                 return v;
 653         }
 654         if (idx == DSP_MIX_AUXVOL_L) {
 655                 v = inb(s->iobase + CODEC_CMI_AUX_VOL) & 0xf0;
 656                 return v;
 657         }
 658         outb(idx, s->iobase + CODEC_SB16_ADDR);
 659         udelay(10);
 660         v = inb(s->iobase + CODEC_SB16_DATA);
 661         udelay(10);
 662         // pseudo bits
 663         if (idx == DSP_MIX_OUTMIXIDX) {
 664                 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x30;
 665                 pseudo <<= 1;
 666                 v |= pseudo;
 667         }
 668         if (idx == DSP_MIX_ADCMIXIDX_L) {
 669                 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x40;
 670                 pseudo <<= 1;
 671                 v |= pseudo;
 672         }
 673         if (idx == DSP_MIX_ADCMIXIDX_R) {
 674                 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x80;
 675                 v |= pseudo;
 676         }
 677         return v;
 678 }
 679
 680 static void set_fmt_unlocked(struct cm_state *s, unsigned char mask, unsigned char data)
 681 {
 682         if (mask && s->chip_version > 0) {      /* 8338 cannot keep this */
 683                 s->fmt = inb(s->iobase + CODEC_CMI_CHFORMAT);
 684                 udelay(10);
 685         }
 686         s->fmt = (s->fmt & mask) | data;
 687         outb(s->fmt, s->iobase + CODEC_CMI_CHFORMAT);
 688         udelay(10);
 689 }
 690
 691 static void set_fmt(struct cm_state *s, unsigned char mask, unsigned char data)
 692 {
 693         unsigned long flags;
 694
 695         spin_lock_irqsave(&s->lock, flags);
 696         set_fmt_unlocked(s,mask,data);
 697         spin_unlock_irqrestore(&s->lock, flags);
 698 }
 699
 700 static void frobindir(struct cm_state *s, unsigned char idx, unsigned char mask, unsigned char data)
 701 {
 702         outb(idx, s->iobase + CODEC_SB16_ADDR);
 703         udelay(10);
 704         outb((inb(s->iobase + CODEC_SB16_DATA) & mask) | data, s->iobase + CODEC_SB16_DATA);
 705         udelay(10);
 706 }
 707
 708 static struct {
 709         unsigned        rate;
 710         unsigned        lower;
 711         unsigned        upper;
 712         unsigned char   freq;
 713 } rate_lookup[] =
 714 {
 715         { 5512,         (0 + 5512) / 2,         (5512 + 8000) / 2,      0 },
 716         { 8000,         (5512 + 8000) / 2,      (8000 + 11025) / 2,     4 },
 717         { 11025,        (8000 + 11025) / 2,     (11025 + 16000) / 2,    1 },
 718         { 16000,        (11025 + 16000) / 2,    (16000 + 22050) / 2,    5 },
 719         { 22050,        (16000 + 22050) / 2,    (22050 + 32000) / 2,    2 },
 720         { 32000,        (22050 + 32000) / 2,    (32000 + 44100) / 2,    6 },
 721         { 44100,        (32000 + 44100) / 2,    (44100 + 48000) / 2,    3 },
 722         { 48000,        (44100 + 48000) / 2,    48000,                  7 }
 723 };
 724
 725 static void set_spdif_copyright(struct cm_state *s, int spdif_copyright)
 726 {
 727         /* enable SPDIF-in Copyright */
 728         maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~SPDCOPYRHT, spdif_copyright ? SPDCOPYRHT : 0);
 729 }
 730
 731 static void set_spdif_loop(struct cm_state *s, int spdif_loop)
 732 {
 733         /* enable SPDIF loop */
 734         if (spdif_loop) {
 735                 s->status |= DO_SPDIF_LOOP;
 736                 /* turn on spdif-in to spdif-out */
 737                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, SPDFLOOP);
 738         } else {
 739                 s->status &= ~DO_SPDIF_LOOP;
 740                 /* turn off spdif-in to spdif-out */
 741                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~SPDFLOOP, 0);
 742         }
 743 }
 744
 745 static void set_spdif_monitor(struct cm_state *s, int channel)
 746 {
 747         // SPDO2DAC
 748         maskw(s->iobase + CODEC_CMI_FUNCTRL1, ~SPDO2DAC, channel == 2 ? SPDO2DAC : 0);
 749         // CDPLAY
 750         if (s->chip_version >= 39)
 751                 maskb(s->iobase + CODEC_CMI_MIXER1, ~CDPLAY, channel ? CDPLAY : 0);
 752 }
 753
 754 static void set_spdifout_level(struct cm_state *s, int level5v)
 755 {
 756         /* SPDO5V */
 757         if (s->chip_version > 0)
 758                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~SPDO5V, level5v ? SPDO5V : 0);
 759 }
 760
 761 static void set_spdifin_inverse(struct cm_state *s, int spdif_inverse)
 762 {
 763         if (s->chip_version == 0)       /* 8338 has not this feature */
 764                 return;
 765         if (spdif_inverse) {
 766                 /* turn on spdif-in inverse */
 767                 if (s->chip_version >= 39)
 768                         maskb(s->iobase + CODEC_CMI_CHFORMAT, ~0, INVSPDIFI);
 769                 else
 770                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 1);
 771         } else {
 772                 /* turn off spdif-ininverse */
 773                 if (s->chip_version >= 39)
 774                         maskb(s->iobase + CODEC_CMI_CHFORMAT, ~INVSPDIFI, 0);
 775                 else
 776                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~1, 0);
 777         }
 778 }
 779
 780 static void set_spdifin_channel2(struct cm_state *s, int channel2)
 781 {
 782         /* SELSPDIFI2 */
 783         if (s->chip_version >= 39)
 784                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 1, ~SELSPDIFI2, channel2 ? SELSPDIFI2 : 0);
 785 }
 786
 787 static void set_spdifin_valid(struct cm_state *s, int valid)
 788 {
 789         /* SPDVALID */
 790         maskb(s->iobase + CODEC_CMI_MISC, ~SPDVALID, valid ? SPDVALID : 0);
 791 }
 792
 793 static void set_spdifout_unlocked(struct cm_state *s, unsigned rate)
 794 {
 795         if (rate != 48000 && rate != 44100)
 796                 rate = 0;
 797         if (rate == 48000 || rate == 44100) {
 798                 set_spdif_loop(s, 0);
 799                 // SPDF_1
 800                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~0, SPDF_1);
 801                 // SPDIFI48K SPDF_AC97
 802                 maskl(s->iobase + CODEC_CMI_MISC_CTRL, ~SPDIF48K, rate == 48000 ? SPDIF48K : 0);
 803                 if (s->chip_version >= 55)
 804                 // SPD32KFMT
 805                         maskb(s->iobase + CODEC_CMI_MISC_CTRL2, ~SPD32KFMT, rate == 48000 ? SPD32KFMT : 0);
 806                 if (s->chip_version > 0)
 807                 // ENSPDOUT
 808                         maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~0, ENSPDOUT);
 809                 // monitor SPDIF out
 810                 set_spdif_monitor(s, 2);
 811                 s->status |= DO_SPDIF_OUT;
 812         } else {
 813                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~SPDF_1, 0);
 814                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~ENSPDOUT, 0);
 815                 // monitor none
 816                 set_spdif_monitor(s, 0);
 817                 s->status &= ~DO_SPDIF_OUT;
 818         }
 819 }
 820
 821 static void set_spdifout(struct cm_state *s, unsigned rate)
 822 {
 823         unsigned long flags;
 824
 825         spin_lock_irqsave(&s->lock, flags);
 826         set_spdifout_unlocked(s,rate);
 827         spin_unlock_irqrestore(&s->lock, flags);
 828 }
 829
 830 static void set_spdifin_unlocked(struct cm_state *s, unsigned rate)
 831 {
 832         if (rate == 48000 || rate == 44100) {
 833                 // SPDF_1
 834                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~0, SPDF_1);
 835                 // SPDIFI48K SPDF_AC97
 836                 maskl(s->iobase + CODEC_CMI_MISC_CTRL, ~SPDIF48K, rate == 48000 ? SPDIF48K : 0);
 837                 s->status |= DO_SPDIF_IN;
 838         } else {
 839                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~SPDF_1, 0);
 840                 s->status &= ~DO_SPDIF_IN;
 841         }
 842 }
 843
 844 static void set_spdifin(struct cm_state *s, unsigned rate)
 845 {
 846         unsigned long flags;
 847
 848         spin_lock_irqsave(&s->lock, flags);
 849         set_spdifin_unlocked(s,rate);
 850         spin_unlock_irqrestore(&s->lock, flags);
 851 }
 852
 853 /* find parity for bit 4~30 */
 854 static unsigned parity(unsigned data)
 855 {
 856         unsigned parity = 0;
 857         int counter = 4;
 858
 859         data >>= 4;     // start from bit 4
 860         while (counter <= 30) {
 861                 if (data & 1)
 862                         parity++;
 863                 data >>= 1;
 864                 counter++;
 865         }
 866         return parity & 1;
 867 }
 868
 869 static void set_ac3_unlocked(struct cm_state *s, unsigned rate)
 870 {
 871         if (!(s->capability & CAN_AC3))
 872                 return;
 873         /* enable AC3 */
 874         if (rate && rate != 44100)
 875                 rate = 48000;
 876         if (rate == 48000 || rate == 44100) {
 877                 // mute DAC
 878                 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, WSMUTE);
 879                 if (s->chip_version >= 39)
 880                         maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~0, MUTECH1);
 881                 // AC3EN for 039, 0x04
 882                 if (s->chip_version >= 39) {
 883                         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, AC3_EN);
 884                         if (s->chip_version == 55)
 885                                 maskb(s->iobase + CODEC_CMI_SPDIF_CTRL, ~2, 0);
 886                 // AC3EN for 037, 0x10
 887                 } else if (s->chip_version == 37)
 888                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 0x10);
 889                 if (s->capability & CAN_AC3_HW) {
 890                         // SPD24SEL for 039, 0x20, but cannot be set
 891                         if (s->chip_version == 39)
 892                                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, SPD24SEL);
 893                         // SPD24SEL for 037, 0x02
 894                         else if (s->chip_version == 37)
 895                                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 0x02);
 896                         if (s->chip_version >= 39)
 897                                 maskb(s->iobase + CODEC_CMI_MIXER1, ~CDPLAY, 0);
 898
 899                         s->status |= DO_AC3_HW;
 900                  } else {
 901                         // SPD32SEL for 037 & 039
 902                         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, SPD32SEL);
 903                         // set 176K sample rate to fix 033 HW bug
 904                         if (s->chip_version == 33) {
 905                                 if (rate == 48000)
 906                                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0, 0x08);
 907                                 else
 908                                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0x08, 0);
 909                         }
 910                         s->status |= DO_AC3_SW;
 911                 }
 912         } else {
 913                 maskb(s->iobase + CODEC_CMI_MIXER1, ~WSMUTE, 0);
 914                 if (s->chip_version >= 39)
 915                         maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~MUTECH1, 0);
 916                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~(SPD24SEL|0x12), 0);
 917                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~(SPD32SEL|AC3_EN), 0);
 918                 if (s->chip_version == 33)
 919                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0x08, 0);
 920                 if (s->chip_version >= 39)
 921                         maskb(s->iobase + CODEC_CMI_MIXER1, ~0, CDPLAY);
 922                 s->status &= ~DO_AC3;
 923         }
 924         s->spdif_counter = 0;
 925 }
 926
 927 static void set_line_as_rear(struct cm_state *s, int use_line_as_rear)
 928 {
 929         if (!(s->capability & CAN_LINE_AS_REAR))
 930                 return;
 931         if (use_line_as_rear) {
 932                 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, SPK4);
 933                 s->status |= DO_LINE_AS_REAR;
 934         } else {
 935                 maskb(s->iobase + CODEC_CMI_MIXER1, ~SPK4, 0);
 936                 s->status &= ~DO_LINE_AS_REAR;
 937         }
 938 }
 939
 940 static void set_line_as_bass(struct cm_state *s, int use_line_as_bass)
 941 {
 942         if (!(s->capability & CAN_LINE_AS_BASS))
 943                 return;
 944         if (use_line_as_bass) {
 945                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~0, CB2LIN);
 946                 s->status |= DO_LINE_AS_BASS;
 947         } else {
 948                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CB2LIN, 0);
 949                 s->status &= ~DO_LINE_AS_BASS;
 950         }
 951 }
 952
 953 static void set_mic_as_bass(struct cm_state *s, int use_mic_as_bass)
 954 {
 955         if (!(s->capability & CAN_MIC_AS_BASS))
 956                 return;
 957         if (use_mic_as_bass) {
 958                 maskb(s->iobase + CODEC_CMI_MISC, ~0, 0x04);
 959                 s->status |= DO_MIC_AS_BASS;
 960         } else {
 961                 maskb(s->iobase + CODEC_CMI_MISC, ~0x04, 0);
 962                 s->status &= ~DO_MIC_AS_BASS;
 963         }
 964 }
 965
 966 static void set_hw_copy(struct cm_state *s, int hw_copy)
 967 {
 968         if (s->max_channels > 2 && hw_copy)
 969                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~0, N4SPK3D);
 970         else
 971                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~N4SPK3D, 0);
 972 }
 973
 974 static void set_ac3(struct cm_state *s, unsigned rate)
 975 {
 976         unsigned long flags;
 977
 978         spin_lock_irqsave(&s->lock, flags);
 979         set_spdifout_unlocked(s, rate);
 980         set_ac3_unlocked(s, rate);
 981         spin_unlock_irqrestore(&s->lock, flags);
 982 }
 983
 984 static int trans_ac3(struct cm_state *s, void *dest, const char __user *source, int size)
 985 {
 986         int   i = size / 2;
 987         unsigned long data;
 988         unsigned short data16;
 989         unsigned long *dst = (unsigned long *) dest;
 990         unsigned short __user *src = (unsigned short __user *)source;
 991         int err;
 992
 993         do {
 994                 if ((err = __get_user(data16, src++)))
 995                         return err;
 996                 data = (unsigned long)le16_to_cpu(data16);
 997                 data <<= 12;                    // ok for 16-bit data
 998                 if (s->spdif_counter == 2 || s->spdif_counter == 3)
 999                         data |= 0x40000000;     // indicate AC-3 raw data
1000                 if (parity(data))
1001                         data |= 0x80000000;     // parity
1002                 if (s->spdif_counter == 0)
1003                         data |= 3;              // preamble 'M'
1004                 else if (s->spdif_counter & 1)
1005                         data |= 5;              // odd, 'W'
1006                 else
1007                         data |= 9;              // even, 'M'
1008                 *dst++ = cpu_to_le32(data);
1009                 s->spdif_counter++;
1010                 if (s->spdif_counter == 384)
1011                         s->spdif_counter = 0;
1012         } while (--i);
1013
1014         return 0;
1015 }
1016
1017 static void set_adc_rate_unlocked(struct cm_state *s, unsigned rate)
1018 {
1019         unsigned char freq = 4;
1020         int     i;
1021
1022         if (rate > 48000)
1023                 rate = 48000;
1024         if (rate < 8000)
1025                 rate = 8000;
1026         for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1027                 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1028                         rate = rate_lookup[i].rate;
1029                         freq = rate_lookup[i].freq;
1030                         break;
1031                 }
1032         }
1033         s->rateadc = rate;
1034         freq <<= CM_FREQ_ADCSHIFT;
1035
1036         maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~ASFC, freq);
1037 }
1038
1039 static void set_adc_rate(struct cm_state *s, unsigned rate)
1040 {
1041         unsigned long flags;
1042         unsigned char freq = 4;
1043         int     i;
1044
1045         if (rate > 48000)
1046                 rate = 48000;
1047         if (rate < 8000)
1048                 rate = 8000;
1049         for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1050                 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1051                         rate = rate_lookup[i].rate;
1052                         freq = rate_lookup[i].freq;
1053                         break;
1054                 }
1055         }
1056         s->rateadc = rate;
1057         freq <<= CM_FREQ_ADCSHIFT;
1058
1059         spin_lock_irqsave(&s->lock, flags);
1060         maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~ASFC, freq);
1061         spin_unlock_irqrestore(&s->lock, flags);
1062 }
1063
1064 static void set_dac_rate(struct cm_state *s, unsigned rate)
1065 {
1066         unsigned long flags;
1067         unsigned char freq = 4;
1068         int     i;
1069
1070         if (rate > 48000)
1071                 rate = 48000;
1072         if (rate < 8000)
1073                 rate = 8000;
1074         for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1075                 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1076                         rate = rate_lookup[i].rate;
1077                         freq = rate_lookup[i].freq;
1078                         break;
1079                 }
1080         }
1081         s->ratedac = rate;
1082         freq <<= CM_FREQ_DACSHIFT;
1083
1084         spin_lock_irqsave(&s->lock, flags);
1085         maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~DSFC, freq);
1086         spin_unlock_irqrestore(&s->lock, flags);
1087
1088         if (s->curr_channels <= 2 && spdif_out)
1089                 set_spdifout(s, rate);
1090         if (s->status & DO_DUAL_DAC)
1091                 set_dac1_rate(s, rate);
1092 }
1093
1094 /* --------------------------------------------------------------------- */
1095 static inline void reset_adc(struct cm_state *s)
1096 {
1097         /* reset bus master */
1098         outb(s->enable | RSTADC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1099         udelay(10);
1100         outb(s->enable & ~RSTADC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1101 }
1102
1103 static inline void reset_dac(struct cm_state *s)
1104 {
1105         /* reset bus master */
1106         outb(s->enable | RSTDAC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1107         udelay(10);
1108         outb(s->enable & ~RSTDAC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1109         if (s->status & DO_DUAL_DAC)
1110                 reset_adc(s);
1111 }
1112
1113 static inline void pause_adc(struct cm_state *s)
1114 {
1115         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, PAUSEADC);
1116 }
1117
1118 static inline void pause_dac(struct cm_state *s)
1119 {
1120         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, PAUSEDAC);
1121         if (s->status & DO_DUAL_DAC)
1122                 pause_adc(s);
1123 }
1124
1125 static inline void disable_adc(struct cm_state *s)
1126 {
1127         /* disable channel */
1128         s->enable &= ~ENADC;
1129         outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1130         reset_adc(s);
1131 }
1132
1133 static inline void disable_dac(struct cm_state *s)
1134 {
1135         /* disable channel */
1136         s->enable &= ~ENDAC;
1137         outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1138         reset_dac(s);
1139         if (s->status & DO_DUAL_DAC)
1140                 disable_adc(s);
1141 }
1142
1143 static inline void enable_adc(struct cm_state *s)
1144 {
1145         if (!(s->enable & ENADC)) {
1146                 /* enable channel */
1147                 s->enable |= ENADC;
1148                 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1149         }
1150         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~PAUSEADC, 0);
1151 }
1152
1153 static inline void enable_dac_unlocked(struct cm_state *s)
1154 {
1155         if (!(s->enable & ENDAC)) {
1156                 /* enable channel */
1157                 s->enable |= ENDAC;
1158                 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1159         }
1160         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~PAUSEDAC, 0);
1161
1162         if (s->status & DO_DUAL_DAC)
1163                 enable_adc(s);
1164 }
1165
1166 static inline void stop_adc_unlocked(struct cm_state *s)
1167 {
1168         if (s->enable & ENADC) {
1169                 /* disable interrupt */
1170                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~ENADCINT, 0);
1171                 disable_adc(s);
1172         }
1173 }
1174
1175 static inline void stop_adc(struct cm_state *s)
1176 {
1177         unsigned long flags;
1178
1179         spin_lock_irqsave(&s->lock, flags);
1180         stop_adc_unlocked(s);
1181         spin_unlock_irqrestore(&s->lock, flags);
1182
1183 }
1184
1185 static inline void stop_dac_unlocked(struct cm_state *s)
1186 {
1187         if (s->enable & ENDAC) {
1188                 /* disable interrupt */
1189                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~ENDACINT, 0);
1190                 disable_dac(s);
1191         }
1192         if (s->status & DO_DUAL_DAC)
1193                 stop_dac1_unlocked(s);
1194 }
1195
1196 static inline void stop_dac(struct cm_state *s)
1197 {
1198         unsigned long flags;
1199
1200         spin_lock_irqsave(&s->lock, flags);
1201         stop_dac_unlocked(s);
1202         spin_unlock_irqrestore(&s->lock, flags);
1203 }
1204
1205 static inline void start_adc_unlocked(struct cm_state *s)
1206 {
1207         if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
1208             && s->dma_adc.ready) {
1209                 /* enable interrupt */
1210                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENADCINT);
1211                 enable_adc(s);
1212         }
1213 }
1214
1215 static void start_adc(struct cm_state *s)
1216 {
1217         unsigned long flags;
1218
1219         spin_lock_irqsave(&s->lock, flags);
1220         start_adc_unlocked(s);
1221         spin_unlock_irqrestore(&s->lock, flags);
1222 }
1223
1224 static void start_dac1_unlocked(struct cm_state *s)
1225 {
1226         if ((s->dma_adc.mapped || s->dma_adc.count > 0) && s->dma_adc.ready) {
1227                 /* enable interrupt */
1228                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENADCINT);
1229                 enable_dac_unlocked(s);
1230         }
1231 }
1232
1233 static void start_dac_unlocked(struct cm_state *s)
1234 {
1235         if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
1236                 /* enable interrupt */
1237                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENDACINT);
1238                 enable_dac_unlocked(s);
1239         }
1240         if (s->status & DO_DUAL_DAC)
1241                 start_dac1_unlocked(s);
1242 }
1243
1244 static void start_dac(struct cm_state *s)
1245 {
1246         unsigned long flags;
1247
1248         spin_lock_irqsave(&s->lock, flags);
1249         start_dac_unlocked(s);
1250         spin_unlock_irqrestore(&s->lock, flags);
1251 }
1252
1253 static int prog_dmabuf(struct cm_state *s, unsigned rec);
1254
1255 static int set_dac_channels(struct cm_state *s, int channels)
1256 {
1257         unsigned long flags;
1258         static unsigned int fmmute = 0;
1259
1260         spin_lock_irqsave(&s->lock, flags);
1261
1262         if ((channels > 2) && (channels <= s->max_channels)
1263          && (((s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK) == (CM_CFMT_STEREO | CM_CFMT_16BIT))) {
1264             set_spdifout_unlocked(s, 0);
1265             if (s->capability & CAN_MULTI_CH_HW) {
1266                 // NXCHG
1267                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0, NXCHG);
1268                 // CHB3D or CHB3D5C
1269                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 3, ~(CHB3D5C|CHB3D), channels > 4 ? CHB3D5C : CHB3D);
1270                 // CHB3D6C
1271                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CHB3D6C, channels == 6 ? CHB3D6C : 0);
1272                 // ENCENTER
1273                 maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~ENCENTER, channels == 6 ? ENCENTER : 0);
1274                 s->status |= DO_MULTI_CH_HW;
1275             } else if (s->capability & CAN_DUAL_DAC) {
1276                 unsigned char fmtm = ~0, fmts = 0;
1277                 ssize_t ret;
1278
1279                 // ENDBDAC, turn on double DAC mode
1280                 // XCHGDAC, CH0 -> back, CH1->front
1281                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, ENDBDAC|XCHGDAC);
1282                 // mute FM
1283                 fmmute = inb(s->iobase + CODEC_CMI_MIXER1) & FMMUTE;
1284                 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, FMMUTE);
1285                 s->status |= DO_DUAL_DAC;
1286                 // prepare secondary buffer
1287                 spin_unlock_irqrestore(&s->lock, flags);
1288                 ret = prog_dmabuf(s, 1);
1289                 if (ret) return ret;
1290                 spin_lock_irqsave(&s->lock, flags);
1291
1292                 // copy the hw state
1293                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_DACSHIFT);
1294                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_ADCSHIFT);
1295                 // the HW only support 16-bit stereo
1296                 fmts |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
1297                 fmts |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
1298                 fmts |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
1299                 fmts |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
1300
1301                 set_fmt_unlocked(s, fmtm, fmts);
1302                 set_adc_rate_unlocked(s, s->ratedac);
1303             }
1304             // disable 4 speaker mode (analog duplicate)
1305             set_hw_copy(s, 0);
1306             s->curr_channels = channels;
1307
1308             // enable jack redirect
1309             set_line_as_rear(s, use_line_as_rear);
1310             if (channels > 4) {
1311                     set_line_as_bass(s, use_line_as_bass);
1312                     set_mic_as_bass(s, use_mic_as_bass);
1313             }
1314         } else {
1315             if (s->status & DO_MULTI_CH_HW) {
1316                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~NXCHG, 0);
1317                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 3, ~(CHB3D5C|CHB3D), 0);
1318                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CHB3D6C, 0);
1319             } else if (s->status & DO_DUAL_DAC) {
1320                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~ENDBDAC, 0);
1321                 maskb(s->iobase + CODEC_CMI_MIXER1, ~FMMUTE, fmmute);
1322             }
1323             // enable 4 speaker mode (analog duplicate)
1324             set_hw_copy(s, hw_copy);
1325             s->status &= ~DO_MULTI_CH;
1326             s->curr_channels = s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1;
1327             // disable jack redirect
1328             set_line_as_rear(s, hw_copy ? use_line_as_rear : 0);
1329             set_line_as_bass(s, 0);
1330             set_mic_as_bass(s, 0);
1331         }
1332         spin_unlock_irqrestore(&s->lock, flags);
1333         return s->curr_channels;
1334 }
1335
1336 /* --------------------------------------------------------------------- */
1337
1338 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
1339 #define DMABUF_MINORDER 1
1340
1341 static void dealloc_dmabuf(struct cm_state *s, struct dmabuf *db)
1342 {
1343         struct page *pstart, *pend;
1344
1345         if (db->rawbuf) {
1346                 /* undo marking the pages as reserved */
1347                 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1348                 for (pstart = virt_to_page(db->rawbuf); pstart <= pend; pstart++)
1349                         ClearPageReserved(pstart);
1350                 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
1351         }
1352         db->rawbuf = NULL;
1353         db->mapped = db->ready = 0;
1354 }
1355
1356 /* Ch1 is used for playback, Ch0 is used for recording */
1357
1358 static int prog_dmabuf(struct cm_state *s, unsigned rec)
1359 {
1360         struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1361         unsigned rate = rec ? s->rateadc : s->ratedac;
1362         int order;
1363         unsigned bytepersec;
1364         unsigned bufs;
1365         struct page *pstart, *pend;
1366         unsigned char fmt;
1367         unsigned long flags;
1368
1369         fmt = s->fmt;
1370         if (rec) {
1371                 stop_adc(s);
1372                 fmt >>= CM_CFMT_ADCSHIFT;
1373         } else {
1374                 stop_dac(s);
1375                 fmt >>= CM_CFMT_DACSHIFT;
1376         }
1377
1378         fmt &= CM_CFMT_MASK;
1379         db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1380         if (!db->rawbuf) {
1381                 db->ready = db->mapped = 0;
1382                 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
1383                         if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
1384                                 break;
1385                 if (!db->rawbuf || !db->dmaaddr)
1386                         return -ENOMEM;
1387                 db->buforder = order;
1388                 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
1389                 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1390                 for (pstart = virt_to_page(db->rawbuf); pstart <= pend; pstart++)
1391                         SetPageReserved(pstart);
1392         }
1393         bytepersec = rate << sample_shift[fmt];
1394         bufs = PAGE_SIZE << db->buforder;
1395         if (db->ossfragshift) {
1396                 if ((1000 << db->ossfragshift) < bytepersec)
1397                         db->fragshift = ld2(bytepersec/1000);
1398                 else
1399                         db->fragshift = db->ossfragshift;
1400         } else {
1401                 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1402                 if (db->fragshift < 3)
1403                         db->fragshift = 3;
1404         }
1405         db->numfrag = bufs >> db->fragshift;
1406         while (db->numfrag < 4 && db->fragshift > 3) {
1407                 db->fragshift--;
1408                 db->numfrag = bufs >> db->fragshift;
1409         }
1410         db->fragsize = 1 << db->fragshift;
1411         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1412                 db->numfrag = db->ossmaxfrags;
1413         /* to make fragsize >= 4096 */
1414         db->fragsamples = db->fragsize >> sample_shift[fmt];
1415         db->dmasize = db->numfrag << db->fragshift;
1416         db->dmasamples = db->dmasize >> sample_shift[fmt];
1417         memset(db->rawbuf, (fmt & CM_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
1418         spin_lock_irqsave(&s->lock, flags);
1419         if (rec) {
1420                 if (s->status & DO_DUAL_DAC)
1421                     set_dmadac1(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1422                 else
1423                     set_dmaadc(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1424                 /* program sample counts */
1425                 set_countdac(s, db->fragsamples);
1426         } else {
1427                 set_dmadac(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1428                 /* program sample counts */
1429                 set_countdac(s, db->fragsamples);
1430         }
1431         spin_unlock_irqrestore(&s->lock, flags);
1432         db->enabled = 1;
1433         db->ready = 1;
1434         return 0;
1435 }
1436
1437 static inline void clear_advance(struct cm_state *s)
1438 {
1439         unsigned char c = (s->fmt & (CM_CFMT_16BIT << CM_CFMT_DACSHIFT)) ? 0 : 0x80;
1440         unsigned char *buf = s->dma_dac.rawbuf;
1441         unsigned char *buf1 = s->dma_adc.rawbuf;
1442         unsigned bsize = s->dma_dac.dmasize;
1443         unsigned bptr = s->dma_dac.swptr;
1444         unsigned len = s->dma_dac.fragsize;
1445
1446         if (bptr + len > bsize) {
1447                 unsigned x = bsize - bptr;
1448                 memset(buf + bptr, c, x);
1449                 if (s->status & DO_DUAL_DAC)
1450                         memset(buf1 + bptr, c, x);
1451                 bptr = 0;
1452                 len -= x;
1453         }
1454         memset(buf + bptr, c, len);
1455         if (s->status & DO_DUAL_DAC)
1456                 memset(buf1 + bptr, c, len);
1457 }
1458
1459 /* call with spinlock held! */
1460 static void cm_update_ptr(struct cm_state *s)
1461 {
1462         unsigned hwptr;
1463         int diff;
1464
1465         /* update ADC pointer */
1466         if (s->dma_adc.ready) {
1467             if (s->status & DO_DUAL_DAC) {
1468                     /* the dac part will finish for this */
1469             } else {
1470                 hwptr = get_dmaadc(s) % s->dma_adc.dmasize;
1471                 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1472                 s->dma_adc.hwptr = hwptr;
1473                 s->dma_adc.total_bytes += diff;
1474                 s->dma_adc.count += diff;
1475                 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1476                         wake_up(&s->dma_adc.wait);
1477                 if (!s->dma_adc.mapped) {
1478                         if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1479                                 pause_adc(s);
1480                                 s->dma_adc.error++;
1481                         }
1482                 }
1483             }
1484         }
1485         /* update DAC pointer */
1486         if (s->dma_dac.ready) {
1487                 hwptr = get_dmadac(s) % s->dma_dac.dmasize;
1488                 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1489                 s->dma_dac.hwptr = hwptr;
1490                 s->dma_dac.total_bytes += diff;
1491                 if (s->status & DO_DUAL_DAC) {
1492                         s->dma_adc.hwptr = hwptr;
1493                         s->dma_adc.total_bytes += diff;
1494                 }
1495                 if (s->dma_dac.mapped) {
1496                         s->dma_dac.count += diff;
1497                         if (s->status & DO_DUAL_DAC)
1498                                 s->dma_adc.count += diff;
1499                         if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1500                                 wake_up(&s->dma_dac.wait);
1501                 } else {
1502                         s->dma_dac.count -= diff;
1503                         if (s->status & DO_DUAL_DAC)
1504                                 s->dma_adc.count -= diff;
1505                         if (s->dma_dac.count <= 0) {
1506                                 pause_dac(s);
1507                                 s->dma_dac.error++;
1508                         } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1509                                 clear_advance(s);
1510                                 s->dma_dac.endcleared = 1;
1511                                 if (s->status & DO_DUAL_DAC)
1512                                         s->dma_adc.endcleared = 1;
1513                         }
1514                         if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
1515                                 wake_up(&s->dma_dac.wait);
1516                 }
1517         }
1518 }
1519
1520 static irqreturn_t cm_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1521 {
1522         struct cm_state *s = (struct cm_state *)dev_id;
1523         unsigned int intsrc, intstat;
1524         unsigned char mask = 0;
1525
1526         /* fastpath out, to ease interrupt sharing */
1527         intsrc = inl(s->iobase + CODEC_CMI_INT_STATUS);
1528         if (!(intsrc & 0x80000000))
1529                 return IRQ_NONE;
1530         spin_lock(&s->lock);
1531         intstat = inb(s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1532         /* acknowledge interrupt */
1533         if (intsrc & ADCINT)
1534                 mask |= ENADCINT;
1535         if (intsrc & DACINT)
1536                 mask |= ENDACINT;
1537         outb(intstat & ~mask, s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1538         outb(intstat | mask, s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1539         cm_update_ptr(s);
1540         spin_unlock(&s->lock);
1541 #ifdef CONFIG_SOUND_CMPCI_MIDI
1542         if (intsrc & 0x00010000) {      // UART interrupt
1543                 if (s->midi_devc && intchk_mpu401((void *)s->midi_devc))
1544                         mpuintr(irq, (void *)s->midi_devc, regs);
1545                 else
1546                         inb(s->iomidi);// dummy read
1547         }
1548 #endif
1549         return IRQ_HANDLED;
1550 }
1551
1552 /* --------------------------------------------------------------------- */
1553
1554 static const char invalid_magic[] = KERN_CRIT "cmpci: invalid magic value\n";
1555
1556 #define VALIDATE_STATE(s)                         \
1557 ({                                                \
1558         if (!(s) || (s)->magic != CM_MAGIC) { \
1559                 printk(invalid_magic);            \
1560                 return -ENXIO;                    \
1561         }                                         \
1562 })
1563
1564 /* --------------------------------------------------------------------- */
1565
1566 #define MT_4          1
1567 #define MT_5MUTE      2
1568 #define MT_4MUTEMONO  3
1569 #define MT_6MUTE      4
1570 #define MT_5MUTEMONO  5
1571
1572 static const struct {
1573         unsigned left;
1574         unsigned right;
1575         unsigned type;
1576         unsigned rec;
1577         unsigned play;
1578 } mixtable[SOUND_MIXER_NRDEVICES] = {
1579         [SOUND_MIXER_CD]     = { DSP_MIX_CDVOLIDX_L,     DSP_MIX_CDVOLIDX_R,     MT_5MUTE,     0x04, 0x06 },
1580         [SOUND_MIXER_LINE]   = { DSP_MIX_LINEVOLIDX_L,   DSP_MIX_LINEVOLIDX_R,   MT_5MUTE,     0x10, 0x18 },
1581         [SOUND_MIXER_MIC]    = { DSP_MIX_MICVOLIDX,      DSP_MIX_MICVOLIDX,      MT_5MUTEMONO, 0x01, 0x01 },
1582         [SOUND_MIXER_SYNTH]  = { DSP_MIX_FMVOLIDX_L,     DSP_MIX_FMVOLIDX_R,     MT_5MUTE,     0x40, 0x00 },
1583         [SOUND_MIXER_VOLUME] = { DSP_MIX_MASTERVOLIDX_L, DSP_MIX_MASTERVOLIDX_R, MT_5MUTE,     0x00, 0x00 },
1584         [SOUND_MIXER_PCM]    = { DSP_MIX_VOICEVOLIDX_L,  DSP_MIX_VOICEVOLIDX_R,  MT_5MUTE,     0x00, 0x00 },
1585         [SOUND_MIXER_LINE1]  = { DSP_MIX_AUXVOL_L,       DSP_MIX_AUXVOL_R,       MT_5MUTE,     0x80, 0x60 },
1586         [SOUND_MIXER_SPEAKER]= { DSP_MIX_SPKRVOLIDX,     DSP_MIX_SPKRVOLIDX,     MT_5MUTEMONO, 0x00, 0x01 }
1587 };
1588
1589 static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
1590 {
1591         [SOUND_MIXER_CD]     = 1,
1592         [SOUND_MIXER_LINE]   = 2,
1593         [SOUND_MIXER_MIC]    = 3,
1594         [SOUND_MIXER_SYNTH]  = 4,
1595         [SOUND_MIXER_VOLUME] = 5,
1596         [SOUND_MIXER_PCM]    = 6,
1597         [SOUND_MIXER_LINE1]  = 7,
1598         [SOUND_MIXER_SPEAKER]= 8
1599 };
1600
1601 static unsigned mixer_outmask(struct cm_state *s)
1602 {
1603         unsigned long flags;
1604         int i, j, k;
1605
1606         spin_lock_irqsave(&s->lock, flags);
1607         j = rdmixer(s, DSP_MIX_OUTMIXIDX);
1608         spin_unlock_irqrestore(&s->lock, flags);
1609         for (k = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1610                 if (j & mixtable[i].play)
1611                         k |= 1 << i;
1612         return k;
1613 }
1614
1615 static unsigned mixer_recmask(struct cm_state *s)
1616 {
1617         unsigned long flags;
1618         int i, j, k;
1619
1620         spin_lock_irqsave(&s->lock, flags);
1621         j = rdmixer(s, DSP_MIX_ADCMIXIDX_L);
1622         spin_unlock_irqrestore(&s->lock, flags);
1623         for (k = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1624                 if (j & mixtable[i].rec)
1625                         k |= 1 << i;
1626         return k;
1627 }
1628
1629 static int mixer_ioctl(struct cm_state *s, unsigned int cmd, unsigned long arg)
1630 {
1631         unsigned long flags;
1632         int i, val, j;
1633         unsigned char l, r, rl, rr;
1634         void __user *argp = (void __user *)arg;
1635         int __user *p = argp;
1636
1637         VALIDATE_STATE(s);
1638         if (cmd == SOUND_MIXER_INFO) {
1639                 mixer_info info;
1640                 memset(&info, 0, sizeof(info));
1641                 strlcpy(info.id, "cmpci", sizeof(info.id));
1642                 strlcpy(info.name, "C-Media PCI", sizeof(info.name));
1643                 info.modify_counter = s->mix.modcnt;
1644                 if (copy_to_user(argp, &info, sizeof(info)))
1645                         return -EFAULT;
1646                 return 0;
1647         }
1648         if (cmd == SOUND_OLD_MIXER_INFO) {
1649                 _old_mixer_info info;
1650                 memset(&info, 0, sizeof(info));
1651                 strlcpy(info.id, "cmpci", sizeof(info.id));
1652                 strlcpy(info.name, "C-Media cmpci", sizeof(info.name));
1653                 if (copy_to_user(argp, &info, sizeof(info)))
1654                         return -EFAULT;
1655                 return 0;
1656         }
1657         if (cmd == OSS_GETVERSION)
1658                 return put_user(SOUND_VERSION, p);
1659         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1660                 return -EINVAL;
1661         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1662                 switch (_IOC_NR(cmd)) {
1663                 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1664                         val = mixer_recmask(s);
1665                         return put_user(val, p);
1666
1667                 case SOUND_MIXER_OUTSRC: /* Arg contains a bit for each recording source */
1668                         val = mixer_outmask(s);
1669                         return put_user(val, p);
1670
1671                 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
1672                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1673                                 if (mixtable[i].type)
1674                                         val |= 1 << i;
1675                         return put_user(val, p);
1676
1677                 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1678                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1679                                 if (mixtable[i].rec)
1680                                         val |= 1 << i;
1681                         return put_user(val, p);
1682
1683                 case SOUND_MIXER_OUTMASK: /* Arg contains a bit for each supported recording source */
1684                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1685                                 if (mixtable[i].play)
1686                                         val |= 1 << i;
1687                         return put_user(val, p);
1688
1689                  case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1690                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1691                                 if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
1692                                         val |= 1 << i;
1693                         return put_user(val, p);
1694
1695                 case SOUND_MIXER_CAPS:
1696                         return put_user(0, p);
1697
1698                 default:
1699                         i = _IOC_NR(cmd);
1700                         if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1701                                 return -EINVAL;
1702                         if (!volidx[i])
1703                                 return -EINVAL;
1704                         return put_user(s->mix.vol[volidx[i]-1], p);
1705                 }
1706         }
1707         if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
1708                 return -EINVAL;
1709         s->mix.modcnt++;
1710         switch (_IOC_NR(cmd)) {
1711         case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1712                 if (get_user(val, p))
1713                         return -EFAULT;
1714                 i = generic_hweight32(val);
1715                 for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1716                         if (!(val & (1 << i)))
1717                                 continue;
1718                         if (!mixtable[i].rec) {
1719                                 val &= ~(1 << i);
1720                                 continue;
1721                         }
1722                         j |= mixtable[i].rec;
1723                 }
1724                 spin_lock_irqsave(&s->lock, flags);
1725                 wrmixer(s, DSP_MIX_ADCMIXIDX_L, j);
1726                 wrmixer(s, DSP_MIX_ADCMIXIDX_R, (j & 1) | (j>>1) | (j & 0x80));
1727                 spin_unlock_irqrestore(&s->lock, flags);
1728                 return 0;
1729
1730         case SOUND_MIXER_OUTSRC: /* Arg contains a bit for each recording source */
1731                 if (get_user(val, p))
1732                         return -EFAULT;
1733                 for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1734                         if (!(val & (1 << i)))
1735                                 continue;
1736                         if (!mixtable[i].play) {
1737                                 val &= ~(1 << i);
1738                                 continue;
1739                         }
1740                         j |= mixtable[i].play;
1741                 }
1742                 spin_lock_irqsave(&s->lock, flags);
1743                 wrmixer(s, DSP_MIX_OUTMIXIDX, j);
1744                 spin_unlock_irqrestore(&s->lock, flags);
1745                 return 0;
1746
1747         default:
1748                 i = _IOC_NR(cmd);
1749                 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1750                         return -EINVAL;
1751                 if (get_user(val, p))
1752                         return -EFAULT;
1753                 l = val & 0xff;
1754                 r = (val >> 8) & 0xff;
1755                 if (l > 100)
1756                         l = 100;
1757                 if (r > 100)
1758                         r = 100;
1759                 spin_lock_irqsave(&s->lock, flags);
1760                 switch (mixtable[i].type) {
1761                 case MT_4:
1762                         if (l >= 10)
1763                                 l -= 10;
1764                         if (r >= 10)
1765                                 r -= 10;
1766                         frobindir(s, mixtable[i].left, 0xf0, l / 6);
1767                         frobindir(s, mixtable[i].right, 0xf0, l / 6);
1768                         break;
1769
1770                 case MT_4MUTEMONO:
1771                         rl = (l < 4 ? 0 : (l - 5) / 3) & 31;
1772                         rr = (rl >> 2) & 7;
1773                         wrmixer(s, mixtable[i].left, rl<<3);
1774                         if (i == SOUND_MIXER_MIC)
1775                                 maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, rr<<1);
1776                         break;
1777
1778                 case MT_5MUTEMONO:
1779                         rl = l < 4 ? 0 : (l - 5) / 3;
1780                         wrmixer(s, mixtable[i].left, rl<<3);
1781                         l = rdmixer(s, DSP_MIX_OUTMIXIDX) & ~mixtable[i].play;
1782                         r = rl ? mixtable[i].play : 0;
1783                         wrmixer(s, DSP_MIX_OUTMIXIDX, l | r);
1784                         /* for recording */
1785                         if (i == SOUND_MIXER_MIC) {
1786                                 if (s->chip_version >= 37) {
1787                                         rr = rl >> 1;
1788                                         maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, (rr&0x07)<<1);
1789                                         frobindir(s, DSP_MIX_EXTENSION, ~0x01, rr>>3);
1790                                 } else {
1791                                         rr = rl >> 2;
1792                                         maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, rr<<1);
1793                                 }
1794                         }
1795                         break;
1796
1797                 case MT_5MUTE:
1798                         rl = l < 4 ? 0 : (l - 5) / 3;
1799                         rr = r < 4 ? 0 : (r - 5) / 3;
1800                         wrmixer(s, mixtable[i].left, rl<<3);
1801                         wrmixer(s, mixtable[i].right, rr<<3);
1802                         l = rdmixer(s, DSP_MIX_OUTMIXIDX);
1803                         l &= ~mixtable[i].play;
1804                         r = (rl|rr) ? mixtable[i].play : 0;
1805                         wrmixer(s, DSP_MIX_OUTMIXIDX, l | r);
1806                         break;
1807
1808                 case MT_6MUTE:
1809                         if (l < 6)
1810                                 rl = 0x00;
1811                         else
1812                                 rl = l * 2 / 3;
1813                         if (r < 6)
1814                                 rr = 0x00;
1815                         else
1816                                 rr = r * 2 / 3;
1817                         wrmixer(s, mixtable[i].left, rl);
1818                         wrmixer(s, mixtable[i].right, rr);
1819                         break;
1820                 }
1821                 spin_unlock_irqrestore(&s->lock, flags);
1822
1823                 if (!volidx[i])
1824                         return -EINVAL;
1825                 s->mix.vol[volidx[i]-1] = val;
1826                 return put_user(s->mix.vol[volidx[i]-1], p);
1827         }
1828 }
1829
1830 /* --------------------------------------------------------------------- */
1831
1832 static int cm_open_mixdev(struct inode *inode, struct file *file)
1833 {
1834         int minor = iminor(inode);
1835         struct list_head *list;
1836         struct cm_state *s;
1837
1838         for (list = devs.next; ; list = list->next) {
1839                 if (list == &devs)
1840                         return -ENODEV;
1841                 s = list_entry(list, struct cm_state, devs);
1842                 if (s->dev_mixer == minor)
1843                         break;
1844         }
1845         VALIDATE_STATE(s);
1846         file->private_data = s;
1847         return nonseekable_open(inode, file);
1848 }
1849
1850 static int cm_release_mixdev(struct inode *inode, struct file *file)
1851 {
1852         struct cm_state *s = (struct cm_state *)file->private_data;
1853
1854         VALIDATE_STATE(s);
1855         return 0;
1856 }
1857
1858 static int cm_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1859 {
1860         return mixer_ioctl((struct cm_state *)file->private_data, cmd, arg);
1861 }
1862
1863 static /*const*/ struct file_operations cm_mixer_fops = {
1864         .owner   = THIS_MODULE,
1865         .llseek  = no_llseek,
1866         .ioctl   = cm_ioctl_mixdev,
1867         .open    = cm_open_mixdev,
1868         .release = cm_release_mixdev,
1869 };
1870
1871
1872 /* --------------------------------------------------------------------- */
1873
1874 static int drain_dac(struct cm_state *s, int nonblock)
1875 {
1876         DECLARE_WAITQUEUE(wait, current);
1877         unsigned long flags;
1878         int count, tmo;
1879
1880         if (s->dma_dac.mapped || !s->dma_dac.ready)
1881                 return 0;
1882         add_wait_queue(&s->dma_dac.wait, &wait);
1883         for (;;) {
1884                 __set_current_state(TASK_INTERRUPTIBLE);
1885                 spin_lock_irqsave(&s->lock, flags);
1886                 count = s->dma_dac.count;
1887                 spin_unlock_irqrestore(&s->lock, flags);
1888                 if (count <= 0)
1889                         break;
1890                 if (signal_pending(current))
1891                         break;
1892                 if (nonblock) {
1893                         remove_wait_queue(&s->dma_dac.wait, &wait);
1894                         set_current_state(TASK_RUNNING);
1895                         return -EBUSY;
1896                 }
1897                 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
1898                 tmo >>= sample_shift[(s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK];
1899                 if (!schedule_timeout(tmo + 1))
1900                         DBG(printk(KERN_DEBUG "cmpci: dma timed out??\n");)
1901         }
1902         remove_wait_queue(&s->dma_dac.wait, &wait);
1903         set_current_state(TASK_RUNNING);
1904         if (signal_pending(current))
1905                 return -ERESTARTSYS;
1906         return 0;
1907 }
1908
1909 /* --------------------------------------------------------------------- */
1910
1911 static ssize_t cm_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1912 {
1913         struct cm_state *s = (struct cm_state *)file->private_data;
1914         DECLARE_WAITQUEUE(wait, current);
1915         ssize_t ret;
1916         unsigned long flags;
1917         unsigned swptr;
1918         int cnt;
1919
1920         VALIDATE_STATE(s);
1921         if (s->dma_adc.mapped)
1922                 return -ENXIO;
1923         if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1924                 return ret;
1925         if (!access_ok(VERIFY_WRITE, buffer, count))
1926                 return -EFAULT;
1927         ret = 0;
1928
1929         add_wait_queue(&s->dma_adc.wait, &wait);
1930         while (count > 0) {
1931                 spin_lock_irqsave(&s->lock, flags);
1932                 swptr = s->dma_adc.swptr;
1933                 cnt = s->dma_adc.dmasize-swptr;
1934                 if (s->dma_adc.count < cnt)
1935                         cnt = s->dma_adc.count;
1936                 if (cnt <= 0)
1937                         __set_current_state(TASK_INTERRUPTIBLE);
1938                 spin_unlock_irqrestore(&s->lock, flags);
1939                 if (cnt > count)
1940                         cnt = count;
1941                 if (cnt <= 0) {
1942                         if (s->dma_adc.enabled)
1943                                 start_adc(s);
1944                         if (file->f_flags & O_NONBLOCK) {
1945                                 if (!ret)
1946                                         ret = -EAGAIN;
1947                                 goto out;
1948                         }
1949                         if (!schedule_timeout(HZ)) {
1950                                 printk(KERN_DEBUG "cmpci: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1951                                        s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1952                                        s->dma_adc.hwptr, s->dma_adc.swptr);
1953                                 spin_lock_irqsave(&s->lock, flags);
1954                                 stop_adc_unlocked(s);
1955                                 set_dmaadc(s, s->dma_adc.dmaaddr, s->dma_adc.dmasamples);
1956                                 /* program sample counts */
1957                                 set_countadc(s, s->dma_adc.fragsamples);
1958                                 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1959                                 spin_unlock_irqrestore(&s->lock, flags);
1960                         }
1961                         if (signal_pending(current)) {
1962                                 if (!ret)
1963                                         ret = -ERESTARTSYS;
1964                                 goto out;
1965                         }
1966                         continue;
1967                 }
1968                 if (s->status & DO_BIGENDIAN_R) {
1969                         int     i, err;
1970                         unsigned char *src;
1971                         char __user *dst = buffer;
1972                         unsigned char data[2];
1973
1974                         src = (unsigned char *) (s->dma_adc.rawbuf + swptr);
1975                         // copy left/right sample at one time
1976                         for (i = 0; i < cnt / 2; i++) {
1977                                 data[0] = src[1];
1978                                 data[1] = src[0];
1979                                 if ((err = __put_user(data[0], dst++))) {
1980                                         ret = err;
1981                                         goto out;
1982                                 }
1983                                 if ((err = __put_user(data[1], dst++))) {
1984                                         ret = err;
1985                                         goto out;
1986                                 }
1987                                 src += 2;
1988                         }
1989                 } else if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1990                         if (!ret)
1991                                 ret = -EFAULT;
1992                         goto out;
1993                 }
1994                 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1995                 spin_lock_irqsave(&s->lock, flags);
1996                 s->dma_adc.swptr = swptr;
1997                 s->dma_adc.count -= cnt;
1998                 count -= cnt;
1999                 buffer += cnt;
2000                 ret += cnt;
2001                 if (s->dma_adc.enabled)
2002                         start_adc_unlocked(s);
2003                 spin_unlock_irqrestore(&s->lock, flags);
2004         }
2005 out:
2006         remove_wait_queue(&s->dma_adc.wait, &wait);
2007         set_current_state(TASK_RUNNING);
2008         return ret;
2009 }
2010
2011 static ssize_t cm_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2012 {
2013         struct cm_state *s = (struct cm_state *)file->private_data;
2014         DECLARE_WAITQUEUE(wait, current);
2015         ssize_t ret;
2016         unsigned long flags;
2017         unsigned swptr;
2018         int cnt;
2019
2020         VALIDATE_STATE(s);
2021         if (s->dma_dac.mapped)
2022                 return -ENXIO;
2023         if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2024                 return ret;
2025         if (!access_ok(VERIFY_READ, buffer, count))
2026                 return -EFAULT;
2027         if (s->status & DO_DUAL_DAC) {
2028                 if (s->dma_adc.mapped)
2029                         return -ENXIO;
2030                 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2031                         return ret;
2032         }
2033         if (!access_ok(VERIFY_READ, buffer, count))
2034                 return -EFAULT;
2035         ret = 0;
2036
2037         add_wait_queue(&s->dma_dac.wait, &wait);
2038         while (count > 0) {
2039                 spin_lock_irqsave(&s->lock, flags);
2040                 if (s->dma_dac.count < 0) {
2041                         s->dma_dac.count = 0;
2042                         s->dma_dac.swptr = s->dma_dac.hwptr;
2043                 }
2044                 if (s->status & DO_DUAL_DAC) {
2045                         s->dma_adc.swptr = s->dma_dac.swptr;
2046                         s->dma_adc.count = s->dma_dac.count;
2047                         s->dma_adc.endcleared = s->dma_dac.endcleared;
2048                 }
2049                 swptr = s->dma_dac.swptr;
2050                 cnt = s->dma_dac.dmasize-swptr;
2051                 if (s->status & DO_AC3_SW) {
2052                         if (s->dma_dac.count + 2 * cnt > s->dma_dac.dmasize)
2053                                 cnt = (s->dma_dac.dmasize - s->dma_dac.count) / 2;
2054                 } else {
2055                         if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
2056                                 cnt = s->dma_dac.dmasize - s->dma_dac.count;
2057                 }
2058                 if (cnt <= 0)
2059                         __set_current_state(TASK_INTERRUPTIBLE);
2060                 spin_unlock_irqrestore(&s->lock, flags);
2061                 if (cnt > count)
2062                         cnt = count;
2063                 if ((s->status & DO_DUAL_DAC) && (cnt > count / 2))
2064                     cnt = count / 2;
2065                 if (cnt <= 0) {
2066                         if (s->dma_dac.enabled)
2067                                 start_dac(s);
2068                         if (file->f_flags & O_NONBLOCK) {
2069                                 if (!ret)
2070                                         ret = -EAGAIN;
2071                                 goto out;
2072                         }
2073                         if (!schedule_timeout(HZ)) {
2074                                 printk(KERN_DEBUG "cmpci: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
2075                                        s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
2076                                        s->dma_dac.hwptr, s->dma_dac.swptr);
2077                                 spin_lock_irqsave(&s->lock, flags);
2078                                 stop_dac_unlocked(s);
2079                                 set_dmadac(s, s->dma_dac.dmaaddr, s->dma_dac.dmasamples);
2080                                 /* program sample counts */
2081                                 set_countdac(s, s->dma_dac.fragsamples);
2082                                 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
2083                                 if (s->status & DO_DUAL_DAC)  {
2084                                         set_dmadac1(s, s->dma_adc.dmaaddr, s->dma_adc.dmasamples);
2085                                         s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
2086                                 }
2087                                 spin_unlock_irqrestore(&s->lock, flags);
2088                         }
2089                         if (signal_pending(current)) {
2090                                 if (!ret)
2091                                         ret = -ERESTARTSYS;
2092                                 goto out;
2093                         }
2094                         continue;
2095                 }
2096                 if (s->status & DO_AC3_SW) {
2097                         int err;
2098
2099                         // clip exceeded data, caught by 033 and 037
2100                         if (swptr + 2 * cnt > s->dma_dac.dmasize)
2101                                 cnt = (s->dma_dac.dmasize - swptr) / 2;
2102                         if ((err = trans_ac3(s, s->dma_dac.rawbuf + swptr, buffer, cnt))) {
2103                                 ret = err;
2104                                 goto out;
2105                         }
2106                         swptr = (swptr + 2 * cnt) % s->dma_dac.dmasize;
2107                 } else if ((s->status & DO_DUAL_DAC) && (s->status & DO_BIGENDIAN_W)) {
2108                         int     i, err;
2109                         const char __user *src = buffer;
2110                         unsigned char *dst0, *dst1;
2111                         unsigned char data[8];
2112
2113                         dst0 = (unsigned char *) (s->dma_dac.rawbuf + swptr);
2114                         dst1 = (unsigned char *) (s->dma_adc.rawbuf + swptr);
2115                         // copy left/right sample at one time
2116                         for (i = 0; i < cnt / 4; i++) {
2117                                 if ((err = __get_user(data[0], src++))) {
2118                                         ret = err;
2119                                         goto out;
2120                                 }
2121                                 if ((err = __get_user(data[1], src++))) {
2122                                         ret = err;
2123                                         goto out;
2124                                 }
2125                                 if ((err = __get_user(data[2], src++))) {
2126                                         ret = err;
2127                                         goto out;
2128                                 }
2129                                 if ((err = __get_user(data[3], src++))) {
2130                                         ret = err;
2131                                         goto out;
2132                                 }
2133                                 if ((err = __get_user(data[4], src++))) {
2134                                         ret = err;
2135                                         goto out;
2136                                 }
2137                                 if ((err = __get_user(data[5], src++))) {
2138                                         ret = err;
2139                                         goto out;
2140                                 }
2141                                 if ((err = __get_user(data[6], src++))) {
2142                                         ret = err;
2143                                         goto out;
2144                                 }
2145                                 if ((err = __get_user(data[7], src++))) {
2146                                         ret = err;
2147                                         goto out;
2148                                 }
2149                                 dst0[0] = data[1];
2150                                 dst0[1] = data[0];
2151                                 dst0[2] = data[3];
2152                                 dst0[3] = data[2];
2153                                 dst1[0] = data[5];
2154                                 dst1[1] = data[4];
2155                                 dst1[2] = data[7];
2156                                 dst1[3] = data[6];
2157                                 dst0 += 4;
2158                                 dst1 += 4;
2159                         }
2160                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2161                 } else if (s->status & DO_DUAL_DAC) {
2162                         int     i, err;
2163                         unsigned long __user *src = (unsigned long __user *) buffer;
2164                         unsigned long *dst0, *dst1;
2165
2166                         dst0 = (unsigned long *) (s->dma_dac.rawbuf + swptr);
2167                         dst1 = (unsigned long *) (s->dma_adc.rawbuf + swptr);
2168                         // copy left/right sample at one time
2169                         for (i = 0; i < cnt / 4; i++) {
2170                                 if ((err = __get_user(*dst0++, src++))) {
2171                                         ret = err;
2172                                         goto out;
2173                                 }
2174                                 if ((err = __get_user(*dst1++, src++))) {
2175                                         ret = err;
2176                                         goto out;
2177                                 }
2178                         }
2179                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2180                 } else if (s->status & DO_BIGENDIAN_W) {
2181                         int     i, err;
2182                         const char __user *src = buffer;
2183                         unsigned char *dst;
2184                         unsigned char data[2];
2185
2186                         dst = (unsigned char *) (s->dma_dac.rawbuf + swptr);
2187                         // swap hi/lo bytes for each sample
2188                         for (i = 0; i < cnt / 2; i++) {
2189                                 if ((err = __get_user(data[0], src++))) {
2190                                         ret = err;
2191                                         goto out;
2192                                 }
2193                                 if ((err = __get_user(data[1], src++))) {
2194                                         ret = err;
2195                                         goto out;
2196                                 }
2197                                 dst[0] = data[1];
2198                                 dst[1] = data[0];
2199                                 dst += 2;
2200                         }
2201                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2202                 } else {
2203                         if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
2204                                 if (!ret)
2205                                         ret = -EFAULT;
2206                                 goto out;
2207                         }
2208                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2209                 }
2210                 spin_lock_irqsave(&s->lock, flags);
2211                 s->dma_dac.swptr = swptr;
2212                 s->dma_dac.count += cnt;
2213                 if (s->status & DO_AC3_SW)
2214                         s->dma_dac.count += cnt;
2215                 s->dma_dac.endcleared = 0;
2216                 spin_unlock_irqrestore(&s->lock, flags);
2217                 count -= cnt;
2218                 buffer += cnt;
2219                 ret += cnt;
2220                 if (s->status & DO_DUAL_DAC) {
2221                         count -= cnt;
2222                         buffer += cnt;
2223                         ret += cnt;
2224                 }
2225                 if (s->dma_dac.enabled)
2226                         start_dac(s);
2227         }
2228 out:
2229         remove_wait_queue(&s->dma_dac.wait, &wait);
2230         set_current_state(TASK_RUNNING);
2231         return ret;
2232 }
2233
2234 static unsigned int cm_poll(struct file *file, struct poll_table_struct *wait)
2235 {
2236         struct cm_state *s = (struct cm_state *)file->private_data;
2237         unsigned long flags;
2238         unsigned int mask = 0;
2239
2240         VALIDATE_STATE(s);
2241         if (file->f_mode & FMODE_WRITE) {
2242                 if (!s->dma_dac.ready && prog_dmabuf(s, 0))
2243                         return 0;
2244                 poll_wait(file, &s->dma_dac.wait, wait);
2245         }
2246         if (file->f_mode & FMODE_READ) {
2247                 if (!s->dma_adc.ready && prog_dmabuf(s, 1))
2248                         return 0;
2249                 poll_wait(file, &s->dma_adc.wait, wait);
2250         }
2251         spin_lock_irqsave(&s->lock, flags);
2252         cm_update_ptr(s);
2253         if (file->f_mode & FMODE_READ) {
2254                 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
2255                         mask |= POLLIN | POLLRDNORM;
2256         }
2257         if (file->f_mode & FMODE_WRITE) {
2258                 if (s->dma_dac.mapped) {
2259                         if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
2260                                 mask |= POLLOUT | POLLWRNORM;
2261                 } else {
2262                         if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
2263                                 mask |= POLLOUT | POLLWRNORM;
2264                 }
2265         }
2266         spin_unlock_irqrestore(&s->lock, flags);
2267         return mask;
2268 }
2269
2270 static int cm_mmap(struct file *file, struct vm_area_struct *vma)
2271 {
2272         struct cm_state *s = (struct cm_state *)file->private_data;
2273         struct dmabuf *db;
2274         int ret = -EINVAL;
2275         unsigned long size;
2276
2277         VALIDATE_STATE(s);
2278         lock_kernel();
2279         if (vma->vm_flags & VM_WRITE) {
2280                 if ((ret = prog_dmabuf(s, 0)) != 0)
2281                         goto out;
2282                 db = &s->dma_dac;
2283         } else if (vma->vm_flags & VM_READ) {
2284                 if ((ret = prog_dmabuf(s, 1)) != 0)
2285                         goto out;
2286                 db = &s->dma_adc;
2287         } else
2288                 goto out;
2289         ret = -EINVAL;
2290         if (vma->vm_pgoff != 0)
2291                 goto out;
2292         size = vma->vm_end - vma->vm_start;
2293         if (size > (PAGE_SIZE << db->buforder))
2294                 goto out;
2295         ret = -EINVAL;
2296         if (remap_pfn_range(vma, vma->vm_start,
2297                                 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
2298                                 size, vma->vm_page_prot))
2299                 goto out;
2300         db->mapped = 1;
2301         ret = 0;
2302 out:
2303         unlock_kernel();
2304         return ret;
2305 }
2306
2307 #define SNDCTL_SPDIF_COPYRIGHT  _SIOW('S',  0, int)       // set/reset S/PDIF copy protection
2308 #define SNDCTL_SPDIF_LOOP       _SIOW('S',  1, int)       // set/reset S/PDIF loop
2309 #define SNDCTL_SPDIF_MONITOR    _SIOW('S',  2, int)       // set S/PDIF monitor
2310 #define SNDCTL_SPDIF_LEVEL      _SIOW('S',  3, int)       // set/reset S/PDIF out level
2311 #define SNDCTL_SPDIF_INV        _SIOW('S',  4, int)       // set/reset S/PDIF in inverse
2312 #define SNDCTL_SPDIF_SEL2       _SIOW('S',  5, int)       // set S/PDIF in #2
2313 #define SNDCTL_SPDIF_VALID      _SIOW('S',  6, int)       // set S/PDIF valid
2314 #define SNDCTL_SPDIFOUT         _SIOW('S',  7, int)       // set S/PDIF out
2315 #define SNDCTL_SPDIFIN          _SIOW('S',  8, int)       // set S/PDIF out
2316
2317 static int cm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2318 {
2319         struct cm_state *s = (struct cm_state *)file->private_data;
2320         unsigned long flags;
2321         audio_buf_info abinfo;
2322         count_info cinfo;
2323         int val, mapped, ret;
2324         unsigned char fmtm, fmtd;
2325         void __user *argp = (void __user *)arg;
2326         int __user *p = argp;
2327
2328         VALIDATE_STATE(s);
2329         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
2330                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
2331         switch (cmd) {
2332         case OSS_GETVERSION:
2333                 return put_user(SOUND_VERSION, p);
2334
2335         case SNDCTL_DSP_SYNC:
2336                 if (file->f_mode & FMODE_WRITE)
2337                         return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
2338                 return 0;
2339
2340         case SNDCTL_DSP_SETDUPLEX:
2341                 return 0;
2342
2343         case SNDCTL_DSP_GETCAPS:
2344                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP | DSP_CAP_BIND, p);
2345
2346         case SNDCTL_DSP_RESET:
2347                 if (file->f_mode & FMODE_WRITE) {
2348                         stop_dac(s);
2349                         synchronize_irq(s->irq);
2350                         s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
2351                         if (s->status & DO_DUAL_DAC)
2352                                 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2353                 }
2354                 if (file->f_mode & FMODE_READ) {
2355                         stop_adc(s);
2356                         synchronize_irq(s->irq);
2357                         s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2358                 }
2359                 return 0;
2360
2361         case SNDCTL_DSP_SPEED:
2362                 if (get_user(val, p))
2363                         return -EFAULT;
2364                 if (val >= 0) {
2365                         if (file->f_mode & FMODE_READ) {
2366                                 spin_lock_irqsave(&s->lock, flags);
2367                                 stop_adc_unlocked(s);
2368                                 s->dma_adc.ready = 0;
2369                                 set_adc_rate_unlocked(s, val);
2370                                 spin_unlock_irqrestore(&s->lock, flags);
2371                         }
2372                         if (file->f_mode & FMODE_WRITE) {
2373                                 stop_dac(s);
2374                                 s->dma_dac.ready = 0;
2375                                 if (s->status & DO_DUAL_DAC)
2376                                         s->dma_adc.ready = 0;
2377                                 set_dac_rate(s, val);
2378                         }
2379                 }
2380                 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
2381
2382         case SNDCTL_DSP_STEREO:
2383                 if (get_user(val, p))
2384                         return -EFAULT;
2385                 fmtd = 0;
2386                 fmtm = ~0;
2387                 if (file->f_mode & FMODE_READ) {
2388                         stop_adc(s);
2389                         s->dma_adc.ready = 0;
2390                         if (val)
2391                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2392                         else
2393                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2394                 }
2395                 if (file->f_mode & FMODE_WRITE) {
2396                         stop_dac(s);
2397                         s->dma_dac.ready = 0;
2398                         if (val)
2399                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2400                         else
2401                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_DACSHIFT);
2402                         if (s->status & DO_DUAL_DAC) {
2403                                 s->dma_adc.ready = 0;
2404                                 if (val)
2405                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2406                                 else
2407                                         fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2408                         }
2409                 }
2410                 set_fmt(s, fmtm, fmtd);
2411                 return 0;
2412
2413         case SNDCTL_DSP_CHANNELS:
2414                 if (get_user(val, p))
2415                         return -EFAULT;
2416                 if (val != 0) {
2417                         fmtd = 0;
2418                         fmtm = ~0;
2419                         if (file->f_mode & FMODE_READ) {
2420                                 stop_adc(s);
2421                                 s->dma_adc.ready = 0;
2422                                 if (val >= 2)
2423                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2424                                 else
2425                                         fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2426                         }
2427                         if (file->f_mode & FMODE_WRITE) {
2428                                 stop_dac(s);
2429                                 s->dma_dac.ready = 0;
2430                                 if (val >= 2)
2431                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2432                                 else
2433                                         fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_DACSHIFT);
2434                                 if (s->status & DO_DUAL_DAC) {
2435                                         s->dma_adc.ready = 0;
2436                                         if (val >= 2)
2437                                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2438                                         else
2439                                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2440                                 }
2441                         }
2442                         set_fmt(s, fmtm, fmtd);
2443                         if ((s->capability & CAN_MULTI_CH)
2444                              && (file->f_mode & FMODE_WRITE)) {
2445                                 val = set_dac_channels(s, val);
2446                                 return put_user(val, p);
2447                         }
2448                 }
2449                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_STEREO << CM_CFMT_ADCSHIFT)
2450                                            : (CM_CFMT_STEREO << CM_CFMT_DACSHIFT))) ? 2 : 1, p);
2451
2452         case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2453                 return put_user(AFMT_S16_BE|AFMT_S16_LE|AFMT_U8|
2454                         ((s->capability & CAN_AC3) ? AFMT_AC3 : 0), p);
2455
2456         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2457                 if (get_user(val, p))
2458                         return -EFAULT;
2459                 if (val != AFMT_QUERY) {
2460                         fmtd = 0;
2461                         fmtm = ~0;
2462                         if (file->f_mode & FMODE_READ) {
2463                                 stop_adc(s);
2464                                 s->dma_adc.ready = 0;
2465                                 if (val == AFMT_S16_BE || val == AFMT_S16_LE)
2466                                         fmtd |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
2467                                 else
2468                                         fmtm &= ~(CM_CFMT_16BIT << CM_CFMT_ADCSHIFT);
2469                                 if (val == AFMT_S16_BE)
2470                                         s->status |= DO_BIGENDIAN_R;
2471                                 else
2472                                         s->status &= ~DO_BIGENDIAN_R;
2473                         }
2474                         if (file->f_mode & FMODE_WRITE) {
2475                                 stop_dac(s);
2476                                 s->dma_dac.ready = 0;
2477                                 if (val == AFMT_S16_BE || val == AFMT_S16_LE || val == AFMT_AC3)
2478                                         fmtd |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
2479                                 else
2480                                         fmtm &= ~(CM_CFMT_16BIT << CM_CFMT_DACSHIFT);
2481                                 if (val == AFMT_AC3) {
2482                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2483                                         set_ac3(s, 48000);
2484                                 } else
2485                                         set_ac3(s, 0);
2486                                 if (s->status & DO_DUAL_DAC) {
2487                                         s->dma_adc.ready = 0;
2488                                         if (val == AFMT_S16_BE || val == AFMT_S16_LE)
2489                                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2490                                         else
2491                                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2492                                 }
2493                                 if (val == AFMT_S16_BE)
2494                                         s->status |= DO_BIGENDIAN_W;
2495                                 else
2496                                         s->status &= ~DO_BIGENDIAN_W;
2497                         }
2498                         set_fmt(s, fmtm, fmtd);
2499                 }
2500                 if (s->status & DO_AC3) return put_user(AFMT_AC3, p);
2501                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_16BIT << CM_CFMT_ADCSHIFT)
2502                                            : (CM_CFMT_16BIT << CM_CFMT_DACSHIFT))) ? val : AFMT_U8, p);
2503
2504         case SNDCTL_DSP_POST:
2505                 return 0;
2506
2507         case SNDCTL_DSP_GETTRIGGER:
2508                 val = 0;
2509                 if (s->status & DO_DUAL_DAC) {
2510                         if (file->f_mode & FMODE_WRITE &&
2511                          (s->enable & ENDAC) &&
2512                          (s->enable & ENADC))
2513                                 val |= PCM_ENABLE_OUTPUT;
2514                         return put_user(val, p);
2515                 }
2516                 if (file->f_mode & FMODE_READ && s->enable & ENADC)
2517                         val |= PCM_ENABLE_INPUT;
2518                 if (file->f_mode & FMODE_WRITE && s->enable & ENDAC)
2519                         val |= PCM_ENABLE_OUTPUT;
2520                 return put_user(val, p);
2521
2522         case SNDCTL_DSP_SETTRIGGER:
2523                 if (get_user(val, p))
2524                         return -EFAULT;
2525                 if (file->f_mode & FMODE_READ) {
2526                         if (val & PCM_ENABLE_INPUT) {
2527                                 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2528                                         return ret;
2529                                 s->dma_adc.enabled = 1;
2530                                 start_adc(s);
2531                         } else {
2532                                 s->dma_adc.enabled = 0;
2533                                 stop_adc(s);
2534                         }
2535                 }
2536                 if (file->f_mode & FMODE_WRITE) {
2537                         if (val & PCM_ENABLE_OUTPUT) {
2538                                 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2539                                         return ret;
2540                                 if (s->status & DO_DUAL_DAC) {
2541                                         if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2542                                                 return ret;
2543                                 }
2544                                 s->dma_dac.enabled = 1;
2545                                 start_dac(s);
2546                         } else {
2547                                 s->dma_dac.enabled = 0;
2548                                 stop_dac(s);
2549                         }
2550                 }
2551                 return 0;
2552
2553         case SNDCTL_DSP_GETOSPACE:
2554                 if (!(file->f_mode & FMODE_WRITE))
2555                         return -EINVAL;
2556                 if (!(s->enable & ENDAC) && (val = prog_dmabuf(s, 0)) != 0)
2557                         return val;
2558                 spin_lock_irqsave(&s->lock, flags);
2559                 cm_update_ptr(s);
2560                 abinfo.fragsize = s->dma_dac.fragsize;
2561                 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
2562                 abinfo.fragstotal = s->dma_dac.numfrag;
2563                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2564                 spin_unlock_irqrestore(&s->lock, flags);
2565                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2566
2567         case SNDCTL_DSP_GETISPACE:
2568                 if (!(file->f_mode & FMODE_READ))
2569                         return -EINVAL;
2570                 if (!(s->enable & ENADC) && (val = prog_dmabuf(s, 1)) != 0)
2571                         return val;
2572                 spin_lock_irqsave(&s->lock, flags);
2573                 cm_update_ptr(s);
2574                 abinfo.fragsize = s->dma_adc.fragsize;
2575                 abinfo.bytes = s->dma_adc.count;
2576                 abinfo.fragstotal = s->dma_adc.numfrag;
2577                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
2578                 spin_unlock_irqrestore(&s->lock, flags);
2579                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2580
2581         case SNDCTL_DSP_NONBLOCK:
2582                 file->f_flags |= O_NONBLOCK;
2583                 return 0;
2584
2585         case SNDCTL_DSP_GETODELAY:
2586                 if (!(file->f_mode & FMODE_WRITE))
2587                         return -EINVAL;
2588                 spin_lock_irqsave(&s->lock, flags);
2589                 cm_update_ptr(s);
2590                 val = s->dma_dac.count;
2591                 spin_unlock_irqrestore(&s->lock, flags);
2592                 return put_user(val, p);
2593
2594         case SNDCTL_DSP_GETIPTR:
2595                 if (!(file->f_mode & FMODE_READ))
2596                         return -EINVAL;
2597                 spin_lock_irqsave(&s->lock, flags);
2598                 cm_update_ptr(s);
2599                 cinfo.bytes = s->dma_adc.total_bytes;
2600                 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
2601                 cinfo.ptr = s->dma_adc.hwptr;
2602                 if (s->dma_adc.mapped)
2603                         s->dma_adc.count &= s->dma_adc.fragsize-1;
2604                 spin_unlock_irqrestore(&s->lock, flags);
2605                 return copy_to_user(argp, &cinfo, sizeof(cinfo))  ? -EFAULT : 0;
2606
2607         case SNDCTL_DSP_GETOPTR:
2608                 if (!(file->f_mode & FMODE_WRITE))
2609                         return -EINVAL;
2610                 spin_lock_irqsave(&s->lock, flags);
2611                 cm_update_ptr(s);
2612                 cinfo.bytes = s->dma_dac.total_bytes;
2613                 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
2614                 cinfo.ptr = s->dma_dac.hwptr;
2615                 if (s->dma_dac.mapped)
2616                         s->dma_dac.count &= s->dma_dac.fragsize-1;
2617                 if (s->status & DO_DUAL_DAC) {
2618                         if (s->dma_adc.mapped)
2619                                 s->dma_adc.count &= s->dma_adc.fragsize-1;
2620                 }
2621                 spin_unlock_irqrestore(&s->lock, flags);
2622                 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2623
2624         case SNDCTL_DSP_GETBLKSIZE:
2625                 if (file->f_mode & FMODE_WRITE) {
2626                         if ((val = prog_dmabuf(s, 0)))
2627                                 return val;
2628                         if (s->status & DO_DUAL_DAC) {
2629                                 if ((val = prog_dmabuf(s, 1)))
2630                                         return val;
2631                                 return put_user(2 * s->dma_dac.fragsize, p);
2632                         }
2633                         return put_user(s->dma_dac.fragsize, p);
2634                 }
2635                 if ((val = prog_dmabuf(s, 1)))
2636                         return val;
2637                 return put_user(s->dma_adc.fragsize, p);
2638
2639         case SNDCTL_DSP_SETFRAGMENT:
2640                 if (get_user(val, p))
2641                         return -EFAULT;
2642                 if (file->f_mode & FMODE_READ) {
2643                         s->dma_adc.ossfragshift = val & 0xffff;
2644                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
2645                         if (s->dma_adc.ossfragshift < 4)
2646                                 s->dma_adc.ossfragshift = 4;
2647                         if (s->dma_adc.ossfragshift > 15)
2648                                 s->dma_adc.ossfragshift = 15;
2649                         if (s->dma_adc.ossmaxfrags < 4)
2650                                 s->dma_adc.ossmaxfrags = 4;
2651                 }
2652                 if (file->f_mode & FMODE_WRITE) {
2653                         s->dma_dac.ossfragshift = val & 0xffff;
2654                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
2655                         if (s->dma_dac.ossfragshift < 4)
2656                                 s->dma_dac.ossfragshift = 4;
2657                         if (s->dma_dac.ossfragshift > 15)
2658                                 s->dma_dac.ossfragshift = 15;
2659                         if (s->dma_dac.ossmaxfrags < 4)
2660                                 s->dma_dac.ossmaxfrags = 4;
2661                         if (s->status & DO_DUAL_DAC) {
2662                                 s->dma_adc.ossfragshift = s->dma_dac.ossfragshift;
2663                                 s->dma_adc.ossmaxfrags = s->dma_dac.ossmaxfrags;
2664                         }
2665                 }
2666                 return 0;
2667
2668         case SNDCTL_DSP_SUBDIVIDE:
2669                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
2670                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
2671                         return -EINVAL;
2672                 if (get_user(val, p))
2673                         return -EFAULT;
2674                 if (val != 1 && val != 2 && val != 4)
2675                         return -EINVAL;
2676                 if (file->f_mode & FMODE_READ)
2677                         s->dma_adc.subdivision = val;
2678                 if (file->f_mode & FMODE_WRITE) {
2679                         s->dma_dac.subdivision = val;
2680                         if (s->status & DO_DUAL_DAC)
2681                                 s->dma_adc.subdivision = val;
2682                 }
2683                 return 0;
2684
2685         case SOUND_PCM_READ_RATE:
2686                 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
2687
2688         case SOUND_PCM_READ_CHANNELS:
2689                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_STEREO << CM_CFMT_ADCSHIFT) : (CM_CFMT_STEREO << CM_CFMT_DACSHIFT))) ? 2 : 1, p);
2690
2691         case SOUND_PCM_READ_BITS:
2692                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_16BIT << CM_CFMT_ADCSHIFT) : (CM_CFMT_16BIT << CM_CFMT_DACSHIFT))) ? 16 : 8, p);
2693
2694         case SOUND_PCM_READ_FILTER:
2695                 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
2696
2697         case SNDCTL_DSP_GETCHANNELMASK:
2698                 return put_user(DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE|DSP_BIND_SPDIF, p);
2699
2700         case SNDCTL_DSP_BIND_CHANNEL:
2701                 if (get_user(val, p))
2702                         return -EFAULT;
2703                 if (val == DSP_BIND_QUERY) {
2704                         val = DSP_BIND_FRONT;
2705                         if (s->status & DO_SPDIF_OUT)
2706                                 val |= DSP_BIND_SPDIF;
2707                         else {
2708                                 if (s->curr_channels == 4)
2709                                         val |= DSP_BIND_SURR;
2710                                 if (s->curr_channels > 4)
2711                                         val |= DSP_BIND_CENTER_LFE;
2712                         }
2713                 } else {
2714                         if (file->f_mode & FMODE_READ) {
2715                                 stop_adc(s);
2716                                 s->dma_adc.ready = 0;
2717                                 if (val & DSP_BIND_SPDIF) {
2718                                         set_spdifin(s, s->rateadc);
2719                                         if (!(s->status & DO_SPDIF_OUT))
2720                                                 val &= ~DSP_BIND_SPDIF;
2721                                 }
2722                         }
2723                         if (file->f_mode & FMODE_WRITE) {
2724                                 stop_dac(s);
2725                                 s->dma_dac.ready = 0;
2726                                 if (val & DSP_BIND_SPDIF) {
2727                                         set_spdifout(s, s->ratedac);
2728                                         set_dac_channels(s, s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1);
2729                                         if (!(s->status & DO_SPDIF_OUT))
2730                                                 val &= ~DSP_BIND_SPDIF;
2731                                 } else {
2732                                         int channels;
2733                                         int mask;
2734
2735                                         mask = val & (DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE);
2736                                         switch (mask) {
2737                                             case DSP_BIND_FRONT:
2738                                                 channels = 2;
2739                                                 break;
2740                                             case DSP_BIND_FRONT|DSP_BIND_SURR:
2741                                                 channels = 4;
2742                                                 break;
2743                                             case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2744                                                 channels = 6;
2745                                                 break;
2746                                             default:
2747                                                 channels = s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1;
2748                                                 break;
2749                                         }
2750                                         set_dac_channels(s, channels);
2751                                 }
2752                         }
2753                 }
2754                 return put_user(val, p);
2755
2756         case SOUND_PCM_WRITE_FILTER:
2757         case SNDCTL_DSP_MAPINBUF:
2758         case SNDCTL_DSP_MAPOUTBUF:
2759         case SNDCTL_DSP_SETSYNCRO:
2760                 return -EINVAL;
2761         case SNDCTL_SPDIF_COPYRIGHT:
2762                 if (get_user(val, p))
2763                         return -EFAULT;
2764                 set_spdif_copyright(s, val);
2765                 return 0;
2766         case SNDCTL_SPDIF_LOOP:
2767                 if (get_user(val, p))
2768                         return -EFAULT;
2769                 set_spdif_loop(s, val);
2770                 return 0;
2771         case SNDCTL_SPDIF_MONITOR:
2772                 if (get_user(val, p))
2773                         return -EFAULT;
2774                 set_spdif_monitor(s, val);
2775                 return 0;
2776         case SNDCTL_SPDIF_LEVEL:
2777                 if (get_user(val, p))
2778                         return -EFAULT;
2779                 set_spdifout_level(s, val);
2780                 return 0;
2781         case SNDCTL_SPDIF_INV:
2782                 if (get_user(val, p))
2783                         return -EFAULT;
2784                 set_spdifin_inverse(s, val);
2785                 return 0;
2786         case SNDCTL_SPDIF_SEL2:
2787                 if (get_user(val, p))
2788                         return -EFAULT;
2789                 set_spdifin_channel2(s, val);
2790                 return 0;
2791         case SNDCTL_SPDIF_VALID:
2792                 if (get_user(val, p))
2793                         return -EFAULT;
2794                 set_spdifin_valid(s, val);
2795                 return 0;
2796         case SNDCTL_SPDIFOUT:
2797                 if (get_user(val, p))
2798                         return -EFAULT;
2799                 set_spdifout(s, val ? s->ratedac : 0);
2800                 return 0;
2801         case SNDCTL_SPDIFIN:
2802                 if (get_user(val, p))
2803                         return -EFAULT;
2804                 set_spdifin(s, val ? s->rateadc : 0);
2805                 return 0;
2806         }
2807         return mixer_ioctl(s, cmd, arg);
2808 }
2809
2810 static int cm_open(struct inode *inode, struct file *file)
2811 {
2812         int minor = iminor(inode);
2813         DECLARE_WAITQUEUE(wait, current);
2814         unsigned char fmtm = ~0, fmts = 0;
2815         struct list_head *list;
2816         struct cm_state *s;
2817
2818         for (list = devs.next; ; list = list->next) {
2819                 if (list == &devs)
2820                         return -ENODEV;
2821                 s = list_entry(list, struct cm_state, devs);
2822                 if (!((s->dev_audio ^ minor) & ~0xf))
2823                         break;
2824         }
2825         VALIDATE_STATE(s);
2826         file->private_data = s;
2827         /* wait for device to become free */
2828         down(&s->open_sem);
2829         while (s->open_mode & file->f_mode) {
2830                 if (file->f_flags & O_NONBLOCK) {
2831                         up(&s->open_sem);
2832                         return -EBUSY;
2833                 }
2834                 add_wait_queue(&s->open_wait, &wait);
2835                 __set_current_state(TASK_INTERRUPTIBLE);
2836                 up(&s->open_sem);
2837                 schedule();
2838                 remove_wait_queue(&s->open_wait, &wait);
2839                 set_current_state(TASK_RUNNING);
2840                 if (signal_pending(current))
2841                         return -ERESTARTSYS;
2842                 down(&s->open_sem);
2843         }
2844         if (file->f_mode & FMODE_READ) {
2845                 s->status &= ~DO_BIGENDIAN_R;
2846                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_ADCSHIFT);
2847                 if ((minor & 0xf) == SND_DEV_DSP16)
2848                         fmts |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
2849                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2850                 s->dma_adc.enabled = 1;
2851                 set_adc_rate(s, 8000);
2852                 // spdif-in is turnned off by default
2853                 set_spdifin(s, 0);
2854         }
2855         if (file->f_mode & FMODE_WRITE) {
2856                 s->status &= ~DO_BIGENDIAN_W;
2857                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_DACSHIFT);
2858                 if ((minor & 0xf) == SND_DEV_DSP16)
2859                         fmts |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
2860                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2861                 s->dma_dac.enabled = 1;
2862                 set_dac_rate(s, 8000);
2863                 // clear previous multichannel, spdif, ac3 state
2864                 set_spdifout(s, 0);
2865                 set_ac3(s, 0);
2866                 set_dac_channels(s, 1);
2867         }
2868         set_fmt(s, fmtm, fmts);
2869         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2870         up(&s->open_sem);
2871         return nonseekable_open(inode, file);
2872 }
2873
2874 static int cm_release(struct inode *inode, struct file *file)
2875 {
2876         struct cm_state *s = (struct cm_state *)file->private_data;
2877
2878         VALIDATE_STATE(s);
2879         lock_kernel();
2880         if (file->f_mode & FMODE_WRITE)
2881                 drain_dac(s, file->f_flags & O_NONBLOCK);
2882         down(&s->open_sem);
2883         if (file->f_mode & FMODE_WRITE) {
2884                 stop_dac(s);
2885
2886                 dealloc_dmabuf(s, &s->dma_dac);
2887                 if (s->status & DO_DUAL_DAC)
2888                         dealloc_dmabuf(s, &s->dma_adc);
2889
2890                 if (s->status & DO_MULTI_CH)
2891                         set_dac_channels(s, 1);
2892                 if (s->status & DO_AC3)
2893                         set_ac3(s, 0);
2894                 if (s->status & DO_SPDIF_OUT)
2895                         set_spdifout(s, 0);
2896                 /* enable SPDIF loop */
2897                 set_spdif_loop(s, spdif_loop);
2898                 s->status &= ~DO_BIGENDIAN_W;
2899         }
2900         if (file->f_mode & FMODE_READ) {
2901                 stop_adc(s);
2902                 dealloc_dmabuf(s, &s->dma_adc);
2903                 s->status &= ~DO_BIGENDIAN_R;
2904         }
2905         s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2906         up(&s->open_sem);
2907         wake_up(&s->open_wait);
2908         unlock_kernel();
2909         return 0;
2910 }
2911
2912 static /*const*/ struct file_operations cm_audio_fops = {
2913         .owner   = THIS_MODULE,
2914         .llseek  = no_llseek,
2915         .read    = cm_read,
2916         .write   = cm_write,
2917         .poll    = cm_poll,
2918         .ioctl   = cm_ioctl,
2919         .mmap    = cm_mmap,
2920         .open    = cm_open,
2921         .release = cm_release,
2922 };
2923
2924 /* --------------------------------------------------------------------- */
2925
2926 static struct initvol {
2927         int mixch;
2928         int vol;
2929 } initvol[] __devinitdata = {
2930         { SOUND_MIXER_WRITE_CD, 0x4f4f },
2931         { SOUND_MIXER_WRITE_LINE, 0x4f4f },
2932         { SOUND_MIXER_WRITE_MIC, 0x4f4f },
2933         { SOUND_MIXER_WRITE_SYNTH, 0x4f4f },
2934         { SOUND_MIXER_WRITE_VOLUME, 0x4f4f },
2935         { SOUND_MIXER_WRITE_PCM, 0x4f4f }
2936 };
2937
2938 /* check chip version and capability */
2939 static int query_chip(struct cm_state *s)
2940 {
2941         int ChipVersion = -1;
2942         unsigned char RegValue;
2943
2944         // check reg 0Ch, bit 24-31
2945         RegValue = inb(s->iobase + CODEC_CMI_INT_HLDCLR + 3);
2946         if (RegValue == 0) {
2947             // check reg 08h, bit 24-28
2948             RegValue = inb(s->iobase + CODEC_CMI_CHFORMAT + 3);
2949             RegValue &= 0x1f;
2950             if (RegValue == 0) {
2951                 ChipVersion = 33;
2952                 s->max_channels = 4;
2953                 s->capability |= CAN_AC3_SW;
2954                 s->capability |= CAN_DUAL_DAC;
2955             } else {
2956                 ChipVersion = 37;
2957                 s->max_channels = 4;
2958                 s->capability |= CAN_AC3_HW;
2959                 s->capability |= CAN_DUAL_DAC;
2960             }
2961         } else {
2962             // check reg 0Ch, bit 26
2963             if (RegValue & (1 << (26-24))) {
2964                 ChipVersion = 39;
2965                 if (RegValue & (1 << (24-24)))
2966                     s->max_channels = 6;
2967                 else
2968                     s->max_channels = 4;
2969                 s->capability |= CAN_AC3_HW;
2970                 s->capability |= CAN_DUAL_DAC;
2971                 s->capability |= CAN_MULTI_CH_HW;
2972                 s->capability |= CAN_LINE_AS_BASS;
2973                 s->capability |= CAN_MIC_AS_BASS;
2974             } else {
2975                 ChipVersion = 55; // 4 or 6 channels
2976                 s->max_channels = 6;
2977                 s->capability |= CAN_AC3_HW;
2978                 s->capability |= CAN_DUAL_DAC;
2979                 s->capability |= CAN_MULTI_CH_HW;
2980                 s->capability |= CAN_LINE_AS_BASS;
2981                 s->capability |= CAN_MIC_AS_BASS;
2982             }
2983         }
2984         s->capability |= CAN_LINE_AS_REAR;
2985         return ChipVersion;
2986 }
2987
2988 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
2989 static int __devinit cm_create_gameport(struct cm_state *s, int io_port)
2990 {
2991         struct gameport *gp;
2992
2993         if (!request_region(io_port, CM_EXTENT_GAME, "cmpci GAME")) {
2994                 printk(KERN_ERR "cmpci: gameport io ports 0x%#x in use\n", io_port);
2995                 return -EBUSY;
2996         }
2997
2998         if (!(s->gameport = gp = gameport_allocate_port())) {
2999                 printk(KERN_ERR "cmpci: can not allocate memory for gameport\n");
3000                 release_region(io_port, CM_EXTENT_GAME);
3001                 return -ENOMEM;
3002         }
3003
3004         gameport_set_name(gp, "C-Media GP");
3005         gameport_set_phys(gp, "pci%s/gameport0", pci_name(s->dev));
3006         gp->dev.parent = &s->dev->dev;
3007         gp->io = io_port;
3008
3009         /* enable joystick */
3010         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x02);
3011
3012         gameport_register_port(gp);
3013
3014         return 0;
3015 }
3016
3017 static void __devexit cm_free_gameport(struct cm_state *s)
3018 {
3019         if (s->gameport) {
3020                 int gpio = s->gameport->io;
3021
3022                 gameport_unregister_port(s->gameport);
3023                 s->gameport = NULL;
3024                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x02, 0);
3025                 release_region(gpio, CM_EXTENT_GAME);
3026         }
3027 }
3028 #else
3029 static inline int cm_create_gameport(struct cm_state *s, int io_port) { return -ENOSYS; }
3030 static inline void cm_free_gameport(struct cm_state *s) { }
3031 #endif
3032
3033 #define echo_option(x)\
3034 if (x) strcat(options, "" #x " ")
3035
3036 static int __devinit cm_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
3037 {
3038         struct cm_state *s;
3039         mm_segment_t fs;
3040         int i, val, ret;
3041         unsigned char reg_mask;
3042         int timeout;
3043         struct resource *ports;
3044         struct {
3045                 unsigned short  deviceid;
3046                 char            *devicename;
3047         } devicetable[] = {
3048                 { PCI_DEVICE_ID_CMEDIA_CM8338A, "CM8338A" },
3049                 { PCI_DEVICE_ID_CMEDIA_CM8338B, "CM8338B" },
3050                 { PCI_DEVICE_ID_CMEDIA_CM8738,  "CM8738" },
3051                 { PCI_DEVICE_ID_CMEDIA_CM8738B, "CM8738B" },
3052         };
3053         char    *devicename = "unknown";
3054         char    options[256];
3055
3056         if ((ret = pci_enable_device(pcidev)))
3057                 return ret;
3058         if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
3059                 return -ENODEV;
3060         if (pcidev->irq == 0)
3061                 return -ENODEV;
3062         i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
3063         if (i) {
3064                 printk(KERN_WARNING "cmpci: architecture does not support 32bit PCI busmaster DMA\n");
3065                 return i;
3066         }
3067         s = kmalloc(sizeof(*s), GFP_KERNEL);
3068         if (!s) {
3069                 printk(KERN_WARNING "cmpci: out of memory\n");
3070                 return -ENOMEM;
3071         }
3072         /* search device name */
3073         for (i = 0; i < sizeof(devicetable) / sizeof(devicetable[0]); i++) {
3074                 if (devicetable[i].deviceid == pcidev->device) {
3075                         devicename = devicetable[i].devicename;
3076                         break;
3077                 }
3078         }
3079         memset(s, 0, sizeof(struct cm_state));
3080         init_waitqueue_head(&s->dma_adc.wait);
3081         init_waitqueue_head(&s->dma_dac.wait);
3082         init_waitqueue_head(&s->open_wait);
3083         init_MUTEX(&s->open_sem);
3084         spin_lock_init(&s->lock);
3085         s->magic = CM_MAGIC;
3086         s->dev = pcidev;
3087         s->iobase = pci_resource_start(pcidev, 0);
3088         s->iosynth = fmio;
3089         s->iomidi = mpuio;
3090 #ifdef CONFIG_SOUND_CMPCI_MIDI
3091         s->midi_devc = 0;
3092 #endif
3093         s->status = 0;
3094         if (s->iobase == 0)
3095                 return -ENODEV;
3096         s->irq = pcidev->irq;
3097
3098         if (!request_region(s->iobase, CM_EXTENT_CODEC, "cmpci")) {
3099                 printk(KERN_ERR "cmpci: io ports %#x-%#x in use\n", s->iobase, s->iobase+CM_EXTENT_CODEC-1);
3100                 ret = -EBUSY;
3101                 goto err_region5;
3102         }
3103         /* dump parameters */
3104         strcpy(options, "cmpci: ");
3105         echo_option(joystick);
3106         echo_option(spdif_inverse);
3107         echo_option(spdif_loop);
3108         echo_option(spdif_out);
3109         echo_option(use_line_as_rear);
3110         echo_option(use_line_as_bass);
3111         echo_option(use_mic_as_bass);
3112         echo_option(mic_boost);
3113         echo_option(hw_copy);
3114         printk(KERN_INFO "%s\n", options);
3115
3116         /* initialize codec registers */
3117         outb(0, s->iobase + CODEC_CMI_INT_HLDCLR + 2);  /* disable ints */
3118         outb(0, s->iobase + CODEC_CMI_FUNCTRL0 + 2); /* disable channels */
3119         /* reset mixer */
3120         wrmixer(s, DSP_MIX_DATARESETIDX, 0);
3121
3122         /* request irq */
3123         if ((ret = request_irq(s->irq, cm_interrupt, SA_SHIRQ, "cmpci", s))) {
3124                 printk(KERN_ERR "cmpci: irq %u in use\n", s->irq);
3125                 goto err_irq;
3126         }
3127         printk(KERN_INFO "cmpci: found %s adapter at io %#x irq %u\n",
3128                devicename, s->iobase, s->irq);
3129         /* register devices */
3130         if ((s->dev_audio = register_sound_dsp(&cm_audio_fops, -1)) < 0) {
3131                 ret = s->dev_audio;
3132                 goto err_dev1;
3133         }
3134         if ((s->dev_mixer = register_sound_mixer(&cm_mixer_fops, -1)) < 0) {
3135                 ret = s->dev_mixer;
3136                 goto err_dev2;
3137         }
3138         pci_set_master(pcidev); /* enable bus mastering */
3139         /* initialize the chips */
3140         fs = get_fs();
3141         set_fs(KERNEL_DS);
3142         /* set mixer output */
3143         frobindir(s, DSP_MIX_OUTMIXIDX, 0x1f, 0x1f);
3144         /* set mixer input */
3145         val = SOUND_MASK_LINE|SOUND_MASK_SYNTH|SOUND_MASK_CD|SOUND_MASK_MIC;
3146         mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
3147         for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
3148                 val = initvol[i].vol;
3149                 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
3150         }
3151         set_fs(fs);
3152         /* use channel 1 for playback, channel 0 for record */
3153         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC1, CHADC0);
3154         /* turn off VMIC3 - mic boost */
3155         if (mic_boost)
3156                 maskb(s->iobase + CODEC_CMI_MIXER2, ~1, 0);
3157         else
3158                 maskb(s->iobase + CODEC_CMI_MIXER2, ~0, 1);
3159         s->deviceid = pcidev->device;
3160
3161         if (pcidev->device == PCI_DEVICE_ID_CMEDIA_CM8738
3162          || pcidev->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
3163
3164                 /* chip version and hw capability check */
3165                 s->chip_version = query_chip(s);
3166                 printk(KERN_INFO "cmpci: chip version = 0%d\n", s->chip_version);
3167
3168                 /* set SPDIF-in inverse before enable SPDIF loop */
3169                 set_spdifin_inverse(s, spdif_inverse);
3170
3171                 /* use SPDIF in #1 */
3172                 set_spdifin_channel2(s, 0);
3173         } else {
3174                 s->chip_version = 0;
3175                 /* 8338 will fall here */
3176                 s->max_channels = 4;
3177                 s->capability |= CAN_DUAL_DAC;
3178                 s->capability |= CAN_LINE_AS_REAR;
3179         }
3180         /* enable SPDIF loop */
3181         set_spdif_loop(s, spdif_loop);
3182
3183         // enable 4 speaker mode (analog duplicate)
3184         set_hw_copy(s, hw_copy);
3185
3186         reg_mask = 0;
3187 #ifdef CONFIG_SOUND_CMPCI_FM
3188         /* disable FM */
3189         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3190         if (s->iosynth) {
3191             /* don't enable OPL3 if there is one */
3192             if (opl3_detect(s->iosynth, NULL)) {
3193                 s->iosynth = 0;
3194             } else {
3195                 /* set IO based at 0x388 */
3196                 switch (s->iosynth) {
3197                     case 0x388:
3198                         reg_mask = 0;
3199                         break;
3200                     case 0x3C8:
3201                         reg_mask = 0x01;
3202                         break;
3203                     case 0x3E0:
3204                         reg_mask = 0x02;
3205                         break;
3206                     case 0x3E8:
3207                         reg_mask = 0x03;
3208                         break;
3209                     default:
3210                         s->iosynth = 0;
3211                         break;
3212                 }
3213                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0x03, reg_mask);
3214                 /* enable FM */
3215                 if (s->iosynth) {
3216                         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, 8);
3217                         if (opl3_detect(s->iosynth, NULL))
3218                                 ret = opl3_init(s->iosynth, NULL, THIS_MODULE);
3219                         else {
3220                                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3221                                 s->iosynth = 0;
3222                         }
3223                 }
3224             }
3225         }
3226 #endif
3227 #ifdef CONFIG_SOUND_CMPCI_MIDI
3228         switch (s->iomidi) {
3229             case 0x330:
3230                 reg_mask = 0;
3231                 break;
3232             case 0x320:
3233                 reg_mask = 0x20;
3234                 break;
3235             case 0x310:
3236                 reg_mask = 0x40;
3237                 break;
3238             case 0x300:
3239                 reg_mask = 0x60;
3240                 break;
3241             default:
3242                 s->iomidi = 0;
3243                 goto skip_mpu;
3244         }
3245         ports = request_region(s->iomidi, 2, "mpu401");
3246         if (!ports)
3247                 goto skip_mpu;
3248         /* disable MPU-401 */
3249         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x04, 0);
3250         s->mpu_data.name = "cmpci mpu";
3251         s->mpu_data.io_base = s->iomidi;
3252         s->mpu_data.irq = -s->irq;      // tell mpu401 to share irq
3253         if (probe_mpu401(&s->mpu_data, ports)) {
3254                 release_region(s->iomidi, 2);
3255                 s->iomidi = 0;
3256                 goto skip_mpu;
3257         }
3258         maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0x60, reg_mask);
3259         /* enable MPU-401 */
3260         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x04);
3261         /* clear all previously received interrupt */
3262         for (timeout = 900000; timeout > 0; timeout--) {
3263                 if ((inb(s->iomidi + 1) && 0x80) == 0)
3264                         inb(s->iomidi);
3265                 else
3266                         break;
3267         }
3268         if (!probe_mpu401(&s->mpu_data, ports)) {
3269                 release_region(s->iomidi, 2);
3270                 s->iomidi = 0;
3271                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x04);
3272         } else {
3273                 attach_mpu401(&s->mpu_data, THIS_MODULE);
3274                 s->midi_devc = s->mpu_data.slots[1];
3275         }
3276 skip_mpu:
3277 #endif
3278         /* disable joystick port */
3279         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x02, 0);
3280         if (joystick)
3281                 cm_create_gameport(s, 0x200);
3282
3283         /* store it in the driver field */
3284         pci_set_drvdata(pcidev, s);
3285         /* put it into driver list */
3286         list_add_tail(&s->devs, &devs);
3287         /* increment devindex */
3288         if (devindex < NR_DEVICE-1)
3289                 devindex++;
3290         return 0;
3291
3292 err_dev2:
3293         unregister_sound_dsp(s->dev_audio);
3294 err_dev1:
3295         printk(KERN_ERR "cmpci: cannot register misc device\n");
3296         free_irq(s->irq, s);
3297 err_irq:
3298         release_region(s->iobase, CM_EXTENT_CODEC);
3299 err_region5:
3300         kfree(s);
3301         return ret;
3302 }
3303
3304 /* --------------------------------------------------------------------- */
3305
3306 MODULE_AUTHOR("ChenLi Tien, cltien@cmedia.com.tw");
3307 MODULE_DESCRIPTION("CM8x38 Audio Driver");
3308 MODULE_LICENSE("GPL");
3309
3310 static void __devexit cm_remove(struct pci_dev *dev)
3311 {
3312         struct cm_state *s = pci_get_drvdata(dev);
3313
3314         if (!s)
3315                 return;
3316
3317         cm_free_gameport(s);
3318
3319 #ifdef CONFIG_SOUND_CMPCI_FM
3320         if (s->iosynth) {
3321                 /* disable FM */
3322                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3323         }
3324 #endif
3325 #ifdef CONFIG_SOUND_CMPCI_MIDI
3326         if (s->iomidi) {
3327                 unload_mpu401(&s->mpu_data);
3328                 /* disable MPU-401 */
3329                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x04, 0);
3330         }
3331 #endif
3332         set_spdif_loop(s, 0);
3333         list_del(&s->devs);
3334         outb(0, s->iobase + CODEC_CMI_INT_HLDCLR + 2);  /* disable ints */
3335         synchronize_irq(s->irq);
3336         outb(0, s->iobase + CODEC_CMI_FUNCTRL0 + 2); /* disable channels */
3337         free_irq(s->irq, s);
3338
3339         /* reset mixer */
3340         wrmixer(s, DSP_MIX_DATARESETIDX, 0);
3341
3342         release_region(s->iobase, CM_EXTENT_CODEC);
3343         unregister_sound_dsp(s->dev_audio);
3344         unregister_sound_mixer(s->dev_mixer);
3345         kfree(s);
3346         pci_set_drvdata(dev, NULL);
3347 }
3348
3349 static struct pci_device_id id_table[] __devinitdata = {
3350         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3351         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3352         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3353         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3354         { 0, }
3355 };
3356
3357 MODULE_DEVICE_TABLE(pci, id_table);
3358
3359 static struct pci_driver cm_driver = {
3360        .name     = "cmpci",
3361        .id_table = id_table,
3362        .probe    = cm_probe,
3363        .remove   = __devexit_p(cm_remove)
3364 };
3365
3366 static int __init init_cmpci(void)
3367 {
3368         printk(KERN_INFO "cmpci: version $Revision: 6.82 $ time " __TIME__ " " __DATE__ "\n");
3369         return pci_module_init(&cm_driver);
3370 }
3371
3372 static void __exit cleanup_cmpci(void)
3373 {
3374         printk(KERN_INFO "cmpci: unloading\n");
3375         pci_unregister_driver(&cm_driver);
3376 }
3377
3378 module_init(init_cmpci);
3379 module_exit(cleanup_cmpci);