sound/oss/au1550_ac97.c

   1 /*
   2  * au1550_ac97.c  --  Sound driver for Alchemy Au1550 MIPS Internet Edge
   3  *                    Processor.
   4  *
   5  * Copyright 2004 Embedded Edge, LLC
   6  *      dan@embeddededge.com
   7  *
   8  * Mostly copied from the au1000.c driver and some from the
   9  * PowerMac dbdma driver.
  10  * We assume the processor can do memory coherent DMA.
  11  *
  12  * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
  13  *
  14  *  This program is free software; you can redistribute  it and/or modify it
  15  *  under  the terms of  the GNU General  Public License as published by the
  16  *  Free Software Foundation;  either version 2 of the  License, or (at your
  17  *  option) any later version.
  18  *
  19  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  20  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  21  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  22  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  23  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  25  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  27  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  *  You should have received a copy of the  GNU General Public License along
  31  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  32  *  675 Mass Ave, Cambridge, MA 02139, USA.
  33  *
  34  */
  35
  36 #undef DEBUG
  37
  38 #include <linux/version.h>
  39 #include <linux/module.h>
  40 #include <linux/string.h>
  41 #include <linux/ioport.h>
  42 #include <linux/sched.h>
  43 #include <linux/delay.h>
  44 #include <linux/sound.h>
  45 #include <linux/slab.h>
  46 #include <linux/soundcard.h>
  47 #include <linux/init.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/kernel.h>
  50 #include <linux/poll.h>
  51 #include <linux/pci.h>
  52 #include <linux/bitops.h>
  53 #include <linux/spinlock.h>
  54 #include <linux/smp_lock.h>
  55 #include <linux/ac97_codec.h>
  56 #include <asm/io.h>
  57 #include <asm/uaccess.h>
  58 #include <asm/hardirq.h>
  59 #include <asm/mach-au1x00/au1000.h>
  60 #include <asm/mach-au1x00/au1xxx_psc.h>
  61 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  62
  63 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  64
  65 /* misc stuff */
  66 #define POLL_COUNT   0x50000
  67 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  68
  69 /* The number of DBDMA ring descriptors to allocate.  No sense making
  70  * this too large....if you can't keep up with a few you aren't likely
  71  * to be able to with lots of them, either.
  72  */
  73 #define NUM_DBDMA_DESCRIPTORS 4
  74
  75 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
  76
  77 /* Boot options
  78  * 0 = no VRA, 1 = use VRA if codec supports it
  79  */
  80 static int      vra = 1;
  81 MODULE_PARM(vra, "i");
  82 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  83
  84 static struct au1550_state {
  85         /* soundcore stuff */
  86         int             dev_audio;
  87
  88         struct ac97_codec *codec;
  89         unsigned        codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
  90         unsigned        codec_ext_caps;  /* AC'97 reg 28h, "Extended Audio ID" */
  91         int             no_vra;         /* do not use VRA */
  92
  93         spinlock_t      lock;
  94         struct semaphore open_sem;
  95         struct semaphore sem;
  96         mode_t          open_mode;
  97         wait_queue_head_t open_wait;
  98
  99         struct dmabuf {
 100                 u32             dmanr;
 101                 unsigned        sample_rate;
 102                 unsigned        src_factor;
 103                 unsigned        sample_size;
 104                 int             num_channels;
 105                 int             dma_bytes_per_sample;
 106                 int             user_bytes_per_sample;
 107                 int             cnt_factor;
 108
 109                 void            *rawbuf;
 110                 unsigned        buforder;
 111                 unsigned        numfrag;
 112                 unsigned        fragshift;
 113                 void            *nextIn;
 114                 void            *nextOut;
 115                 int             count;
 116                 unsigned        total_bytes;
 117                 unsigned        error;
 118                 wait_queue_head_t wait;
 119
 120                 /* redundant, but makes calculations easier */
 121                 unsigned        fragsize;
 122                 unsigned        dma_fragsize;
 123                 unsigned        dmasize;
 124                 unsigned        dma_qcount;
 125
 126                 /* OSS stuff */
 127                 unsigned        mapped:1;
 128                 unsigned        ready:1;
 129                 unsigned        stopped:1;
 130                 unsigned        ossfragshift;
 131                 int             ossmaxfrags;
 132                 unsigned        subdivision;
 133         } dma_dac, dma_adc;
 134 } au1550_state;
 135
 136 static unsigned
 137 ld2(unsigned int x)
 138 {
 139         unsigned        r = 0;
 140
 141         if (x >= 0x10000) {
 142                 x >>= 16;
 143                 r += 16;
 144         }
 145         if (x >= 0x100) {
 146                 x >>= 8;
 147                 r += 8;
 148         }
 149         if (x >= 0x10) {
 150                 x >>= 4;
 151                 r += 4;
 152         }
 153         if (x >= 4) {
 154                 x >>= 2;
 155                 r += 2;
 156         }
 157         if (x >= 2)
 158                 r++;
 159         return r;
 160 }
 161
 162 static void
 163 au1550_delay(int msec)
 164 {
 165         unsigned long   tmo;
 166         signed long     tmo2;
 167
 168         if (in_interrupt())
 169                 return;
 170
 171         tmo = jiffies + (msec * HZ) / 1000;
 172         for (;;) {
 173                 tmo2 = tmo - jiffies;
 174                 if (tmo2 <= 0)
 175                         break;
 176                 schedule_timeout(tmo2);
 177         }
 178 }
 179
 180 static u16
 181 rdcodec(struct ac97_codec *codec, u8 addr)
 182 {
 183         struct au1550_state *s = (struct au1550_state *)codec->private_data;
 184         unsigned long   flags;
 185         u32             cmd, val;
 186         u16             data;
 187         int             i;
 188
 189         spin_lock_irqsave(&s->lock, flags);
 190
 191         for (i = 0; i < POLL_COUNT; i++) {
 192                 val = au_readl(PSC_AC97STAT);
 193                 au_sync();
 194                 if (!(val & PSC_AC97STAT_CP))
 195                         break;
 196         }
 197         if (i == POLL_COUNT)
 198                 err("rdcodec: codec cmd pending expired!");
 199
 200         cmd = (u32)PSC_AC97CDC_INDX(addr);
 201         cmd |= PSC_AC97CDC_RD;  /* read command */
 202         au_writel(cmd, PSC_AC97CDC);
 203         au_sync();
 204
 205         /* now wait for the data
 206         */
 207         for (i = 0; i < POLL_COUNT; i++) {
 208                 val = au_readl(PSC_AC97STAT);
 209                 au_sync();
 210                 if (!(val & PSC_AC97STAT_CP))
 211                         break;
 212         }
 213         if (i == POLL_COUNT) {
 214                 err("rdcodec: read poll expired!");
 215                 return 0;
 216         }
 217
 218         /* wait for command done?
 219         */
 220         for (i = 0; i < POLL_COUNT; i++) {
 221                 val = au_readl(PSC_AC97EVNT);
 222                 au_sync();
 223                 if (val & PSC_AC97EVNT_CD)
 224                         break;
 225         }
 226         if (i == POLL_COUNT) {
 227                 err("rdcodec: read cmdwait expired!");
 228                 return 0;
 229         }
 230
 231         data = au_readl(PSC_AC97CDC) & 0xffff;
 232         au_sync();
 233
 234         /* Clear command done event.
 235         */
 236         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
 237         au_sync();
 238
 239         spin_unlock_irqrestore(&s->lock, flags);
 240
 241         return data;
 242 }
 243
 244
 245 static void
 246 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
 247 {
 248         struct au1550_state *s = (struct au1550_state *)codec->private_data;
 249         unsigned long   flags;
 250         u32             cmd, val;
 251         int             i;
 252
 253         spin_lock_irqsave(&s->lock, flags);
 254
 255         for (i = 0; i < POLL_COUNT; i++) {
 256                 val = au_readl(PSC_AC97STAT);
 257                 au_sync();
 258                 if (!(val & PSC_AC97STAT_CP))
 259                         break;
 260         }
 261         if (i == POLL_COUNT)
 262                 err("wrcodec: codec cmd pending expired!");
 263
 264         cmd = (u32)PSC_AC97CDC_INDX(addr);
 265         cmd |= (u32)data;
 266         au_writel(cmd, PSC_AC97CDC);
 267         au_sync();
 268
 269         for (i = 0; i < POLL_COUNT; i++) {
 270                 val = au_readl(PSC_AC97STAT);
 271                 au_sync();
 272                 if (!(val & PSC_AC97STAT_CP))
 273                         break;
 274         }
 275         if (i == POLL_COUNT)
 276                 err("wrcodec: codec cmd pending expired!");
 277
 278         for (i = 0; i < POLL_COUNT; i++) {
 279                 val = au_readl(PSC_AC97EVNT);
 280                 au_sync();
 281                 if (val & PSC_AC97EVNT_CD)
 282                         break;
 283         }
 284         if (i == POLL_COUNT)
 285                 err("wrcodec: read cmdwait expired!");
 286
 287         /* Clear command done event.
 288         */
 289         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
 290         au_sync();
 291
 292         spin_unlock_irqrestore(&s->lock, flags);
 293 }
 294
 295 static void
 296 waitcodec(struct ac97_codec *codec)
 297 {
 298         u16     temp;
 299         u32     val;
 300         int     i;
 301
 302         /* codec_wait is used to wait for a ready state after
 303          * an AC97C_RESET.
 304          */
 305         au1550_delay(10);
 306
 307         /* first poll the CODEC_READY tag bit
 308         */
 309         for (i = 0; i < POLL_COUNT; i++) {
 310                 val = au_readl(PSC_AC97STAT);
 311                 au_sync();
 312                 if (val & PSC_AC97STAT_CR)
 313                         break;
 314         }
 315         if (i == POLL_COUNT) {
 316                 err("waitcodec: CODEC_READY poll expired!");
 317                 return;
 318         }
 319
 320         /* get AC'97 powerdown control/status register
 321         */
 322         temp = rdcodec(codec, AC97_POWER_CONTROL);
 323
 324         /* If anything is powered down, power'em up
 325         */
 326         if (temp & 0x7f00) {
 327                 /* Power on
 328                 */
 329                 wrcodec(codec, AC97_POWER_CONTROL, 0);
 330                 au1550_delay(100);
 331
 332                 /* Reread
 333                 */
 334                 temp = rdcodec(codec, AC97_POWER_CONTROL);
 335         }
 336
 337         /* Check if Codec REF,ANL,DAC,ADC ready
 338         */
 339         if ((temp & 0x7f0f) != 0x000f)
 340                 err("codec reg 26 status (0x%x) not ready!!", temp);
 341 }
 342
 343 /* stop the ADC before calling */
 344 static void
 345 set_adc_rate(struct au1550_state *s, unsigned rate)
 346 {
 347         struct dmabuf  *adc = &s->dma_adc;
 348         struct dmabuf  *dac = &s->dma_dac;
 349         unsigned        adc_rate, dac_rate;
 350         u16             ac97_extstat;
 351
 352         if (s->no_vra) {
 353                 /* calc SRC factor
 354                 */
 355                 adc->src_factor = ((96000 / rate) + 1) >> 1;
 356                 adc->sample_rate = 48000 / adc->src_factor;
 357                 return;
 358         }
 359
 360         adc->src_factor = 1;
 361
 362         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
 363
 364         rate = rate > 48000 ? 48000 : rate;
 365
 366         /* enable VRA
 367         */
 368         wrcodec(s->codec, AC97_EXTENDED_STATUS,
 369                 ac97_extstat | AC97_EXTSTAT_VRA);
 370
 371         /* now write the sample rate
 372         */
 373         wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
 374
 375         /* read it back for actual supported rate
 376         */
 377         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
 378
 379         pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
 380
 381         /* some codec's don't allow unequal DAC and ADC rates, in which case
 382          * writing one rate reg actually changes both.
 383          */
 384         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
 385         if (dac->num_channels > 2)
 386                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
 387         if (dac->num_channels > 4)
 388                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
 389
 390         adc->sample_rate = adc_rate;
 391         dac->sample_rate = dac_rate;
 392 }
 393
 394 /* stop the DAC before calling */
 395 static void
 396 set_dac_rate(struct au1550_state *s, unsigned rate)
 397 {
 398         struct dmabuf  *dac = &s->dma_dac;
 399         struct dmabuf  *adc = &s->dma_adc;
 400         unsigned        adc_rate, dac_rate;
 401         u16             ac97_extstat;
 402
 403         if (s->no_vra) {
 404                 /* calc SRC factor
 405                 */
 406                 dac->src_factor = ((96000 / rate) + 1) >> 1;
 407                 dac->sample_rate = 48000 / dac->src_factor;
 408                 return;
 409         }
 410
 411         dac->src_factor = 1;
 412
 413         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
 414
 415         rate = rate > 48000 ? 48000 : rate;
 416
 417         /* enable VRA
 418         */
 419         wrcodec(s->codec, AC97_EXTENDED_STATUS,
 420                 ac97_extstat | AC97_EXTSTAT_VRA);
 421
 422         /* now write the sample rate
 423         */
 424         wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
 425
 426         /* I don't support different sample rates for multichannel,
 427          * so make these channels the same.
 428          */
 429         if (dac->num_channels > 2)
 430                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
 431         if (dac->num_channels > 4)
 432                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
 433         /* read it back for actual supported rate
 434         */
 435         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
 436
 437         pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
 438
 439         /* some codec's don't allow unequal DAC and ADC rates, in which case
 440          * writing one rate reg actually changes both.
 441          */
 442         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
 443
 444         dac->sample_rate = dac_rate;
 445         adc->sample_rate = adc_rate;
 446 }
 447
 448 static void
 449 stop_dac(struct au1550_state *s)
 450 {
 451         struct dmabuf  *db = &s->dma_dac;
 452         u32             stat;
 453         unsigned long   flags;
 454
 455         if (db->stopped)
 456                 return;
 457
 458         spin_lock_irqsave(&s->lock, flags);
 459
 460         au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
 461         au_sync();
 462
 463         /* Wait for Transmit Busy to show disabled.
 464         */
 465         do {
 466                 stat = readl((void *)PSC_AC97STAT);
 467                 au_sync();
 468         } while ((stat & PSC_AC97STAT_TB) != 0);
 469
 470         au1xxx_dbdma_reset(db->dmanr);
 471
 472         db->stopped = 1;
 473
 474         spin_unlock_irqrestore(&s->lock, flags);
 475 }
 476
 477 static void
 478 stop_adc(struct au1550_state *s)
 479 {
 480         struct dmabuf  *db = &s->dma_adc;
 481         unsigned long   flags;
 482         u32             stat;
 483
 484         if (db->stopped)
 485                 return;
 486
 487         spin_lock_irqsave(&s->lock, flags);
 488
 489         au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
 490         au_sync();
 491
 492         /* Wait for Receive Busy to show disabled.
 493         */
 494         do {
 495                 stat = readl((void *)PSC_AC97STAT);
 496                 au_sync();
 497         } while ((stat & PSC_AC97STAT_RB) != 0);
 498
 499         au1xxx_dbdma_reset(db->dmanr);
 500
 501         db->stopped = 1;
 502
 503         spin_unlock_irqrestore(&s->lock, flags);
 504 }
 505
 506
 507 static void
 508 set_xmit_slots(int num_channels)
 509 {
 510         u32     ac97_config, stat;
 511
 512         ac97_config = au_readl(PSC_AC97CFG);
 513         au_sync();
 514         ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
 515         au_writel(ac97_config, PSC_AC97CFG);
 516         au_sync();
 517
 518         switch (num_channels) {
 519         case 6:         /* stereo with surround and center/LFE,
 520                          * slots 3,4,6,7,8,9
 521                          */
 522                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
 523                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
 524
 525         case 4:         /* stereo with surround, slots 3,4,7,8 */
 526                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
 527                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
 528
 529         case 2:         /* stereo, slots 3,4 */
 530         case 1:         /* mono */
 531                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
 532                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
 533         }
 534
 535         au_writel(ac97_config, PSC_AC97CFG);
 536         au_sync();
 537
 538         ac97_config |= PSC_AC97CFG_DE_ENABLE;
 539         au_writel(ac97_config, PSC_AC97CFG);
 540         au_sync();
 541
 542         /* Wait for Device ready.
 543         */
 544         do {
 545                 stat = readl((void *)PSC_AC97STAT);
 546                 au_sync();
 547         } while ((stat & PSC_AC97STAT_DR) == 0);
 548 }
 549
 550 static void
 551 set_recv_slots(int num_channels)
 552 {
 553         u32     ac97_config, stat;
 554
 555         ac97_config = au_readl(PSC_AC97CFG);
 556         au_sync();
 557         ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
 558         au_writel(ac97_config, PSC_AC97CFG);
 559         au_sync();
 560
 561         /* Always enable slots 3 and 4 (stereo). Slot 6 is
 562          * optional Mic ADC, which we don't support yet.
 563          */
 564         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
 565         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
 566
 567         au_writel(ac97_config, PSC_AC97CFG);
 568         au_sync();
 569
 570         ac97_config |= PSC_AC97CFG_DE_ENABLE;
 571         au_writel(ac97_config, PSC_AC97CFG);
 572         au_sync();
 573
 574         /* Wait for Device ready.
 575         */
 576         do {
 577                 stat = readl((void *)PSC_AC97STAT);
 578                 au_sync();
 579         } while ((stat & PSC_AC97STAT_DR) == 0);
 580 }
 581
 582 static void
 583 start_dac(struct au1550_state *s)
 584 {
 585         struct dmabuf  *db = &s->dma_dac;
 586         unsigned long   flags;
 587
 588         if (!db->stopped)
 589                 return;
 590
 591         spin_lock_irqsave(&s->lock, flags);
 592
 593         set_xmit_slots(db->num_channels);
 594         au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
 595         au_sync();
 596         au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
 597         au_sync();
 598
 599         au1xxx_dbdma_start(db->dmanr);
 600
 601         db->stopped = 0;
 602
 603         spin_unlock_irqrestore(&s->lock, flags);
 604 }
 605
 606 static void
 607 start_adc(struct au1550_state *s)
 608 {
 609         struct dmabuf  *db = &s->dma_adc;
 610         int     i;
 611
 612         if (!db->stopped)
 613                 return;
 614
 615         /* Put two buffers on the ring to get things started.
 616         */
 617         for (i=0; i<2; i++) {
 618                 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
 619
 620                 db->nextIn += db->dma_fragsize;
 621                 if (db->nextIn >= db->rawbuf + db->dmasize)
 622                         db->nextIn -= db->dmasize;
 623         }
 624
 625         set_recv_slots(db->num_channels);
 626         au1xxx_dbdma_start(db->dmanr);
 627         au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
 628         au_sync();
 629         au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
 630         au_sync();
 631
 632         db->stopped = 0;
 633 }
 634
 635 static int
 636 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
 637 {
 638         unsigned user_bytes_per_sec;
 639         unsigned        bufs;
 640         unsigned        rate = db->sample_rate;
 641
 642         if (!db->rawbuf) {
 643                 db->ready = db->mapped = 0;
 644                 db->buforder = 5;       /* 32 * PAGE_SIZE */
 645                 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
 646                 if (!db->rawbuf)
 647                         return -ENOMEM;
 648         }
 649
 650         db->cnt_factor = 1;
 651         if (db->sample_size == 8)
 652                 db->cnt_factor *= 2;
 653         if (db->num_channels == 1)
 654                 db->cnt_factor *= 2;
 655         db->cnt_factor *= db->src_factor;
 656
 657         db->count = 0;
 658         db->dma_qcount = 0;
 659         db->nextIn = db->nextOut = db->rawbuf;
 660
 661         db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
 662         db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
 663                                         2 : db->num_channels);
 664
 665         user_bytes_per_sec = rate * db->user_bytes_per_sample;
 666         bufs = PAGE_SIZE << db->buforder;
 667         if (db->ossfragshift) {
 668                 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
 669                         db->fragshift = ld2(user_bytes_per_sec/1000);
 670                 else
 671                         db->fragshift = db->ossfragshift;
 672         } else {
 673                 db->fragshift = ld2(user_bytes_per_sec / 100 /
 674                                     (db->subdivision ? db->subdivision : 1));
 675                 if (db->fragshift < 3)
 676                         db->fragshift = 3;
 677         }
 678
 679         db->fragsize = 1 << db->fragshift;
 680         db->dma_fragsize = db->fragsize * db->cnt_factor;
 681         db->numfrag = bufs / db->dma_fragsize;
 682
 683         while (db->numfrag < 4 && db->fragshift > 3) {
 684                 db->fragshift--;
 685                 db->fragsize = 1 << db->fragshift;
 686                 db->dma_fragsize = db->fragsize * db->cnt_factor;
 687                 db->numfrag = bufs / db->dma_fragsize;
 688         }
 689
 690         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
 691                 db->numfrag = db->ossmaxfrags;
 692
 693         db->dmasize = db->dma_fragsize * db->numfrag;
 694         memset(db->rawbuf, 0, bufs);
 695
 696         pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
 697             rate, db->sample_size, db->num_channels);
 698         pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
 699             db->fragsize, db->cnt_factor, db->dma_fragsize);
 700         pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
 701
 702         db->ready = 1;
 703         return 0;
 704 }
 705
 706 static int
 707 prog_dmabuf_adc(struct au1550_state *s)
 708 {
 709         stop_adc(s);
 710         return prog_dmabuf(s, &s->dma_adc);
 711
 712 }
 713
 714 static int
 715 prog_dmabuf_dac(struct au1550_state *s)
 716 {
 717         stop_dac(s);
 718         return prog_dmabuf(s, &s->dma_dac);
 719 }
 720
 721
 722 /* hold spinlock for the following */
 723 static void
 724 dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 725 {
 726         struct au1550_state *s = (struct au1550_state *) dev_id;
 727         struct dmabuf  *db = &s->dma_dac;
 728         u32     ac97c_stat;
 729
 730         ac97c_stat = au_readl(PSC_AC97STAT);
 731         if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
 732                 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
 733         db->dma_qcount--;
 734
 735         if (db->count >= db->fragsize) {
 736                 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
 737                                                         db->fragsize) == 0) {
 738                         err("qcount < 2 and no ring room!");
 739                 }
 740                 db->nextOut += db->fragsize;
 741                 if (db->nextOut >= db->rawbuf + db->dmasize)
 742                         db->nextOut -= db->dmasize;
 743                 db->count -= db->fragsize;
 744                 db->total_bytes += db->dma_fragsize;
 745                 db->dma_qcount++;
 746         }
 747
 748         /* wake up anybody listening */
 749         if (waitqueue_active(&db->wait))
 750                 wake_up(&db->wait);
 751 }
 752
 753
 754 static void
 755 adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 756 {
 757         struct  au1550_state *s = (struct au1550_state *)dev_id;
 758         struct  dmabuf  *dp = &s->dma_adc;
 759         u32     obytes;
 760         char    *obuf;
 761
 762         /* Pull the buffer from the dma queue.
 763         */
 764         au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
 765
 766         if ((dp->count + obytes) > dp->dmasize) {
 767                 /* Overrun. Stop ADC and log the error
 768                 */
 769                 stop_adc(s);
 770                 dp->error++;
 771                 err("adc overrun");
 772                 return;
 773         }
 774
 775         /* Put a new empty buffer on the destination DMA.
 776         */
 777         au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
 778
 779         dp->nextIn += dp->dma_fragsize;
 780         if (dp->nextIn >= dp->rawbuf + dp->dmasize)
 781                 dp->nextIn -= dp->dmasize;
 782
 783         dp->count += obytes;
 784         dp->total_bytes += obytes;
 785
 786         /* wake up anybody listening
 787         */
 788         if (waitqueue_active(&dp->wait))
 789                 wake_up(&dp->wait);
 790
 791 }
 792
 793 static loff_t
 794 au1550_llseek(struct file *file, loff_t offset, int origin)
 795 {
 796         return -ESPIPE;
 797 }
 798
 799
 800 static int
 801 au1550_open_mixdev(struct inode *inode, struct file *file)
 802 {
 803         file->private_data = &au1550_state;
 804         return 0;
 805 }
 806
 807 static int
 808 au1550_release_mixdev(struct inode *inode, struct file *file)
 809 {
 810         return 0;
 811 }
 812
 813 static int
 814 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
 815                         unsigned long arg)
 816 {
 817         return codec->mixer_ioctl(codec, cmd, arg);
 818 }
 819
 820 static int
 821 au1550_ioctl_mixdev(struct inode *inode, struct file *file,
 822                                unsigned int cmd, unsigned long arg)
 823 {
 824         struct au1550_state *s = (struct au1550_state *)file->private_data;
 825         struct ac97_codec *codec = s->codec;
 826
 827         return mixdev_ioctl(codec, cmd, arg);
 828 }
 829
 830 static /*const */ struct file_operations au1550_mixer_fops = {
 831         owner:THIS_MODULE,
 832         llseek:au1550_llseek,
 833         ioctl:au1550_ioctl_mixdev,
 834         open:au1550_open_mixdev,
 835         release:au1550_release_mixdev,
 836 };
 837
 838 static int
 839 drain_dac(struct au1550_state *s, int nonblock)
 840 {
 841         unsigned long   flags;
 842         int             count, tmo;
 843
 844         if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
 845                 return 0;
 846
 847         for (;;) {
 848                 spin_lock_irqsave(&s->lock, flags);
 849                 count = s->dma_dac.count;
 850                 spin_unlock_irqrestore(&s->lock, flags);
 851                 if (count <= s->dma_dac.fragsize)
 852                         break;
 853                 if (signal_pending(current))
 854                         break;
 855                 if (nonblock)
 856                         return -EBUSY;
 857                 tmo = 1000 * count / (s->no_vra ?
 858                                       48000 : s->dma_dac.sample_rate);
 859                 tmo /= s->dma_dac.dma_bytes_per_sample;
 860                 au1550_delay(tmo);
 861         }
 862         if (signal_pending(current))
 863                 return -ERESTARTSYS;
 864         return 0;
 865 }
 866
 867 static inline u8 S16_TO_U8(s16 ch)
 868 {
 869         return (u8) (ch >> 8) + 0x80;
 870 }
 871 static inline s16 U8_TO_S16(u8 ch)
 872 {
 873         return (s16) (ch - 0x80) << 8;
 874 }
 875
 876 /*
 877  * Translates user samples to dma buffer suitable for AC'97 DAC data:
 878  *     If mono, copy left channel to right channel in dma buffer.
 879  *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
 880  *     If interpolating (no VRA), duplicate every audio frame src_factor times.
 881  */
 882 static int
 883 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
 884                                                                int dmacount)
 885 {
 886         int             sample, i;
 887         int             interp_bytes_per_sample;
 888         int             num_samples;
 889         int             mono = (db->num_channels == 1);
 890         char            usersample[12];
 891         s16             ch, dmasample[6];
 892
 893         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
 894                 /* no translation necessary, just copy
 895                 */
 896                 if (copy_from_user(dmabuf, userbuf, dmacount))
 897                         return -EFAULT;
 898                 return dmacount;
 899         }
 900
 901         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
 902         num_samples = dmacount / interp_bytes_per_sample;
 903
 904         for (sample = 0; sample < num_samples; sample++) {
 905                 if (copy_from_user(usersample, userbuf,
 906                                    db->user_bytes_per_sample)) {
 907                         return -EFAULT;
 908                 }
 909
 910                 for (i = 0; i < db->num_channels; i++) {
 911                         if (db->sample_size == 8)
 912                                 ch = U8_TO_S16(usersample[i]);
 913                         else
 914                                 ch = *((s16 *) (&usersample[i * 2]));
 915                         dmasample[i] = ch;
 916                         if (mono)
 917                                 dmasample[i + 1] = ch;  /* right channel */
 918                 }
 919
 920                 /* duplicate every audio frame src_factor times
 921                 */
 922                 for (i = 0; i < db->src_factor; i++)
 923                         memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
 924
 925                 userbuf += db->user_bytes_per_sample;
 926                 dmabuf += interp_bytes_per_sample;
 927         }
 928
 929         return num_samples * interp_bytes_per_sample;
 930 }
 931
 932 /*
 933  * Translates AC'97 ADC samples to user buffer:
 934  *     If mono, send only left channel to user buffer.
 935  *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
 936  *     If decimating (no VRA), skip over src_factor audio frames.
 937  */
 938 static int
 939 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
 940                                                              int dmacount)
 941 {
 942         int             sample, i;
 943         int             interp_bytes_per_sample;
 944         int             num_samples;
 945         int             mono = (db->num_channels == 1);
 946         char            usersample[12];
 947
 948         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
 949                 /* no translation necessary, just copy
 950                 */
 951                 if (copy_to_user(userbuf, dmabuf, dmacount))
 952                         return -EFAULT;
 953                 return dmacount;
 954         }
 955
 956         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
 957         num_samples = dmacount / interp_bytes_per_sample;
 958
 959         for (sample = 0; sample < num_samples; sample++) {
 960                 for (i = 0; i < db->num_channels; i++) {
 961                         if (db->sample_size == 8)
 962                                 usersample[i] =
 963                                         S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
 964                         else
 965                                 *((s16 *) (&usersample[i * 2])) =
 966                                         *((s16 *) (&dmabuf[i * 2]));
 967                 }
 968
 969                 if (copy_to_user(userbuf, usersample,
 970                                  db->user_bytes_per_sample)) {
 971                         return -EFAULT;
 972                 }
 973
 974                 userbuf += db->user_bytes_per_sample;
 975                 dmabuf += interp_bytes_per_sample;
 976         }
 977
 978         return num_samples * interp_bytes_per_sample;
 979 }
 980
 981 /*
 982  * Copy audio data to/from user buffer from/to dma buffer, taking care
 983  * that we wrap when reading/writing the dma buffer. Returns actual byte
 984  * count written to or read from the dma buffer.
 985  */
 986 static int
 987 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
 988 {
 989         char           *bufptr = to_user ? db->nextOut : db->nextIn;
 990         char           *bufend = db->rawbuf + db->dmasize;
 991         int             cnt, ret;
 992
 993         if (bufptr + count > bufend) {
 994                 int             partial = (int) (bufend - bufptr);
 995                 if (to_user) {
 996                         if ((cnt = translate_to_user(db, userbuf,
 997                                                      bufptr, partial)) < 0)
 998                                 return cnt;
 999                         ret = cnt;
1000                         if ((cnt = translate_to_user(db, userbuf + partial,
1001                                                      db->rawbuf,
1002                                                      count - partial)) < 0)
1003                                 return cnt;
1004                         ret += cnt;
1005                 } else {
1006                         if ((cnt = translate_from_user(db, bufptr, userbuf,
1007                                                        partial)) < 0)
1008                                 return cnt;
1009                         ret = cnt;
1010                         if ((cnt = translate_from_user(db, db->rawbuf,
1011                                                        userbuf + partial,
1012                                                        count - partial)) < 0)
1013                                 return cnt;
1014                         ret += cnt;
1015                 }
1016         } else {
1017                 if (to_user)
1018                         ret = translate_to_user(db, userbuf, bufptr, count);
1019                 else
1020                         ret = translate_from_user(db, bufptr, userbuf, count);
1021         }
1022
1023         return ret;
1024 }
1025
1026
1027 static ssize_t
1028 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1029 {
1030         struct au1550_state *s = (struct au1550_state *)file->private_data;
1031         struct dmabuf  *db = &s->dma_adc;
1032         DECLARE_WAITQUEUE(wait, current);
1033         ssize_t         ret;
1034         unsigned long   flags;
1035         int             cnt, usercnt, avail;
1036
1037         if (db->mapped)
1038                 return -ENXIO;
1039         if (!access_ok(VERIFY_WRITE, buffer, count))
1040                 return -EFAULT;
1041         ret = 0;
1042
1043         count *= db->cnt_factor;
1044
1045         down(&s->sem);
1046         add_wait_queue(&db->wait, &wait);
1047
1048         while (count > 0) {
1049                 /* wait for samples in ADC dma buffer
1050                 */
1051                 do {
1052                         if (db->stopped)
1053                                 start_adc(s);
1054                         spin_lock_irqsave(&s->lock, flags);
1055                         avail = db->count;
1056                         if (avail <= 0)
1057                                 __set_current_state(TASK_INTERRUPTIBLE);
1058                         spin_unlock_irqrestore(&s->lock, flags);
1059                         if (avail <= 0) {
1060                                 if (file->f_flags & O_NONBLOCK) {
1061                                         if (!ret)
1062                                                 ret = -EAGAIN;
1063                                         goto out;
1064                                 }
1065                                 up(&s->sem);
1066                                 schedule();
1067                                 if (signal_pending(current)) {
1068                                         if (!ret)
1069                                                 ret = -ERESTARTSYS;
1070                                         goto out2;
1071                                 }
1072                                 down(&s->sem);
1073                         }
1074                 } while (avail <= 0);
1075
1076                 /* copy from nextOut to user
1077                 */
1078                 if ((cnt = copy_dmabuf_user(db, buffer,
1079                                             count > avail ?
1080                                             avail : count, 1)) < 0) {
1081                         if (!ret)
1082                                 ret = -EFAULT;
1083                         goto out;
1084                 }
1085
1086                 spin_lock_irqsave(&s->lock, flags);
1087                 db->count -= cnt;
1088                 db->nextOut += cnt;
1089                 if (db->nextOut >= db->rawbuf + db->dmasize)
1090                         db->nextOut -= db->dmasize;
1091                 spin_unlock_irqrestore(&s->lock, flags);
1092
1093                 count -= cnt;
1094                 usercnt = cnt / db->cnt_factor;
1095                 buffer += usercnt;
1096                 ret += usercnt;
1097         }                       /* while (count > 0) */
1098
1099 out:
1100         up(&s->sem);
1101 out2:
1102         remove_wait_queue(&db->wait, &wait);
1103         set_current_state(TASK_RUNNING);
1104         return ret;
1105 }
1106
1107 static ssize_t
1108 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1109 {
1110         struct au1550_state *s = (struct au1550_state *)file->private_data;
1111         struct dmabuf  *db = &s->dma_dac;
1112         DECLARE_WAITQUEUE(wait, current);
1113         ssize_t         ret = 0;
1114         unsigned long   flags;
1115         int             cnt, usercnt, avail;
1116
1117         pr_debug("write: count=%d\n", count);
1118
1119         if (db->mapped)
1120                 return -ENXIO;
1121         if (!access_ok(VERIFY_READ, buffer, count))
1122                 return -EFAULT;
1123
1124         count *= db->cnt_factor;
1125
1126         down(&s->sem);
1127         add_wait_queue(&db->wait, &wait);
1128
1129         while (count > 0) {
1130                 /* wait for space in playback buffer
1131                 */
1132                 do {
1133                         spin_lock_irqsave(&s->lock, flags);
1134                         avail = (int) db->dmasize - db->count;
1135                         if (avail <= 0)
1136                                 __set_current_state(TASK_INTERRUPTIBLE);
1137                         spin_unlock_irqrestore(&s->lock, flags);
1138                         if (avail <= 0) {
1139                                 if (file->f_flags & O_NONBLOCK) {
1140                                         if (!ret)
1141                                                 ret = -EAGAIN;
1142                                         goto out;
1143                                 }
1144                                 up(&s->sem);
1145                                 schedule();
1146                                 if (signal_pending(current)) {
1147                                         if (!ret)
1148                                                 ret = -ERESTARTSYS;
1149                                         goto out2;
1150                                 }
1151                                 down(&s->sem);
1152                         }
1153                 } while (avail <= 0);
1154
1155                 /* copy from user to nextIn
1156                 */
1157                 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1158                                             count > avail ?
1159                                             avail : count, 0)) < 0) {
1160                         if (!ret)
1161                                 ret = -EFAULT;
1162                         goto out;
1163                 }
1164
1165                 spin_lock_irqsave(&s->lock, flags);
1166                 db->count += cnt;
1167                 db->nextIn += cnt;
1168                 if (db->nextIn >= db->rawbuf + db->dmasize)
1169                         db->nextIn -= db->dmasize;
1170
1171                 /* If the data is available, we want to keep two buffers
1172                  * on the dma queue.  If the queue count reaches zero,
1173                  * we know the dma has stopped.
1174                  */
1175                 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1176                         if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
1177                                                         db->fragsize) == 0) {
1178                                 err("qcount < 2 and no ring room!");
1179                         }
1180                         db->nextOut += db->fragsize;
1181                         if (db->nextOut >= db->rawbuf + db->dmasize)
1182                                 db->nextOut -= db->dmasize;
1183                         db->total_bytes += db->dma_fragsize;
1184                         if (db->dma_qcount == 0)
1185                                 start_dac(s);
1186                         db->dma_qcount++;
1187                 }
1188                 spin_unlock_irqrestore(&s->lock, flags);
1189
1190                 count -= cnt;
1191                 usercnt = cnt / db->cnt_factor;
1192                 buffer += usercnt;
1193                 ret += usercnt;
1194         }                       /* while (count > 0) */
1195
1196 out:
1197         up(&s->sem);
1198 out2:
1199         remove_wait_queue(&db->wait, &wait);
1200         set_current_state(TASK_RUNNING);
1201         return ret;
1202 }
1203
1204
1205 /* No kernel lock - we have our own spinlock */
1206 static unsigned int
1207 au1550_poll(struct file *file, struct poll_table_struct *wait)
1208 {
1209         struct au1550_state *s = (struct au1550_state *)file->private_data;
1210         unsigned long   flags;
1211         unsigned int    mask = 0;
1212
1213         if (file->f_mode & FMODE_WRITE) {
1214                 if (!s->dma_dac.ready)
1215                         return 0;
1216                 poll_wait(file, &s->dma_dac.wait, wait);
1217         }
1218         if (file->f_mode & FMODE_READ) {
1219                 if (!s->dma_adc.ready)
1220                         return 0;
1221                 poll_wait(file, &s->dma_adc.wait, wait);
1222         }
1223
1224         spin_lock_irqsave(&s->lock, flags);
1225
1226         if (file->f_mode & FMODE_READ) {
1227                 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1228                         mask |= POLLIN | POLLRDNORM;
1229         }
1230         if (file->f_mode & FMODE_WRITE) {
1231                 if (s->dma_dac.mapped) {
1232                         if (s->dma_dac.count >=
1233                             (signed)s->dma_dac.dma_fragsize)
1234                                 mask |= POLLOUT | POLLWRNORM;
1235                 } else {
1236                         if ((signed) s->dma_dac.dmasize >=
1237                             s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1238                                 mask |= POLLOUT | POLLWRNORM;
1239                 }
1240         }
1241         spin_unlock_irqrestore(&s->lock, flags);
1242         return mask;
1243 }
1244
1245 static int
1246 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1247 {
1248         struct au1550_state *s = (struct au1550_state *)file->private_data;
1249         struct dmabuf  *db;
1250         unsigned long   size;
1251         int ret = 0;
1252
1253         lock_kernel();
1254         down(&s->sem);
1255         if (vma->vm_flags & VM_WRITE)
1256                 db = &s->dma_dac;
1257         else if (vma->vm_flags & VM_READ)
1258                 db = &s->dma_adc;
1259         else {
1260                 ret = -EINVAL;
1261                 goto out;
1262         }
1263         if (vma->vm_pgoff != 0) {
1264                 ret = -EINVAL;
1265                 goto out;
1266         }
1267         size = vma->vm_end - vma->vm_start;
1268         if (size > (PAGE_SIZE << db->buforder)) {
1269                 ret = -EINVAL;
1270                 goto out;
1271         }
1272         if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1273                              size, vma->vm_page_prot)) {
1274                 ret = -EAGAIN;
1275                 goto out;
1276         }
1277         vma->vm_flags &= ~VM_IO;
1278         db->mapped = 1;
1279 out:
1280         up(&s->sem);
1281         unlock_kernel();
1282         return ret;
1283 }
1284
1285 #ifdef DEBUG
1286 static struct ioctl_str_t {
1287         unsigned int    cmd;
1288         const char     *str;
1289 } ioctl_str[] = {
1290         {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1291         {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1292         {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1293         {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1294         {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1295         {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1296         {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1297         {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1298         {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1299         {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1300         {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1301         {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1302         {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1303         {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1304         {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1305         {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1306         {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1307         {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1308         {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1309         {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1310         {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1311         {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1312         {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1313         {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1314         {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1315         {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1316         {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1317         {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1318         {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1319         {OSS_GETVERSION, "OSS_GETVERSION"},
1320         {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1321         {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1322         {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1323         {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1324 };
1325 #endif
1326
1327 static int
1328 dma_count_done(struct dmabuf *db)
1329 {
1330         if (db->stopped)
1331                 return 0;
1332
1333         return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1334 }
1335
1336
1337 static int
1338 au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1339                                                         unsigned long arg)
1340 {
1341         struct au1550_state *s = (struct au1550_state *)file->private_data;
1342         unsigned long   flags;
1343         audio_buf_info  abinfo;
1344         count_info      cinfo;
1345         int             count;
1346         int             val, mapped, ret, diff;
1347
1348         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1349                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1350
1351 #ifdef DEBUG
1352         for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1353                 if (ioctl_str[count].cmd == cmd)
1354                         break;
1355         }
1356         if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1357                 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1358         else
1359                 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1360 #endif
1361
1362         switch (cmd) {
1363         case OSS_GETVERSION:
1364                 return put_user(SOUND_VERSION, (int *) arg);
1365
1366         case SNDCTL_DSP_SYNC:
1367                 if (file->f_mode & FMODE_WRITE)
1368                         return drain_dac(s, file->f_flags & O_NONBLOCK);
1369                 return 0;
1370
1371         case SNDCTL_DSP_SETDUPLEX:
1372                 return 0;
1373
1374         case SNDCTL_DSP_GETCAPS:
1375                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1376                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1377
1378         case SNDCTL_DSP_RESET:
1379                 if (file->f_mode & FMODE_WRITE) {
1380                         stop_dac(s);
1381                         synchronize_irq();
1382                         s->dma_dac.count = s->dma_dac.total_bytes = 0;
1383                         s->dma_dac.nextIn = s->dma_dac.nextOut =
1384                                 s->dma_dac.rawbuf;
1385                 }
1386                 if (file->f_mode & FMODE_READ) {
1387                         stop_adc(s);
1388                         synchronize_irq();
1389                         s->dma_adc.count = s->dma_adc.total_bytes = 0;
1390                         s->dma_adc.nextIn = s->dma_adc.nextOut =
1391                                 s->dma_adc.rawbuf;
1392                 }
1393                 return 0;
1394
1395         case SNDCTL_DSP_SPEED:
1396                 if (get_user(val, (int *) arg))
1397                         return -EFAULT;
1398                 if (val >= 0) {
1399                         if (file->f_mode & FMODE_READ) {
1400                                 stop_adc(s);
1401                                 set_adc_rate(s, val);
1402                         }
1403                         if (file->f_mode & FMODE_WRITE) {
1404                                 stop_dac(s);
1405                                 set_dac_rate(s, val);
1406                         }
1407                         if (s->open_mode & FMODE_READ)
1408                                 if ((ret = prog_dmabuf_adc(s)))
1409                                         return ret;
1410                         if (s->open_mode & FMODE_WRITE)
1411                                 if ((ret = prog_dmabuf_dac(s)))
1412                                         return ret;
1413                 }
1414                 return put_user((file->f_mode & FMODE_READ) ?
1415                                 s->dma_adc.sample_rate :
1416                                 s->dma_dac.sample_rate,
1417                                 (int *)arg);
1418
1419         case SNDCTL_DSP_STEREO:
1420                 if (get_user(val, (int *) arg))
1421                         return -EFAULT;
1422                 if (file->f_mode & FMODE_READ) {
1423                         stop_adc(s);
1424                         s->dma_adc.num_channels = val ? 2 : 1;
1425                         if ((ret = prog_dmabuf_adc(s)))
1426                                 return ret;
1427                 }
1428                 if (file->f_mode & FMODE_WRITE) {
1429                         stop_dac(s);
1430                         s->dma_dac.num_channels = val ? 2 : 1;
1431                         if (s->codec_ext_caps & AC97_EXT_DACS) {
1432                                 /* disable surround and center/lfe in AC'97
1433                                 */
1434                                 u16 ext_stat = rdcodec(s->codec,
1435                                                        AC97_EXTENDED_STATUS);
1436                                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1437                                         ext_stat | (AC97_EXTSTAT_PRI |
1438                                                     AC97_EXTSTAT_PRJ |
1439                                                     AC97_EXTSTAT_PRK));
1440                         }
1441                         if ((ret = prog_dmabuf_dac(s)))
1442                                 return ret;
1443                 }
1444                 return 0;
1445
1446         case SNDCTL_DSP_CHANNELS:
1447                 if (get_user(val, (int *) arg))
1448                         return -EFAULT;
1449                 if (val != 0) {
1450                         if (file->f_mode & FMODE_READ) {
1451                                 if (val < 0 || val > 2)
1452                                         return -EINVAL;
1453                                 stop_adc(s);
1454                                 s->dma_adc.num_channels = val;
1455                                 if ((ret = prog_dmabuf_adc(s)))
1456                                         return ret;
1457                         }
1458                         if (file->f_mode & FMODE_WRITE) {
1459                                 switch (val) {
1460                                 case 1:
1461                                 case 2:
1462                                         break;
1463                                 case 3:
1464                                 case 5:
1465                                         return -EINVAL;
1466                                 case 4:
1467                                         if (!(s->codec_ext_caps &
1468                                               AC97_EXTID_SDAC))
1469                                                 return -EINVAL;
1470                                         break;
1471                                 case 6:
1472                                         if ((s->codec_ext_caps &
1473                                              AC97_EXT_DACS) != AC97_EXT_DACS)
1474                                                 return -EINVAL;
1475                                         break;
1476                                 default:
1477                                         return -EINVAL;
1478                                 }
1479
1480                                 stop_dac(s);
1481                                 if (val <= 2 &&
1482                                     (s->codec_ext_caps & AC97_EXT_DACS)) {
1483                                         /* disable surround and center/lfe
1484                                          * channels in AC'97
1485                                          */
1486                                         u16             ext_stat =
1487                                                 rdcodec(s->codec,
1488                                                         AC97_EXTENDED_STATUS);
1489                                         wrcodec(s->codec,
1490                                                 AC97_EXTENDED_STATUS,
1491                                                 ext_stat | (AC97_EXTSTAT_PRI |
1492                                                             AC97_EXTSTAT_PRJ |
1493                                                             AC97_EXTSTAT_PRK));
1494                                 } else if (val >= 4) {
1495                                         /* enable surround, center/lfe
1496                                          * channels in AC'97
1497                                          */
1498                                         u16             ext_stat =
1499                                                 rdcodec(s->codec,
1500                                                         AC97_EXTENDED_STATUS);
1501                                         ext_stat &= ~AC97_EXTSTAT_PRJ;
1502                                         if (val == 6)
1503                                                 ext_stat &=
1504                                                         ~(AC97_EXTSTAT_PRI |
1505                                                           AC97_EXTSTAT_PRK);
1506                                         wrcodec(s->codec,
1507                                                 AC97_EXTENDED_STATUS,
1508                                                 ext_stat);
1509                                 }
1510
1511                                 s->dma_dac.num_channels = val;
1512                                 if ((ret = prog_dmabuf_dac(s)))
1513                                         return ret;
1514                         }
1515                 }
1516                 return put_user(val, (int *) arg);
1517
1518         case SNDCTL_DSP_GETFMTS:        /* Returns a mask */
1519                 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1520
1521         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1522                 if (get_user(val, (int *) arg))
1523                         return -EFAULT;
1524                 if (val != AFMT_QUERY) {
1525                         if (file->f_mode & FMODE_READ) {
1526                                 stop_adc(s);
1527                                 if (val == AFMT_S16_LE)
1528                                         s->dma_adc.sample_size = 16;
1529                                 else {
1530                                         val = AFMT_U8;
1531                                         s->dma_adc.sample_size = 8;
1532                                 }
1533                                 if ((ret = prog_dmabuf_adc(s)))
1534                                         return ret;
1535                         }
1536                         if (file->f_mode & FMODE_WRITE) {
1537                                 stop_dac(s);
1538                                 if (val == AFMT_S16_LE)
1539                                         s->dma_dac.sample_size = 16;
1540                                 else {
1541                                         val = AFMT_U8;
1542                                         s->dma_dac.sample_size = 8;
1543                                 }
1544                                 if ((ret = prog_dmabuf_dac(s)))
1545                                         return ret;
1546                         }
1547                 } else {
1548                         if (file->f_mode & FMODE_READ)
1549                                 val = (s->dma_adc.sample_size == 16) ?
1550                                         AFMT_S16_LE : AFMT_U8;
1551                         else
1552                                 val = (s->dma_dac.sample_size == 16) ?
1553                                         AFMT_S16_LE : AFMT_U8;
1554                 }
1555                 return put_user(val, (int *) arg);
1556
1557         case SNDCTL_DSP_POST:
1558                 return 0;
1559
1560         case SNDCTL_DSP_GETTRIGGER:
1561                 val = 0;
1562                 spin_lock_irqsave(&s->lock, flags);
1563                 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1564                         val |= PCM_ENABLE_INPUT;
1565                 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1566                         val |= PCM_ENABLE_OUTPUT;
1567                 spin_unlock_irqrestore(&s->lock, flags);
1568                 return put_user(val, (int *) arg);
1569
1570         case SNDCTL_DSP_SETTRIGGER:
1571                 if (get_user(val, (int *) arg))
1572                         return -EFAULT;
1573                 if (file->f_mode & FMODE_READ) {
1574                         if (val & PCM_ENABLE_INPUT)
1575                                 start_adc(s);
1576                         else
1577                                 stop_adc(s);
1578                 }
1579                 if (file->f_mode & FMODE_WRITE) {
1580                         if (val & PCM_ENABLE_OUTPUT)
1581                                 start_dac(s);
1582                         else
1583                                 stop_dac(s);
1584                 }
1585                 return 0;
1586
1587         case SNDCTL_DSP_GETOSPACE:
1588                 if (!(file->f_mode & FMODE_WRITE))
1589                         return -EINVAL;
1590                 abinfo.fragsize = s->dma_dac.fragsize;
1591                 spin_lock_irqsave(&s->lock, flags);
1592                 count = s->dma_dac.count;
1593                 count -= dma_count_done(&s->dma_dac);
1594                 spin_unlock_irqrestore(&s->lock, flags);
1595                 if (count < 0)
1596                         count = 0;
1597                 abinfo.bytes = (s->dma_dac.dmasize - count) /
1598                         s->dma_dac.cnt_factor;
1599                 abinfo.fragstotal = s->dma_dac.numfrag;
1600                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1601                 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1602                 return copy_to_user((void *) arg, &abinfo,
1603                                     sizeof(abinfo)) ? -EFAULT : 0;
1604
1605         case SNDCTL_DSP_GETISPACE:
1606                 if (!(file->f_mode & FMODE_READ))
1607                         return -EINVAL;
1608                 abinfo.fragsize = s->dma_adc.fragsize;
1609                 spin_lock_irqsave(&s->lock, flags);
1610                 count = s->dma_adc.count;
1611                 count += dma_count_done(&s->dma_adc);
1612                 spin_unlock_irqrestore(&s->lock, flags);
1613                 if (count < 0)
1614                         count = 0;
1615                 abinfo.bytes = count / s->dma_adc.cnt_factor;
1616                 abinfo.fragstotal = s->dma_adc.numfrag;
1617                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1618                 return copy_to_user((void *) arg, &abinfo,
1619                                     sizeof(abinfo)) ? -EFAULT : 0;
1620
1621         case SNDCTL_DSP_NONBLOCK:
1622                 file->f_flags |= O_NONBLOCK;
1623                 return 0;
1624
1625         case SNDCTL_DSP_GETODELAY:
1626                 if (!(file->f_mode & FMODE_WRITE))
1627                         return -EINVAL;
1628                 spin_lock_irqsave(&s->lock, flags);
1629                 count = s->dma_dac.count;
1630                 count -= dma_count_done(&s->dma_dac);
1631                 spin_unlock_irqrestore(&s->lock, flags);
1632                 if (count < 0)
1633                         count = 0;
1634                 count /= s->dma_dac.cnt_factor;
1635                 return put_user(count, (int *) arg);
1636
1637         case SNDCTL_DSP_GETIPTR:
1638                 if (!(file->f_mode & FMODE_READ))
1639                         return -EINVAL;
1640                 spin_lock_irqsave(&s->lock, flags);
1641                 cinfo.bytes = s->dma_adc.total_bytes;
1642                 count = s->dma_adc.count;
1643                 if (!s->dma_adc.stopped) {
1644                         diff = dma_count_done(&s->dma_adc);
1645                         count += diff;
1646                         cinfo.bytes += diff;
1647                         cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
1648                                 virt_to_phys(s->dma_adc.rawbuf);
1649                 } else
1650                         cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1651                                 virt_to_phys(s->dma_adc.rawbuf);
1652                 if (s->dma_adc.mapped)
1653                         s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1654                 spin_unlock_irqrestore(&s->lock, flags);
1655                 if (count < 0)
1656                         count = 0;
1657                 cinfo.blocks = count >> s->dma_adc.fragshift;
1658                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1659
1660         case SNDCTL_DSP_GETOPTR:
1661                 if (!(file->f_mode & FMODE_READ))
1662                         return -EINVAL;
1663                 spin_lock_irqsave(&s->lock, flags);
1664                 cinfo.bytes = s->dma_dac.total_bytes;
1665                 count = s->dma_dac.count;
1666                 if (!s->dma_dac.stopped) {
1667                         diff = dma_count_done(&s->dma_dac);
1668                         count -= diff;
1669                         cinfo.bytes += diff;
1670                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1671                                 virt_to_phys(s->dma_dac.rawbuf);
1672                 } else
1673                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1674                                 virt_to_phys(s->dma_dac.rawbuf);
1675                 if (s->dma_dac.mapped)
1676                         s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1677                 spin_unlock_irqrestore(&s->lock, flags);
1678                 if (count < 0)
1679                         count = 0;
1680                 cinfo.blocks = count >> s->dma_dac.fragshift;
1681                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1682
1683         case SNDCTL_DSP_GETBLKSIZE:
1684                 if (file->f_mode & FMODE_WRITE)
1685                         return put_user(s->dma_dac.fragsize, (int *) arg);
1686                 else
1687                         return put_user(s->dma_adc.fragsize, (int *) arg);
1688
1689         case SNDCTL_DSP_SETFRAGMENT:
1690                 if (get_user(val, (int *) arg))
1691                         return -EFAULT;
1692                 if (file->f_mode & FMODE_READ) {
1693                         stop_adc(s);
1694                         s->dma_adc.ossfragshift = val & 0xffff;
1695                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1696                         if (s->dma_adc.ossfragshift < 4)
1697                                 s->dma_adc.ossfragshift = 4;
1698                         if (s->dma_adc.ossfragshift > 15)
1699                                 s->dma_adc.ossfragshift = 15;
1700                         if (s->dma_adc.ossmaxfrags < 4)
1701                                 s->dma_adc.ossmaxfrags = 4;
1702                         if ((ret = prog_dmabuf_adc(s)))
1703                                 return ret;
1704                 }
1705                 if (file->f_mode & FMODE_WRITE) {
1706                         stop_dac(s);
1707                         s->dma_dac.ossfragshift = val & 0xffff;
1708                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1709                         if (s->dma_dac.ossfragshift < 4)
1710                                 s->dma_dac.ossfragshift = 4;
1711                         if (s->dma_dac.ossfragshift > 15)
1712                                 s->dma_dac.ossfragshift = 15;
1713                         if (s->dma_dac.ossmaxfrags < 4)
1714                                 s->dma_dac.ossmaxfrags = 4;
1715                         if ((ret = prog_dmabuf_dac(s)))
1716                                 return ret;
1717                 }
1718                 return 0;
1719
1720         case SNDCTL_DSP_SUBDIVIDE:
1721                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1722                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1723                         return -EINVAL;
1724                 if (get_user(val, (int *) arg))
1725                         return -EFAULT;
1726                 if (val != 1 && val != 2 && val != 4)
1727                         return -EINVAL;
1728                 if (file->f_mode & FMODE_READ) {
1729                         stop_adc(s);
1730                         s->dma_adc.subdivision = val;
1731                         if ((ret = prog_dmabuf_adc(s)))
1732                                 return ret;
1733                 }
1734                 if (file->f_mode & FMODE_WRITE) {
1735                         stop_dac(s);
1736                         s->dma_dac.subdivision = val;
1737                         if ((ret = prog_dmabuf_dac(s)))
1738                                 return ret;
1739                 }
1740                 return 0;
1741
1742         case SOUND_PCM_READ_RATE:
1743                 return put_user((file->f_mode & FMODE_READ) ?
1744                                 s->dma_adc.sample_rate :
1745                                 s->dma_dac.sample_rate,
1746                                 (int *)arg);
1747
1748         case SOUND_PCM_READ_CHANNELS:
1749                 if (file->f_mode & FMODE_READ)
1750                         return put_user(s->dma_adc.num_channels, (int *)arg);
1751                 else
1752                         return put_user(s->dma_dac.num_channels, (int *)arg);
1753
1754         case SOUND_PCM_READ_BITS:
1755                 if (file->f_mode & FMODE_READ)
1756                         return put_user(s->dma_adc.sample_size, (int *)arg);
1757                 else
1758                         return put_user(s->dma_dac.sample_size, (int *)arg);
1759
1760         case SOUND_PCM_WRITE_FILTER:
1761         case SNDCTL_DSP_SETSYNCRO:
1762         case SOUND_PCM_READ_FILTER:
1763                 return -EINVAL;
1764         }
1765
1766         return mixdev_ioctl(s->codec, cmd, arg);
1767 }
1768
1769
1770 static int
1771 au1550_open(struct inode *inode, struct file *file)
1772 {
1773         int             minor = MINOR(inode->i_rdev);
1774         DECLARE_WAITQUEUE(wait, current);
1775         struct au1550_state *s = &au1550_state;
1776         int             ret;
1777
1778 #ifdef DEBUG
1779         if (file->f_flags & O_NONBLOCK)
1780                 pr_debug("open: non-blocking\n");
1781         else
1782                 pr_debug("open: blocking\n");
1783 #endif
1784
1785         file->private_data = s;
1786         /* wait for device to become free */
1787         down(&s->open_sem);
1788         while (s->open_mode & file->f_mode) {
1789                 if (file->f_flags & O_NONBLOCK) {
1790                         up(&s->open_sem);
1791                         return -EBUSY;
1792                 }
1793                 add_wait_queue(&s->open_wait, &wait);
1794                 __set_current_state(TASK_INTERRUPTIBLE);
1795                 up(&s->open_sem);
1796                 schedule();
1797                 remove_wait_queue(&s->open_wait, &wait);
1798                 set_current_state(TASK_RUNNING);
1799                 if (signal_pending(current))
1800                         return -ERESTARTSYS;
1801                 down(&s->open_sem);
1802         }
1803
1804         stop_dac(s);
1805         stop_adc(s);
1806
1807         if (file->f_mode & FMODE_READ) {
1808                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1809                         s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1810                 s->dma_adc.num_channels = 1;
1811                 s->dma_adc.sample_size = 8;
1812                 set_adc_rate(s, 8000);
1813                 if ((minor & 0xf) == SND_DEV_DSP16)
1814                         s->dma_adc.sample_size = 16;
1815         }
1816
1817         if (file->f_mode & FMODE_WRITE) {
1818                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1819                         s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1820                 s->dma_dac.num_channels = 1;
1821                 s->dma_dac.sample_size = 8;
1822                 set_dac_rate(s, 8000);
1823                 if ((minor & 0xf) == SND_DEV_DSP16)
1824                         s->dma_dac.sample_size = 16;
1825         }
1826
1827         if (file->f_mode & FMODE_READ) {
1828                 if ((ret = prog_dmabuf_adc(s)))
1829                         return ret;
1830         }
1831         if (file->f_mode & FMODE_WRITE) {
1832                 if ((ret = prog_dmabuf_dac(s)))
1833                         return ret;
1834         }
1835
1836         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1837         up(&s->open_sem);
1838         init_MUTEX(&s->sem);
1839         return 0;
1840 }
1841
1842 static int
1843 au1550_release(struct inode *inode, struct file *file)
1844 {
1845         struct au1550_state *s = (struct au1550_state *)file->private_data;
1846
1847         lock_kernel();
1848
1849         if (file->f_mode & FMODE_WRITE) {
1850                 unlock_kernel();
1851                 drain_dac(s, file->f_flags & O_NONBLOCK);
1852                 lock_kernel();
1853         }
1854
1855         down(&s->open_sem);
1856         if (file->f_mode & FMODE_WRITE) {
1857                 stop_dac(s);
1858                 kfree(s->dma_dac.rawbuf);
1859                 s->dma_dac.rawbuf = NULL;
1860         }
1861         if (file->f_mode & FMODE_READ) {
1862                 stop_adc(s);
1863                 kfree(s->dma_adc.rawbuf);
1864                 s->dma_adc.rawbuf = NULL;
1865         }
1866         s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1867         up(&s->open_sem);
1868         wake_up(&s->open_wait);
1869         unlock_kernel();
1870         return 0;
1871 }
1872
1873 static /*const */ struct file_operations au1550_audio_fops = {
1874         owner:          THIS_MODULE,
1875         llseek:         au1550_llseek,
1876         read:           au1550_read,
1877         write:          au1550_write,
1878         poll:           au1550_poll,
1879         ioctl:          au1550_ioctl,
1880         mmap:           au1550_mmap,
1881         open:           au1550_open,
1882         release:        au1550_release,
1883 };
1884
1885 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1886 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1887
1888 static int __devinit
1889 au1550_probe(void)
1890 {
1891         struct au1550_state *s = &au1550_state;
1892         int             val;
1893
1894         memset(s, 0, sizeof(struct au1550_state));
1895
1896         init_waitqueue_head(&s->dma_adc.wait);
1897         init_waitqueue_head(&s->dma_dac.wait);
1898         init_waitqueue_head(&s->open_wait);
1899         init_MUTEX(&s->open_sem);
1900         spin_lock_init(&s->lock);
1901
1902         s->codec = ac97_alloc_codec();
1903         if(s->codec == NULL) {
1904                 err("Out of memory");
1905                 return -1;
1906         }
1907         s->codec->private_data = s;
1908         s->codec->id = 0;
1909         s->codec->codec_read = rdcodec;
1910         s->codec->codec_write = wrcodec;
1911         s->codec->codec_wait = waitcodec;
1912
1913         if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1914                             0x30, "Au1550 AC97")) {
1915                 err("AC'97 ports in use");
1916         }
1917
1918         /* Allocate the DMA Channels
1919         */
1920         if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1921             DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1922                 err("Can't get DAC DMA");
1923                 goto err_dma1;
1924         }
1925         au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1926         if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1927                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1928                 err("Can't get DAC DMA descriptors");
1929                 goto err_dma1;
1930         }
1931
1932         if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1933             DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1934                 err("Can't get ADC DMA");
1935                 goto err_dma2;
1936         }
1937         au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1938         if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1939                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1940                 err("Can't get ADC DMA descriptors");
1941                 goto err_dma2;
1942         }
1943
1944         pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1945
1946         /* register devices */
1947
1948         if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1949                 goto err_dev1;
1950         if ((s->codec->dev_mixer =
1951              register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1952                 goto err_dev2;
1953
1954         /* The GPIO for the appropriate PSC was configured by the
1955          * board specific start up.
1956          *
1957          * configure PSC for AC'97
1958          */
1959         au_writel(0, AC97_PSC_CTRL);    /* Disable PSC */
1960         au_sync();
1961         au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1962         au_sync();
1963
1964         /* cold reset the AC'97
1965         */
1966         au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1967         au_sync();
1968         au1550_delay(10);
1969         au_writel(0, PSC_AC97RST);
1970         au_sync();
1971
1972         /* need to delay around 500msec(bleech) to give
1973            some CODECs enough time to wakeup */
1974         au1550_delay(500);
1975
1976         /* warm reset the AC'97 to start the bitclk
1977         */
1978         au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1979         au_sync();
1980         udelay(100);
1981         au_writel(0, PSC_AC97RST);
1982         au_sync();
1983
1984         /* Enable PSC
1985         */
1986         au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
1987         au_sync();
1988
1989         /* Wait for PSC ready.
1990         */
1991         do {
1992                 val = readl((void *)PSC_AC97STAT);
1993                 au_sync();
1994         } while ((val & PSC_AC97STAT_SR) == 0);
1995
1996         /* Configure AC97 controller.
1997          * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
1998          */
1999         val = PSC_AC97CFG_SET_LEN(16);
2000         val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2001
2002         /* Enable device so we can at least
2003          * talk over the AC-link.
2004          */
2005         au_writel(val, PSC_AC97CFG);
2006         au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2007         au_sync();
2008         val |= PSC_AC97CFG_DE_ENABLE;
2009         au_writel(val, PSC_AC97CFG);
2010         au_sync();
2011
2012         /* Wait for Device ready.
2013         */
2014         do {
2015                 val = readl((void *)PSC_AC97STAT);
2016                 au_sync();
2017         } while ((val & PSC_AC97STAT_DR) == 0);
2018
2019         /* codec init */
2020         if (!ac97_probe_codec(s->codec))
2021                 goto err_dev3;
2022
2023         s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2024         s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2025         pr_info("AC'97 Base/Extended ID = %04x/%04x",
2026              s->codec_base_caps, s->codec_ext_caps);
2027
2028         if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2029                 /* codec does not support VRA
2030                 */
2031                 s->no_vra = 1;
2032         } else if (!vra) {
2033                 /* Boot option says disable VRA
2034                 */
2035                 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2036                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2037                         ac97_extstat & ~AC97_EXTSTAT_VRA);
2038                 s->no_vra = 1;
2039         }
2040         if (s->no_vra)
2041                 pr_info("no VRA, interpolating and decimating");
2042
2043         /* set mic to be the recording source */
2044         val = SOUND_MASK_MIC;
2045         mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2046                      (unsigned long) &val);
2047
2048         return 0;
2049
2050  err_dev3:
2051         unregister_sound_mixer(s->codec->dev_mixer);
2052  err_dev2:
2053         unregister_sound_dsp(s->dev_audio);
2054  err_dev1:
2055         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2056  err_dma2:
2057         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2058  err_dma1:
2059         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2060
2061         ac97_release_codec(s->codec);
2062         return -1;
2063 }
2064
2065 static void __devinit
2066 au1550_remove(void)
2067 {
2068         struct au1550_state *s = &au1550_state;
2069
2070         if (!s)
2071                 return;
2072         synchronize_irq();
2073         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2074         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2075         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2076         unregister_sound_dsp(s->dev_audio);
2077         unregister_sound_mixer(s->codec->dev_mixer);
2078         ac97_release_codec(s->codec);
2079 }
2080
2081 static int __init
2082 init_au1550(void)
2083 {
2084         return au1550_probe();
2085 }
2086
2087 static void __exit
2088 cleanup_au1550(void)
2089 {
2090         au1550_remove();
2091 }
2092
2093 module_init(init_au1550);
2094 module_exit(cleanup_au1550);
2095
2096 #ifndef MODULE
2097
2098 static int __init
2099 au1550_setup(char *options)
2100 {
2101         char           *this_opt;
2102
2103         if (!options || !*options)
2104                 return 0;
2105
2106         while ((this_opt = strsep(&options, ","))) {
2107                 if (!*this_opt)
2108                         continue;
2109                 if (!strncmp(this_opt, "vra", 3)) {
2110                         vra = 1;
2111                 }
2112         }
2113
2114         return 1;
2115 }
2116
2117 __setup("au1550_audio=", au1550_setup);
2118
2119 #endif /* MODULE */