sound/oss/ad1848.c

   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  *
  16  *
  17  *
  18  * Copyright (C) by Hannu Savolainen 1993-1997
  19  *
  20  * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
  21  * Version 2 (June 1991). See the "COPYING" file distributed with this software
  22  * for more info.
  23  *
  24  *
  25  * Thomas Sailer        : ioctl code reworked (vmalloc/vfree removed)
  26  *                        general sleep/wakeup clean up.
  27  * Alan Cox             : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
  28  *                        of irqs. Use dev_id.
  29  * Christoph Hellwig    : adapted to module_init/module_exit
  30  * Aki Laukkanen        : added power management support
  31  * Arnaldo C. de Melo   : added missing restore_flags in ad1848_resume
  32  * Miguel Freitas       : added ISA PnP support
  33  * Alan Cox             : Added CS4236->4239 identification
  34  * Daniel T. Cobra      : Alernate config/mixer for later chips
  35  * Alan Cox             : Merged chip idents and config code
  36  *
  37  * TODO
  38  *              APM save restore assist code on IBM thinkpad
  39  *
  40  * Status:
  41  *              Tested. Believed fully functional.
  42  */
  43
  44 #include <linux/config.h>
  45 #include <linux/init.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/module.h>
  48 #include <linux/stddef.h>
  49 #include <linux/isapnp.h>
  50 #include <linux/pnp.h>
  51 #include <linux/spinlock.h>
  52
  53 #define DEB(x)
  54 #define DEB1(x)
  55 #include "sound_config.h"
  56
  57 #include "ad1848.h"
  58 #include "ad1848_mixer.h"
  59
  60 typedef struct
  61 {
  62         spinlock_t      lock;
  63         int             base;
  64         int             irq;
  65         int             dma1, dma2;
  66         int             dual_dma;       /* 1, when two DMA channels allocated */
  67         int             subtype;
  68         unsigned char   MCE_bit;
  69         unsigned char   saved_regs[64]; /* Includes extended register space */
  70         int             debug_flag;
  71
  72         int             audio_flags;
  73         int             record_dev, playback_dev;
  74
  75         int             xfer_count;
  76         int             audio_mode;
  77         int             open_mode;
  78         int             intr_active;
  79         char           *chip_name, *name;
  80         int             model;
  81 #define MD_1848         1
  82 #define MD_4231         2
  83 #define MD_4231A        3
  84 #define MD_1845         4
  85 #define MD_4232         5
  86 #define MD_C930         6
  87 #define MD_IWAVE        7
  88 #define MD_4235         8 /* Crystal Audio CS4235  */
  89 #define MD_1845_SSCAPE  9 /* Ensoniq Soundscape PNP*/
  90 #define MD_4236         10 /* 4236 and higher */
  91 #define MD_42xB         11 /* CS 42xB */
  92 #define MD_4239         12 /* CS4239 */
  93
  94         /* Mixer parameters */
  95         int             recmask;
  96         int             supported_devices, orig_devices;
  97         int             supported_rec_devices, orig_rec_devices;
  98         int            *levels;
  99         short           mixer_reroute[32];
 100         int             dev_no;
 101         volatile unsigned long timer_ticks;
 102         int             timer_running;
 103         int             irq_ok;
 104         mixer_ents     *mix_devices;
 105         int             mixer_output_port;
 106 } ad1848_info;
 107
 108 typedef struct ad1848_port_info
 109 {
 110         int             open_mode;
 111         int             speed;
 112         unsigned char   speed_bits;
 113         int             channels;
 114         int             audio_format;
 115         unsigned char   format_bits;
 116 }
 117 ad1848_port_info;
 118
 119 static struct address_info cfg;
 120 static int nr_ad1848_devs;
 121
 122 static int deskpro_xl;
 123 static int deskpro_m;
 124 static int soundpro;
 125
 126 static volatile signed char irq2dev[17] = {
 127         -1, -1, -1, -1, -1, -1, -1, -1,
 128         -1, -1, -1, -1, -1, -1, -1, -1, -1
 129 };
 130
 131 #ifndef EXCLUDE_TIMERS
 132 static int timer_installed = -1;
 133 #endif
 134
 135 static int loaded;
 136
 137 static int ad_format_mask[13 /*devc->model */ ] =
 138 {
 139         0,
 140         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 141         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 142         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 143         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,       /* AD1845 */
 144         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 145         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 146         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 147         AFMT_U8 | AFMT_S16_LE /* CS4235 */,
 148         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW        /* Ensoniq Soundscape*/,
 149         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 150         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 151         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
 152 };
 153
 154 static ad1848_info adev_info[MAX_AUDIO_DEV];
 155
 156 #define io_Index_Addr(d)        ((d)->base)
 157 #define io_Indexed_Data(d)      ((d)->base+1)
 158 #define io_Status(d)            ((d)->base+2)
 159 #define io_Polled_IO(d)         ((d)->base+3)
 160
 161 static struct {
 162      unsigned char flags;
 163 #define CAP_F_TIMER 0x01
 164 } capabilities [10 /*devc->model */ ] = {
 165      {0}
 166     ,{0}           /* MD_1848  */
 167     ,{CAP_F_TIMER} /* MD_4231  */
 168     ,{CAP_F_TIMER} /* MD_4231A */
 169     ,{CAP_F_TIMER} /* MD_1845  */
 170     ,{CAP_F_TIMER} /* MD_4232  */
 171     ,{0}           /* MD_C930  */
 172     ,{CAP_F_TIMER} /* MD_IWAVE */
 173     ,{0}           /* MD_4235  */
 174     ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
 175 };
 176
 177 #ifdef CONFIG_PNP
 178 static int isapnp       = 1;
 179 static int isapnpjump;
 180 static int reverse;
 181
 182 static int audio_activated;
 183 #else
 184 static int isapnp;
 185 #endif
 186
 187
 188
 189 static int      ad1848_open(int dev, int mode);
 190 static void     ad1848_close(int dev);
 191 static void     ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
 192 static void     ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
 193 static int      ad1848_prepare_for_output(int dev, int bsize, int bcount);
 194 static int      ad1848_prepare_for_input(int dev, int bsize, int bcount);
 195 static void     ad1848_halt(int dev);
 196 static void     ad1848_halt_input(int dev);
 197 static void     ad1848_halt_output(int dev);
 198 static void     ad1848_trigger(int dev, int bits);
 199
 200 #ifndef EXCLUDE_TIMERS
 201 static int ad1848_tmr_install(int dev);
 202 static void ad1848_tmr_reprogram(int dev);
 203 #endif
 204
 205 static int ad_read(ad1848_info * devc, int reg)
 206 {
 207         int x;
 208         int timeout = 900000;
 209
 210         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 211                 timeout--;
 212
 213         if(reg < 32)
 214         {
 215                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 216                 x = inb(io_Indexed_Data(devc));
 217         }
 218         else
 219         {
 220                 int xreg, xra;
 221
 222                 xreg = (reg & 0xff) - 32;
 223                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 224                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 225                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 226                 x = inb(io_Indexed_Data(devc));
 227         }
 228
 229         return x;
 230 }
 231
 232 static void ad_write(ad1848_info * devc, int reg, int data)
 233 {
 234         int timeout = 900000;
 235
 236         while (timeout > 0 && inb(devc->base) == 0x80)  /* Are we initializing */
 237                 timeout--;
 238
 239         if(reg < 32)
 240         {
 241                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 242                 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
 243         }
 244         else
 245         {
 246                 int xreg, xra;
 247
 248                 xreg = (reg & 0xff) - 32;
 249                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 250                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 251                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 252                 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
 253         }
 254 }
 255
 256 static void wait_for_calibration(ad1848_info * devc)
 257 {
 258         int timeout = 0;
 259
 260         /*
 261          * Wait until the auto calibration process has finished.
 262          *
 263          * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 264          * 2)       Wait until the ACI bit of I11 gets on and then off.
 265          */
 266
 267         timeout = 100000;
 268         while (timeout > 0 && inb(devc->base) == 0x80)
 269                 timeout--;
 270         if (inb(devc->base) & 0x80)
 271                 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
 272
 273         timeout = 100;
 274         while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
 275                 timeout--;
 276         if (!(ad_read(devc, 11) & 0x20))
 277                 return;
 278
 279         timeout = 80000;
 280         while (timeout > 0 && (ad_read(devc, 11) & 0x20))
 281                 timeout--;
 282         if (ad_read(devc, 11) & 0x20)
 283                 if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
 284                         printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
 285 }
 286
 287 static void ad_mute(ad1848_info * devc)
 288 {
 289         int i;
 290         unsigned char prev;
 291
 292         /*
 293          * Save old register settings and mute output channels
 294          */
 295
 296         for (i = 6; i < 8; i++)
 297         {
 298                 prev = devc->saved_regs[i] = ad_read(devc, i);
 299         }
 300
 301 }
 302
 303 static void ad_unmute(ad1848_info * devc)
 304 {
 305 }
 306
 307 static void ad_enter_MCE(ad1848_info * devc)
 308 {
 309         int timeout = 1000;
 310         unsigned short prev;
 311
 312         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 313                 timeout--;
 314
 315         devc->MCE_bit = 0x40;
 316         prev = inb(io_Index_Addr(devc));
 317         if (prev & 0x40)
 318         {
 319                 return;
 320         }
 321         outb((devc->MCE_bit), io_Index_Addr(devc));
 322 }
 323
 324 static void ad_leave_MCE(ad1848_info * devc)
 325 {
 326         unsigned char prev, acal;
 327         int timeout = 1000;
 328
 329         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 330                 timeout--;
 331
 332         acal = ad_read(devc, 9);
 333
 334         devc->MCE_bit = 0x00;
 335         prev = inb(io_Index_Addr(devc));
 336         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 337
 338         if ((prev & 0x40) == 0) /* Not in MCE mode */
 339         {
 340                 return;
 341         }
 342         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 343         if (acal & 0x08)        /* Auto calibration is enabled */
 344                 wait_for_calibration(devc);
 345 }
 346
 347 static int ad1848_set_recmask(ad1848_info * devc, int mask)
 348 {
 349         unsigned char   recdev;
 350         int             i, n;
 351         unsigned long flags;
 352
 353         mask &= devc->supported_rec_devices;
 354
 355         /* Rename the mixer bits if necessary */
 356         for (i = 0; i < 32; i++)
 357         {
 358                 if (devc->mixer_reroute[i] != i)
 359                 {
 360                         if (mask & (1 << i))
 361                         {
 362                                 mask &= ~(1 << i);
 363                                 mask |= (1 << devc->mixer_reroute[i]);
 364                         }
 365                 }
 366         }
 367
 368         n = 0;
 369         for (i = 0; i < 32; i++)        /* Count selected device bits */
 370                 if (mask & (1 << i))
 371                         n++;
 372
 373         spin_lock_irqsave(&devc->lock,flags);
 374         if (!soundpro) {
 375                 if (n == 0)
 376                         mask = SOUND_MASK_MIC;
 377                 else if (n != 1) {      /* Too many devices selected */
 378                         mask &= ~devc->recmask; /* Filter out active settings */
 379
 380                         n = 0;
 381                         for (i = 0; i < 32; i++)        /* Count selected device bits */
 382                                 if (mask & (1 << i))
 383                                         n++;
 384
 385                         if (n != 1)
 386                                 mask = SOUND_MASK_MIC;
 387                 }
 388                 switch (mask) {
 389                 case SOUND_MASK_MIC:
 390                         recdev = 2;
 391                         break;
 392
 393                 case SOUND_MASK_LINE:
 394                 case SOUND_MASK_LINE3:
 395                         recdev = 0;
 396                         break;
 397
 398                 case SOUND_MASK_CD:
 399                 case SOUND_MASK_LINE1:
 400                         recdev = 1;
 401                         break;
 402
 403                 case SOUND_MASK_IMIX:
 404                         recdev = 3;
 405                         break;
 406
 407                 default:
 408                         mask = SOUND_MASK_MIC;
 409                         recdev = 2;
 410                 }
 411
 412                 recdev <<= 6;
 413                 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
 414                 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
 415         } else { /* soundpro */
 416                 unsigned char val;
 417                 int set_rec_bit;
 418                 int j;
 419
 420                 for (i = 0; i < 32; i++) {      /* For each bit */
 421                         if ((devc->supported_rec_devices & (1 << i)) == 0)
 422                                 continue;       /* Device not supported */
 423
 424                         for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
 425                                 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
 426                                         continue;
 427
 428                                 /*
 429                                  * This is tricky:
 430                                  * set_rec_bit becomes 1 if the corresponding bit in mask is set
 431                                  * then it gets flipped if the polarity is inverse
 432                                  */
 433                                 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
 434
 435                                 val = ad_read(devc, devc->mix_devices[i][j].recreg);
 436                                 val &= ~(1 << devc->mix_devices[i][j].recpos);
 437                                 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
 438                                 ad_write(devc, devc->mix_devices[i][j].recreg, val);
 439                         }
 440                 }
 441         }
 442         spin_unlock_irqrestore(&devc->lock,flags);
 443
 444         /* Rename the mixer bits back if necessary */
 445         for (i = 0; i < 32; i++)
 446         {
 447                 if (devc->mixer_reroute[i] != i)
 448                 {
 449                         if (mask & (1 << devc->mixer_reroute[i]))
 450                         {
 451                                 mask &= ~(1 << devc->mixer_reroute[i]);
 452                                 mask |= (1 << i);
 453                         }
 454                 }
 455         }
 456         devc->recmask = mask;
 457         return mask;
 458 }
 459
 460 static void change_bits(ad1848_info * devc, unsigned char *regval,
 461                         unsigned char *muteval, int dev, int chn, int newval)
 462 {
 463         unsigned char mask;
 464         int shift;
 465         int mute;
 466         int mutemask;
 467         int set_mute_bit;
 468
 469         set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
 470
 471         if (devc->mix_devices[dev][chn].polarity == 1)  /* Reverse */
 472                 newval = 100 - newval;
 473
 474         mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
 475         shift = devc->mix_devices[dev][chn].bitpos;
 476
 477         if (devc->mix_devices[dev][chn].mutepos == 8)
 478         {                       /* if there is no mute bit */
 479                 mute = 0;       /* No mute bit; do nothing special */
 480                 mutemask = ~0;  /* No mute bit; do nothing special */
 481         }
 482         else
 483         {
 484                 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
 485                 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
 486         }
 487
 488         newval = (int) ((newval * mask) + 50) / 100;    /* Scale it */
 489         *regval &= ~(mask << shift);                    /* Clear bits */
 490         *regval |= (newval & mask) << shift;            /* Set new value */
 491
 492         *muteval &= mutemask;
 493         *muteval |= mute;
 494 }
 495
 496 static int ad1848_mixer_get(ad1848_info * devc, int dev)
 497 {
 498         if (!((1 << dev) & devc->supported_devices))
 499                 return -EINVAL;
 500
 501         dev = devc->mixer_reroute[dev];
 502
 503         return devc->levels[dev];
 504 }
 505
 506 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
 507 {
 508         int regoffs, muteregoffs;
 509         unsigned char val, muteval;
 510         unsigned long flags;
 511
 512         regoffs = devc->mix_devices[dev][channel].regno;
 513         muteregoffs = devc->mix_devices[dev][channel].mutereg;
 514         val = ad_read(devc, regoffs);
 515
 516         if (muteregoffs != regoffs) {
 517                 muteval = ad_read(devc, muteregoffs);
 518                 change_bits(devc, &val, &muteval, dev, channel, value);
 519         }
 520         else
 521                 change_bits(devc, &val, &val, dev, channel, value);
 522
 523         spin_lock_irqsave(&devc->lock,flags);
 524         ad_write(devc, regoffs, val);
 525         devc->saved_regs[regoffs] = val;
 526         if (muteregoffs != regoffs) {
 527                 ad_write(devc, muteregoffs, muteval);
 528                 devc->saved_regs[muteregoffs] = muteval;
 529         }
 530         spin_unlock_irqrestore(&devc->lock,flags);
 531 }
 532
 533 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
 534 {
 535         int left = value & 0x000000ff;
 536         int right = (value & 0x0000ff00) >> 8;
 537         int retvol;
 538
 539         if (dev > 31)
 540                 return -EINVAL;
 541
 542         if (!(devc->supported_devices & (1 << dev)))
 543                 return -EINVAL;
 544
 545         dev = devc->mixer_reroute[dev];
 546
 547         if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
 548                 return -EINVAL;
 549
 550         if (left > 100)
 551                 left = 100;
 552         if (right > 100)
 553                 right = 100;
 554
 555         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)       /* Mono control */
 556                 right = left;
 557
 558         retvol = left | (right << 8);
 559
 560         /* Scale volumes */
 561         left = mix_cvt[left];
 562         right = mix_cvt[right];
 563
 564         devc->levels[dev] = retvol;
 565
 566         /*
 567          * Set the left channel
 568          */
 569         ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
 570
 571         /*
 572          * Set the right channel
 573          */
 574         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
 575                 goto out;
 576         ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
 577
 578  out:
 579         return retvol;
 580 }
 581
 582 static void ad1848_mixer_reset(ad1848_info * devc)
 583 {
 584         int i;
 585         char name[32];
 586         unsigned long flags;
 587
 588         devc->mix_devices = &(ad1848_mix_devices[0]);
 589
 590         sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
 591
 592         for (i = 0; i < 32; i++)
 593                 devc->mixer_reroute[i] = i;
 594
 595         devc->supported_rec_devices = MODE1_REC_DEVICES;
 596
 597         switch (devc->model)
 598         {
 599                 case MD_4231:
 600                 case MD_4231A:
 601                 case MD_1845:
 602                 case MD_1845_SSCAPE:
 603                         devc->supported_devices = MODE2_MIXER_DEVICES;
 604                         break;
 605
 606                 case MD_C930:
 607                         devc->supported_devices = C930_MIXER_DEVICES;
 608                         devc->mix_devices = &(c930_mix_devices[0]);
 609                         break;
 610
 611                 case MD_IWAVE:
 612                         devc->supported_devices = MODE3_MIXER_DEVICES;
 613                         devc->mix_devices = &(iwave_mix_devices[0]);
 614                         break;
 615
 616                 case MD_42xB:
 617                 case MD_4239:
 618                         devc->mix_devices = &(cs42xb_mix_devices[0]);
 619                         devc->supported_devices = MODE3_MIXER_DEVICES;
 620                         break;
 621                 case MD_4232:
 622                 case MD_4235:
 623                 case MD_4236:
 624                         devc->supported_devices = MODE3_MIXER_DEVICES;
 625                         break;
 626
 627                 case MD_1848:
 628                         if (soundpro) {
 629                                 devc->supported_devices = SPRO_MIXER_DEVICES;
 630                                 devc->supported_rec_devices = SPRO_REC_DEVICES;
 631                                 devc->mix_devices = &(spro_mix_devices[0]);
 632                                 break;
 633                         }
 634
 635                 default:
 636                         devc->supported_devices = MODE1_MIXER_DEVICES;
 637         }
 638
 639         devc->orig_devices = devc->supported_devices;
 640         devc->orig_rec_devices = devc->supported_rec_devices;
 641
 642         devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
 643
 644         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 645         {
 646                 if (devc->supported_devices & (1 << i))
 647                         ad1848_mixer_set(devc, i, devc->levels[i]);
 648         }
 649
 650         ad1848_set_recmask(devc, SOUND_MASK_MIC);
 651
 652         devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
 653
 654         spin_lock_irqsave(&devc->lock,flags);
 655         if (!soundpro) {
 656                 if (devc->mixer_output_port & AUDIO_SPEAKER)
 657                         ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 658                 else
 659                         ad_write(devc, 26, ad_read(devc, 26) | 0x40);   /* Mute mono out */
 660         } else {
 661                 /*
 662                  * From the "wouldn't it be nice if the mixer API had (better)
 663                  * support for custom stuff" category
 664                  */
 665                 /* Enable surround mode and SB16 mixer */
 666                 ad_write(devc, 16, 0x60);
 667         }
 668         spin_unlock_irqrestore(&devc->lock,flags);
 669 }
 670
 671 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
 672 {
 673         ad1848_info *devc = mixer_devs[dev]->devc;
 674         int val;
 675
 676         if (cmd == SOUND_MIXER_PRIVATE1)
 677         {
 678                 if (get_user(val, (int __user *)arg))
 679                         return -EFAULT;
 680
 681                 if (val != 0xffff)
 682                 {
 683                         unsigned long flags;
 684                         val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
 685                         devc->mixer_output_port = val;
 686                         val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT;        /* Always on */
 687                         devc->mixer_output_port = val;
 688                         spin_lock_irqsave(&devc->lock,flags);
 689                         if (val & AUDIO_SPEAKER)
 690                                 ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 691                         else
 692                                 ad_write(devc, 26, ad_read(devc, 26) | 0x40);           /* Mute mono out */
 693                         spin_unlock_irqrestore(&devc->lock,flags);
 694                 }
 695                 val = devc->mixer_output_port;
 696                 return put_user(val, (int __user *)arg);
 697         }
 698         if (cmd == SOUND_MIXER_PRIVATE2)
 699         {
 700                 if (get_user(val, (int __user *)arg))
 701                         return -EFAULT;
 702                 return(ad1848_control(AD1848_MIXER_REROUTE, val));
 703         }
 704         if (((cmd >> 8) & 0xff) == 'M')
 705         {
 706                 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
 707                 {
 708                         switch (cmd & 0xff)
 709                         {
 710                                 case SOUND_MIXER_RECSRC:
 711                                         if (get_user(val, (int __user *)arg))
 712                                                 return -EFAULT;
 713                                         val = ad1848_set_recmask(devc, val);
 714                                         break;
 715
 716                                 default:
 717                                         if (get_user(val, (int __user *)arg))
 718                                         return -EFAULT;
 719                                         val = ad1848_mixer_set(devc, cmd & 0xff, val);
 720                                         break;
 721                         }
 722                         return put_user(val, (int __user *)arg);
 723                 }
 724                 else
 725                 {
 726                         switch (cmd & 0xff)
 727                         {
 728                                 /*
 729                                  * Return parameters
 730                                  */
 731
 732                                 case SOUND_MIXER_RECSRC:
 733                                         val = devc->recmask;
 734                                         break;
 735
 736                                 case SOUND_MIXER_DEVMASK:
 737                                         val = devc->supported_devices;
 738                                         break;
 739
 740                                 case SOUND_MIXER_STEREODEVS:
 741                                         val = devc->supported_devices;
 742                                         if (devc->model != MD_C930)
 743                                                 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
 744                                         break;
 745
 746                                 case SOUND_MIXER_RECMASK:
 747                                         val = devc->supported_rec_devices;
 748                                         break;
 749
 750                                 case SOUND_MIXER_CAPS:
 751                                         val=SOUND_CAP_EXCL_INPUT;
 752                                         break;
 753
 754                                 default:
 755                                         val = ad1848_mixer_get(devc, cmd & 0xff);
 756                                         break;
 757                         }
 758                         return put_user(val, (int __user *)arg);
 759                 }
 760         }
 761         else
 762                 return -EINVAL;
 763 }
 764
 765 static int ad1848_set_speed(int dev, int arg)
 766 {
 767         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
 768         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 769
 770         /*
 771          * The sampling speed is encoded in the least significant nibble of I8. The
 772          * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
 773          * three bits select the divisor (indirectly):
 774          *
 775          * The available speeds are in the following table. Keep the speeds in
 776          * the increasing order.
 777          */
 778         typedef struct
 779         {
 780                 int             speed;
 781                 unsigned char   bits;
 782         }
 783         speed_struct;
 784
 785         static speed_struct speed_table[] =
 786         {
 787                 {5510, (0 << 1) | 1},
 788                 {5510, (0 << 1) | 1},
 789                 {6620, (7 << 1) | 1},
 790                 {8000, (0 << 1) | 0},
 791                 {9600, (7 << 1) | 0},
 792                 {11025, (1 << 1) | 1},
 793                 {16000, (1 << 1) | 0},
 794                 {18900, (2 << 1) | 1},
 795                 {22050, (3 << 1) | 1},
 796                 {27420, (2 << 1) | 0},
 797                 {32000, (3 << 1) | 0},
 798                 {33075, (6 << 1) | 1},
 799                 {37800, (4 << 1) | 1},
 800                 {44100, (5 << 1) | 1},
 801                 {48000, (6 << 1) | 0}
 802         };
 803
 804         int i, n, selected = -1;
 805
 806         n = sizeof(speed_table) / sizeof(speed_struct);
 807
 808         if (arg <= 0)
 809                 return portc->speed;
 810
 811         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)    /* AD1845 has different timer than others */
 812         {
 813                 if (arg < 4000)
 814                         arg = 4000;
 815                 if (arg > 50000)
 816                         arg = 50000;
 817
 818                 portc->speed = arg;
 819                 portc->speed_bits = speed_table[3].bits;
 820                 return portc->speed;
 821         }
 822         if (arg < speed_table[0].speed)
 823                 selected = 0;
 824         if (arg > speed_table[n - 1].speed)
 825                 selected = n - 1;
 826
 827         for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 828         {
 829                 if (speed_table[i].speed == arg)
 830                         selected = i;
 831                 else if (speed_table[i].speed > arg)
 832                 {
 833                         int diff1, diff2;
 834
 835                         diff1 = arg - speed_table[i - 1].speed;
 836                         diff2 = speed_table[i].speed - arg;
 837
 838                         if (diff1 < diff2)
 839                                 selected = i - 1;
 840                         else
 841                                 selected = i;
 842                 }
 843         }
 844         if (selected == -1)
 845         {
 846                 printk(KERN_WARNING "ad1848: Can't find speed???\n");
 847                 selected = 3;
 848         }
 849         portc->speed = speed_table[selected].speed;
 850         portc->speed_bits = speed_table[selected].bits;
 851         return portc->speed;
 852 }
 853
 854 static short ad1848_set_channels(int dev, short arg)
 855 {
 856         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 857
 858         if (arg != 1 && arg != 2)
 859                 return portc->channels;
 860
 861         portc->channels = arg;
 862         return arg;
 863 }
 864
 865 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
 866 {
 867         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 868         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 869
 870         static struct format_tbl
 871         {
 872                   int             format;
 873                   unsigned char   bits;
 874         }
 875         format2bits[] =
 876         {
 877                 {
 878                         0, 0
 879                 }
 880                 ,
 881                 {
 882                         AFMT_MU_LAW, 1
 883                 }
 884                 ,
 885                 {
 886                         AFMT_A_LAW, 3
 887                 }
 888                 ,
 889                 {
 890                         AFMT_IMA_ADPCM, 5
 891                 }
 892                 ,
 893                 {
 894                         AFMT_U8, 0
 895                 }
 896                 ,
 897                 {
 898                         AFMT_S16_LE, 2
 899                 }
 900                 ,
 901                 {
 902                         AFMT_S16_BE, 6
 903                 }
 904                 ,
 905                 {
 906                         AFMT_S8, 0
 907                 }
 908                 ,
 909                 {
 910                         AFMT_U16_LE, 0
 911                 }
 912                 ,
 913                 {
 914                         AFMT_U16_BE, 0
 915                 }
 916         };
 917         int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
 918
 919         if (arg == 0)
 920                 return portc->audio_format;
 921
 922         if (!(arg & ad_format_mask[devc->model]))
 923                 arg = AFMT_U8;
 924
 925         portc->audio_format = arg;
 926
 927         for (i = 0; i < n; i++)
 928                 if (format2bits[i].format == arg)
 929                 {
 930                         if ((portc->format_bits = format2bits[i].bits) == 0)
 931                                 return portc->audio_format = AFMT_U8;           /* Was not supported */
 932
 933                         return arg;
 934                 }
 935         /* Still hanging here. Something must be terribly wrong */
 936         portc->format_bits = 0;
 937         return portc->audio_format = AFMT_U8;
 938 }
 939
 940 static struct audio_driver ad1848_audio_driver =
 941 {
 942         .owner                  = THIS_MODULE,
 943         .open                   = ad1848_open,
 944         .close                  = ad1848_close,
 945         .output_block           = ad1848_output_block,
 946         .start_input            = ad1848_start_input,
 947         .prepare_for_input      = ad1848_prepare_for_input,
 948         .prepare_for_output     = ad1848_prepare_for_output,
 949         .halt_io                = ad1848_halt,
 950         .halt_input             = ad1848_halt_input,
 951         .halt_output            = ad1848_halt_output,
 952         .trigger                = ad1848_trigger,
 953         .set_speed              = ad1848_set_speed,
 954         .set_bits               = ad1848_set_bits,
 955         .set_channels           = ad1848_set_channels
 956 };
 957
 958 static struct mixer_operations ad1848_mixer_operations =
 959 {
 960         .owner  = THIS_MODULE,
 961         .id     = "SOUNDPORT",
 962         .name   = "AD1848/CS4248/CS4231",
 963         .ioctl  = ad1848_mixer_ioctl
 964 };
 965
 966 static int ad1848_open(int dev, int mode)
 967 {
 968         ad1848_info    *devc;
 969         ad1848_port_info *portc;
 970         unsigned long   flags;
 971
 972         if (dev < 0 || dev >= num_audiodevs)
 973                 return -ENXIO;
 974
 975         devc = (ad1848_info *) audio_devs[dev]->devc;
 976         portc = (ad1848_port_info *) audio_devs[dev]->portc;
 977
 978         /* here we don't have to protect against intr */
 979         spin_lock(&devc->lock);
 980         if (portc->open_mode || (devc->open_mode & mode))
 981         {
 982                 spin_unlock(&devc->lock);
 983                 return -EBUSY;
 984         }
 985         devc->dual_dma = 0;
 986
 987         if (audio_devs[dev]->flags & DMA_DUPLEX)
 988         {
 989                 devc->dual_dma = 1;
 990         }
 991         devc->intr_active = 0;
 992         devc->audio_mode = 0;
 993         devc->open_mode |= mode;
 994         portc->open_mode = mode;
 995         spin_unlock(&devc->lock);
 996         ad1848_trigger(dev, 0);
 997
 998         if (mode & OPEN_READ)
 999                 devc->record_dev = dev;
1000         if (mode & OPEN_WRITE)
1001                 devc->playback_dev = dev;
1002 /*
1003  * Mute output until the playback really starts. This decreases clicking (hope so).
1004  */
1005         spin_lock_irqsave(&devc->lock,flags);
1006         ad_mute(devc);
1007         spin_unlock_irqrestore(&devc->lock,flags);
1008
1009         return 0;
1010 }
1011
1012 static void ad1848_close(int dev)
1013 {
1014         unsigned long   flags;
1015         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1016         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1017
1018         DEB(printk("ad1848_close(void)\n"));
1019
1020         devc->intr_active = 0;
1021         ad1848_halt(dev);
1022
1023         spin_lock_irqsave(&devc->lock,flags);
1024
1025         devc->audio_mode = 0;
1026         devc->open_mode &= ~portc->open_mode;
1027         portc->open_mode = 0;
1028
1029         ad_unmute(devc);
1030         spin_unlock_irqrestore(&devc->lock,flags);
1031 }
1032
1033 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1034 {
1035         unsigned long   flags, cnt;
1036         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1037         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1038
1039         cnt = count;
1040
1041         if (portc->audio_format == AFMT_IMA_ADPCM)
1042         {
1043                 cnt /= 4;
1044         }
1045         else
1046         {
1047                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1048                         cnt >>= 1;
1049         }
1050         if (portc->channels > 1)
1051                 cnt >>= 1;
1052         cnt--;
1053
1054         if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1055             intrflag &&
1056             cnt == devc->xfer_count)
1057         {
1058                 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1059                 devc->intr_active = 1;
1060                 return; /*
1061                          * Auto DMA mode on. No need to react
1062                          */
1063         }
1064         spin_lock_irqsave(&devc->lock,flags);
1065
1066         ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1067         ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1068
1069         devc->xfer_count = cnt;
1070         devc->audio_mode |= PCM_ENABLE_OUTPUT;
1071         devc->intr_active = 1;
1072         spin_unlock_irqrestore(&devc->lock,flags);
1073 }
1074
1075 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1076 {
1077         unsigned long   flags, cnt;
1078         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1079         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1080
1081         cnt = count;
1082         if (portc->audio_format == AFMT_IMA_ADPCM)
1083         {
1084                 cnt /= 4;
1085         }
1086         else
1087         {
1088                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1089                         cnt >>= 1;
1090         }
1091         if (portc->channels > 1)
1092                 cnt >>= 1;
1093         cnt--;
1094
1095         if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1096                 intrflag &&
1097                 cnt == devc->xfer_count)
1098         {
1099                 devc->audio_mode |= PCM_ENABLE_INPUT;
1100                 devc->intr_active = 1;
1101                 return; /*
1102                          * Auto DMA mode on. No need to react
1103                          */
1104         }
1105         spin_lock_irqsave(&devc->lock,flags);
1106
1107         if (devc->model == MD_1848)
1108         {
1109                   ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1110                   ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1111         }
1112         else
1113         {
1114                   ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1115                   ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1116         }
1117
1118         ad_unmute(devc);
1119
1120         devc->xfer_count = cnt;
1121         devc->audio_mode |= PCM_ENABLE_INPUT;
1122         devc->intr_active = 1;
1123         spin_unlock_irqrestore(&devc->lock,flags);
1124 }
1125
1126 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1127 {
1128         int             timeout;
1129         unsigned char   fs, old_fs, tmp = 0;
1130         unsigned long   flags;
1131         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1132         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1133
1134         ad_mute(devc);
1135
1136         spin_lock_irqsave(&devc->lock,flags);
1137         fs = portc->speed_bits | (portc->format_bits << 5);
1138
1139         if (portc->channels > 1)
1140                 fs |= 0x10;
1141
1142         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1143
1144         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1145         {
1146                 fs &= 0xf0;     /* Mask off the rate select bits */
1147
1148                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1149                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1150         }
1151         old_fs = ad_read(devc, 8);
1152
1153         if (devc->model == MD_4232 || devc->model >= MD_4236)
1154         {
1155                 tmp = ad_read(devc, 16);
1156                 ad_write(devc, 16, tmp | 0x30);
1157         }
1158         if (devc->model == MD_IWAVE)
1159                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1160
1161         ad_write(devc, 8, fs);
1162
1163         /*
1164          * Write to I8 starts resynchronization. Wait until it completes.
1165          */
1166
1167         timeout = 0;
1168         while (timeout < 100 && inb(devc->base) != 0x80)
1169                 timeout++;
1170         timeout = 0;
1171         while (timeout < 10000 && inb(devc->base) == 0x80)
1172                 timeout++;
1173
1174         if (devc->model >= MD_4232)
1175                 ad_write(devc, 16, tmp & ~0x30);
1176
1177         ad_leave_MCE(devc);     /*
1178                                  * Starts the calibration process.
1179                                  */
1180         spin_unlock_irqrestore(&devc->lock,flags);
1181         devc->xfer_count = 0;
1182
1183 #ifndef EXCLUDE_TIMERS
1184         if (dev == timer_installed && devc->timer_running)
1185                 if ((fs & 0x01) != (old_fs & 0x01))
1186                 {
1187                         ad1848_tmr_reprogram(dev);
1188                 }
1189 #endif
1190         ad1848_halt_output(dev);
1191         return 0;
1192 }
1193
1194 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1195 {
1196         int timeout;
1197         unsigned char fs, old_fs, tmp = 0;
1198         unsigned long flags;
1199         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1200         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1201
1202         if (devc->audio_mode)
1203                 return 0;
1204
1205         spin_lock_irqsave(&devc->lock,flags);
1206         fs = portc->speed_bits | (portc->format_bits << 5);
1207
1208         if (portc->channels > 1)
1209                 fs |= 0x10;
1210
1211         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1212
1213         if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE))        /* Use alternate speed select registers */
1214         {
1215                 fs &= 0xf0;     /* Mask off the rate select bits */
1216
1217                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1218                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1219         }
1220         if (devc->model == MD_4232)
1221         {
1222                 tmp = ad_read(devc, 16);
1223                 ad_write(devc, 16, tmp | 0x30);
1224         }
1225         if (devc->model == MD_IWAVE)
1226                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1227
1228         /*
1229          * If mode >= 2 (CS4231), set I28. It's the capture format register.
1230          */
1231
1232         if (devc->model != MD_1848)
1233         {
1234                 old_fs = ad_read(devc, 28);
1235                 ad_write(devc, 28, fs);
1236
1237                 /*
1238                  * Write to I28 starts resynchronization. Wait until it completes.
1239                  */
1240
1241                 timeout = 0;
1242                 while (timeout < 100 && inb(devc->base) != 0x80)
1243                         timeout++;
1244
1245                 timeout = 0;
1246                 while (timeout < 10000 && inb(devc->base) == 0x80)
1247                         timeout++;
1248
1249                 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1250                 {
1251                         /*
1252                          * CS4231 compatible devices don't have separate sampling rate selection
1253                          * register for recording an playback. The I8 register is shared so we have to
1254                          * set the speed encoding bits of it too.
1255                          */
1256                         unsigned char   tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1257
1258                         ad_write(devc, 8, tmp);
1259                         /*
1260                          * Write to I8 starts resynchronization. Wait until it completes.
1261                          */
1262                         timeout = 0;
1263                         while (timeout < 100 && inb(devc->base) != 0x80)
1264                                 timeout++;
1265
1266                         timeout = 0;
1267                         while (timeout < 10000 && inb(devc->base) == 0x80)
1268                                 timeout++;
1269                 }
1270         }
1271         else
1272         {                       /* For AD1848 set I8. */
1273
1274                 old_fs = ad_read(devc, 8);
1275                 ad_write(devc, 8, fs);
1276                 /*
1277                  * Write to I8 starts resynchronization. Wait until it completes.
1278                  */
1279                 timeout = 0;
1280                 while (timeout < 100 && inb(devc->base) != 0x80)
1281                         timeout++;
1282                 timeout = 0;
1283                 while (timeout < 10000 && inb(devc->base) == 0x80)
1284                         timeout++;
1285         }
1286
1287         if (devc->model == MD_4232)
1288                 ad_write(devc, 16, tmp & ~0x30);
1289
1290         ad_leave_MCE(devc);     /*
1291                                  * Starts the calibration process.
1292                                  */
1293         spin_unlock_irqrestore(&devc->lock,flags);
1294         devc->xfer_count = 0;
1295
1296 #ifndef EXCLUDE_TIMERS
1297         if (dev == timer_installed && devc->timer_running)
1298         {
1299                 if ((fs & 0x01) != (old_fs & 0x01))
1300                 {
1301                         ad1848_tmr_reprogram(dev);
1302                 }
1303         }
1304 #endif
1305         ad1848_halt_input(dev);
1306         return 0;
1307 }
1308
1309 static void ad1848_halt(int dev)
1310 {
1311         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1312         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1313
1314         unsigned char   bits = ad_read(devc, 9);
1315
1316         if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1317                 ad1848_halt_output(dev);
1318
1319         if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1320                 ad1848_halt_input(dev);
1321         devc->audio_mode = 0;
1322 }
1323
1324 static void ad1848_halt_input(int dev)
1325 {
1326         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1327         unsigned long   flags;
1328
1329         if (!(ad_read(devc, 9) & 0x02))
1330                 return;         /* Capture not enabled */
1331
1332         spin_lock_irqsave(&devc->lock,flags);
1333
1334         ad_mute(devc);
1335
1336         {
1337                 int             tmout;
1338
1339                 if(!isa_dma_bridge_buggy)
1340                         disable_dma(audio_devs[dev]->dmap_in->dma);
1341
1342                 for (tmout = 0; tmout < 100000; tmout++)
1343                         if (ad_read(devc, 11) & 0x10)
1344                                 break;
1345                 ad_write(devc, 9, ad_read(devc, 9) & ~0x02);    /* Stop capture */
1346
1347                 if(!isa_dma_bridge_buggy)
1348                         enable_dma(audio_devs[dev]->dmap_in->dma);
1349                 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1350         }
1351
1352         outb(0, io_Status(devc));       /* Clear interrupt status */
1353         outb(0, io_Status(devc));       /* Clear interrupt status */
1354
1355         devc->audio_mode &= ~PCM_ENABLE_INPUT;
1356
1357         spin_unlock_irqrestore(&devc->lock,flags);
1358 }
1359
1360 static void ad1848_halt_output(int dev)
1361 {
1362         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1363         unsigned long flags;
1364
1365         if (!(ad_read(devc, 9) & 0x01))
1366                 return;         /* Playback not enabled */
1367
1368         spin_lock_irqsave(&devc->lock,flags);
1369
1370         ad_mute(devc);
1371         {
1372                 int             tmout;
1373
1374                 if(!isa_dma_bridge_buggy)
1375                         disable_dma(audio_devs[dev]->dmap_out->dma);
1376
1377                 for (tmout = 0; tmout < 100000; tmout++)
1378                         if (ad_read(devc, 11) & 0x10)
1379                                 break;
1380                 ad_write(devc, 9, ad_read(devc, 9) & ~0x01);    /* Stop playback */
1381
1382                 if(!isa_dma_bridge_buggy)
1383                        enable_dma(audio_devs[dev]->dmap_out->dma);
1384
1385                 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1386         }
1387
1388         outb((0), io_Status(devc));     /* Clear interrupt status */
1389         outb((0), io_Status(devc));     /* Clear interrupt status */
1390
1391         devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1392
1393         spin_unlock_irqrestore(&devc->lock,flags);
1394 }
1395
1396 static void ad1848_trigger(int dev, int state)
1397 {
1398         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1399         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1400         unsigned long   flags;
1401         unsigned char   tmp, old;
1402
1403         spin_lock_irqsave(&devc->lock,flags);
1404         state &= devc->audio_mode;
1405
1406         tmp = old = ad_read(devc, 9);
1407
1408         if (portc->open_mode & OPEN_READ)
1409         {
1410                   if (state & PCM_ENABLE_INPUT)
1411                           tmp |= 0x02;
1412                   else
1413                           tmp &= ~0x02;
1414         }
1415         if (portc->open_mode & OPEN_WRITE)
1416         {
1417                 if (state & PCM_ENABLE_OUTPUT)
1418                         tmp |= 0x01;
1419                 else
1420                         tmp &= ~0x01;
1421         }
1422         /* ad_mute(devc); */
1423         if (tmp != old)
1424         {
1425                   ad_write(devc, 9, tmp);
1426                   ad_unmute(devc);
1427         }
1428         spin_unlock_irqrestore(&devc->lock,flags);
1429 }
1430
1431 static void ad1848_init_hw(ad1848_info * devc)
1432 {
1433         int i;
1434         int *init_values;
1435
1436         /*
1437          * Initial values for the indirect registers of CS4248/AD1848.
1438          */
1439         static int      init_values_a[] =
1440         {
1441                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1442                 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1443
1444         /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1445                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1446                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1447         };
1448
1449         static int      init_values_b[] =
1450         {
1451                 /*
1452                    Values for the newer chips
1453                    Some of the register initialization values were changed. In
1454                    order to get rid of the click that preceded PCM playback,
1455                    calibration was disabled on the 10th byte. On that same byte,
1456                    dual DMA was enabled; on the 11th byte, ADC dithering was
1457                    enabled, since that is theoretically desirable; on the 13th
1458                    byte, Mode 3 was selected, to enable access to extended
1459                    registers.
1460                  */
1461                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1462                 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1463                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1464                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1465         };
1466
1467         /*
1468          *      Select initialisation data
1469          */
1470
1471         init_values = init_values_a;
1472         if(devc->model >= MD_4236)
1473                 init_values = init_values_b;
1474
1475         for (i = 0; i < 16; i++)
1476                 ad_write(devc, i, init_values[i]);
1477
1478
1479         ad_mute(devc);          /* Initialize some variables */
1480         ad_unmute(devc);        /* Leave it unmuted now */
1481
1482         if (devc->model > MD_1848)
1483         {
1484                 if (devc->model == MD_1845_SSCAPE)
1485                         ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1486                 else
1487                         ad_write(devc, 12, ad_read(devc, 12) | 0x40);           /* Mode2 = enabled */
1488
1489                 if (devc->model == MD_IWAVE)
1490                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1491
1492                 if (devc->model != MD_1845_SSCAPE)
1493                         for (i = 16; i < 32; i++)
1494                                 ad_write(devc, i, init_values[i]);
1495
1496                 if (devc->model == MD_IWAVE)
1497                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1498         }
1499         if (devc->model > MD_1848)
1500         {
1501                 if (devc->audio_flags & DMA_DUPLEX)
1502                         ad_write(devc, 9, ad_read(devc, 9) & ~0x04);    /* Dual DMA mode */
1503                 else
1504                         ad_write(devc, 9, ad_read(devc, 9) | 0x04);     /* Single DMA mode */
1505
1506                 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1507                         ad_write(devc, 27, ad_read(devc, 27) | 0x08);           /* Alternate freq select enabled */
1508
1509                 if (devc->model == MD_IWAVE)
1510                 {               /* Some magic Interwave specific initialization */
1511                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1512                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1513                         ad_write(devc, 17, 0xc2);       /* Alternate feature enable */
1514                 }
1515         }
1516         else
1517         {
1518                   devc->audio_flags &= ~DMA_DUPLEX;
1519                   ad_write(devc, 9, ad_read(devc, 9) | 0x04);   /* Single DMA mode */
1520                   if (soundpro)
1521                           ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1522         }
1523
1524         outb((0), io_Status(devc));     /* Clear pending interrupts */
1525
1526         /*
1527          * Toggle the MCE bit. It completes the initialization phase.
1528          */
1529
1530         ad_enter_MCE(devc);     /* In case the bit was off */
1531         ad_leave_MCE(devc);
1532
1533         ad1848_mixer_reset(devc);
1534 }
1535
1536 int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1537 {
1538         unsigned char tmp;
1539         ad1848_info *devc = &adev_info[nr_ad1848_devs];
1540         unsigned char tmp1 = 0xff, tmp2 = 0xff;
1541         int optiC930 = 0;       /* OPTi 82C930 flag */
1542         int interwave = 0;
1543         int ad1847_flag = 0;
1544         int cs4248_flag = 0;
1545         int sscape_flag = 0;
1546         int io_base = ports->start;
1547
1548         int i;
1549
1550         DDB(printk("ad1848_detect(%x)\n", io_base));
1551
1552         if (ad_flags)
1553         {
1554                 if (*ad_flags == 0x12345678)
1555                 {
1556                         interwave = 1;
1557                         *ad_flags = 0;
1558                 }
1559
1560                 if (*ad_flags == 0x87654321)
1561                 {
1562                         sscape_flag = 1;
1563                         *ad_flags = 0;
1564                 }
1565
1566                 if (*ad_flags == 0x12345677)
1567                 {
1568                     cs4248_flag = 1;
1569                     *ad_flags = 0;
1570                 }
1571         }
1572         if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1573         {
1574                 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1575                 return 0;
1576         }
1577         spin_lock_init(&devc->lock);
1578         devc->base = io_base;
1579         devc->irq_ok = 0;
1580         devc->timer_running = 0;
1581         devc->MCE_bit = 0x40;
1582         devc->irq = 0;
1583         devc->open_mode = 0;
1584         devc->chip_name = devc->name = "AD1848";
1585         devc->model = MD_1848;  /* AD1848 or CS4248 */
1586         devc->levels = NULL;
1587         devc->debug_flag = 0;
1588
1589         /*
1590          * Check that the I/O address is in use.
1591          *
1592          * The bit 0x80 of the base I/O port is known to be 0 after the
1593          * chip has performed its power on initialization. Just assume
1594          * this has happened before the OS is starting.
1595          *
1596          * If the I/O address is unused, it typically returns 0xff.
1597          */
1598
1599         if (inb(devc->base) == 0xff)
1600         {
1601                 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1602         }
1603
1604         /*
1605          * Wait for the device to stop initialization
1606          */
1607
1608         DDB(printk("ad1848_detect() - step 0\n"));
1609
1610         for (i = 0; i < 10000000; i++)
1611         {
1612                 unsigned char   x = inb(devc->base);
1613
1614                 if (x == 0xff || !(x & 0x80))
1615                         break;
1616         }
1617
1618         DDB(printk("ad1848_detect() - step A\n"));
1619
1620         if (inb(devc->base) == 0x80)    /* Not ready. Let's wait */
1621                 ad_leave_MCE(devc);
1622
1623         if ((inb(devc->base) & 0x80) != 0x00)   /* Not a AD1848 */
1624         {
1625                 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1626                 return 0;
1627         }
1628
1629         /*
1630          * Test if it's possible to change contents of the indirect registers.
1631          * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1632          * so try to avoid using it.
1633          */
1634
1635         DDB(printk("ad1848_detect() - step B\n"));
1636         ad_write(devc, 0, 0xaa);
1637         ad_write(devc, 1, 0x45);        /* 0x55 with bit 0x10 clear */
1638
1639         if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1640         {
1641                 if (tmp2 == 0x65)       /* AD1847 has couple of bits hardcoded to 1 */
1642                         ad1847_flag = 1;
1643                 else
1644                 {
1645                         DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1646                         return 0;
1647                 }
1648         }
1649         DDB(printk("ad1848_detect() - step C\n"));
1650         ad_write(devc, 0, 0x45);
1651         ad_write(devc, 1, 0xaa);
1652
1653         if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1654         {
1655                 if (tmp2 == 0x8a)       /* AD1847 has few bits hardcoded to 1 */
1656                         ad1847_flag = 1;
1657                 else
1658                 {
1659                         DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1660                         return 0;
1661                 }
1662         }
1663
1664         /*
1665          * The indirect register I12 has some read only bits. Let's
1666          * try to change them.
1667          */
1668
1669         DDB(printk("ad1848_detect() - step D\n"));
1670         tmp = ad_read(devc, 12);
1671         ad_write(devc, 12, (~tmp) & 0x0f);
1672
1673         if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1674         {
1675                 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1676                 return 0;
1677         }
1678
1679         /*
1680          * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1681          *   0x01=RevB and 0x0A=RevC.
1682          */
1683
1684         /*
1685          * The original AD1848/CS4248 has just 15 indirect registers. This means
1686          * that I0 and I16 should return the same value (etc.).
1687          * However this doesn't work with CS4248. Actually it seems to be impossible
1688          * to detect if the chip is a CS4231 or CS4248.
1689          * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1690          * with CS4231.
1691          */
1692
1693         /*
1694          * OPTi 82C930 has mode2 control bit in another place. This test will fail
1695          * with it. Accept this situation as a possible indication of this chip.
1696          */
1697
1698         DDB(printk("ad1848_detect() - step F\n"));
1699         ad_write(devc, 12, 0);  /* Mode2=disabled */
1700
1701         for (i = 0; i < 16; i++)
1702         {
1703                 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1704                 {
1705                         DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1706                         if (!ad1847_flag)
1707                                 optiC930 = 1;
1708                         break;
1709                 }
1710         }
1711
1712         /*
1713          * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1714          * The bit 0x80 is always 1 in CS4248 and CS4231.
1715          */
1716
1717         DDB(printk("ad1848_detect() - step G\n"));
1718
1719         if (ad_flags && *ad_flags == 400)
1720                 *ad_flags = 0;
1721         else
1722                 ad_write(devc, 12, 0x40);       /* Set mode2, clear 0x80 */
1723
1724
1725         if (ad_flags)
1726                 *ad_flags = 0;
1727
1728         tmp1 = ad_read(devc, 12);
1729         if (tmp1 & 0x80)
1730         {
1731                 if (ad_flags)
1732                         *ad_flags |= AD_F_CS4248;
1733
1734                 devc->chip_name = "CS4248";     /* Our best knowledge just now */
1735         }
1736         if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1737         {
1738                 /*
1739                  *      CS4231 detected - is it?
1740                  *
1741                  *      Verify that setting I0 doesn't change I16.
1742                  */
1743
1744                 DDB(printk("ad1848_detect() - step H\n"));
1745                 ad_write(devc, 16, 0);  /* Set I16 to known value */
1746
1747                 ad_write(devc, 0, 0x45);
1748                 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1749                 {
1750                         ad_write(devc, 0, 0xaa);
1751                         if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1752                         {
1753                                 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1754                                 return 0;
1755                         }
1756
1757                         /*
1758                          * Verify that some bits of I25 are read only.
1759                          */
1760
1761                         DDB(printk("ad1848_detect() - step I\n"));
1762                         tmp1 = ad_read(devc, 25);       /* Original bits */
1763                         ad_write(devc, 25, ~tmp1);      /* Invert all bits */
1764                         if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1765                         {
1766                                 int id;
1767
1768                                 /*
1769                                  *      It's at least CS4231
1770                                  */
1771
1772                                 devc->chip_name = "CS4231";
1773                                 devc->model = MD_4231;
1774
1775                                 /*
1776                                  * It could be an AD1845 or CS4231A as well.
1777                                  * CS4231 and AD1845 report the same revision info in I25
1778                                  * while the CS4231A reports different.
1779                                  */
1780
1781                                 id = ad_read(devc, 25);
1782                                 if ((id & 0xe7) == 0x80)        /* Device busy??? */
1783                                         id = ad_read(devc, 25);
1784                                 if ((id & 0xe7) == 0x80)        /* Device still busy??? */
1785                                         id = ad_read(devc, 25);
1786                                 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1787
1788                                 if ((id & 0xe7) == 0x80) {
1789                                         /*
1790                                          * It must be a CS4231 or AD1845. The register I23 of
1791                                          * CS4231 is undefined and it appears to be read only.
1792                                          * AD1845 uses I23 for setting sample rate. Assume
1793                                          * the chip is AD1845 if I23 is changeable.
1794                                          */
1795
1796                                         unsigned char   tmp = ad_read(devc, 23);
1797                                         ad_write(devc, 23, ~tmp);
1798
1799                                         if (interwave)
1800                                         {
1801                                                 devc->model = MD_IWAVE;
1802                                                 devc->chip_name = "IWave";
1803                                         }
1804                                         else if (ad_read(devc, 23) != tmp)      /* AD1845 ? */
1805                                         {
1806                                                 devc->chip_name = "AD1845";
1807                                                 devc->model = MD_1845;
1808                                         }
1809                                         else if (cs4248_flag)
1810                                         {
1811                                                 if (ad_flags)
1812                                                           *ad_flags |= AD_F_CS4248;
1813                                                 devc->chip_name = "CS4248";
1814                                                 devc->model = MD_1848;
1815                                                 ad_write(devc, 12, ad_read(devc, 12) & ~0x40);  /* Mode2 off */
1816                                         }
1817                                         ad_write(devc, 23, tmp);        /* Restore */
1818                                 }
1819                                 else
1820                                 {
1821                                         switch (id & 0x1f) {
1822                                         case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1823                                                 {
1824                                                         int xid;
1825                                                         ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1826                                                         ad_write(devc, 23, 0x9c); /* select extended register 25 */
1827                                                         xid = inb(io_Indexed_Data(devc));
1828                                                         ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1829                                                         switch (xid & 0x1f)
1830                                                         {
1831                                                                 case 0x00:
1832                                                                         devc->chip_name = "CS4237B(B)";
1833                                                                         devc->model = MD_42xB;
1834                                                                         break;
1835                                                                 case 0x08:
1836                                                                         /* Seems to be a 4238 ?? */
1837                                                                         devc->chip_name = "CS4238";
1838                                                                         devc->model = MD_42xB;
1839                                                                         break;
1840                                                                 case 0x09:
1841                                                                         devc->chip_name = "CS4238B";
1842                                                                         devc->model = MD_42xB;
1843                                                                         break;
1844                                                                 case 0x0b:
1845                                                                         devc->chip_name = "CS4236B";
1846                                                                         devc->model = MD_4236;
1847                                                                         break;
1848                                                                 case 0x10:
1849                                                                         devc->chip_name = "CS4237B";
1850                                                                         devc->model = MD_42xB;
1851                                                                         break;
1852                                                                 case 0x1d:
1853                                                                         devc->chip_name = "CS4235";
1854                                                                         devc->model = MD_4235;
1855                                                                         break;
1856                                                                 case 0x1e:
1857                                                                         devc->chip_name = "CS4239";
1858                                                                         devc->model = MD_4239;
1859                                                                         break;
1860                                                                 default:
1861                                                                         printk("Chip ident is %X.\n", xid&0x1F);
1862                                                                         devc->chip_name = "CS42xx";
1863                                                                         devc->model = MD_4232;
1864                                                                         break;
1865                                                         }
1866                                                 }
1867                                                 break;
1868
1869                                         case 2: /* CS4232/CS4232A */
1870                                                 devc->chip_name = "CS4232";
1871                                                 devc->model = MD_4232;
1872                                                 break;
1873
1874                                         case 0:
1875                                                 if ((id & 0xe0) == 0xa0)
1876                                                 {
1877                                                         devc->chip_name = "CS4231A";
1878                                                         devc->model = MD_4231A;
1879                                                 }
1880                                                 else
1881                                                 {
1882                                                         devc->chip_name = "CS4321";
1883                                                         devc->model = MD_4231;
1884                                                 }
1885                                                 break;
1886
1887                                         default: /* maybe */
1888                                                 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1889                                                 if (optiC930)
1890                                                 {
1891                                                         devc->chip_name = "82C930";
1892                                                         devc->model = MD_C930;
1893                                                 }
1894                                                 else
1895                                                 {
1896                                                         devc->chip_name = "CS4231";
1897                                                         devc->model = MD_4231;
1898                                                 }
1899                                         }
1900                                 }
1901                         }
1902                         ad_write(devc, 25, tmp1);       /* Restore bits */
1903
1904                         DDB(printk("ad1848_detect() - step K\n"));
1905                 }
1906         } else if (tmp1 == 0x0a) {
1907                 /*
1908                  * Is it perhaps a SoundPro CMI8330?
1909                  * If so, then we should be able to change indirect registers
1910                  * greater than I15 after activating MODE2, even though reading
1911                  * back I12 does not show it.
1912                  */
1913
1914                 /*
1915                  * Let's try comparing register values
1916                  */
1917                 for (i = 0; i < 16; i++) {
1918                         if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1919                                 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1920                                 soundpro = 1;
1921                                 devc->chip_name = "SoundPro CMI 8330";
1922                                 break;
1923                         }
1924                 }
1925         }
1926
1927         DDB(printk("ad1848_detect() - step L\n"));
1928         if (ad_flags)
1929         {
1930                   if (devc->model != MD_1848)
1931                           *ad_flags |= AD_F_CS4231;
1932         }
1933         DDB(printk("ad1848_detect() - Detected OK\n"));
1934
1935         if (devc->model == MD_1848 && ad1847_flag)
1936                 devc->chip_name = "AD1847";
1937
1938
1939         if (sscape_flag == 1)
1940                 devc->model = MD_1845_SSCAPE;
1941
1942         return 1;
1943 }
1944
1945 int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1946                 int dma_capture, int share_dma, int *osp, struct module *owner)
1947 {
1948         /*
1949          * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1950          *   so that this driver doesn't need to allocate/deallocate it.
1951          *   The actually used IRQ is ABS(irq).
1952          */
1953
1954         int my_dev;
1955         char dev_name[100];
1956         int e;
1957
1958         ad1848_info  *devc = &adev_info[nr_ad1848_devs];
1959
1960         ad1848_port_info *portc = NULL;
1961
1962         devc->irq = (irq > 0) ? irq : 0;
1963         devc->open_mode = 0;
1964         devc->timer_ticks = 0;
1965         devc->dma1 = dma_playback;
1966         devc->dma2 = dma_capture;
1967         devc->subtype = cfg.card_subtype;
1968         devc->audio_flags = DMA_AUTOMODE;
1969         devc->playback_dev = devc->record_dev = 0;
1970         if (name != NULL)
1971                 devc->name = name;
1972
1973         if (name != NULL && name[0] != 0)
1974                 sprintf(dev_name,
1975                         "%s (%s)", name, devc->chip_name);
1976         else
1977                 sprintf(dev_name,
1978                         "Generic audio codec (%s)", devc->chip_name);
1979
1980         rename_region(ports, devc->name);
1981
1982         conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1983
1984         if (devc->model == MD_1848 || devc->model == MD_C930)
1985                 devc->audio_flags |= DMA_HARDSTOP;
1986
1987         if (devc->model > MD_1848)
1988         {
1989                 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1990                         devc->audio_flags &= ~DMA_DUPLEX;
1991                 else
1992                         devc->audio_flags |= DMA_DUPLEX;
1993         }
1994
1995         portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1996         if(portc==NULL) {
1997                 release_region(devc->base, 4);
1998                 return -1;
1999         }
2000
2001         if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2002                                              dev_name,
2003                                              &ad1848_audio_driver,
2004                                              sizeof(struct audio_driver),
2005                                              devc->audio_flags,
2006                                              ad_format_mask[devc->model],
2007                                              devc,
2008                                              dma_playback,
2009                                              dma_capture)) < 0)
2010         {
2011                 release_region(devc->base, 4);
2012                 kfree(portc);
2013                 return -1;
2014         }
2015
2016         audio_devs[my_dev]->portc = portc;
2017         audio_devs[my_dev]->mixer_dev = -1;
2018         if (owner)
2019                 audio_devs[my_dev]->d->owner = owner;
2020         memset((char *) portc, 0, sizeof(*portc));
2021
2022         nr_ad1848_devs++;
2023
2024         ad1848_init_hw(devc);
2025
2026         if (irq > 0)
2027         {
2028                 devc->dev_no = my_dev;
2029                 if (request_irq(devc->irq, adintr, 0, devc->name, (void *)my_dev) < 0)
2030                 {
2031                         printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2032                         /* Don't free it either then.. */
2033                         devc->irq = 0;
2034                 }
2035                 if (capabilities[devc->model].flags & CAP_F_TIMER)
2036                 {
2037 #ifndef CONFIG_SMP
2038                         int x;
2039                         unsigned char tmp = ad_read(devc, 16);
2040 #endif
2041
2042                         devc->timer_ticks = 0;
2043
2044                         ad_write(devc, 21, 0x00);       /* Timer MSB */
2045                         ad_write(devc, 20, 0x10);       /* Timer LSB */
2046 #ifndef CONFIG_SMP
2047                         ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2048                         for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2049                         ad_write(devc, 16, tmp & ~0x40);        /* Disable timer */
2050
2051                         if (devc->timer_ticks == 0)
2052                                 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2053                         else
2054                         {
2055                                 DDB(printk("Interrupt test OK\n"));
2056                                 devc->irq_ok = 1;
2057                         }
2058 #else
2059                         devc->irq_ok = 1;
2060 #endif
2061                 }
2062                 else
2063                         devc->irq_ok = 1;       /* Couldn't test. assume it's OK */
2064         } else if (irq < 0)
2065                 irq2dev[-irq] = devc->dev_no = my_dev;
2066
2067 #ifndef EXCLUDE_TIMERS
2068         if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2069             devc->irq_ok)
2070                 ad1848_tmr_install(my_dev);
2071 #endif
2072
2073         if (!share_dma)
2074         {
2075                 if (sound_alloc_dma(dma_playback, devc->name))
2076                         printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2077
2078                 if (dma_capture != dma_playback)
2079                         if (sound_alloc_dma(dma_capture, devc->name))
2080                                 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2081         }
2082
2083         if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2084                                      dev_name,
2085                                      &ad1848_mixer_operations,
2086                                      sizeof(struct mixer_operations),
2087                                      devc)) >= 0)
2088         {
2089                 audio_devs[my_dev]->mixer_dev = e;
2090                 if (owner)
2091                         mixer_devs[e]->owner = owner;
2092         }
2093         return my_dev;
2094 }
2095
2096 int ad1848_control(int cmd, int arg)
2097 {
2098         ad1848_info *devc;
2099         unsigned long flags;
2100
2101         if (nr_ad1848_devs < 1)
2102                 return -ENODEV;
2103
2104         devc = &adev_info[nr_ad1848_devs - 1];
2105
2106         switch (cmd)
2107         {
2108                 case AD1848_SET_XTAL:   /* Change clock frequency of AD1845 (only ) */
2109                         if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
2110                                 return -EINVAL;
2111                         spin_lock_irqsave(&devc->lock,flags);
2112                         ad_enter_MCE(devc);
2113                         ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2114                         ad_leave_MCE(devc);
2115                         spin_unlock_irqrestore(&devc->lock,flags);
2116                         break;
2117
2118                 case AD1848_MIXER_REROUTE:
2119                 {
2120                         int o = (arg >> 8) & 0xff;
2121                         int n = arg & 0xff;
2122
2123                         if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2124                                 return -EINVAL;
2125
2126                         if (!(devc->supported_devices & (1 << o)) &&
2127                             !(devc->supported_rec_devices & (1 << o)))
2128                                 return -EINVAL;
2129
2130                         if (n == SOUND_MIXER_NONE)
2131                         {       /* Just hide this control */
2132                                 ad1848_mixer_set(devc, o, 0);   /* Shut up it */
2133                                 devc->supported_devices &= ~(1 << o);
2134                                 devc->supported_rec_devices &= ~(1 << o);
2135                                 break;
2136                         }
2137
2138                         /* Make the mixer control identified by o to appear as n */
2139                         if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2140                                 return -EINVAL;
2141
2142                         devc->mixer_reroute[n] = o;     /* Rename the control */
2143                         if (devc->supported_devices & (1 << o))
2144                                 devc->supported_devices |= (1 << n);
2145                         if (devc->supported_rec_devices & (1 << o))
2146                                 devc->supported_rec_devices |= (1 << n);
2147
2148                         devc->supported_devices &= ~(1 << o);
2149                         devc->supported_rec_devices &= ~(1 << o);
2150                 }
2151                 break;
2152         }
2153         return 0;
2154 }
2155
2156 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2157 {
2158         int i, mixer, dev = 0;
2159         ad1848_info *devc = NULL;
2160
2161         for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2162         {
2163                 if (adev_info[i].base == io_base)
2164                 {
2165                         devc = &adev_info[i];
2166                         dev = devc->dev_no;
2167                 }
2168         }
2169
2170         if (devc != NULL)
2171         {
2172                 kfree(audio_devs[dev]->portc);
2173                 release_region(devc->base, 4);
2174
2175                 if (!share_dma)
2176                 {
2177                         if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2178                                 free_irq(devc->irq, (void *)devc->dev_no);
2179
2180                         sound_free_dma(dma_playback);
2181
2182                         if (dma_playback != dma_capture)
2183                                 sound_free_dma(dma_capture);
2184
2185                 }
2186                 mixer = audio_devs[devc->dev_no]->mixer_dev;
2187                 if(mixer>=0)
2188                         sound_unload_mixerdev(mixer);
2189
2190                 nr_ad1848_devs--;
2191                 for ( ; i < nr_ad1848_devs ; i++)
2192                         adev_info[i] = adev_info[i+1];
2193         }
2194         else
2195                 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2196 }
2197
2198 irqreturn_t adintr(int irq, void *dev_id, struct pt_regs *dummy)
2199 {
2200         unsigned char status;
2201         ad1848_info *devc;
2202         int dev;
2203         int alt_stat = 0xff;
2204         unsigned char c930_stat = 0;
2205         int cnt = 0;
2206
2207         dev = (int)dev_id;
2208         devc = (ad1848_info *) audio_devs[dev]->devc;
2209
2210 interrupt_again:                /* Jump back here if int status doesn't reset */
2211
2212         status = inb(io_Status(devc));
2213
2214         if (status == 0x80)
2215                 printk(KERN_DEBUG "adintr: Why?\n");
2216         if (devc->model == MD_1848)
2217                 outb((0), io_Status(devc));     /* Clear interrupt status */
2218
2219         if (status & 0x01)
2220         {
2221                 if (devc->model == MD_C930)
2222                 {               /* 82C930 has interrupt status register in MAD16 register MC11 */
2223
2224                         spin_lock(&devc->lock);
2225
2226                         /* 0xe0e is C930 address port
2227                          * 0xe0f is C930 data port
2228                          */
2229                         outb(11, 0xe0e);
2230                         c930_stat = inb(0xe0f);
2231                         outb((~c930_stat), 0xe0f);
2232
2233                         spin_unlock(&devc->lock);
2234
2235                         alt_stat = (c930_stat << 2) & 0x30;
2236                 }
2237                 else if (devc->model != MD_1848)
2238                 {
2239                         spin_lock(&devc->lock);
2240                         alt_stat = ad_read(devc, 24);
2241                         ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat);      /* Selective ack */
2242                         spin_unlock(&devc->lock);
2243                 }
2244
2245                 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2246                 {
2247                         DMAbuf_inputintr(devc->record_dev);
2248                 }
2249                 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2250                       (alt_stat & 0x10))
2251                 {
2252                         DMAbuf_outputintr(devc->playback_dev, 1);
2253                 }
2254                 if (devc->model != MD_1848 && (alt_stat & 0x40))        /* Timer interrupt */
2255                 {
2256                         devc->timer_ticks++;
2257 #ifndef EXCLUDE_TIMERS
2258                         if (timer_installed == dev && devc->timer_running)
2259                                 sound_timer_interrupt();
2260 #endif
2261                 }
2262         }
2263 /*
2264  * Sometimes playback or capture interrupts occur while a timer interrupt
2265  * is being handled. The interrupt will not be retriggered if we don't
2266  * handle it now. Check if an interrupt is still pending and restart
2267  * the handler in this case.
2268  */
2269         if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2270         {
2271                   goto interrupt_again;
2272         }
2273         return IRQ_HANDLED;
2274 }
2275
2276 /*
2277  *      Experimental initialization sequence for the integrated sound system
2278  *      of the Compaq Deskpro M.
2279  */
2280
2281 static int init_deskpro_m(struct address_info *hw_config)
2282 {
2283         unsigned char   tmp;
2284
2285         if ((tmp = inb(0xc44)) == 0xff)
2286         {
2287                 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2288                 return 0;
2289         }
2290
2291         outb(0x10, 0xc44);
2292         outb(0x40, 0xc45);
2293         outb(0x00, 0xc46);
2294         outb(0xe8, 0xc47);
2295         outb(0x14, 0xc44);
2296         outb(0x40, 0xc45);
2297         outb(0x00, 0xc46);
2298         outb(0xe8, 0xc47);
2299         outb(0x10, 0xc44);
2300
2301         return 1;
2302 }
2303
2304 /*
2305  *      Experimental initialization sequence for the integrated sound system
2306  *      of Compaq Deskpro XL.
2307  */
2308
2309 static int init_deskpro(struct address_info *hw_config)
2310 {
2311         unsigned char   tmp;
2312
2313         if ((tmp = inb(0xc44)) == 0xff)
2314         {
2315                 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2316                 return 0;
2317         }
2318         outb((tmp | 0x04), 0xc44);      /* Select bank 1 */
2319         if (inb(0xc44) != 0x04)
2320         {
2321                 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2322                 return 0;
2323         }
2324         /*
2325          * OK. It looks like a Deskpro so let's proceed.
2326          */
2327
2328         /*
2329          * I/O port 0xc44 Audio configuration register.
2330          *
2331          * bits 0xc0:   Audio revision bits
2332          *              0x00 = Compaq Business Audio
2333          *              0x40 = MS Sound System Compatible (reset default)
2334          *              0x80 = Reserved
2335          *              0xc0 = Reserved
2336          * bit 0x20:    No Wait State Enable
2337          *              0x00 = Disabled (reset default, DMA mode)
2338          *              0x20 = Enabled (programmed I/O mode)
2339          * bit 0x10:    MS Sound System Decode Enable
2340          *              0x00 = Decoding disabled (reset default)
2341          *              0x10 = Decoding enabled
2342          * bit 0x08:    FM Synthesis Decode Enable
2343          *              0x00 = Decoding Disabled (reset default)
2344          *              0x08 = Decoding enabled
2345          * bit 0x04     Bank select
2346          *              0x00 = Bank 0
2347          *              0x04 = Bank 1
2348          * bits 0x03    MSS Base address
2349          *              0x00 = 0x530 (reset default)
2350          *              0x01 = 0x604
2351          *              0x02 = 0xf40
2352          *              0x03 = 0xe80
2353          */
2354
2355 #ifdef DEBUGXL
2356         /* Debug printing */
2357         printk("Port 0xc44 (before): ");
2358         outb((tmp & ~0x04), 0xc44);
2359         printk("%02x ", inb(0xc44));
2360         outb((tmp | 0x04), 0xc44);
2361         printk("%02x\n", inb(0xc44));
2362 #endif
2363
2364         /* Set bank 1 of the register */
2365         tmp = 0x58;             /* MSS Mode, MSS&FM decode enabled */
2366
2367         switch (hw_config->io_base)
2368         {
2369                 case 0x530:
2370                         tmp |= 0x00;
2371                         break;
2372                 case 0x604:
2373                         tmp |= 0x01;
2374                         break;
2375                 case 0xf40:
2376                         tmp |= 0x02;
2377                         break;
2378                 case 0xe80:
2379                         tmp |= 0x03;
2380                         break;
2381                 default:
2382                         DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2383                         return 0;
2384         }
2385         outb((tmp & ~0x04), 0xc44);     /* Write to bank=0 */
2386
2387 #ifdef DEBUGXL
2388         /* Debug printing */
2389         printk("Port 0xc44 (after): ");
2390         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2391         printk("%02x ", inb(0xc44));
2392         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2393         printk("%02x\n", inb(0xc44));
2394 #endif
2395
2396         /*
2397          * I/O port 0xc45 FM Address Decode/MSS ID Register.
2398          *
2399          * bank=0, bits 0xfe:   FM synthesis Decode Compare bits 7:1 (default=0x88)
2400          * bank=0, bit 0x01:    SBIC Power Control Bit
2401          *                      0x00 = Powered up
2402          *                      0x01 = Powered down
2403          * bank=1, bits 0xfc:   MSS ID (default=0x40)
2404          */
2405
2406 #ifdef DEBUGXL
2407         /* Debug printing */
2408         printk("Port 0xc45 (before): ");
2409         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2410         printk("%02x ", inb(0xc45));
2411         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2412         printk("%02x\n", inb(0xc45));
2413 #endif
2414
2415         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2416         outb((0x88), 0xc45);    /* FM base 7:0 = 0x88 */
2417         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2418         outb((0x10), 0xc45);    /* MSS ID = 0x10 (MSS port returns 0x04) */
2419
2420 #ifdef DEBUGXL
2421         /* Debug printing */
2422         printk("Port 0xc45 (after): ");
2423         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2424         printk("%02x ", inb(0xc45));
2425         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2426         printk("%02x\n", inb(0xc45));
2427 #endif
2428
2429
2430         /*
2431          * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2432          *
2433          * bank=0, bits 0xff:   FM synthesis Decode Compare bits 15:8 (default=0x03)
2434          * bank=1, bits 0xff:   Audio addressing ASIC id
2435          */
2436
2437 #ifdef DEBUGXL
2438         /* Debug printing */
2439         printk("Port 0xc46 (before): ");
2440         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2441         printk("%02x ", inb(0xc46));
2442         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2443         printk("%02x\n", inb(0xc46));
2444 #endif
2445
2446         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2447         outb((0x03), 0xc46);    /* FM base 15:8 = 0x03 */
2448         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2449         outb((0x11), 0xc46);    /* ASIC ID = 0x11 */
2450
2451 #ifdef DEBUGXL
2452         /* Debug printing */
2453         printk("Port 0xc46 (after): ");
2454         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2455         printk("%02x ", inb(0xc46));
2456         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2457         printk("%02x\n", inb(0xc46));
2458 #endif
2459
2460         /*
2461          * I/O port 0xc47 FM Address Decode Register.
2462          *
2463          * bank=0, bits 0xff:   Decode enable selection for various FM address bits
2464          * bank=1, bits 0xff:   Reserved
2465          */
2466
2467 #ifdef DEBUGXL
2468         /* Debug printing */
2469         printk("Port 0xc47 (before): ");
2470         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2471         printk("%02x ", inb(0xc47));
2472         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2473         printk("%02x\n", inb(0xc47));
2474 #endif
2475
2476         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2477         outb((0x7c), 0xc47);    /* FM decode enable bits = 0x7c */
2478         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2479         outb((0x00), 0xc47);    /* Reserved bank1 = 0x00 */
2480
2481 #ifdef DEBUGXL
2482         /* Debug printing */
2483         printk("Port 0xc47 (after): ");
2484         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2485         printk("%02x ", inb(0xc47));
2486         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2487         printk("%02x\n", inb(0xc47));
2488 #endif
2489
2490         /*
2491          * I/O port 0xc6f = Audio Disable Function Register
2492          */
2493
2494 #ifdef DEBUGXL
2495         printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2496 #endif
2497
2498         outb((0x80), 0xc6f);
2499
2500 #ifdef DEBUGXL
2501         printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2502 #endif
2503
2504         return 1;
2505 }
2506
2507 int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
2508 {
2509         unsigned char   tmp;
2510
2511         DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2512
2513         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2514         {
2515                 /* check_opl3(0x388, hw_config); */
2516                 return ad1848_detect(ports, NULL, hw_config->osp);
2517         }
2518
2519         if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2520         {
2521                 if (!init_deskpro(hw_config))
2522                         return 0;
2523         }
2524
2525         if (deskpro_m)  /* Compaq Deskpro M */
2526         {
2527                 if (!init_deskpro_m(hw_config))
2528                         return 0;
2529         }
2530
2531         /*
2532            * Check if the IO port returns valid signature. The original MS Sound
2533            * system returns 0x04 while some cards (AudioTrix Pro for example)
2534            * return 0x00 or 0x0f.
2535          */
2536
2537         if ((tmp = inb(hw_config->io_base + 3)) == 0xff)        /* Bus float */
2538         {
2539                   int             ret;
2540
2541                   DDB(printk("I/O address is inactive (%x)\n", tmp));
2542                   if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2543                           return 0;
2544                   return 1;
2545         }
2546         DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2547         if ((tmp & 0x3f) != 0x04 &&
2548             (tmp & 0x3f) != 0x0f &&
2549             (tmp & 0x3f) != 0x00)
2550         {
2551                 int ret;
2552
2553                 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2554                 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2555                 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2556                         return 0;
2557
2558                 hw_config->card_subtype = 1;
2559                 return 1;
2560         }
2561         if ((hw_config->irq != 5)  &&
2562             (hw_config->irq != 7)  &&
2563             (hw_config->irq != 9)  &&
2564             (hw_config->irq != 10) &&
2565             (hw_config->irq != 11) &&
2566             (hw_config->irq != 12))
2567         {
2568                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2569                 return 0;
2570         }
2571         if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2572         {
2573                   printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2574                   return 0;
2575         }
2576         /*
2577          * Check that DMA0 is not in use with a 8 bit board.
2578          */
2579
2580         if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2581         {
2582                 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2583                 return 0;
2584         }
2585         if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2586         {
2587                 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2588                 return 0;
2589         }
2590         return ad1848_detect(ports, NULL, hw_config->osp);
2591 }
2592
2593 void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
2594 {
2595         static signed char interrupt_bits[12] =
2596         {
2597                 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2598         };
2599         signed char     bits;
2600         char            dma2_bit = 0;
2601
2602         static char     dma_bits[4] =
2603         {
2604                 1, 2, 0, 3
2605         };
2606
2607         int config_port = hw_config->io_base + 0;
2608         int version_port = hw_config->io_base + 3;
2609         int dma = hw_config->dma;
2610         int dma2 = hw_config->dma2;
2611
2612         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2613         {
2614                 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2615                                                     hw_config->irq,
2616                                                     hw_config->dma,
2617                                                     hw_config->dma2, 0,
2618                                                     hw_config->osp,
2619                                                     owner);
2620                 return;
2621         }
2622         /*
2623          * Set the IRQ and DMA addresses.
2624          */
2625
2626         bits = interrupt_bits[hw_config->irq];
2627         if (bits == -1)
2628         {
2629                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2630                 release_region(ports->start, 4);
2631                 release_region(ports->start - 4, 4);
2632                 return;
2633         }
2634         outb((bits | 0x40), config_port);
2635         if ((inb(version_port) & 0x40) == 0)
2636                 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2637
2638 /*
2639  * Handle the capture DMA channel
2640  */
2641
2642         if (dma2 != -1 && dma2 != dma)
2643         {
2644                 if (!((dma == 0 && dma2 == 1) ||
2645                         (dma == 1 && dma2 == 0) ||
2646                         (dma == 3 && dma2 == 0)))
2647                 {       /* Unsupported combination. Try to swap channels */
2648                         int tmp = dma;
2649
2650                         dma = dma2;
2651                         dma2 = tmp;
2652                 }
2653                 if ((dma == 0 && dma2 == 1) ||
2654                         (dma == 1 && dma2 == 0) ||
2655                         (dma == 3 && dma2 == 0))
2656                 {
2657                         dma2_bit = 0x04;        /* Enable capture DMA */
2658                 }
2659                 else
2660                 {
2661                         printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2662                         dma2 = dma;
2663                 }
2664         }
2665         else
2666         {
2667                 dma2 = dma;
2668         }
2669
2670         hw_config->dma = dma;
2671         hw_config->dma2 = dma2;
2672
2673         outb((bits | dma_bits[dma] | dma2_bit), config_port);   /* Write IRQ+DMA setup */
2674
2675         hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2676                                           hw_config->irq,
2677                                           dma, dma2, 0,
2678                                           hw_config->osp,
2679                                           THIS_MODULE);
2680 }
2681
2682 void unload_ms_sound(struct address_info *hw_config)
2683 {
2684         ad1848_unload(hw_config->io_base + 4,
2685                       hw_config->irq,
2686                       hw_config->dma,
2687                       hw_config->dma2, 0);
2688         sound_unload_audiodev(hw_config->slots[0]);
2689         release_region(hw_config->io_base, 4);
2690 }
2691
2692 #ifndef EXCLUDE_TIMERS
2693
2694 /*
2695  * Timer stuff (for /dev/music).
2696  */
2697
2698 static unsigned int current_interval;
2699
2700 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2701 {
2702         unsigned long   flags;
2703         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2704         unsigned long   xtal_nsecs;     /* nanoseconds per xtal oscillator tick */
2705         unsigned long   divider;
2706
2707         spin_lock_irqsave(&devc->lock,flags);
2708
2709         /*
2710          * Length of the timer interval (in nanoseconds) depends on the
2711          * selected crystal oscillator. Check this from bit 0x01 of I8.
2712          *
2713          * AD1845 has just one oscillator which has cycle time of 10.050 us
2714          * (when a 24.576 MHz xtal oscillator is used).
2715          *
2716          * Convert requested interval to nanoseconds before computing
2717          * the timer divider.
2718          */
2719
2720         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2721                 xtal_nsecs = 10050;
2722         else if (ad_read(devc, 8) & 0x01)
2723                 xtal_nsecs = 9920;
2724         else
2725                 xtal_nsecs = 9969;
2726
2727         divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2728
2729         if (divider < 100)      /* Don't allow shorter intervals than about 1ms */
2730                 divider = 100;
2731
2732         if (divider > 65535)    /* Overflow check */
2733                 divider = 65535;
2734
2735         ad_write(devc, 21, (divider >> 8) & 0xff);      /* Set upper bits */
2736         ad_write(devc, 20, divider & 0xff);     /* Set lower bits */
2737         ad_write(devc, 16, ad_read(devc, 16) | 0x40);   /* Start the timer */
2738         devc->timer_running = 1;
2739         spin_unlock_irqrestore(&devc->lock,flags);
2740
2741         return current_interval = (divider * xtal_nsecs + 500) / 1000;
2742 }
2743
2744 static void ad1848_tmr_reprogram(int dev)
2745 {
2746         /*
2747          *    Audio driver has changed sampling rate so that a different xtal
2748          *      oscillator was selected. We have to reprogram the timer rate.
2749          */
2750
2751         ad1848_tmr_start(dev, current_interval);
2752         sound_timer_syncinterval(current_interval);
2753 }
2754
2755 static void ad1848_tmr_disable(int dev)
2756 {
2757         unsigned long   flags;
2758         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2759
2760         spin_lock_irqsave(&devc->lock,flags);
2761         ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2762         devc->timer_running = 0;
2763         spin_unlock_irqrestore(&devc->lock,flags);
2764 }
2765
2766 static void ad1848_tmr_restart(int dev)
2767 {
2768         unsigned long   flags;
2769         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2770
2771         if (current_interval == 0)
2772                 return;
2773
2774         spin_lock_irqsave(&devc->lock,flags);
2775         ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2776         devc->timer_running = 1;
2777         spin_unlock_irqrestore(&devc->lock,flags);
2778 }
2779
2780 static struct sound_lowlev_timer ad1848_tmr =
2781 {
2782         0,
2783         2,
2784         ad1848_tmr_start,
2785         ad1848_tmr_disable,
2786         ad1848_tmr_restart
2787 };
2788
2789 static int ad1848_tmr_install(int dev)
2790 {
2791         if (timer_installed != -1)
2792                 return 0;       /* Don't install another timer */
2793
2794         timer_installed = ad1848_tmr.dev = dev;
2795         sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2796
2797         return 1;
2798 }
2799 #endif /* EXCLUDE_TIMERS */
2800
2801 EXPORT_SYMBOL(ad1848_detect);
2802 EXPORT_SYMBOL(ad1848_init);
2803 EXPORT_SYMBOL(ad1848_unload);
2804 EXPORT_SYMBOL(ad1848_control);
2805 EXPORT_SYMBOL(adintr);
2806 EXPORT_SYMBOL(probe_ms_sound);
2807 EXPORT_SYMBOL(attach_ms_sound);
2808 EXPORT_SYMBOL(unload_ms_sound);
2809
2810 static int __initdata io = -1;
2811 static int __initdata irq = -1;
2812 static int __initdata dma = -1;
2813 static int __initdata dma2 = -1;
2814 static int __initdata type = 0;
2815
2816 module_param(io, int, 0);               /* I/O for a raw AD1848 card */
2817 module_param(irq, int, 0);              /* IRQ to use */
2818 module_param(dma, int, 0);              /* First DMA channel */
2819 module_param(dma2, int, 0);             /* Second DMA channel */
2820 module_param(type, int, 0);             /* Card type */
2821 module_param(deskpro_xl, bool, 0);      /* Special magic for Deskpro XL boxen */
2822 module_param(deskpro_m, bool, 0);       /* Special magic for Deskpro M box */
2823 module_param(soundpro, bool, 0);        /* More special magic for SoundPro chips */
2824
2825 #ifdef CONFIG_PNP
2826 module_param(isapnp, int, 0);
2827 module_param(isapnpjump, int, 0);
2828 module_param(reverse, bool, 0);
2829 MODULE_PARM_DESC(isapnp,        "When set to 0, Plug & Play support will be disabled");
2830 MODULE_PARM_DESC(isapnpjump,    "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2831 MODULE_PARM_DESC(reverse,       "When set to 1, will reverse ISAPnP search order");
2832
2833 static struct pnp_dev   *ad1848_dev  = NULL;
2834
2835 /* Please add new entries at the end of the table */
2836 static struct {
2837         char *name;
2838         unsigned short  card_vendor, card_device,
2839                         vendor, function;
2840         short mss_io, irq, dma, dma2;   /* index into isapnp table */
2841         int type;
2842 } ad1848_isapnp_list[] __initdata = {
2843         {"CMI 8330 SoundPRO",
2844                 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2845                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2846                 0, 0, 0,-1, 0},
2847         {"CS4232 based card",
2848                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2849                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2850                 0, 0, 0, 1, 0},
2851         {"CS4232 based card",
2852                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2853                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2854                 0, 0, 0, 1, 0},
2855         {"OPL3-SA2 WSS mode",
2856                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2857                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2858                 1, 0, 0, 1, 1},
2859         {"Advanced Gravis InterWave Audio",
2860                 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2861                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2862                 0, 0, 0, 1, 0},
2863         {NULL}
2864 };
2865
2866 static struct isapnp_device_id id_table[] __devinitdata = {
2867         {       ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2868                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2869         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2870                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2871         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2872                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2873         /* The main driver for this card is opl3sa2
2874         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2875                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2876         */
2877         {       ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2878                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2879         {0}
2880 };
2881
2882 MODULE_DEVICE_TABLE(isapnp, id_table);
2883
2884 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2885 {
2886         int err;
2887
2888         err = pnp_device_attach(dev);
2889         if (err < 0)
2890                 return(NULL);
2891
2892         if((err = pnp_activate_dev(dev)) < 0) {
2893                 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2894
2895                 pnp_device_detach(dev);
2896
2897                 return(NULL);
2898         }
2899         audio_activated = 1;
2900         return(dev);
2901 }
2902
2903 static struct pnp_dev *ad1848_init_generic(struct pnp_card *bus, struct address_info *hw_config, int slot)
2904 {
2905
2906         /* Configure Audio device */
2907         if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
2908         {
2909                 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
2910                 {
2911                         hw_config->io_base      = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
2912                         hw_config->irq          = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
2913                         hw_config->dma          = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
2914                         if(ad1848_isapnp_list[slot].dma2 != -1)
2915                                 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
2916                         else
2917                                 hw_config->dma2 = -1;
2918                         hw_config->card_subtype = ad1848_isapnp_list[slot].type;
2919                 } else
2920                         return(NULL);
2921         } else
2922                 return(NULL);
2923
2924         return(ad1848_dev);
2925 }
2926
2927 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
2928 {
2929         char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
2930
2931         /* Initialize this baby. */
2932
2933         if(ad1848_init_generic(bus, hw_config, slot)) {
2934                 /* We got it. */
2935
2936                 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
2937                        busname,
2938                        hw_config->io_base, hw_config->irq, hw_config->dma,
2939                        hw_config->dma2);
2940                 return 1;
2941         }
2942         return 0;
2943 }
2944
2945 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
2946 {
2947         static int first = 1;
2948         int i;
2949
2950         /* Count entries in sb_isapnp_list */
2951         for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
2952         i--;
2953
2954         /* Check and adjust isapnpjump */
2955         if( isapnpjump < 0 || isapnpjump > i) {
2956                 isapnpjump = reverse ? i : 0;
2957                 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
2958         }
2959
2960         if(!first || !reverse)
2961                 i = isapnpjump;
2962         first = 0;
2963         while(ad1848_isapnp_list[i].card_vendor != 0) {
2964                 static struct pnp_card *bus = NULL;
2965
2966                 while ((bus = pnp_find_card(
2967                                 ad1848_isapnp_list[i].card_vendor,
2968                                 ad1848_isapnp_list[i].card_device,
2969                                 bus))) {
2970
2971                         if(ad1848_isapnp_init(hw_config, bus, i)) {
2972                                 isapnpjump = i; /* start next search from here */
2973                                 return 0;
2974                         }
2975                 }
2976                 i += reverse ? -1 : 1;
2977         }
2978
2979         return -ENODEV;
2980 }
2981 #endif
2982
2983
2984 static int __init init_ad1848(void)
2985 {
2986         printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2987
2988 #ifdef CONFIG_PNP
2989         if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
2990                 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
2991                 isapnp = 0;
2992         }
2993 #endif
2994
2995         if(io != -1) {
2996                 struct resource *ports;
2997                 if( isapnp == 0 )
2998                 {
2999                         if(irq == -1 || dma == -1) {
3000                                 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3001                                 return -EINVAL;
3002                         }
3003
3004                         cfg.irq = irq;
3005                         cfg.io_base = io;
3006                         cfg.dma = dma;
3007                         cfg.dma2 = dma2;
3008                         cfg.card_subtype = type;
3009                 }
3010
3011                 ports = request_region(io + 4, 4, "ad1848");
3012
3013                 if (!ports)
3014                         return -EBUSY;
3015
3016                 if (!request_region(io, 4, "WSS config")) {
3017                         release_region(io + 4, 4);
3018                         return -EBUSY;
3019                 }
3020
3021                 if (!probe_ms_sound(&cfg, ports)) {
3022                         release_region(io + 4, 4);
3023                         release_region(io, 4);
3024                         return -ENODEV;
3025                 }
3026                 attach_ms_sound(&cfg, ports, THIS_MODULE);
3027                 loaded = 1;
3028         }
3029         return 0;
3030 }
3031
3032 static void __exit cleanup_ad1848(void)
3033 {
3034         if(loaded)
3035                 unload_ms_sound(&cfg);
3036
3037 #ifdef CONFIG_PNP
3038         if(ad1848_dev){
3039                 if(audio_activated)
3040                         pnp_device_detach(ad1848_dev);
3041         }
3042 #endif
3043 }
3044
3045 module_init(init_ad1848);
3046 module_exit(cleanup_ad1848);
3047
3048 #ifndef MODULE
3049 static int __init setup_ad1848(char *str)
3050 {
3051         /* io, irq, dma, dma2, type */
3052         int ints[6];
3053
3054         str = get_options(str, ARRAY_SIZE(ints), ints);
3055
3056         io      = ints[1];
3057         irq     = ints[2];
3058         dma     = ints[3];
3059         dma2    = ints[4];
3060         type    = ints[5];
3061
3062         return 1;
3063 }
3064
3065 __setup("ad1848=", setup_ad1848);
3066 #endif
3067 MODULE_LICENSE("GPL");