2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
20 #include <sound/ac97_codec.h>
21 #include <sound/pxa2xx-lib.h>
24 #include <mach/regs-ac97.h>
25 #include <mach/pxa2xx-gpio.h>
26 #include <mach/audio.h>
28 static DEFINE_MUTEX(car_mutex);
29 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
30 static volatile long gsr_bits;
31 static struct clk *ac97_clk;
32 static struct clk *ac97conf_clk;
37 * o Slot 12 read from modem space will hang controller.
38 * o CDONE, SDONE interrupt fails after any slot 12 IO.
40 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
41 * 1 jiffy timeout if interrupt never comes).
44 unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
46 unsigned short val = -1;
47 volatile u32 *reg_addr;
49 mutex_lock(&car_mutex);
51 /* set up primary or secondary codec space */
52 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
53 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
55 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
56 reg_addr += (reg >> 1);
58 /* start read access across the ac97 link */
59 GSR = GSR_CDONE | GSR_SDONE;
62 if (reg == AC97_GPIO_STATUS)
64 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
65 !((GSR | gsr_bits) & GSR_SDONE)) {
66 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
67 __func__, reg, GSR | gsr_bits);
73 GSR = GSR_CDONE | GSR_SDONE;
76 /* but we've just started another cycle... */
77 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
79 out: mutex_unlock(&car_mutex);
82 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
84 void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
87 volatile u32 *reg_addr;
89 mutex_lock(&car_mutex);
91 /* set up primary or secondary codec space */
92 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
93 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
95 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
96 reg_addr += (reg >> 1);
98 GSR = GSR_CDONE | GSR_SDONE;
101 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
102 !((GSR | gsr_bits) & GSR_CDONE))
103 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
104 __func__, reg, GSR | gsr_bits);
106 mutex_unlock(&car_mutex);
108 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
111 static inline void pxa_ac97_warm_pxa25x(void)
115 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
116 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
119 static inline void pxa_ac97_cold_pxa25x(void)
121 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
122 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
127 GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
128 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
133 static inline void pxa_ac97_warm_pxa27x(void)
137 /* warm reset broken on Bulverde,
138 so manually keep AC97 reset high */
139 pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
142 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
146 static inline void pxa_ac97_cold_pxa27x(void)
148 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
149 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
153 /* PXA27x Developers Manual section 13.5.2.2.1 */
154 clk_enable(ac97conf_clk);
156 clk_disable(ac97conf_clk);
163 static inline void pxa_ac97_warm_pxa3xx(void)
169 /* Can't use interrupts */
171 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
175 static inline void pxa_ac97_cold_pxa3xx(void)
179 /* Hold CLKBPB for 100us */
185 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
186 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
190 /* Can't use interrupts on PXA3xx */
191 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
193 GCR = GCR_WARM_RST | GCR_COLD_RST;
194 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
199 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
203 pxa_ac97_warm_pxa25x();
208 pxa_ac97_warm_pxa27x();
213 pxa_ac97_warm_pxa3xx();
218 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
219 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
227 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
229 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
233 pxa_ac97_cold_pxa25x();
238 pxa_ac97_cold_pxa27x();
243 pxa_ac97_cold_pxa3xx();
248 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
249 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
257 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
260 void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
262 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
263 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
265 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
267 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
277 /* Although we don't use those we still need to clear them
278 since they tend to spuriously trigger when MMC is used
279 (hardware bug? go figure)... */
280 if (cpu_is_pxa27x()) {
293 int pxa2xx_ac97_hw_suspend(void)
295 GCR |= GCR_ACLINK_OFF;
296 clk_disable(ac97_clk);
299 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
301 int pxa2xx_ac97_hw_resume(void)
303 if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
304 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
305 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
306 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
307 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
309 if (cpu_is_pxa27x()) {
310 /* Use GPIO 113 as AC97 Reset on Bulverde */
311 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
313 clk_enable(ac97_clk);
316 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
319 int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
323 if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
324 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
325 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
326 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
327 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
330 if (cpu_is_pxa27x()) {
331 /* Use GPIO 113 as AC97 Reset on Bulverde */
332 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
333 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
334 if (IS_ERR(ac97conf_clk)) {
335 ret = PTR_ERR(ac97conf_clk);
341 ac97_clk = clk_get(&dev->dev, "AC97CLK");
342 if (IS_ERR(ac97_clk)) {
343 ret = PTR_ERR(ac97_clk);
348 ret = clk_enable(ac97_clk);
352 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
359 GCR |= GCR_ACLINK_OFF;
365 clk_put(ac97conf_clk);
371 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
373 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
375 GCR |= GCR_ACLINK_OFF;
376 free_irq(IRQ_AC97, NULL);
378 clk_put(ac97conf_clk);
381 clk_disable(ac97_clk);
385 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
387 MODULE_AUTHOR("Nicolas Pitre");
388 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
389 MODULE_LICENSE("GPL");