2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
29 /* Scan and identify a NAND device */
30 extern int nand_scan (struct mtd_info *mtd, int max_chips);
31 /* Separate phases of nand_scan(), allowing board driver to intervene
32 * and override command or ECC setup according to flash type */
33 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
34 struct nand_flash_dev *table);
35 extern int nand_scan_tail(struct mtd_info *mtd);
37 /* Free resources held by the NAND device */
38 extern void nand_release (struct mtd_info *mtd);
40 /* Internal helper for board drivers which need to override command function */
41 extern void nand_wait_ready(struct mtd_info *mtd);
43 /* locks all blockes present in the device */
44 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
46 /* unlocks specified locked blockes */
47 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
49 /* The maximum number of NAND chips in an array */
50 #define NAND_MAX_CHIPS 8
52 /* This constant declares the max. oobsize / page, which
53 * is supported now. If you add a chip with bigger oobsize/page
54 * adjust this accordingly.
56 #define NAND_MAX_OOBSIZE 576
57 #define NAND_MAX_PAGESIZE 8192
60 * Constants for hardware specific CLE/ALE/NCE function
62 * These are bits which can be or'ed to set/clear multiple
65 /* Select the chip by setting nCE to low */
67 /* Select the command latch by setting CLE to high */
69 /* Select the address latch by setting ALE to high */
72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
74 #define NAND_CTRL_CHANGE 0x80
77 * Standard NAND flash commands
79 #define NAND_CMD_READ0 0
80 #define NAND_CMD_READ1 1
81 #define NAND_CMD_RNDOUT 5
82 #define NAND_CMD_PAGEPROG 0x10
83 #define NAND_CMD_READOOB 0x50
84 #define NAND_CMD_ERASE1 0x60
85 #define NAND_CMD_STATUS 0x70
86 #define NAND_CMD_STATUS_MULTI 0x71
87 #define NAND_CMD_SEQIN 0x80
88 #define NAND_CMD_RNDIN 0x85
89 #define NAND_CMD_READID 0x90
90 #define NAND_CMD_ERASE2 0xd0
91 #define NAND_CMD_PARAM 0xec
92 #define NAND_CMD_RESET 0xff
94 #define NAND_CMD_LOCK 0x2a
95 #define NAND_CMD_UNLOCK1 0x23
96 #define NAND_CMD_UNLOCK2 0x24
98 /* Extended commands for large page devices */
99 #define NAND_CMD_READSTART 0x30
100 #define NAND_CMD_RNDOUTSTART 0xE0
101 #define NAND_CMD_CACHEDPROG 0x15
103 /* Extended commands for AG-AND device */
105 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
106 * there is no way to distinguish that from NAND_CMD_READ0
107 * until the remaining sequence of commands has been completed
108 * so add a high order bit and mask it off in the command.
110 #define NAND_CMD_DEPLETE1 0x100
111 #define NAND_CMD_DEPLETE2 0x38
112 #define NAND_CMD_STATUS_MULTI 0x71
113 #define NAND_CMD_STATUS_ERROR 0x72
114 /* multi-bank error status (banks 0-3) */
115 #define NAND_CMD_STATUS_ERROR0 0x73
116 #define NAND_CMD_STATUS_ERROR1 0x74
117 #define NAND_CMD_STATUS_ERROR2 0x75
118 #define NAND_CMD_STATUS_ERROR3 0x76
119 #define NAND_CMD_STATUS_RESET 0x7f
120 #define NAND_CMD_STATUS_CLEAR 0xff
122 #define NAND_CMD_NONE -1
125 #define NAND_STATUS_FAIL 0x01
126 #define NAND_STATUS_FAIL_N1 0x02
127 #define NAND_STATUS_TRUE_READY 0x20
128 #define NAND_STATUS_READY 0x40
129 #define NAND_STATUS_WP 0x80
132 * Constants for ECC_MODES
138 NAND_ECC_HW_SYNDROME,
139 NAND_ECC_HW_OOB_FIRST,
143 * Constants for Hardware ECC
145 /* Reset Hardware ECC for read */
146 #define NAND_ECC_READ 0
147 /* Reset Hardware ECC for write */
148 #define NAND_ECC_WRITE 1
149 /* Enable Hardware ECC before syndrom is read back from flash */
150 #define NAND_ECC_READSYN 2
152 /* Bit mask for flags passed to do_nand_read_ecc */
153 #define NAND_GET_DEVICE 0x80
156 /* Option constants for bizarre disfunctionality and real
159 /* Chip can not auto increment pages */
160 #define NAND_NO_AUTOINCR 0x00000001
161 /* Buswitdh is 16 bit */
162 #define NAND_BUSWIDTH_16 0x00000002
163 /* Device supports partial programming without padding */
164 #define NAND_NO_PADDING 0x00000004
165 /* Chip has cache program function */
166 #define NAND_CACHEPRG 0x00000008
167 /* Chip has copy back function */
168 #define NAND_COPYBACK 0x00000010
169 /* AND Chip which has 4 banks and a confusing page / block
170 * assignment. See Renesas datasheet for further information */
171 #define NAND_IS_AND 0x00000020
172 /* Chip has a array of 4 pages which can be read without
173 * additional ready /busy waits */
174 #define NAND_4PAGE_ARRAY 0x00000040
175 /* Chip requires that BBT is periodically rewritten to prevent
176 * bits from adjacent blocks from 'leaking' in altering data.
177 * This happens with the Renesas AG-AND chips, possibly others. */
178 #define BBT_AUTO_REFRESH 0x00000080
179 /* Chip does not require ready check on read. True
180 * for all large page devices, as they do not support
182 #define NAND_NO_READRDY 0x00000100
183 /* Chip does not allow subpage writes */
184 #define NAND_NO_SUBPAGE_WRITE 0x00000200
186 /* Device is one of 'new' xD cards that expose fake nand command set */
187 #define NAND_BROKEN_XD 0x00000400
189 /* Device behaves just like nand, but is readonly */
190 #define NAND_ROM 0x00000800
192 /* Options valid for Samsung large page devices */
193 #define NAND_SAMSUNG_LP_OPTIONS \
194 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
196 /* Macros to identify the above */
197 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
198 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
199 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
200 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
201 /* Large page NAND with SOFT_ECC should support subpage reads */
202 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
203 && (chip->page_shift > 9))
205 /* Mask to zero out the chip options, which come from the id table */
206 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
208 /* Non chip related options */
209 /* Use a flash based bad block table. This option is passed to the
210 * default bad block table function. */
211 #define NAND_USE_FLASH_BBT 0x00010000
212 /* This option skips the bbt scan during initialization. */
213 #define NAND_SKIP_BBTSCAN 0x00020000
214 /* This option is defined if the board driver allocates its own buffers
215 (e.g. because it needs them DMA-coherent */
216 #define NAND_OWN_BUFFERS 0x00040000
217 /* Chip may not exist, so silence any errors in scan */
218 #define NAND_SCAN_SILENT_NODEV 0x00080000
220 /* Options set by nand scan */
221 /* Nand scan has allocated controller struct */
222 #define NAND_CONTROLLER_ALLOC 0x80000000
224 /* Cell info constants */
225 #define NAND_CI_CHIPNR_MSK 0x03
226 #define NAND_CI_CELLTYPE_MSK 0x0C
231 struct nand_onfi_params {
232 /* rev info and features block */
233 u8 sig[4]; /* 'O' 'N' 'F' 'I' */
239 /* manufacturer information block */
240 char manufacturer[12];
246 /* memory organization block */
247 __le32 byte_per_page;
248 __le16 spare_bytes_per_page;
249 __le32 data_bytes_per_ppage;
250 __le16 spare_bytes_per_ppage;
251 __le32 pages_per_block;
252 __le32 blocks_per_lun;
257 __le16 block_endurance;
258 u8 guaranteed_good_blocks;
259 __le16 guaranteed_block_endurance;
260 u8 programs_per_page;
267 /* electrical parameter block */
268 u8 io_pin_capacitance_max;
269 __le16 async_timing_mode;
270 __le16 program_cache_timing_mode;
275 __le16 src_sync_timing_mode;
276 __le16 src_ssync_features;
277 __le16 clk_pin_capacitance_typ;
278 __le16 io_pin_capacitance_typ;
279 __le16 input_pin_capacitance_typ;
280 u8 input_pin_capacitance_max;
281 u8 driver_strenght_support;
290 } __attribute__((packed));
292 #define ONFI_CRC_BASE 0x4F4E
295 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
296 * @lock: protection lock
297 * @active: the mtd device which holds the controller currently
298 * @wq: wait queue to sleep on if a NAND operation is in progress
299 * used instead of the per chip wait queue when a hw controller is available
301 struct nand_hw_control {
303 struct nand_chip *active;
304 wait_queue_head_t wq;
308 * struct nand_ecc_ctrl - Control structure for ecc
310 * @steps: number of ecc steps per page
311 * @size: data bytes per ecc step
312 * @bytes: ecc bytes per step
313 * @total: total number of ecc bytes per page
314 * @prepad: padding information for syndrome based ecc generators
315 * @postpad: padding information for syndrome based ecc generators
316 * @layout: ECC layout control struct pointer
317 * @hwctl: function to control hardware ecc generator. Must only
318 * be provided if an hardware ECC is available
319 * @calculate: function for ecc calculation or readback from ecc hardware
320 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
321 * @read_page_raw: function to read a raw page without ECC
322 * @write_page_raw: function to write a raw page without ECC
323 * @read_page: function to read a page according to the ecc generator requirements
324 * @read_subpage: function to read parts of the page covered by ECC.
325 * @write_page: function to write a page according to the ecc generator requirements
326 * @read_oob: function to read chip OOB data
327 * @write_oob: function to write chip OOB data
329 struct nand_ecc_ctrl {
330 nand_ecc_modes_t mode;
337 struct nand_ecclayout *layout;
338 void (*hwctl)(struct mtd_info *mtd, int mode);
339 int (*calculate)(struct mtd_info *mtd,
342 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
345 int (*read_page_raw)(struct mtd_info *mtd,
346 struct nand_chip *chip,
347 uint8_t *buf, int page);
348 void (*write_page_raw)(struct mtd_info *mtd,
349 struct nand_chip *chip,
351 int (*read_page)(struct mtd_info *mtd,
352 struct nand_chip *chip,
353 uint8_t *buf, int page);
354 int (*read_subpage)(struct mtd_info *mtd,
355 struct nand_chip *chip,
356 uint32_t offs, uint32_t len,
358 void (*write_page)(struct mtd_info *mtd,
359 struct nand_chip *chip,
361 int (*read_oob)(struct mtd_info *mtd,
362 struct nand_chip *chip,
365 int (*write_oob)(struct mtd_info *mtd,
366 struct nand_chip *chip,
371 * struct nand_buffers - buffer structure for read/write
372 * @ecccalc: buffer for calculated ecc
373 * @ecccode: buffer for ecc read from flash
374 * @databuf: buffer for data - dynamically sized
376 * Do not change the order of buffers. databuf and oobrbuf must be in
379 struct nand_buffers {
380 uint8_t ecccalc[NAND_MAX_OOBSIZE];
381 uint8_t ecccode[NAND_MAX_OOBSIZE];
382 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
386 * struct nand_chip - NAND Private Flash Chip Data
387 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
388 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
389 * @read_byte: [REPLACEABLE] read one byte from the chip
390 * @read_word: [REPLACEABLE] read one word from the chip
391 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
392 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
393 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
394 * @select_chip: [REPLACEABLE] select chip nr
395 * @block_bad: [REPLACEABLE] check, if the block is bad
396 * @block_markbad: [REPLACEABLE] mark the block bad
397 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
398 * ALE/CLE/nCE. Also used to write command and address
399 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
400 * If set to NULL no access to ready/busy is available and the ready/busy information
401 * is read from the chip status register
402 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
403 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
404 * @ecc: [BOARDSPECIFIC] ecc control ctructure
405 * @buffers: buffer structure for read/write
406 * @hwcontrol: platform-specific hardware control structure
407 * @ops: oob operation operands
408 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
409 * @scan_bbt: [REPLACEABLE] function to scan bad block table
410 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
411 * @state: [INTERN] the current state of the NAND device
412 * @oob_poi: poison value buffer
413 * @page_shift: [INTERN] number of address bits in a page (column address bits)
414 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
415 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
416 * @chip_shift: [INTERN] number of address bits in one chip
417 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
418 * special functionality. See the defines for further explanation
419 * @badblockpos: [INTERN] position of the bad block marker in the oob area
420 * @cellinfo: [INTERN] MLC/multichip data from chip ident
421 * @numchips: [INTERN] number of physical chips
422 * @chipsize: [INTERN] the size of one chip for multichip arrays
423 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
424 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
425 * @subpagesize: [INTERN] holds the subpagesize
426 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), non 0 if ONFI supported
427 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is supported, 0 otherwise
428 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
429 * @bbt: [INTERN] bad block table pointer
430 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
431 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
432 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
433 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
434 * which is shared among multiple independend devices
435 * @priv: [OPTIONAL] pointer to private chip date
436 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
437 * (determine if errors are correctable)
438 * @write_page: [REPLACEABLE] High-level page write function
442 void __iomem *IO_ADDR_R;
443 void __iomem *IO_ADDR_W;
445 uint8_t (*read_byte)(struct mtd_info *mtd);
446 u16 (*read_word)(struct mtd_info *mtd);
447 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
448 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
449 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
450 void (*select_chip)(struct mtd_info *mtd, int chip);
451 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
452 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
453 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
455 int (*dev_ready)(struct mtd_info *mtd);
456 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
457 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
458 void (*erase_cmd)(struct mtd_info *mtd, int page);
459 int (*scan_bbt)(struct mtd_info *mtd);
460 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
461 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
462 const uint8_t *buf, int page, int cached, int raw);
465 unsigned int options;
468 int phys_erase_shift;
481 struct nand_onfi_params onfi_params;
486 struct nand_hw_control *controller;
487 struct nand_ecclayout *ecclayout;
489 struct nand_ecc_ctrl ecc;
490 struct nand_buffers *buffers;
491 struct nand_hw_control hwcontrol;
493 struct mtd_oob_ops ops;
496 struct nand_bbt_descr *bbt_td;
497 struct nand_bbt_descr *bbt_md;
499 struct nand_bbt_descr *badblock_pattern;
505 * NAND Flash Manufacturer ID Codes
507 #define NAND_MFR_TOSHIBA 0x98
508 #define NAND_MFR_SAMSUNG 0xec
509 #define NAND_MFR_FUJITSU 0x04
510 #define NAND_MFR_NATIONAL 0x8f
511 #define NAND_MFR_RENESAS 0x07
512 #define NAND_MFR_STMICRO 0x20
513 #define NAND_MFR_HYNIX 0xad
514 #define NAND_MFR_MICRON 0x2c
515 #define NAND_MFR_AMD 0x01
518 * struct nand_flash_dev - NAND Flash Device ID Structure
519 * @name: Identify the device type
520 * @id: device ID code
521 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
522 * If the pagesize is 0, then the real pagesize
523 * and the eraseize are determined from the
524 * extended id bytes in the chip
525 * @erasesize: Size of an erase block in the flash device.
526 * @chipsize: Total chipsize in Mega Bytes
527 * @options: Bitfield to store chip relevant options
529 struct nand_flash_dev {
532 unsigned long pagesize;
533 unsigned long chipsize;
534 unsigned long erasesize;
535 unsigned long options;
539 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
540 * @name: Manufacturer name
541 * @id: manufacturer ID code of device.
543 struct nand_manufacturers {
548 extern struct nand_flash_dev nand_flash_ids[];
549 extern struct nand_manufacturers nand_manuf_ids[];
551 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
552 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
553 extern int nand_default_bbt(struct mtd_info *mtd);
554 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
555 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
557 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
558 size_t * retlen, uint8_t * buf);
561 * struct platform_nand_chip - chip level device structure
562 * @nr_chips: max. number of chips to scan for
563 * @chip_offset: chip number offset
564 * @nr_partitions: number of partitions pointed to by partitions (or zero)
565 * @partitions: mtd partition list
566 * @chip_delay: R/B delay value in us
567 * @options: Option flags, e.g. 16bit buswidth
568 * @ecclayout: ecc layout info structure
569 * @part_probe_types: NULL-terminated array of probe types
570 * @set_parts: platform specific function to set partitions
571 * @priv: hardware controller specific settings
573 struct platform_nand_chip {
577 struct mtd_partition *partitions;
578 struct nand_ecclayout *ecclayout;
580 unsigned int options;
581 const char **part_probe_types;
582 void (*set_parts)(uint64_t size,
583 struct platform_nand_chip *chip);
588 struct platform_device;
591 * struct platform_nand_ctrl - controller level device structure
592 * @probe: platform specific function to probe/setup hardware
593 * @remove: platform specific function to remove/teardown hardware
594 * @hwcontrol: platform specific hardware control structure
595 * @dev_ready: platform specific function to read ready/busy pin
596 * @select_chip: platform specific chip select function
597 * @cmd_ctrl: platform specific function for controlling
598 * ALE/CLE/nCE. Also used to write command and address
599 * @write_buf: platform specific function for write buffer
600 * @read_buf: platform specific function for read buffer
601 * @priv: private data to transport driver specific settings
603 * All fields are optional and depend on the hardware driver requirements
605 struct platform_nand_ctrl {
606 int (*probe)(struct platform_device *pdev);
607 void (*remove)(struct platform_device *pdev);
608 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
609 int (*dev_ready)(struct mtd_info *mtd);
610 void (*select_chip)(struct mtd_info *mtd, int chip);
611 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
613 void (*write_buf)(struct mtd_info *mtd,
614 const uint8_t *buf, int len);
615 void (*read_buf)(struct mtd_info *mtd,
616 uint8_t *buf, int len);
621 * struct platform_nand_data - container structure for platform-specific data
622 * @chip: chip level chip structure
623 * @ctrl: controller level device structure
625 struct platform_nand_data {
626 struct platform_nand_chip chip;
627 struct platform_nand_ctrl ctrl;
630 /* Some helpers to access the data structures */
632 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
634 struct nand_chip *chip = mtd->priv;
639 #endif /* __LINUX_MTD_NAND_H */