2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Freescale DIU Frame Buffer device driver
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
20 #ifndef __FSL_DIU_FB_H__
21 #define __FSL_DIU_FB_H__
23 #include <linux/types.h>
25 struct mfb_chroma_key {
35 struct aoi_display_offset {
40 #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
41 #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
42 #define MFB_SET_ALPHA _IOW('M', 0, __u8)
43 #define MFB_GET_ALPHA _IOR('M', 0, __u8)
44 #define MFB_SET_AOID _IOW('M', 4, struct aoi_display_offset)
45 #define MFB_GET_AOID _IOR('M', 4, struct aoi_display_offset)
46 #define MFB_SET_PIXFMT _IOW('M', 8, __u32)
47 #define MFB_GET_PIXFMT _IOR('M', 8, __u32)
50 * The original definitions of MFB_SET_PIXFMT and MFB_GET_PIXFMT used the
51 * wrong value for 'size' field of the ioctl. The current macros above use the
52 * right size, but we still need to provide backwards compatibility, at least
55 #define MFB_SET_PIXFMT_OLD 0x80014d08
56 #define MFB_GET_PIXFMT_OLD 0x40014d08
59 #include <linux/spinlock.h>
62 * These are the fields of area descriptor(in DDR memory) for every plane
65 /* Word 0(32-bit) in DDR memory */
67 /* __u16 pixel_s:2; */
68 /* __u16 pallete:1; */
70 /* __u16 green_c:2; */
72 /* __u16 alpha_c:3; */
76 __be32 pix_fmt; /* hard coding pixel format */
78 /* Word 1(32-bit) in DDR memory */
81 /* Word 2(32-bit) in DDR memory */
82 /* __u32 delta_xs:11; */
84 /* __u32 delta_ys:11; */
86 /* __u32 g_alpha:8; */
87 __le32 src_size_g_alpha;
89 /* Word 3(32-bit) in DDR memory */
90 /* __u32 delta_xi:11; */
92 /* __u32 delta_yi:11; */
97 /* Word 4(32-bit) in DDR memory */
105 /* Word 5(32-bit) in DDR memory */
106 /*__u32 offset_xd:11;
113 /* Word 6(32-bit) in DDR memory */
119 /* Word 7(32-bit) in DDR memory */
126 /* Word 8(32-bit) in DDR memory */
129 /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
131 } __attribute__ ((packed));
133 /* DIU register map */
155 } __attribute__ ((packed));
161 __u32 mode; /* DIU operation mode */
165 void *vaddr; /* Virtual address */
166 dma_addr_t paddr; /* Physical address */
172 struct diu_addr gamma;
173 struct diu_addr pallete;
174 struct diu_addr cursor;
177 #define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */
178 #define INT_LCDC 64 /* DIU interrupt number */
180 #define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
181 /* 1 for plane 0, 2 for plane 1&2 each */
183 /* Minimum X and Y resolutions */
187 /* HW cursor parameters */
190 /* Modes of operation of DIU */
191 #define MFB_MODE0 0 /* DIU off */
192 #define MFB_MODE1 1 /* All three planes output to display */
193 #define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/
194 #define MFB_MODE3 3 /* All three planes written back to memory */
195 #define MFB_MODE4 4 /* Color bar generation */
197 /* INT_STATUS/INT_MASK field descriptions */
198 #define INT_VSYNC 0x01 /* Vsync interrupt */
199 #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
200 #define INT_UNDRUN 0x04 /* Under run exception interrupt */
201 #define INT_PARERR 0x08 /* Display parameters error interrupt */
202 #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
204 /* Panels'operation modes */
205 #define MFB_TYPE_OUTPUT 0 /* Panel output to display */
206 #define MFB_TYPE_OFF 1 /* Panel off */
207 #define MFB_TYPE_WB 2 /* Panel written back to memory */
208 #define MFB_TYPE_TEST 3 /* Panel generate color bar */
210 #endif /* __KERNEL__ */
211 #endif /* __FSL_DIU_FB_H__ */