2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef __AMD_IOMMU_TYPES_H__
21 #define __AMD_IOMMU_TYPES_H__
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
28 * some size calculation constants
30 #define DEV_TABLE_ENTRY_SIZE 256
31 #define ALIAS_TABLE_ENTRY_SIZE 2
32 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
35 #define LOW_U32(x) ((x) & ((1ULL << 32)-1))
36 #define HIGH_U32(x) (LOW_U32((x) >> 32))
38 /* Length of the MMIO region for the AMD IOMMU */
39 #define MMIO_REGION_LENGTH 0x4000
41 /* Capability offsets used by the driver */
42 #define MMIO_CAP_HDR_OFFSET 0x00
43 #define MMIO_RANGE_OFFSET 0x0c
45 /* Masks, shifts and macros to parse the device range capability */
46 #define MMIO_RANGE_LD_MASK 0xff000000
47 #define MMIO_RANGE_FD_MASK 0x00ff0000
48 #define MMIO_RANGE_BUS_MASK 0x0000ff00
49 #define MMIO_RANGE_LD_SHIFT 24
50 #define MMIO_RANGE_FD_SHIFT 16
51 #define MMIO_RANGE_BUS_SHIFT 8
52 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
53 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
54 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
56 /* Flag masks for the AMD IOMMU exclusion range */
57 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
58 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
60 /* Used offsets into the MMIO space */
61 #define MMIO_DEV_TABLE_OFFSET 0x0000
62 #define MMIO_CMD_BUF_OFFSET 0x0008
63 #define MMIO_EVT_BUF_OFFSET 0x0010
64 #define MMIO_CONTROL_OFFSET 0x0018
65 #define MMIO_EXCL_BASE_OFFSET 0x0020
66 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
67 #define MMIO_CMD_HEAD_OFFSET 0x2000
68 #define MMIO_CMD_TAIL_OFFSET 0x2008
69 #define MMIO_EVT_HEAD_OFFSET 0x2010
70 #define MMIO_EVT_TAIL_OFFSET 0x2018
71 #define MMIO_STATUS_OFFSET 0x2020
73 /* feature control bits */
74 #define CONTROL_IOMMU_EN 0x00ULL
75 #define CONTROL_HT_TUN_EN 0x01ULL
76 #define CONTROL_EVT_LOG_EN 0x02ULL
77 #define CONTROL_EVT_INT_EN 0x03ULL
78 #define CONTROL_COMWAIT_EN 0x04ULL
79 #define CONTROL_PASSPW_EN 0x08ULL
80 #define CONTROL_RESPASSPW_EN 0x09ULL
81 #define CONTROL_COHERENT_EN 0x0aULL
82 #define CONTROL_ISOC_EN 0x0bULL
83 #define CONTROL_CMDBUF_EN 0x0cULL
84 #define CONTROL_PPFLOG_EN 0x0dULL
85 #define CONTROL_PPFINT_EN 0x0eULL
87 /* command specific defines */
88 #define CMD_COMPL_WAIT 0x01
89 #define CMD_INV_DEV_ENTRY 0x02
90 #define CMD_INV_IOMMU_PAGES 0x03
92 #define CMD_COMPL_WAIT_STORE_MASK 0x01
93 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
94 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
96 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
98 /* macros and definitions for device table entries */
99 #define DEV_ENTRY_VALID 0x00
100 #define DEV_ENTRY_TRANSLATION 0x01
101 #define DEV_ENTRY_IR 0x3d
102 #define DEV_ENTRY_IW 0x3e
103 #define DEV_ENTRY_EX 0x67
104 #define DEV_ENTRY_SYSMGT1 0x68
105 #define DEV_ENTRY_SYSMGT2 0x69
106 #define DEV_ENTRY_INIT_PASS 0xb8
107 #define DEV_ENTRY_EINT_PASS 0xb9
108 #define DEV_ENTRY_NMI_PASS 0xba
109 #define DEV_ENTRY_LINT0_PASS 0xbe
110 #define DEV_ENTRY_LINT1_PASS 0xbf
112 /* constants to configure the command buffer */
113 #define CMD_BUFFER_SIZE 8192
114 #define CMD_BUFFER_ENTRIES 512
115 #define MMIO_CMD_SIZE_SHIFT 56
116 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
118 #define PAGE_MODE_1_LEVEL 0x01
119 #define PAGE_MODE_2_LEVEL 0x02
120 #define PAGE_MODE_3_LEVEL 0x03
122 #define IOMMU_PDE_NL_0 0x000ULL
123 #define IOMMU_PDE_NL_1 0x200ULL
124 #define IOMMU_PDE_NL_2 0x400ULL
125 #define IOMMU_PDE_NL_3 0x600ULL
127 #define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
128 #define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
129 #define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
131 #define IOMMU_MAP_SIZE_L1 (1ULL << 21)
132 #define IOMMU_MAP_SIZE_L2 (1ULL << 30)
133 #define IOMMU_MAP_SIZE_L3 (1ULL << 39)
135 #define IOMMU_PTE_P (1ULL << 0)
136 #define IOMMU_PTE_U (1ULL << 59)
137 #define IOMMU_PTE_FC (1ULL << 60)
138 #define IOMMU_PTE_IR (1ULL << 61)
139 #define IOMMU_PTE_IW (1ULL << 62)
141 #define IOMMU_L1_PDE(address) \
142 ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
143 #define IOMMU_L2_PDE(address) \
144 ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
146 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
147 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
148 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
149 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
151 #define IOMMU_PROT_MASK 0x03
152 #define IOMMU_PROT_IR 0x01
153 #define IOMMU_PROT_IW 0x02
155 /* IOMMU capabilities */
156 #define IOMMU_CAP_IOTLB 24
157 #define IOMMU_CAP_NPCACHE 26
159 #define MAX_DOMAIN_ID 65536
162 * This structure contains generic data for IOMMU protection domains
163 * independent of their use.
165 struct protection_domain {
166 spinlock_t lock; /* mostly used to lock the page table*/
167 u16 id; /* the domain id written to the device table */
168 int mode; /* paging mode (0-6 levels) */
169 u64 *pt_root; /* page table root pointer */
170 void *priv; /* private data */
174 * Data container for a dma_ops specific protection domain
176 struct dma_ops_domain {
177 struct list_head list;
179 /* generic protection domain information */
180 struct protection_domain domain;
182 /* size of the aperture for the mappings */
183 unsigned long aperture_size;
185 /* address we start to search for free addresses */
186 unsigned long next_bit;
188 /* address allocation bitmap */
189 unsigned long *bitmap;
192 * Array of PTE pages for the aperture. In this array we save all the
193 * leaf pages of the domain page table used for the aperture. This way
194 * we don't need to walk the page table to find a specific PTE. We can
195 * just calculate its address in constant time.
201 * Structure where we save information about one hardware AMD IOMMU in the
205 struct list_head list;
207 /* locks the accesses to the hardware */
210 /* device id of this IOMMU */
213 * Capability pointer. There could be more than one IOMMU per PCI
214 * device function if there are more than one AMD IOMMU capability
219 /* physical address of MMIO space */
221 /* virtual address of MMIO space */
224 /* capabilities of that IOMMU read from ACPI */
227 /* first device this IOMMU handles. read from PCI */
229 /* last device this IOMMU handles. read from PCI */
232 /* start of exclusion range of that IOMMU */
234 /* length of exclusion range of that IOMMU */
235 u64 exclusion_length;
237 /* command buffer virtual address */
239 /* size of command buffer */
242 /* if one, we need to send a completion wait command */
245 /* default dma_ops domain for that IOMMU */
246 struct dma_ops_domain *default_dom;
250 * List with all IOMMUs in the system. This list is not locked because it is
251 * only written and read at driver initialization or suspend time
253 extern struct list_head amd_iommu_list;
256 * Structure defining one entry in the device table
258 struct dev_table_entry {
263 * One entry for unity mappings parsed out of the ACPI table.
265 struct unity_map_entry {
266 struct list_head list;
268 /* starting device id this entry is used for (including) */
270 /* end device id this entry is used for (including) */
273 /* start address to unity map (including) */
275 /* end address to unity map (including) */
278 /* required protection */
283 * List of all unity mappings. It is not locked because as runtime it is only
284 * read. It is created at ACPI table parsing time.
286 extern struct list_head amd_iommu_unity_map;
289 * Data structures for device handling
293 * Device table used by hardware. Read and write accesses by software are
294 * locked with the amd_iommu_pd_table lock.
296 extern struct dev_table_entry *amd_iommu_dev_table;
299 * Alias table to find requestor ids to device ids. Not locked because only
302 extern u16 *amd_iommu_alias_table;
305 * Reverse lookup table to find the IOMMU which translates a specific device.
307 extern struct amd_iommu **amd_iommu_rlookup_table;
309 /* size of the dma_ops aperture as power of 2 */
310 extern unsigned amd_iommu_aperture_order;
312 /* largest PCI device id we expect translation requests for */
313 extern u16 amd_iommu_last_bdf;
315 /* data structures for protection domain handling */
316 extern struct protection_domain **amd_iommu_pd_table;
318 /* allocation bitmap for domain ids */
319 extern unsigned long *amd_iommu_pd_alloc_bitmap;
321 /* will be 1 if device isolation is enabled */
322 extern int amd_iommu_isolate;
324 /* takes a PCI device id and prints it out in a readable form */
325 static inline void print_devid(u16 devid, int nl)
327 int bus = devid >> 8;
328 int dev = devid >> 3 & 0x1f;
329 int fn = devid & 0x07;
331 printk("%02x:%02x.%x", bus, dev, fn);