2 * PCI Backend - Handles the virtual fields in the configuration space headers.
4 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
7 #include <linux/kernel.h>
10 #include "conf_space.h"
18 #define DRV_NAME "xen-pciback"
19 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
20 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
22 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
27 ret = xen_pcibk_read_config_word(dev, offset, value, data);
28 if (!atomic_read(&dev->enable_cnt))
31 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
32 if (dev->resource[i].flags & IORESOURCE_IO)
33 *value |= PCI_COMMAND_IO;
34 if (dev->resource[i].flags & IORESOURCE_MEM)
35 *value |= PCI_COMMAND_MEMORY;
41 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
43 struct xen_pcibk_dev_data *dev_data;
46 dev_data = pci_get_drvdata(dev);
47 if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
48 if (unlikely(verbose_request))
49 printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
51 err = pci_enable_device(dev);
55 dev_data->enable_intx = 1;
56 } else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
57 if (unlikely(verbose_request))
58 printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
60 pci_disable_device(dev);
62 dev_data->enable_intx = 0;
65 if (!dev->is_busmaster && is_master_cmd(value)) {
66 if (unlikely(verbose_request))
67 printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
72 if (value & PCI_COMMAND_INVALIDATE) {
73 if (unlikely(verbose_request))
75 DRV_NAME ": %s: enable memory-write-invalidate\n",
77 err = pci_set_mwi(dev);
80 DRV_NAME ": %s: cannot enable "
81 "memory-write-invalidate (%d)\n",
83 value &= ~PCI_COMMAND_INVALIDATE;
87 return pci_write_config_word(dev, offset, value);
90 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
92 struct pci_bar_info *bar = data;
95 printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
97 return XEN_PCI_ERR_op_failed;
100 /* A write to obtain the length must happen as a 32-bit write.
101 * This does not (yet) support writing individual bytes
103 if (value == ~PCI_ROM_ADDRESS_ENABLE)
107 pci_read_config_dword(dev, offset, &tmpval);
108 if (tmpval != bar->val && value == bar->val) {
109 /* Allow restoration of bar value. */
110 pci_write_config_dword(dev, offset, bar->val);
115 /* Do we need to support enabling/disabling the rom address here? */
120 /* For the BARs, only allow writes which write ~0 or
121 * the correct resource information
122 * (Needed for when the driver probes the resource usage)
124 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
126 struct pci_bar_info *bar = data;
128 if (unlikely(!bar)) {
129 printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
131 return XEN_PCI_ERR_op_failed;
134 /* A write to obtain the length must happen as a 32-bit write.
135 * This does not (yet) support writing individual bytes
141 pci_read_config_dword(dev, offset, &tmpval);
142 if (tmpval != bar->val && value == bar->val) {
143 /* Allow restoration of bar value. */
144 pci_write_config_dword(dev, offset, bar->val);
152 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
154 struct pci_bar_info *bar = data;
156 if (unlikely(!bar)) {
157 printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
159 return XEN_PCI_ERR_op_failed;
162 *value = bar->which ? bar->len_val : bar->val;
167 static inline void read_dev_bar(struct pci_dev *dev,
168 struct pci_bar_info *bar_info, int offset,
172 struct resource *res = dev->resource;
174 if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
175 pos = PCI_ROM_RESOURCE;
177 pos = (offset - PCI_BASE_ADDRESS_0) / 4;
178 if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
179 PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
180 (PCI_BASE_ADDRESS_SPACE_MEMORY |
181 PCI_BASE_ADDRESS_MEM_TYPE_64))) {
182 bar_info->val = res[pos - 1].start >> 32;
183 bar_info->len_val = res[pos - 1].end >> 32;
188 bar_info->val = res[pos].start |
189 (res[pos].flags & PCI_REGION_FLAG_MASK);
190 bar_info->len_val = res[pos].end - res[pos].start + 1;
193 static void *bar_init(struct pci_dev *dev, int offset)
195 struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
198 return ERR_PTR(-ENOMEM);
200 read_dev_bar(dev, bar, offset, ~0);
206 static void *rom_init(struct pci_dev *dev, int offset)
208 struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
211 return ERR_PTR(-ENOMEM);
213 read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
219 static void bar_reset(struct pci_dev *dev, int offset, void *data)
221 struct pci_bar_info *bar = data;
226 static void bar_release(struct pci_dev *dev, int offset, void *data)
231 static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
232 u16 *value, void *data)
234 *value = dev->vendor;
239 static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
240 u16 *value, void *data)
242 *value = dev->device;
247 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
250 *value = (u8) dev->irq;
255 static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
260 err = pci_read_config_byte(dev, offset, &cur_value);
264 if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
265 || value == PCI_BIST_START)
266 err = pci_write_config_byte(dev, offset, value);
272 static const struct config_field header_common[] = {
274 .offset = PCI_VENDOR_ID,
276 .u.w.read = xen_pcibk_read_vendor,
279 .offset = PCI_DEVICE_ID,
281 .u.w.read = xen_pcibk_read_device,
284 .offset = PCI_COMMAND,
286 .u.w.read = command_read,
287 .u.w.write = command_write,
290 .offset = PCI_INTERRUPT_LINE,
292 .u.b.read = interrupt_read,
295 .offset = PCI_INTERRUPT_PIN,
297 .u.b.read = xen_pcibk_read_config_byte,
300 /* Any side effects of letting driver domain control cache line? */
301 .offset = PCI_CACHE_LINE_SIZE,
303 .u.b.read = xen_pcibk_read_config_byte,
304 .u.b.write = xen_pcibk_write_config_byte,
307 .offset = PCI_LATENCY_TIMER,
309 .u.b.read = xen_pcibk_read_config_byte,
314 .u.b.read = xen_pcibk_read_config_byte,
315 .u.b.write = bist_write,
320 #define CFG_FIELD_BAR(reg_offset) \
322 .offset = reg_offset, \
325 .reset = bar_reset, \
326 .release = bar_release, \
327 .u.dw.read = bar_read, \
328 .u.dw.write = bar_write, \
331 #define CFG_FIELD_ROM(reg_offset) \
333 .offset = reg_offset, \
336 .reset = bar_reset, \
337 .release = bar_release, \
338 .u.dw.read = bar_read, \
339 .u.dw.write = rom_write, \
342 static const struct config_field header_0[] = {
343 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
344 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
345 CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
346 CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
347 CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
348 CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
349 CFG_FIELD_ROM(PCI_ROM_ADDRESS),
353 static const struct config_field header_1[] = {
354 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
355 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
356 CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
360 int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
364 err = xen_pcibk_config_add_fields(dev, header_common);
368 switch (dev->hdr_type) {
369 case PCI_HEADER_TYPE_NORMAL:
370 err = xen_pcibk_config_add_fields(dev, header_0);
373 case PCI_HEADER_TYPE_BRIDGE:
374 err = xen_pcibk_config_add_fields(dev, header_1);
379 printk(KERN_ERR DRV_NAME ": %s: Unsupported header type %d!\n",
380 pci_name(dev), dev->hdr_type);