drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24 #include "via_clock.h"
  25
  26 static struct pll_limit cle266_pll_limits[] = {
  27         {19, 19, 4, 0},
  28         {26, 102, 5, 0},
  29         {53, 112, 6, 0},
  30         {41, 100, 7, 0},
  31         {83, 108, 8, 0},
  32         {87, 118, 9, 0},
  33         {95, 115, 12, 0},
  34         {108, 108, 13, 0},
  35         {83, 83, 17, 0},
  36         {67, 98, 20, 0},
  37         {121, 121, 24, 0},
  38         {99, 99, 29, 0},
  39         {33, 33, 3, 1},
  40         {15, 23, 4, 1},
  41         {37, 121, 5, 1},
  42         {82, 82, 6, 1},
  43         {31, 84, 7, 1},
  44         {83, 83, 8, 1},
  45         {76, 127, 9, 1},
  46         {33, 121, 4, 2},
  47         {91, 118, 5, 2},
  48         {83, 109, 6, 2},
  49         {90, 90, 7, 2},
  50         {93, 93, 2, 3},
  51         {53, 53, 3, 3},
  52         {73, 117, 4, 3},
  53         {101, 127, 5, 3},
  54         {99, 99, 7, 3}
  55 };
  56
  57 static struct pll_limit k800_pll_limits[] = {
  58         {22, 22, 2, 0},
  59         {28, 28, 3, 0},
  60         {81, 112, 3, 1},
  61         {86, 166, 4, 1},
  62         {109, 153, 5, 1},
  63         {66, 116, 3, 2},
  64         {93, 137, 4, 2},
  65         {117, 208, 5, 2},
  66         {30, 30, 2, 3},
  67         {69, 125, 3, 3},
  68         {89, 161, 4, 3},
  69         {121, 208, 5, 3},
  70         {66, 66, 2, 4},
  71         {85, 85, 3, 4},
  72         {141, 161, 4, 4},
  73         {177, 177, 5, 4}
  74 };
  75
  76 static struct pll_limit cx700_pll_limits[] = {
  77         {98, 98, 3, 1},
  78         {86, 86, 4, 1},
  79         {109, 208, 5, 1},
  80         {68, 68, 2, 2},
  81         {95, 116, 3, 2},
  82         {93, 166, 4, 2},
  83         {110, 206, 5, 2},
  84         {174, 174, 7, 2},
  85         {82, 109, 3, 3},
  86         {117, 161, 4, 3},
  87         {112, 208, 5, 3},
  88         {141, 202, 5, 4}
  89 };
  90
  91 static struct pll_limit vx855_pll_limits[] = {
  92         {86, 86, 4, 1},
  93         {108, 208, 5, 1},
  94         {110, 208, 5, 2},
  95         {83, 112, 3, 3},
  96         {103, 161, 4, 3},
  97         {112, 209, 5, 3},
  98         {142, 161, 4, 4},
  99         {141, 176, 5, 4}
 100 };
 101
 102 /* according to VIA Technologies these values are based on experiment */
 103 static struct io_reg scaling_parameters[] = {
 104         {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
 105         {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
 106         {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
 107         {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
 108         {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
 109         {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
 110         {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
 111         {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
 112         {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
 113         {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
 114         {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
 115         {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
 116         {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
 117         {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 118 };
 119
 120 static struct fifo_depth_select display_fifo_depth_reg = {
 121         /* IGA1 FIFO Depth_Select */
 122         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 123         /* IGA2 FIFO Depth_Select */
 124         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 125          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 126 };
 127
 128 static struct fifo_threshold_select fifo_threshold_select_reg = {
 129         /* IGA1 FIFO Threshold Select */
 130         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 131         /* IGA2 FIFO Threshold Select */
 132         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 133 };
 134
 135 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 136         /* IGA1 FIFO High Threshold Select */
 137         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 138         /* IGA2 FIFO High Threshold Select */
 139         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 140 };
 141
 142 static struct display_queue_expire_num display_queue_expire_num_reg = {
 143         /* IGA1 Display Queue Expire Num */
 144         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 145         /* IGA2 Display Queue Expire Num */
 146         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 147 };
 148
 149 /* Definition Fetch Count Registers*/
 150 static struct fetch_count fetch_count_reg = {
 151         /* IGA1 Fetch Count Register */
 152         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 153         /* IGA2 Fetch Count Register */
 154         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 155 };
 156
 157 static struct iga1_crtc_timing iga1_crtc_reg = {
 158         /* IGA1 Horizontal Total */
 159         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 160         /* IGA1 Horizontal Addressable Video */
 161         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 162         /* IGA1 Horizontal Blank Start */
 163         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 164         /* IGA1 Horizontal Blank End */
 165         {IGA1_HOR_BLANK_END_REG_NUM,
 166          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 167         /* IGA1 Horizontal Sync Start */
 168         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 169         /* IGA1 Horizontal Sync End */
 170         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 171         /* IGA1 Vertical Total */
 172         {IGA1_VER_TOTAL_REG_NUM,
 173          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 174         /* IGA1 Vertical Addressable Video */
 175         {IGA1_VER_ADDR_REG_NUM,
 176          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 177         /* IGA1 Vertical Blank Start */
 178         {IGA1_VER_BLANK_START_REG_NUM,
 179          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 180         /* IGA1 Vertical Blank End */
 181         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 182         /* IGA1 Vertical Sync Start */
 183         {IGA1_VER_SYNC_START_REG_NUM,
 184          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 185         /* IGA1 Vertical Sync End */
 186         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 187 };
 188
 189 static struct iga2_crtc_timing iga2_crtc_reg = {
 190         /* IGA2 Horizontal Total */
 191         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 192         /* IGA2 Horizontal Addressable Video */
 193         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 194         /* IGA2 Horizontal Blank Start */
 195         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 196         /* IGA2 Horizontal Blank End */
 197         {IGA2_HOR_BLANK_END_REG_NUM,
 198          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 199         /* IGA2 Horizontal Sync Start */
 200         {IGA2_HOR_SYNC_START_REG_NUM,
 201          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 202         /* IGA2 Horizontal Sync End */
 203         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 204         /* IGA2 Vertical Total */
 205         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 206         /* IGA2 Vertical Addressable Video */
 207         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 208         /* IGA2 Vertical Blank Start */
 209         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 210         /* IGA2 Vertical Blank End */
 211         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 212         /* IGA2 Vertical Sync Start */
 213         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 214         /* IGA2 Vertical Sync End */
 215         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 216 };
 217
 218 static struct rgbLUT palLUT_table[] = {
 219         /* {R,G,B} */
 220         /* Index 0x00~0x03 */
 221         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 222                                                                      0x2A,
 223                                                                      0x2A},
 224         /* Index 0x04~0x07 */
 225         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 226                                                                      0x2A,
 227                                                                      0x2A},
 228         /* Index 0x08~0x0B */
 229         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 230                                                                      0x3F,
 231                                                                      0x3F},
 232         /* Index 0x0C~0x0F */
 233         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 234                                                                      0x3F,
 235                                                                      0x3F},
 236         /* Index 0x10~0x13 */
 237         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 238                                                                      0x0B,
 239                                                                      0x0B},
 240         /* Index 0x14~0x17 */
 241         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 242                                                                      0x18,
 243                                                                      0x18},
 244         /* Index 0x18~0x1B */
 245         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 246                                                                      0x28,
 247                                                                      0x28},
 248         /* Index 0x1C~0x1F */
 249         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 250                                                                      0x3F,
 251                                                                      0x3F},
 252         /* Index 0x20~0x23 */
 253         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 254                                                                      0x00,
 255                                                                      0x3F},
 256         /* Index 0x24~0x27 */
 257         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 258                                                                      0x00,
 259                                                                      0x10},
 260         /* Index 0x28~0x2B */
 261         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 262                                                                      0x2F,
 263                                                                      0x00},
 264         /* Index 0x2C~0x2F */
 265         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 266                                                                      0x3F,
 267                                                                      0x00},
 268         /* Index 0x30~0x33 */
 269         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 270                                                                      0x3F,
 271                                                                      0x2F},
 272         /* Index 0x34~0x37 */
 273         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 274                                                                      0x10,
 275                                                                      0x3F},
 276         /* Index 0x38~0x3B */
 277         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 278                                                                      0x1F,
 279                                                                      0x3F},
 280         /* Index 0x3C~0x3F */
 281         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 282                                                                      0x1F,
 283                                                                      0x27},
 284         /* Index 0x40~0x43 */
 285         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 286                                                                      0x3F,
 287                                                                      0x1F},
 288         /* Index 0x44~0x47 */
 289         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 290                                                                      0x3F,
 291                                                                      0x1F},
 292         /* Index 0x48~0x4B */
 293         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 294                                                                      0x3F,
 295                                                                      0x37},
 296         /* Index 0x4C~0x4F */
 297         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 298                                                                      0x27,
 299                                                                      0x3F},
 300         /* Index 0x50~0x53 */
 301         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 302                                                                      0x2D,
 303                                                                      0x3F},
 304         /* Index 0x54~0x57 */
 305         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 306                                                                      0x2D,
 307                                                                      0x31},
 308         /* Index 0x58~0x5B */
 309         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 310                                                                      0x3A,
 311                                                                      0x2D},
 312         /* Index 0x5C~0x5F */
 313         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 314                                                                      0x3F,
 315                                                                      0x2D},
 316         /* Index 0x60~0x63 */
 317         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 318                                                                      0x3F,
 319                                                                      0x3A},
 320         /* Index 0x64~0x67 */
 321         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 322                                                                      0x31,
 323                                                                      0x3F},
 324         /* Index 0x68~0x6B */
 325         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 326                                                                      0x00,
 327                                                                      0x1C},
 328         /* Index 0x6C~0x6F */
 329         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 330                                                                      0x00,
 331                                                                      0x07},
 332         /* Index 0x70~0x73 */
 333         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 334                                                                      0x15,
 335                                                                      0x00},
 336         /* Index 0x74~0x77 */
 337         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 338                                                                      0x1C,
 339                                                                      0x00},
 340         /* Index 0x78~0x7B */
 341         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 342                                                                      0x1C,
 343                                                                      0x15},
 344         /* Index 0x7C~0x7F */
 345         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 346                                                                      0x07,
 347                                                                      0x1C},
 348         /* Index 0x80~0x83 */
 349         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 350                                                                      0x0E,
 351                                                                      0x1C},
 352         /* Index 0x84~0x87 */
 353         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 354                                                                      0x0E,
 355                                                                      0x11},
 356         /* Index 0x88~0x8B */
 357         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 358                                                                      0x18,
 359                                                                      0x0E},
 360         /* Index 0x8C~0x8F */
 361         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 362                                                                      0x1C,
 363                                                                      0x0E},
 364         /* Index 0x90~0x93 */
 365         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 366                                                                      0x1C,
 367                                                                      0x18},
 368         /* Index 0x94~0x97 */
 369         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 370                                                                      0x11,
 371                                                                      0x1C},
 372         /* Index 0x98~0x9B */
 373         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 374                                                                      0x14,
 375                                                                      0x1C},
 376         /* Index 0x9C~0x9F */
 377         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 378                                                                      0x14,
 379                                                                      0x16},
 380         /* Index 0xA0~0xA3 */
 381         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 382                                                                      0x1A,
 383                                                                      0x14},
 384         /* Index 0xA4~0xA7 */
 385         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 386                                                                      0x1C,
 387                                                                      0x14},
 388         /* Index 0xA8~0xAB */
 389         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 390                                                                      0x1C,
 391                                                                      0x1A},
 392         /* Index 0xAC~0xAF */
 393         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 394                                                                      0x16,
 395                                                                      0x1C},
 396         /* Index 0xB0~0xB3 */
 397         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 398                                                                      0x00,
 399                                                                      0x10},
 400         /* Index 0xB4~0xB7 */
 401         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 402                                                                      0x00,
 403                                                                      0x04},
 404         /* Index 0xB8~0xBB */
 405         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 406                                                                      0x0C,
 407                                                                      0x00},
 408         /* Index 0xBC~0xBF */
 409         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 410                                                                      0x10,
 411                                                                      0x00},
 412         /* Index 0xC0~0xC3 */
 413         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 414                                                                      0x10,
 415                                                                      0x0C},
 416         /* Index 0xC4~0xC7 */
 417         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 418                                                                      0x04,
 419                                                                      0x10},
 420         /* Index 0xC8~0xCB */
 421         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 422                                                                      0x08,
 423                                                                      0x10},
 424         /* Index 0xCC~0xCF */
 425         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 426                                                                      0x08,
 427                                                                      0x0A},
 428         /* Index 0xD0~0xD3 */
 429         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 430                                                                      0x0E,
 431                                                                      0x08},
 432         /* Index 0xD4~0xD7 */
 433         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 434                                                                      0x10,
 435                                                                      0x08},
 436         /* Index 0xD8~0xDB */
 437         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 438                                                                      0x10,
 439                                                                      0x0E},
 440         /* Index 0xDC~0xDF */
 441         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 442                                                                      0x0A,
 443                                                                      0x10},
 444         /* Index 0xE0~0xE3 */
 445         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 446                                                                      0x0B,
 447                                                                      0x10},
 448         /* Index 0xE4~0xE7 */
 449         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 450                                                                      0x0B,
 451                                                                      0x0C},
 452         /* Index 0xE8~0xEB */
 453         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 454                                                                      0x0F,
 455                                                                      0x0B},
 456         /* Index 0xEC~0xEF */
 457         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 458                                                                      0x10,
 459                                                                      0x0B},
 460         /* Index 0xF0~0xF3 */
 461         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 462                                                                      0x10,
 463                                                                      0x0F},
 464         /* Index 0xF4~0xF7 */
 465         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 466                                                                      0x0C,
 467                                                                      0x10},
 468         /* Index 0xF8~0xFB */
 469         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 470                                                                      0x00,
 471                                                                      0x00},
 472         /* Index 0xFC~0xFF */
 473         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 474                                                                      0x00,
 475                                                                      0x00}
 476 };
 477
 478 static struct via_device_mapping device_mapping[] = {
 479         {VIA_LDVP0, "LDVP0"},
 480         {VIA_LDVP1, "LDVP1"},
 481         {VIA_DVP0, "DVP0"},
 482         {VIA_CRT, "CRT"},
 483         {VIA_DVP1, "DVP1"},
 484         {VIA_LVDS1, "LVDS1"},
 485         {VIA_LVDS2, "LVDS2"}
 486 };
 487
 488 /* structure with function pointers to support clock control */
 489 static struct via_clock clock;
 490
 491 static void load_fix_bit_crtc_reg(void);
 492 static void __devinit init_gfx_chip_info(int chip_type);
 493 static void __devinit init_tmds_chip_info(void);
 494 static void __devinit init_lvds_chip_info(void);
 495 static void device_screen_off(void);
 496 static void device_screen_on(void);
 497 static void set_display_channel(void);
 498 static void device_off(void);
 499 static void device_on(void);
 500 static void enable_second_display_channel(void);
 501 static void disable_second_display_channel(void);
 502
 503 void viafb_lock_crt(void)
 504 {
 505         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 506 }
 507
 508 void viafb_unlock_crt(void)
 509 {
 510         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 511         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 512 }
 513
 514 static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 515 {
 516         outb(index, LUT_INDEX_WRITE);
 517         outb(r, LUT_DATA);
 518         outb(g, LUT_DATA);
 519         outb(b, LUT_DATA);
 520 }
 521
 522 static u32 get_dvi_devices(int output_interface)
 523 {
 524         switch (output_interface) {
 525         case INTERFACE_DVP0:
 526                 return VIA_DVP0 | VIA_LDVP0;
 527
 528         case INTERFACE_DVP1:
 529                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 530                         return VIA_LDVP1;
 531                 else
 532                         return VIA_DVP1;
 533
 534         case INTERFACE_DFP_HIGH:
 535                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 536                         return 0;
 537                 else
 538                         return VIA_LVDS2 | VIA_DVP0;
 539
 540         case INTERFACE_DFP_LOW:
 541                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 542                         return 0;
 543                 else
 544                         return VIA_DVP1 | VIA_LVDS1;
 545
 546         case INTERFACE_TMDS:
 547                 return VIA_LVDS1;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static u32 get_lcd_devices(int output_interface)
 554 {
 555         switch (output_interface) {
 556         case INTERFACE_DVP0:
 557                 return VIA_DVP0;
 558
 559         case INTERFACE_DVP1:
 560                 return VIA_DVP1;
 561
 562         case INTERFACE_DFP_HIGH:
 563                 return VIA_LVDS2 | VIA_DVP0;
 564
 565         case INTERFACE_DFP_LOW:
 566                 return VIA_LVDS1 | VIA_DVP1;
 567
 568         case INTERFACE_DFP:
 569                 return VIA_LVDS1 | VIA_LVDS2;
 570
 571         case INTERFACE_LVDS0:
 572         case INTERFACE_LVDS0LVDS1:
 573                 return VIA_LVDS1;
 574
 575         case INTERFACE_LVDS1:
 576                 return VIA_LVDS2;
 577         }
 578
 579         return 0;
 580 }
 581
 582 /*Set IGA path for each device*/
 583 void viafb_set_iga_path(void)
 584 {
 585
 586         if (viafb_SAMM_ON == 1) {
 587                 if (viafb_CRT_ON) {
 588                         if (viafb_primary_dev == CRT_Device)
 589                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 590                         else
 591                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 592                 }
 593
 594                 if (viafb_DVI_ON) {
 595                         if (viafb_primary_dev == DVI_Device)
 596                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 597                         else
 598                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 599                 }
 600
 601                 if (viafb_LCD_ON) {
 602                         if (viafb_primary_dev == LCD_Device) {
 603                                 if (viafb_dual_fb &&
 604                                         (viaparinfo->chip_info->gfx_chip_name ==
 605                                         UNICHROME_CLE266)) {
 606                                         viaparinfo->
 607                                         lvds_setting_info->iga_path = IGA2;
 608                                         viaparinfo->
 609                                         crt_setting_info->iga_path = IGA1;
 610                                         viaparinfo->
 611                                         tmds_setting_info->iga_path = IGA1;
 612                                 } else
 613                                         viaparinfo->
 614                                         lvds_setting_info->iga_path = IGA1;
 615                         } else {
 616                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 617                         }
 618                 }
 619                 if (viafb_LCD2_ON) {
 620                         if (LCD2_Device == viafb_primary_dev)
 621                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 622                         else
 623                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 624                 }
 625         } else {
 626                 viafb_SAMM_ON = 0;
 627
 628                 if (viafb_CRT_ON && viafb_LCD_ON) {
 629                         viaparinfo->crt_setting_info->iga_path = IGA1;
 630                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 631                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 632                         viaparinfo->crt_setting_info->iga_path = IGA1;
 633                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 634                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 635                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 636                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 637                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 638                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 639                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 640                 } else if (viafb_CRT_ON) {
 641                         viaparinfo->crt_setting_info->iga_path = IGA1;
 642                 } else if (viafb_LCD_ON) {
 643                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 644                 } else if (viafb_DVI_ON) {
 645                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 646                 }
 647         }
 648
 649         viaparinfo->shared->iga1_devices = 0;
 650         viaparinfo->shared->iga2_devices = 0;
 651         if (viafb_CRT_ON) {
 652                 if (viaparinfo->crt_setting_info->iga_path == IGA1)
 653                         viaparinfo->shared->iga1_devices |= VIA_CRT;
 654                 else
 655                         viaparinfo->shared->iga2_devices |= VIA_CRT;
 656         }
 657
 658         if (viafb_DVI_ON) {
 659                 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
 660                         viaparinfo->shared->iga1_devices |= get_dvi_devices(
 661                                 viaparinfo->chip_info->
 662                                 tmds_chip_info.output_interface);
 663                 else
 664                         viaparinfo->shared->iga2_devices |= get_dvi_devices(
 665                                 viaparinfo->chip_info->
 666                                 tmds_chip_info.output_interface);
 667         }
 668
 669         if (viafb_LCD_ON) {
 670                 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
 671                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 672                                 viaparinfo->chip_info->
 673                                 lvds_chip_info.output_interface);
 674                 else
 675                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 676                                 viaparinfo->chip_info->
 677                                 lvds_chip_info.output_interface);
 678         }
 679
 680         if (viafb_LCD2_ON) {
 681                 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
 682                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 683                                 viaparinfo->chip_info->
 684                                 lvds_chip_info2.output_interface);
 685                 else
 686                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 687                                 viaparinfo->chip_info->
 688                                 lvds_chip_info2.output_interface);
 689         }
 690 }
 691
 692 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 693 {
 694         outb(0xFF, 0x3C6); /* bit mask of palette */
 695         outb(index, 0x3C8);
 696         outb(red, 0x3C9);
 697         outb(green, 0x3C9);
 698         outb(blue, 0x3C9);
 699 }
 700
 701 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 702 {
 703         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 704         set_color_register(index, red, green, blue);
 705 }
 706
 707 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 708 {
 709         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 710         set_color_register(index, red, green, blue);
 711 }
 712
 713 static void set_source_common(u8 index, u8 offset, u8 iga)
 714 {
 715         u8 value, mask = 1 << offset;
 716
 717         switch (iga) {
 718         case IGA1:
 719                 value = 0x00;
 720                 break;
 721         case IGA2:
 722                 value = mask;
 723                 break;
 724         default:
 725                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 726                 return;
 727         }
 728
 729         via_write_reg_mask(VIACR, index, value, mask);
 730 }
 731
 732 static void set_crt_source(u8 iga)
 733 {
 734         u8 value;
 735
 736         switch (iga) {
 737         case IGA1:
 738                 value = 0x00;
 739                 break;
 740         case IGA2:
 741                 value = 0x40;
 742                 break;
 743         default:
 744                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 745                 return;
 746         }
 747
 748         via_write_reg_mask(VIASR, 0x16, value, 0x40);
 749 }
 750
 751 static inline void set_ldvp0_source(u8 iga)
 752 {
 753         set_source_common(0x6C, 7, iga);
 754 }
 755
 756 static inline void set_ldvp1_source(u8 iga)
 757 {
 758         set_source_common(0x93, 7, iga);
 759 }
 760
 761 static inline void set_dvp0_source(u8 iga)
 762 {
 763         set_source_common(0x96, 4, iga);
 764 }
 765
 766 static inline void set_dvp1_source(u8 iga)
 767 {
 768         set_source_common(0x9B, 4, iga);
 769 }
 770
 771 static inline void set_lvds1_source(u8 iga)
 772 {
 773         set_source_common(0x99, 4, iga);
 774 }
 775
 776 static inline void set_lvds2_source(u8 iga)
 777 {
 778         set_source_common(0x97, 4, iga);
 779 }
 780
 781 void via_set_source(u32 devices, u8 iga)
 782 {
 783         if (devices & VIA_LDVP0)
 784                 set_ldvp0_source(iga);
 785         if (devices & VIA_LDVP1)
 786                 set_ldvp1_source(iga);
 787         if (devices & VIA_DVP0)
 788                 set_dvp0_source(iga);
 789         if (devices & VIA_CRT)
 790                 set_crt_source(iga);
 791         if (devices & VIA_DVP1)
 792                 set_dvp1_source(iga);
 793         if (devices & VIA_LVDS1)
 794                 set_lvds1_source(iga);
 795         if (devices & VIA_LVDS2)
 796                 set_lvds2_source(iga);
 797 }
 798
 799 static void set_crt_state(u8 state)
 800 {
 801         u8 value;
 802
 803         switch (state) {
 804         case VIA_STATE_ON:
 805                 value = 0x00;
 806                 break;
 807         case VIA_STATE_STANDBY:
 808                 value = 0x10;
 809                 break;
 810         case VIA_STATE_SUSPEND:
 811                 value = 0x20;
 812                 break;
 813         case VIA_STATE_OFF:
 814                 value = 0x30;
 815                 break;
 816         default:
 817                 return;
 818         }
 819
 820         via_write_reg_mask(VIACR, 0x36, value, 0x30);
 821 }
 822
 823 static void set_dvp0_state(u8 state)
 824 {
 825         u8 value;
 826
 827         switch (state) {
 828         case VIA_STATE_ON:
 829                 value = 0xC0;
 830                 break;
 831         case VIA_STATE_OFF:
 832                 value = 0x00;
 833                 break;
 834         default:
 835                 return;
 836         }
 837
 838         via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
 839 }
 840
 841 static void set_dvp1_state(u8 state)
 842 {
 843         u8 value;
 844
 845         switch (state) {
 846         case VIA_STATE_ON:
 847                 value = 0x30;
 848                 break;
 849         case VIA_STATE_OFF:
 850                 value = 0x00;
 851                 break;
 852         default:
 853                 return;
 854         }
 855
 856         via_write_reg_mask(VIASR, 0x1E, value, 0x30);
 857 }
 858
 859 static void set_lvds1_state(u8 state)
 860 {
 861         u8 value;
 862
 863         switch (state) {
 864         case VIA_STATE_ON:
 865                 value = 0x03;
 866                 break;
 867         case VIA_STATE_OFF:
 868                 value = 0x00;
 869                 break;
 870         default:
 871                 return;
 872         }
 873
 874         via_write_reg_mask(VIASR, 0x2A, value, 0x03);
 875 }
 876
 877 static void set_lvds2_state(u8 state)
 878 {
 879         u8 value;
 880
 881         switch (state) {
 882         case VIA_STATE_ON:
 883                 value = 0x0C;
 884                 break;
 885         case VIA_STATE_OFF:
 886                 value = 0x00;
 887                 break;
 888         default:
 889                 return;
 890         }
 891
 892         via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
 893 }
 894
 895 void via_set_state(u32 devices, u8 state)
 896 {
 897         /*
 898         TODO: Can we enable/disable these devices? How?
 899         if (devices & VIA_LDVP0)
 900         if (devices & VIA_LDVP1)
 901         */
 902         if (devices & VIA_DVP0)
 903                 set_dvp0_state(state);
 904         if (devices & VIA_CRT)
 905                 set_crt_state(state);
 906         if (devices & VIA_DVP1)
 907                 set_dvp1_state(state);
 908         if (devices & VIA_LVDS1)
 909                 set_lvds1_state(state);
 910         if (devices & VIA_LVDS2)
 911                 set_lvds2_state(state);
 912 }
 913
 914 void via_set_sync_polarity(u32 devices, u8 polarity)
 915 {
 916         if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) {
 917                 printk(KERN_WARNING "viafb: Unsupported polarity: %d\n",
 918                         polarity);
 919                 return;
 920         }
 921
 922         if (devices & VIA_CRT)
 923                 via_write_misc_reg_mask(polarity << 6, 0xC0);
 924         if (devices & VIA_DVP1)
 925                 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);
 926         if (devices & VIA_LVDS1)
 927                 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);
 928         if (devices & VIA_LVDS2)
 929                 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);
 930 }
 931
 932 u32 via_parse_odev(char *input, char **end)
 933 {
 934         char *ptr = input;
 935         u32 odev = 0;
 936         bool next = true;
 937         int i, len;
 938
 939         while (next) {
 940                 next = false;
 941                 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
 942                         len = strlen(device_mapping[i].name);
 943                         if (!strncmp(ptr, device_mapping[i].name, len)) {
 944                                 odev |= device_mapping[i].device;
 945                                 ptr += len;
 946                                 if (*ptr == ',') {
 947                                         ptr++;
 948                                         next = true;
 949                                 }
 950                         }
 951                 }
 952         }
 953
 954         *end = ptr;
 955         return odev;
 956 }
 957
 958 void via_odev_to_seq(struct seq_file *m, u32 odev)
 959 {
 960         int i, count = 0;
 961
 962         for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
 963                 if (odev & device_mapping[i].device) {
 964                         if (count > 0)
 965                                 seq_putc(m, ',');
 966
 967                         seq_puts(m, device_mapping[i].name);
 968                         count++;
 969                 }
 970         }
 971
 972         seq_putc(m, '\n');
 973 }
 974
 975 static void load_fix_bit_crtc_reg(void)
 976 {
 977         /* always set to 1 */
 978         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
 979         /* line compare should set all bits = 1 (extend modes) */
 980         viafb_write_reg(CR18, VIACR, 0xff);
 981         /* line compare should set all bits = 1 (extend modes) */
 982         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
 983         /* line compare should set all bits = 1 (extend modes) */
 984         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
 985         /* line compare should set all bits = 1 (extend modes) */
 986         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
 987         /* line compare should set all bits = 1 (extend modes) */
 988         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
 989         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
 990         /* extend mode always set to e3h */
 991         viafb_write_reg(CR17, VIACR, 0xe3);
 992         /* extend mode always set to 0h */
 993         viafb_write_reg(CR08, VIACR, 0x00);
 994         /* extend mode always set to 0h */
 995         viafb_write_reg(CR14, VIACR, 0x00);
 996
 997         /* If K8M800, enable Prefetch Mode. */
 998         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
 999                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1000                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1001         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1002             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1003                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1004
1005 }
1006
1007 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1008         struct io_register *reg,
1009               int io_type)
1010 {
1011         int reg_mask;
1012         int bit_num = 0;
1013         int data;
1014         int i, j;
1015         int shift_next_reg;
1016         int start_index, end_index, cr_index;
1017         u16 get_bit;
1018
1019         for (i = 0; i < viafb_load_reg_num; i++) {
1020                 reg_mask = 0;
1021                 data = 0;
1022                 start_index = reg[i].start_bit;
1023                 end_index = reg[i].end_bit;
1024                 cr_index = reg[i].io_addr;
1025
1026                 shift_next_reg = bit_num;
1027                 for (j = start_index; j <= end_index; j++) {
1028                         /*if (bit_num==8) timing_value = timing_value >>8; */
1029                         reg_mask = reg_mask | (BIT0 << j);
1030                         get_bit = (timing_value & (BIT0 << bit_num));
1031                         data =
1032                             data | ((get_bit >> shift_next_reg) << start_index);
1033                         bit_num++;
1034                 }
1035                 if (io_type == VIACR)
1036                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1037                 else
1038                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1039         }
1040
1041 }
1042
1043 /* Write Registers */
1044 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1045 {
1046         int i;
1047
1048         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1049
1050         for (i = 0; i < ItemNum; i++)
1051                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1052                         RegTable[i].value, RegTable[i].mask);
1053 }
1054
1055 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1056 {
1057         int reg_value;
1058         int viafb_load_reg_num;
1059         struct io_register *reg = NULL;
1060
1061         switch (set_iga) {
1062         case IGA1:
1063                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1064                 viafb_load_reg_num = fetch_count_reg.
1065                         iga1_fetch_count_reg.reg_num;
1066                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1067                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1068                 break;
1069         case IGA2:
1070                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1071                 viafb_load_reg_num = fetch_count_reg.
1072                         iga2_fetch_count_reg.reg_num;
1073                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1074                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1075                 break;
1076         }
1077
1078 }
1079
1080 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1081 {
1082         int reg_value;
1083         int viafb_load_reg_num;
1084         struct io_register *reg = NULL;
1085         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1086             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1087         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1088             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1089
1090         if (set_iga == IGA1) {
1091                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1092                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1093                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1094                         iga1_fifo_high_threshold =
1095                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1096                         /* If resolution > 1280x1024, expire length = 64, else
1097                            expire length = 128 */
1098                         if ((hor_active > 1280) && (ver_active > 1024))
1099                                 iga1_display_queue_expire_num = 16;
1100                         else
1101                                 iga1_display_queue_expire_num =
1102                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1103
1104                 }
1105
1106                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1107                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1108                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1109                         iga1_fifo_high_threshold =
1110                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1111                         iga1_display_queue_expire_num =
1112                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1113
1114                         /* If resolution > 1280x1024, expire length = 64, else
1115                            expire length = 128 */
1116                         if ((hor_active > 1280) && (ver_active > 1024))
1117                                 iga1_display_queue_expire_num = 16;
1118                         else
1119                                 iga1_display_queue_expire_num =
1120                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1121                 }
1122
1123                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1124                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1125                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1126                         iga1_fifo_high_threshold =
1127                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1128
1129                         /* If resolution > 1280x1024, expire length = 64,
1130                            else expire length = 128 */
1131                         if ((hor_active > 1280) && (ver_active > 1024))
1132                                 iga1_display_queue_expire_num = 16;
1133                         else
1134                                 iga1_display_queue_expire_num =
1135                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1136                 }
1137
1138                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1139                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1140                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1141                         iga1_fifo_high_threshold =
1142                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1143                         iga1_display_queue_expire_num =
1144                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1145                 }
1146
1147                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1148                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1149                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1150                         iga1_fifo_high_threshold =
1151                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1152                         iga1_display_queue_expire_num =
1153                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1154                 }
1155
1156                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1157                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1158                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1159                         iga1_fifo_high_threshold =
1160                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1161                         iga1_display_queue_expire_num =
1162                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1163                 }
1164
1165                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1166                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1167                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1168                         iga1_fifo_high_threshold =
1169                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1170                         iga1_display_queue_expire_num =
1171                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1172                 }
1173
1174                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1175                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1176                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1177                         iga1_fifo_high_threshold =
1178                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1179                         iga1_display_queue_expire_num =
1180                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1181                 }
1182
1183                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1184                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1185                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1186                         iga1_fifo_high_threshold =
1187                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1188                         iga1_display_queue_expire_num =
1189                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1190                 }
1191
1192                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1193                         iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
1194                         iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
1195                         iga1_fifo_high_threshold =
1196                             VX900_IGA1_FIFO_HIGH_THRESHOLD;
1197                         iga1_display_queue_expire_num =
1198                             VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1199                 }
1200
1201                 /* Set Display FIFO Depath Select */
1202                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1203                 viafb_load_reg_num =
1204                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1205                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1206                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1207
1208                 /* Set Display FIFO Threshold Select */
1209                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1210                 viafb_load_reg_num =
1211                     fifo_threshold_select_reg.
1212                     iga1_fifo_threshold_select_reg.reg_num;
1213                 reg =
1214                     fifo_threshold_select_reg.
1215                     iga1_fifo_threshold_select_reg.reg;
1216                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1217
1218                 /* Set FIFO High Threshold Select */
1219                 reg_value =
1220                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1221                 viafb_load_reg_num =
1222                     fifo_high_threshold_select_reg.
1223                     iga1_fifo_high_threshold_select_reg.reg_num;
1224                 reg =
1225                     fifo_high_threshold_select_reg.
1226                     iga1_fifo_high_threshold_select_reg.reg;
1227                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1228
1229                 /* Set Display Queue Expire Num */
1230                 reg_value =
1231                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1232                     (iga1_display_queue_expire_num);
1233                 viafb_load_reg_num =
1234                     display_queue_expire_num_reg.
1235                     iga1_display_queue_expire_num_reg.reg_num;
1236                 reg =
1237                     display_queue_expire_num_reg.
1238                     iga1_display_queue_expire_num_reg.reg;
1239                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1240
1241         } else {
1242                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1243                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1244                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1245                         iga2_fifo_high_threshold =
1246                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1247
1248                         /* If resolution > 1280x1024, expire length = 64,
1249                            else  expire length = 128 */
1250                         if ((hor_active > 1280) && (ver_active > 1024))
1251                                 iga2_display_queue_expire_num = 16;
1252                         else
1253                                 iga2_display_queue_expire_num =
1254                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1255                 }
1256
1257                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1258                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1259                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1260                         iga2_fifo_high_threshold =
1261                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1262
1263                         /* If resolution > 1280x1024, expire length = 64,
1264                            else  expire length = 128 */
1265                         if ((hor_active > 1280) && (ver_active > 1024))
1266                                 iga2_display_queue_expire_num = 16;
1267                         else
1268                                 iga2_display_queue_expire_num =
1269                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1270                 }
1271
1272                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1273                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1274                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1275                         iga2_fifo_high_threshold =
1276                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1277
1278                         /* If resolution > 1280x1024, expire length = 64,
1279                            else expire length = 128 */
1280                         if ((hor_active > 1280) && (ver_active > 1024))
1281                                 iga2_display_queue_expire_num = 16;
1282                         else
1283                                 iga2_display_queue_expire_num =
1284                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1285                 }
1286
1287                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1288                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1289                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1290                         iga2_fifo_high_threshold =
1291                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1292                         iga2_display_queue_expire_num =
1293                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1294                 }
1295
1296                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1297                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1298                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1299                         iga2_fifo_high_threshold =
1300                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1301                         iga2_display_queue_expire_num =
1302                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1303                 }
1304
1305                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1306                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1307                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1308                         iga2_fifo_high_threshold =
1309                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1310                         iga2_display_queue_expire_num =
1311                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1312                 }
1313
1314                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1315                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1316                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1317                         iga2_fifo_high_threshold =
1318                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1319                         iga2_display_queue_expire_num =
1320                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1321                 }
1322
1323                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1324                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1325                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1326                         iga2_fifo_high_threshold =
1327                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1328                         iga2_display_queue_expire_num =
1329                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1330                 }
1331
1332                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1333                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1334                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1335                         iga2_fifo_high_threshold =
1336                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1337                         iga2_display_queue_expire_num =
1338                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1339                 }
1340
1341                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1342                         iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
1343                         iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
1344                         iga2_fifo_high_threshold =
1345                             VX900_IGA2_FIFO_HIGH_THRESHOLD;
1346                         iga2_display_queue_expire_num =
1347                             VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1348                 }
1349
1350                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1351                         /* Set Display FIFO Depath Select */
1352                         reg_value =
1353                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1354                             - 1;
1355                         /* Patch LCD in IGA2 case */
1356                         viafb_load_reg_num =
1357                             display_fifo_depth_reg.
1358                             iga2_fifo_depth_select_reg.reg_num;
1359                         reg =
1360                             display_fifo_depth_reg.
1361                             iga2_fifo_depth_select_reg.reg;
1362                         viafb_load_reg(reg_value,
1363                                 viafb_load_reg_num, reg, VIACR);
1364                 } else {
1365
1366                         /* Set Display FIFO Depath Select */
1367                         reg_value =
1368                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1369                         viafb_load_reg_num =
1370                             display_fifo_depth_reg.
1371                             iga2_fifo_depth_select_reg.reg_num;
1372                         reg =
1373                             display_fifo_depth_reg.
1374                             iga2_fifo_depth_select_reg.reg;
1375                         viafb_load_reg(reg_value,
1376                                 viafb_load_reg_num, reg, VIACR);
1377                 }
1378
1379                 /* Set Display FIFO Threshold Select */
1380                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1381                 viafb_load_reg_num =
1382                     fifo_threshold_select_reg.
1383                     iga2_fifo_threshold_select_reg.reg_num;
1384                 reg =
1385                     fifo_threshold_select_reg.
1386                     iga2_fifo_threshold_select_reg.reg;
1387                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1388
1389                 /* Set FIFO High Threshold Select */
1390                 reg_value =
1391                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1392                 viafb_load_reg_num =
1393                     fifo_high_threshold_select_reg.
1394                     iga2_fifo_high_threshold_select_reg.reg_num;
1395                 reg =
1396                     fifo_high_threshold_select_reg.
1397                     iga2_fifo_high_threshold_select_reg.reg;
1398                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1399
1400                 /* Set Display Queue Expire Num */
1401                 reg_value =
1402                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1403                     (iga2_display_queue_expire_num);
1404                 viafb_load_reg_num =
1405                     display_queue_expire_num_reg.
1406                     iga2_display_queue_expire_num_reg.reg_num;
1407                 reg =
1408                     display_queue_expire_num_reg.
1409                     iga2_display_queue_expire_num_reg.reg;
1410                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1411
1412         }
1413
1414 }
1415
1416 static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
1417         int clk)
1418 {
1419         struct via_pll_config cur, up, down, best = {0, 1, 0};
1420         const u32 f0 = 14318180; /* X1 frequency */
1421         int i, f;
1422
1423         for (i = 0; i < size; i++) {
1424                 cur.rshift = limits[i].rshift;
1425                 cur.divisor = limits[i].divisor;
1426                 cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
1427                 f = abs(get_pll_output_frequency(f0, cur) - clk);
1428                 up = down = cur;
1429                 up.multiplier++;
1430                 down.multiplier--;
1431                 if (abs(get_pll_output_frequency(f0, up) - clk) < f)
1432                         cur = up;
1433                 else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
1434                         cur = down;
1435
1436                 if (cur.multiplier < limits[i].multiplier_min)
1437                         cur.multiplier = limits[i].multiplier_min;
1438                 else if (cur.multiplier > limits[i].multiplier_max)
1439                         cur.multiplier = limits[i].multiplier_max;
1440
1441                 f = abs(get_pll_output_frequency(f0, cur) - clk);
1442                 if (f < abs(get_pll_output_frequency(f0, best) - clk))
1443                         best = cur;
1444         }
1445
1446         return best;
1447 }
1448
1449 static struct via_pll_config get_best_pll_config(int clk)
1450 {
1451         struct via_pll_config config;
1452
1453         switch (viaparinfo->chip_info->gfx_chip_name) {
1454         case UNICHROME_CLE266:
1455         case UNICHROME_K400:
1456                 config = get_pll_config(cle266_pll_limits,
1457                         ARRAY_SIZE(cle266_pll_limits), clk);
1458                 break;
1459         case UNICHROME_K800:
1460         case UNICHROME_PM800:
1461         case UNICHROME_CN700:
1462                 config = get_pll_config(k800_pll_limits,
1463                         ARRAY_SIZE(k800_pll_limits), clk);
1464                 break;
1465         case UNICHROME_CX700:
1466         case UNICHROME_CN750:
1467         case UNICHROME_K8M890:
1468         case UNICHROME_P4M890:
1469         case UNICHROME_P4M900:
1470         case UNICHROME_VX800:
1471                 config = get_pll_config(cx700_pll_limits,
1472                         ARRAY_SIZE(cx700_pll_limits), clk);
1473                 break;
1474         case UNICHROME_VX855:
1475         case UNICHROME_VX900:
1476                 config = get_pll_config(vx855_pll_limits,
1477                         ARRAY_SIZE(vx855_pll_limits), clk);
1478                 break;
1479         }
1480
1481         return config;
1482 }
1483
1484 /* Set VCLK*/
1485 void viafb_set_vclock(u32 clk, int set_iga)
1486 {
1487         struct via_pll_config config = get_best_pll_config(clk);
1488
1489         if (set_iga == IGA1)
1490                 clock.set_primary_pll(config);
1491         if (set_iga == IGA2)
1492                 clock.set_secondary_pll(config);
1493
1494         /* Fire! */
1495         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1496 }
1497
1498 void viafb_load_crtc_timing(struct display_timing device_timing,
1499         int set_iga)
1500 {
1501         int i;
1502         int viafb_load_reg_num = 0;
1503         int reg_value = 0;
1504         struct io_register *reg = NULL;
1505
1506         viafb_unlock_crt();
1507
1508         for (i = 0; i < 12; i++) {
1509                 if (set_iga == IGA1) {
1510                         switch (i) {
1511                         case H_TOTAL_INDEX:
1512                                 reg_value =
1513                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1514                                                            hor_total);
1515                                 viafb_load_reg_num =
1516                                         iga1_crtc_reg.hor_total.reg_num;
1517                                 reg = iga1_crtc_reg.hor_total.reg;
1518                                 break;
1519                         case H_ADDR_INDEX:
1520                                 reg_value =
1521                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1522                                                           hor_addr);
1523                                 viafb_load_reg_num =
1524                                         iga1_crtc_reg.hor_addr.reg_num;
1525                                 reg = iga1_crtc_reg.hor_addr.reg;
1526                                 break;
1527                         case H_BLANK_START_INDEX:
1528                                 reg_value =
1529                                     IGA1_HOR_BLANK_START_FORMULA
1530                                     (device_timing.hor_blank_start);
1531                                 viafb_load_reg_num =
1532                                     iga1_crtc_reg.hor_blank_start.reg_num;
1533                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1534                                 break;
1535                         case H_BLANK_END_INDEX:
1536                                 reg_value =
1537                                     IGA1_HOR_BLANK_END_FORMULA
1538                                     (device_timing.hor_blank_start,
1539                                      device_timing.hor_blank_end);
1540                                 viafb_load_reg_num =
1541                                     iga1_crtc_reg.hor_blank_end.reg_num;
1542                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1543                                 break;
1544                         case H_SYNC_START_INDEX:
1545                                 reg_value =
1546                                     IGA1_HOR_SYNC_START_FORMULA
1547                                     (device_timing.hor_sync_start);
1548                                 viafb_load_reg_num =
1549                                     iga1_crtc_reg.hor_sync_start.reg_num;
1550                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1551                                 break;
1552                         case H_SYNC_END_INDEX:
1553                                 reg_value =
1554                                     IGA1_HOR_SYNC_END_FORMULA
1555                                     (device_timing.hor_sync_start,
1556                                      device_timing.hor_sync_end);
1557                                 viafb_load_reg_num =
1558                                     iga1_crtc_reg.hor_sync_end.reg_num;
1559                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1560                                 break;
1561                         case V_TOTAL_INDEX:
1562                                 reg_value =
1563                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1564                                                            ver_total);
1565                                 viafb_load_reg_num =
1566                                         iga1_crtc_reg.ver_total.reg_num;
1567                                 reg = iga1_crtc_reg.ver_total.reg;
1568                                 break;
1569                         case V_ADDR_INDEX:
1570                                 reg_value =
1571                                     IGA1_VER_ADDR_FORMULA(device_timing.
1572                                                           ver_addr);
1573                                 viafb_load_reg_num =
1574                                         iga1_crtc_reg.ver_addr.reg_num;
1575                                 reg = iga1_crtc_reg.ver_addr.reg;
1576                                 break;
1577                         case V_BLANK_START_INDEX:
1578                                 reg_value =
1579                                     IGA1_VER_BLANK_START_FORMULA
1580                                     (device_timing.ver_blank_start);
1581                                 viafb_load_reg_num =
1582                                     iga1_crtc_reg.ver_blank_start.reg_num;
1583                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1584                                 break;
1585                         case V_BLANK_END_INDEX:
1586                                 reg_value =
1587                                     IGA1_VER_BLANK_END_FORMULA
1588                                     (device_timing.ver_blank_start,
1589                                      device_timing.ver_blank_end);
1590                                 viafb_load_reg_num =
1591                                     iga1_crtc_reg.ver_blank_end.reg_num;
1592                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1593                                 break;
1594                         case V_SYNC_START_INDEX:
1595                                 reg_value =
1596                                     IGA1_VER_SYNC_START_FORMULA
1597                                     (device_timing.ver_sync_start);
1598                                 viafb_load_reg_num =
1599                                     iga1_crtc_reg.ver_sync_start.reg_num;
1600                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1601                                 break;
1602                         case V_SYNC_END_INDEX:
1603                                 reg_value =
1604                                     IGA1_VER_SYNC_END_FORMULA
1605                                     (device_timing.ver_sync_start,
1606                                      device_timing.ver_sync_end);
1607                                 viafb_load_reg_num =
1608                                     iga1_crtc_reg.ver_sync_end.reg_num;
1609                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1610                                 break;
1611
1612                         }
1613                 }
1614
1615                 if (set_iga == IGA2) {
1616                         switch (i) {
1617                         case H_TOTAL_INDEX:
1618                                 reg_value =
1619                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1620                                                            hor_total);
1621                                 viafb_load_reg_num =
1622                                         iga2_crtc_reg.hor_total.reg_num;
1623                                 reg = iga2_crtc_reg.hor_total.reg;
1624                                 break;
1625                         case H_ADDR_INDEX:
1626                                 reg_value =
1627                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1628                                                           hor_addr);
1629                                 viafb_load_reg_num =
1630                                         iga2_crtc_reg.hor_addr.reg_num;
1631                                 reg = iga2_crtc_reg.hor_addr.reg;
1632                                 break;
1633                         case H_BLANK_START_INDEX:
1634                                 reg_value =
1635                                     IGA2_HOR_BLANK_START_FORMULA
1636                                     (device_timing.hor_blank_start);
1637                                 viafb_load_reg_num =
1638                                     iga2_crtc_reg.hor_blank_start.reg_num;
1639                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1640                                 break;
1641                         case H_BLANK_END_INDEX:
1642                                 reg_value =
1643                                     IGA2_HOR_BLANK_END_FORMULA
1644                                     (device_timing.hor_blank_start,
1645                                      device_timing.hor_blank_end);
1646                                 viafb_load_reg_num =
1647                                     iga2_crtc_reg.hor_blank_end.reg_num;
1648                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1649                                 break;
1650                         case H_SYNC_START_INDEX:
1651                                 reg_value =
1652                                     IGA2_HOR_SYNC_START_FORMULA
1653                                     (device_timing.hor_sync_start);
1654                                 if (UNICHROME_CN700 <=
1655                                         viaparinfo->chip_info->gfx_chip_name)
1656                                         viafb_load_reg_num =
1657                                             iga2_crtc_reg.hor_sync_start.
1658                                             reg_num;
1659                                 else
1660                                         viafb_load_reg_num = 3;
1661                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1662                                 break;
1663                         case H_SYNC_END_INDEX:
1664                                 reg_value =
1665                                     IGA2_HOR_SYNC_END_FORMULA
1666                                     (device_timing.hor_sync_start,
1667                                      device_timing.hor_sync_end);
1668                                 viafb_load_reg_num =
1669                                     iga2_crtc_reg.hor_sync_end.reg_num;
1670                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1671                                 break;
1672                         case V_TOTAL_INDEX:
1673                                 reg_value =
1674                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1675                                                            ver_total);
1676                                 viafb_load_reg_num =
1677                                         iga2_crtc_reg.ver_total.reg_num;
1678                                 reg = iga2_crtc_reg.ver_total.reg;
1679                                 break;
1680                         case V_ADDR_INDEX:
1681                                 reg_value =
1682                                     IGA2_VER_ADDR_FORMULA(device_timing.
1683                                                           ver_addr);
1684                                 viafb_load_reg_num =
1685                                         iga2_crtc_reg.ver_addr.reg_num;
1686                                 reg = iga2_crtc_reg.ver_addr.reg;
1687                                 break;
1688                         case V_BLANK_START_INDEX:
1689                                 reg_value =
1690                                     IGA2_VER_BLANK_START_FORMULA
1691                                     (device_timing.ver_blank_start);
1692                                 viafb_load_reg_num =
1693                                     iga2_crtc_reg.ver_blank_start.reg_num;
1694                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1695                                 break;
1696                         case V_BLANK_END_INDEX:
1697                                 reg_value =
1698                                     IGA2_VER_BLANK_END_FORMULA
1699                                     (device_timing.ver_blank_start,
1700                                      device_timing.ver_blank_end);
1701                                 viafb_load_reg_num =
1702                                     iga2_crtc_reg.ver_blank_end.reg_num;
1703                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1704                                 break;
1705                         case V_SYNC_START_INDEX:
1706                                 reg_value =
1707                                     IGA2_VER_SYNC_START_FORMULA
1708                                     (device_timing.ver_sync_start);
1709                                 viafb_load_reg_num =
1710                                     iga2_crtc_reg.ver_sync_start.reg_num;
1711                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1712                                 break;
1713                         case V_SYNC_END_INDEX:
1714                                 reg_value =
1715                                     IGA2_VER_SYNC_END_FORMULA
1716                                     (device_timing.ver_sync_start,
1717                                      device_timing.ver_sync_end);
1718                                 viafb_load_reg_num =
1719                                     iga2_crtc_reg.ver_sync_end.reg_num;
1720                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1721                                 break;
1722
1723                         }
1724                 }
1725                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1726         }
1727
1728         viafb_lock_crt();
1729 }
1730
1731 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1732         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1733 {
1734         struct display_timing crt_reg;
1735         int i;
1736         int index = 0;
1737         int h_addr, v_addr;
1738         u32 clock, refresh = viafb_refresh;
1739
1740         if (viafb_SAMM_ON && set_iga == IGA2)
1741                 refresh = viafb_refresh1;
1742
1743         for (i = 0; i < video_mode->mode_array; i++) {
1744                 index = i;
1745
1746                 if (crt_table[i].refresh_rate == refresh)
1747                         break;
1748         }
1749
1750         crt_reg = crt_table[index].crtc;
1751
1752         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1753         /* So we would delete border. */
1754         if ((viafb_LCD_ON | viafb_DVI_ON)
1755             && video_mode->crtc[0].crtc.hor_addr == 640
1756             && video_mode->crtc[0].crtc.ver_addr == 480
1757             && refresh == 60) {
1758                 /* The border is 8 pixels. */
1759                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1760
1761                 /* Blanking time should add left and right borders. */
1762                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1763         }
1764
1765         h_addr = crt_reg.hor_addr;
1766         v_addr = crt_reg.ver_addr;
1767         if (set_iga == IGA1) {
1768                 viafb_unlock_crt();
1769                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1770                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1771                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1772         }
1773
1774         switch (set_iga) {
1775         case IGA1:
1776                 viafb_load_crtc_timing(crt_reg, IGA1);
1777                 break;
1778         case IGA2:
1779                 viafb_load_crtc_timing(crt_reg, IGA2);
1780                 break;
1781         }
1782
1783         load_fix_bit_crtc_reg();
1784         viafb_lock_crt();
1785         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1786         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1787
1788         /* load FIFO */
1789         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1790             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1791                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1792
1793         clock = crt_reg.hor_total * crt_reg.ver_total
1794                 * crt_table[index].refresh_rate;
1795         viafb_set_vclock(clock, set_iga);
1796
1797 }
1798
1799 void __devinit viafb_init_chip_info(int chip_type)
1800 {
1801         via_clock_init(&clock, chip_type);
1802         init_gfx_chip_info(chip_type);
1803         init_tmds_chip_info();
1804         init_lvds_chip_info();
1805
1806         viaparinfo->crt_setting_info->iga_path = IGA1;
1807
1808         /*Set IGA path for each device */
1809         viafb_set_iga_path();
1810
1811         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1812         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1813         viaparinfo->lvds_setting_info2->display_method =
1814                 viaparinfo->lvds_setting_info->display_method;
1815         viaparinfo->lvds_setting_info2->lcd_mode =
1816                 viaparinfo->lvds_setting_info->lcd_mode;
1817 }
1818
1819 void viafb_update_device_setting(int hres, int vres, int bpp, int flag)
1820 {
1821         if (flag == 0) {
1822                 viaparinfo->tmds_setting_info->h_active = hres;
1823                 viaparinfo->tmds_setting_info->v_active = vres;
1824
1825                 viaparinfo->lvds_setting_info->h_active = hres;
1826                 viaparinfo->lvds_setting_info->v_active = vres;
1827                 viaparinfo->lvds_setting_info->bpp = bpp;
1828                 viaparinfo->lvds_setting_info2->h_active = hres;
1829                 viaparinfo->lvds_setting_info2->v_active = vres;
1830                 viaparinfo->lvds_setting_info2->bpp = bpp;
1831         } else {
1832
1833                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1834                         viaparinfo->tmds_setting_info->h_active = hres;
1835                         viaparinfo->tmds_setting_info->v_active = vres;
1836                 }
1837
1838                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1839                         viaparinfo->lvds_setting_info->h_active = hres;
1840                         viaparinfo->lvds_setting_info->v_active = vres;
1841                         viaparinfo->lvds_setting_info->bpp = bpp;
1842                 }
1843                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1844                         viaparinfo->lvds_setting_info2->h_active = hres;
1845                         viaparinfo->lvds_setting_info2->v_active = vres;
1846                         viaparinfo->lvds_setting_info2->bpp = bpp;
1847                 }
1848         }
1849 }
1850
1851 static void __devinit init_gfx_chip_info(int chip_type)
1852 {
1853         u8 tmp;
1854
1855         viaparinfo->chip_info->gfx_chip_name = chip_type;
1856
1857         /* Check revision of CLE266 Chip */
1858         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1859                 /* CR4F only define in CLE266.CX chip */
1860                 tmp = viafb_read_reg(VIACR, CR4F);
1861                 viafb_write_reg(CR4F, VIACR, 0x55);
1862                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1863                         viaparinfo->chip_info->gfx_chip_revision =
1864                         CLE266_REVISION_AX;
1865                 else
1866                         viaparinfo->chip_info->gfx_chip_revision =
1867                         CLE266_REVISION_CX;
1868                 /* restore orignal CR4F value */
1869                 viafb_write_reg(CR4F, VIACR, tmp);
1870         }
1871
1872         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1873                 tmp = viafb_read_reg(VIASR, SR43);
1874                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1875                 if (tmp & 0x02) {
1876                         viaparinfo->chip_info->gfx_chip_revision =
1877                                 CX700_REVISION_700M2;
1878                 } else if (tmp & 0x40) {
1879                         viaparinfo->chip_info->gfx_chip_revision =
1880                                 CX700_REVISION_700M;
1881                 } else {
1882                         viaparinfo->chip_info->gfx_chip_revision =
1883                                 CX700_REVISION_700;
1884                 }
1885         }
1886
1887         /* Determine which 2D engine we have */
1888         switch (viaparinfo->chip_info->gfx_chip_name) {
1889         case UNICHROME_VX800:
1890         case UNICHROME_VX855:
1891         case UNICHROME_VX900:
1892                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
1893                 break;
1894         case UNICHROME_K8M890:
1895         case UNICHROME_P4M900:
1896                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
1897                 break;
1898         default:
1899                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
1900                 break;
1901         }
1902 }
1903
1904 static void __devinit init_tmds_chip_info(void)
1905 {
1906         viafb_tmds_trasmitter_identify();
1907
1908         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1909                 output_interface) {
1910                 switch (viaparinfo->chip_info->gfx_chip_name) {
1911                 case UNICHROME_CX700:
1912                         {
1913                                 /* we should check support by hardware layout.*/
1914                                 if ((viafb_display_hardware_layout ==
1915                                      HW_LAYOUT_DVI_ONLY)
1916                                     || (viafb_display_hardware_layout ==
1917                                         HW_LAYOUT_LCD_DVI)) {
1918                                         viaparinfo->chip_info->tmds_chip_info.
1919                                             output_interface = INTERFACE_TMDS;
1920                                 } else {
1921                                         viaparinfo->chip_info->tmds_chip_info.
1922                                                 output_interface =
1923                                                 INTERFACE_NONE;
1924                                 }
1925                                 break;
1926                         }
1927                 case UNICHROME_K8M890:
1928                 case UNICHROME_P4M900:
1929                 case UNICHROME_P4M890:
1930                         /* TMDS on PCIE, we set DFPLOW as default. */
1931                         viaparinfo->chip_info->tmds_chip_info.output_interface =
1932                             INTERFACE_DFP_LOW;
1933                         break;
1934                 default:
1935                         {
1936                                 /* set DVP1 default for DVI */
1937                                 viaparinfo->chip_info->tmds_chip_info
1938                                 .output_interface = INTERFACE_DVP1;
1939                         }
1940                 }
1941         }
1942
1943         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
1944                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
1945         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
1946                 &viaparinfo->shared->tmds_setting_info);
1947 }
1948
1949 static void __devinit init_lvds_chip_info(void)
1950 {
1951         viafb_lvds_trasmitter_identify();
1952         viafb_init_lcd_size();
1953         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
1954                                    viaparinfo->lvds_setting_info);
1955         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
1956                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
1957                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
1958         }
1959         /*If CX700,two singel LCD, we need to reassign
1960            LCD interface to different LVDS port */
1961         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
1962             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
1963                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
1964                         lvds_chip_name) && (INTEGRATED_LVDS ==
1965                         viaparinfo->chip_info->
1966                         lvds_chip_info2.lvds_chip_name)) {
1967                         viaparinfo->chip_info->lvds_chip_info.output_interface =
1968                                 INTERFACE_LVDS0;
1969                         viaparinfo->chip_info->lvds_chip_info2.
1970                                 output_interface =
1971                             INTERFACE_LVDS1;
1972                 }
1973         }
1974
1975         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
1976                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
1977         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
1978                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1979         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
1980                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1981 }
1982
1983 void __devinit viafb_init_dac(int set_iga)
1984 {
1985         int i;
1986         u8 tmp;
1987
1988         if (set_iga == IGA1) {
1989                 /* access Primary Display's LUT */
1990                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
1991                 /* turn off LCK */
1992                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
1993                 for (i = 0; i < 256; i++) {
1994                         write_dac_reg(i, palLUT_table[i].red,
1995                                       palLUT_table[i].green,
1996                                       palLUT_table[i].blue);
1997                 }
1998                 /* turn on LCK */
1999                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2000         } else {
2001                 tmp = viafb_read_reg(VIACR, CR6A);
2002                 /* access Secondary Display's LUT */
2003                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2004                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2005                 for (i = 0; i < 256; i++) {
2006                         write_dac_reg(i, palLUT_table[i].red,
2007                                       palLUT_table[i].green,
2008                                       palLUT_table[i].blue);
2009                 }
2010                 /* set IGA1 DAC for default */
2011                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2012                 viafb_write_reg(CR6A, VIACR, tmp);
2013         }
2014 }
2015
2016 static void device_screen_off(void)
2017 {
2018         /* turn off CRT screen (IGA1) */
2019         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2020 }
2021
2022 static void device_screen_on(void)
2023 {
2024         /* turn on CRT screen (IGA1) */
2025         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2026 }
2027
2028 static void set_display_channel(void)
2029 {
2030         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2031         is keeped on lvds_setting_info2 */
2032         if (viafb_LCD2_ON &&
2033                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2034                 /* For dual channel LCD: */
2035                 /* Set to Dual LVDS channel. */
2036                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2037         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2038                 /* For LCD+DFP: */
2039                 /* Set to LVDS1 + TMDS channel. */
2040                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2041         } else if (viafb_DVI_ON) {
2042                 /* Set to single TMDS channel. */
2043                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2044         } else if (viafb_LCD_ON) {
2045                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2046                         /* For dual channel LCD: */
2047                         /* Set to Dual LVDS channel. */
2048                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2049                 } else {
2050                         /* Set to LVDS0 + LVDS1 channel. */
2051                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2052                 }
2053         }
2054 }
2055
2056 static u8 get_sync(struct fb_info *info)
2057 {
2058         u8 polarity = 0;
2059
2060         if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
2061                 polarity |= VIA_HSYNC_NEGATIVE;
2062         if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
2063                 polarity |= VIA_VSYNC_NEGATIVE;
2064         return polarity;
2065 }
2066
2067 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2068         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2069 {
2070         int i, j;
2071         int port;
2072         u32 devices = viaparinfo->shared->iga1_devices
2073                 | viaparinfo->shared->iga2_devices;
2074         u8 value, index, mask;
2075         struct crt_mode_table *crt_timing;
2076         struct crt_mode_table *crt_timing1 = NULL;
2077
2078         device_screen_off();
2079         crt_timing = vmode_tbl->crtc;
2080
2081         if (viafb_SAMM_ON == 1) {
2082                 crt_timing1 = vmode_tbl1->crtc;
2083         }
2084
2085         inb(VIAStatus);
2086         outb(0x00, VIAAR);
2087
2088         /* Write Common Setting for Video Mode */
2089         switch (viaparinfo->chip_info->gfx_chip_name) {
2090         case UNICHROME_CLE266:
2091                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2092                 break;
2093
2094         case UNICHROME_K400:
2095                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2096                 break;
2097
2098         case UNICHROME_K800:
2099         case UNICHROME_PM800:
2100                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2101                 break;
2102
2103         case UNICHROME_CN700:
2104         case UNICHROME_K8M890:
2105         case UNICHROME_P4M890:
2106         case UNICHROME_P4M900:
2107                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2108                 break;
2109
2110         case UNICHROME_CX700:
2111         case UNICHROME_VX800:
2112                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2113                 break;
2114
2115         case UNICHROME_VX855:
2116         case UNICHROME_VX900:
2117                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2118                 break;
2119         }
2120
2121         viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
2122         device_off();
2123         via_set_state(devices, VIA_STATE_OFF);
2124
2125         /* Fill VPIT Parameters */
2126         /* Write Misc Register */
2127         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2128
2129         /* Write Sequencer */
2130         for (i = 1; i <= StdSR; i++)
2131                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2132
2133         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2134
2135         /* Write CRTC */
2136         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2137
2138         /* Write Graphic Controller */
2139         for (i = 0; i < StdGR; i++)
2140                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2141
2142         /* Write Attribute Controller */
2143         for (i = 0; i < StdAR; i++) {
2144                 inb(VIAStatus);
2145                 outb(i, VIAAR);
2146                 outb(VPIT.AR[i], VIAAR);
2147         }
2148
2149         inb(VIAStatus);
2150         outb(0x20, VIAAR);
2151
2152         /* Update Patch Register */
2153
2154         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2155             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2156             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2157             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2158                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2159                         index = res_patch_table[0].io_reg_table[j].index;
2160                         port = res_patch_table[0].io_reg_table[j].port;
2161                         value = res_patch_table[0].io_reg_table[j].value;
2162                         mask = res_patch_table[0].io_reg_table[j].mask;
2163                         viafb_write_reg_mask(index, port, value, mask);
2164                 }
2165         }
2166
2167         via_set_primary_pitch(viafbinfo->fix.line_length);
2168         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2169                 : viafbinfo->fix.line_length);
2170         via_set_primary_color_depth(viaparinfo->depth);
2171         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2172                 : viaparinfo->depth);
2173         via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2174         via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2175         if (viaparinfo->shared->iga2_devices)
2176                 enable_second_display_channel();
2177         else
2178                 disable_second_display_channel();
2179
2180         /* Update Refresh Rate Setting */
2181
2182         /* Clear On Screen */
2183
2184         /* CRT set mode */
2185         if (viafb_CRT_ON) {
2186                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2187                         IGA2)) {
2188                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2189                                 video_bpp1 / 8,
2190                                 viaparinfo->crt_setting_info->iga_path);
2191                 } else {
2192                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2193                                 video_bpp / 8,
2194                                 viaparinfo->crt_setting_info->iga_path);
2195                 }
2196
2197                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2198                 to 8 alignment (1368),there is several pixels (2 pixels)
2199                 on right side of screen. */
2200                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2201                         viafb_unlock_crt();
2202                         viafb_write_reg(CR02, VIACR,
2203                                 viafb_read_reg(VIACR, CR02) - 1);
2204                         viafb_lock_crt();
2205                 }
2206         }
2207
2208         if (viafb_DVI_ON) {
2209                 if (viafb_SAMM_ON &&
2210                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2211                         viafb_dvi_set_mode(viafb_get_mode
2212                                      (viaparinfo->tmds_setting_info->h_active,
2213                                       viaparinfo->tmds_setting_info->
2214                                       v_active),
2215                                      video_bpp1, viaparinfo->
2216                                      tmds_setting_info->iga_path);
2217                 } else {
2218                         viafb_dvi_set_mode(viafb_get_mode
2219                                      (viaparinfo->tmds_setting_info->h_active,
2220                                       viaparinfo->
2221                                       tmds_setting_info->v_active),
2222                                      video_bpp, viaparinfo->
2223                                      tmds_setting_info->iga_path);
2224                 }
2225         }
2226
2227         if (viafb_LCD_ON) {
2228                 if (viafb_SAMM_ON &&
2229                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2230                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2231                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2232                                 lvds_setting_info,
2233                                      &viaparinfo->chip_info->lvds_chip_info);
2234                 } else {
2235                         /* IGA1 doesn't have LCD scaling, so set it center. */
2236                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2237                                 viaparinfo->lvds_setting_info->display_method =
2238                                     LCD_CENTERING;
2239                         }
2240                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2241                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2242                                 lvds_setting_info,
2243                                      &viaparinfo->chip_info->lvds_chip_info);
2244                 }
2245         }
2246         if (viafb_LCD2_ON) {
2247                 if (viafb_SAMM_ON &&
2248                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2249                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2250                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2251                                 lvds_setting_info2,
2252                                      &viaparinfo->chip_info->lvds_chip_info2);
2253                 } else {
2254                         /* IGA1 doesn't have LCD scaling, so set it center. */
2255                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2256                                 viaparinfo->lvds_setting_info2->display_method =
2257                                     LCD_CENTERING;
2258                         }
2259                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2260                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2261                                 lvds_setting_info2,
2262                                      &viaparinfo->chip_info->lvds_chip_info2);
2263                 }
2264         }
2265
2266         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2267             && (viafb_LCD_ON || viafb_DVI_ON))
2268                 set_display_channel();
2269
2270         /* If set mode normally, save resolution information for hot-plug . */
2271         if (!viafb_hotplug) {
2272                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2273                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2274                 viafb_hotplug_bpp = video_bpp;
2275                 viafb_hotplug_refresh = viafb_refresh;
2276
2277                 if (viafb_DVI_ON)
2278                         viafb_DeviceStatus = DVI_Device;
2279                 else
2280                         viafb_DeviceStatus = CRT_Device;
2281         }
2282         device_on();
2283         if (!viafb_dual_fb)
2284                 via_set_sync_polarity(devices, get_sync(viafbinfo));
2285         else {
2286                 via_set_sync_polarity(viaparinfo->shared->iga1_devices,
2287                         get_sync(viafbinfo));
2288                 via_set_sync_polarity(viaparinfo->shared->iga2_devices,
2289                         get_sync(viafbinfo1));
2290         }
2291
2292         clock.set_engine_pll_state(VIA_STATE_ON);
2293         clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
2294         clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
2295
2296 #ifdef CONFIG_FB_VIA_X_COMPATIBILITY
2297         clock.set_primary_pll_state(VIA_STATE_ON);
2298         clock.set_primary_clock_state(VIA_STATE_ON);
2299         clock.set_secondary_pll_state(VIA_STATE_ON);
2300         clock.set_secondary_clock_state(VIA_STATE_ON);
2301 #else
2302         if (viaparinfo->shared->iga1_devices) {
2303                 clock.set_primary_pll_state(VIA_STATE_ON);
2304                 clock.set_primary_clock_state(VIA_STATE_ON);
2305         } else {
2306                 clock.set_primary_pll_state(VIA_STATE_OFF);
2307                 clock.set_primary_clock_state(VIA_STATE_OFF);
2308         }
2309
2310         if (viaparinfo->shared->iga2_devices) {
2311                 clock.set_secondary_pll_state(VIA_STATE_ON);
2312                 clock.set_secondary_clock_state(VIA_STATE_ON);
2313         } else {
2314                 clock.set_secondary_pll_state(VIA_STATE_OFF);
2315                 clock.set_secondary_clock_state(VIA_STATE_OFF);
2316         }
2317 #endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
2318
2319         via_set_state(devices, VIA_STATE_ON);
2320         device_screen_on();
2321         return 1;
2322 }
2323
2324 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2325 {
2326         int i;
2327         struct crt_mode_table *best;
2328         struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2329
2330         if (!vmode)
2331                 return RES_640X480_60HZ_PIXCLOCK;
2332
2333         best = &vmode->crtc[0];
2334         for (i = 1; i < vmode->mode_array; i++) {
2335                 if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
2336                         < abs(best->refresh_rate - vmode_refresh))
2337                         best = &vmode->crtc[i];
2338         }
2339
2340         return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
2341                 * 1000 / best->refresh_rate;
2342 }
2343
2344 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2345 {
2346         int i;
2347         struct crt_mode_table *best;
2348         struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2349
2350         if (!vmode)
2351                 return 60;
2352
2353         best = &vmode->crtc[0];
2354         for (i = 1; i < vmode->mode_array; i++) {
2355                 if (abs(vmode->crtc[i].refresh_rate - long_refresh)
2356                         < abs(best->refresh_rate - long_refresh))
2357                         best = &vmode->crtc[i];
2358         }
2359
2360         if (abs(best->refresh_rate - long_refresh) > 3)
2361                 return 60;
2362
2363         return best->refresh_rate;
2364 }
2365
2366 static void device_off(void)
2367 {
2368         viafb_dvi_disable();
2369         viafb_lcd_disable();
2370 }
2371
2372 static void device_on(void)
2373 {
2374         if (viafb_DVI_ON == 1)
2375                 viafb_dvi_enable();
2376         if (viafb_LCD_ON == 1)
2377                 viafb_lcd_enable();
2378 }
2379
2380 static void enable_second_display_channel(void)
2381 {
2382         /* to enable second display channel. */
2383         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2384         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2385         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2386 }
2387
2388 static void disable_second_display_channel(void)
2389 {
2390         /* to disable second display channel. */
2391         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2392         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2393         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2394 }
2395
2396 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2397                                         *p_gfx_dpa_setting)
2398 {
2399         switch (output_interface) {
2400         case INTERFACE_DVP0:
2401                 {
2402                         /* DVP0 Clock Polarity and Adjust: */
2403                         viafb_write_reg_mask(CR96, VIACR,
2404                                        p_gfx_dpa_setting->DVP0, 0x0F);
2405
2406                         /* DVP0 Clock and Data Pads Driving: */
2407                         viafb_write_reg_mask(SR1E, VIASR,
2408                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2409                         viafb_write_reg_mask(SR2A, VIASR,
2410                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2411                                        BIT4);
2412                         viafb_write_reg_mask(SR1B, VIASR,
2413                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2414                         viafb_write_reg_mask(SR2A, VIASR,
2415                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2416                         break;
2417                 }
2418
2419         case INTERFACE_DVP1:
2420                 {
2421                         /* DVP1 Clock Polarity and Adjust: */
2422                         viafb_write_reg_mask(CR9B, VIACR,
2423                                        p_gfx_dpa_setting->DVP1, 0x0F);
2424
2425                         /* DVP1 Clock and Data Pads Driving: */
2426                         viafb_write_reg_mask(SR65, VIASR,
2427                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2428                         break;
2429                 }
2430
2431         case INTERFACE_DFP_HIGH:
2432                 {
2433                         viafb_write_reg_mask(CR97, VIACR,
2434                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2435                         break;
2436                 }
2437
2438         case INTERFACE_DFP_LOW:
2439                 {
2440                         viafb_write_reg_mask(CR99, VIACR,
2441                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2442                         break;
2443                 }
2444
2445         case INTERFACE_DFP:
2446                 {
2447                         viafb_write_reg_mask(CR97, VIACR,
2448                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2449                         viafb_write_reg_mask(CR99, VIACR,
2450                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2451                         break;
2452                 }
2453         }
2454 }
2455
2456 /*According var's xres, yres fill var's other timing information*/
2457 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2458         struct VideoModeTable *vmode_tbl)
2459 {
2460         struct crt_mode_table *crt_timing = NULL;
2461         struct display_timing crt_reg;
2462         int i = 0, index = 0;
2463         crt_timing = vmode_tbl->crtc;
2464         for (i = 0; i < vmode_tbl->mode_array; i++) {
2465                 index = i;
2466                 if (crt_timing[i].refresh_rate == refresh)
2467                         break;
2468         }
2469
2470         crt_reg = crt_timing[index].crtc;
2471         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2472         var->left_margin =
2473             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2474         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2475         var->hsync_len = crt_reg.hor_sync_end;
2476         var->upper_margin =
2477             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2478         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2479         var->vsync_len = crt_reg.ver_sync_end;
2480         var->sync = 0;
2481         if (crt_timing[index].h_sync_polarity == POSITIVE)
2482                 var->sync |= FB_SYNC_HOR_HIGH_ACT;
2483         if (crt_timing[index].v_sync_polarity == POSITIVE)
2484                 var->sync |= FB_SYNC_VERT_HIGH_ACT;
2485 }