drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h

   1 /*
   2  * ti_hdmi_4xxx_ip.h
   3  *
   4  * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
   5  *
   6  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef _HDMI_TI_4xxx_H_
  22 #define _HDMI_TI_4xxx_H_
  23
  24 #include <linux/string.h>
  25 #include <video/omapdss.h>
  26 #include "ti_hdmi.h"
  27
  28 struct hdmi_reg { u16 idx; };
  29
  30 #define HDMI_REG(idx)                   ((const struct hdmi_reg) { idx })
  31
  32 /* HDMI Wrapper */
  33
  34 #define HDMI_WP_REVISION                        HDMI_REG(0x0)
  35 #define HDMI_WP_SYSCONFIG                       HDMI_REG(0x10)
  36 #define HDMI_WP_IRQSTATUS_RAW                   HDMI_REG(0x24)
  37 #define HDMI_WP_IRQSTATUS                       HDMI_REG(0x28)
  38 #define HDMI_WP_PWR_CTRL                        HDMI_REG(0x40)
  39 #define HDMI_WP_IRQENABLE_SET                   HDMI_REG(0x2C)
  40 #define HDMI_WP_VIDEO_CFG                       HDMI_REG(0x50)
  41 #define HDMI_WP_VIDEO_SIZE                      HDMI_REG(0x60)
  42 #define HDMI_WP_VIDEO_TIMING_H                  HDMI_REG(0x68)
  43 #define HDMI_WP_VIDEO_TIMING_V                  HDMI_REG(0x6C)
  44 #define HDMI_WP_WP_CLK                          HDMI_REG(0x70)
  45 #define HDMI_WP_AUDIO_CFG                       HDMI_REG(0x80)
  46 #define HDMI_WP_AUDIO_CFG2                      HDMI_REG(0x84)
  47 #define HDMI_WP_AUDIO_CTRL                      HDMI_REG(0x88)
  48 #define HDMI_WP_AUDIO_DATA                      HDMI_REG(0x8C)
  49
  50 /* HDMI IP Core System */
  51
  52 #define HDMI_CORE_SYS_VND_IDL                   HDMI_REG(0x0)
  53 #define HDMI_CORE_SYS_DEV_IDL                   HDMI_REG(0x8)
  54 #define HDMI_CORE_SYS_DEV_IDH                   HDMI_REG(0xC)
  55 #define HDMI_CORE_SYS_DEV_REV                   HDMI_REG(0x10)
  56 #define HDMI_CORE_SYS_SRST                      HDMI_REG(0x14)
  57 #define HDMI_CORE_CTRL1                         HDMI_REG(0x20)
  58 #define HDMI_CORE_SYS_SYS_STAT                  HDMI_REG(0x24)
  59 #define HDMI_CORE_SYS_VID_ACEN                  HDMI_REG(0x124)
  60 #define HDMI_CORE_SYS_VID_MODE                  HDMI_REG(0x128)
  61 #define HDMI_CORE_SYS_INTR_STATE                HDMI_REG(0x1C0)
  62 #define HDMI_CORE_SYS_INTR1                     HDMI_REG(0x1C4)
  63 #define HDMI_CORE_SYS_INTR2                     HDMI_REG(0x1C8)
  64 #define HDMI_CORE_SYS_INTR3                     HDMI_REG(0x1CC)
  65 #define HDMI_CORE_SYS_INTR4                     HDMI_REG(0x1D0)
  66 #define HDMI_CORE_SYS_UMASK1                    HDMI_REG(0x1D4)
  67 #define HDMI_CORE_SYS_TMDS_CTRL                 HDMI_REG(0x208)
  68 #define HDMI_CORE_SYS_DE_DLY                    HDMI_REG(0xC8)
  69 #define HDMI_CORE_SYS_DE_CTRL                   HDMI_REG(0xCC)
  70 #define HDMI_CORE_SYS_DE_TOP                    HDMI_REG(0xD0)
  71 #define HDMI_CORE_SYS_DE_CNTL                   HDMI_REG(0xD8)
  72 #define HDMI_CORE_SYS_DE_CNTH                   HDMI_REG(0xDC)
  73 #define HDMI_CORE_SYS_DE_LINL                   HDMI_REG(0xE0)
  74 #define HDMI_CORE_SYS_DE_LINH_1                 HDMI_REG(0xE4)
  75 #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
  76 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
  77 #define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
  78 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
  79
  80 /* HDMI DDC E-DID */
  81 #define HDMI_CORE_DDC_CMD                       HDMI_REG(0x3CC)
  82 #define HDMI_CORE_DDC_STATUS                    HDMI_REG(0x3C8)
  83 #define HDMI_CORE_DDC_ADDR                      HDMI_REG(0x3B4)
  84 #define HDMI_CORE_DDC_OFFSET                    HDMI_REG(0x3BC)
  85 #define HDMI_CORE_DDC_COUNT1                    HDMI_REG(0x3C0)
  86 #define HDMI_CORE_DDC_COUNT2                    HDMI_REG(0x3C4)
  87 #define HDMI_CORE_DDC_DATA                      HDMI_REG(0x3D0)
  88 #define HDMI_CORE_DDC_SEGM                      HDMI_REG(0x3B8)
  89
  90 /* HDMI IP Core Audio Video */
  91
  92 #define HDMI_CORE_AV_HDMI_CTRL                  HDMI_REG(0xBC)
  93 #define HDMI_CORE_AV_DPD                        HDMI_REG(0xF4)
  94 #define HDMI_CORE_AV_PB_CTRL1                   HDMI_REG(0xF8)
  95 #define HDMI_CORE_AV_PB_CTRL2                   HDMI_REG(0xFC)
  96 #define HDMI_CORE_AV_AVI_TYPE                   HDMI_REG(0x100)
  97 #define HDMI_CORE_AV_AVI_VERS                   HDMI_REG(0x104)
  98 #define HDMI_CORE_AV_AVI_LEN                    HDMI_REG(0x108)
  99 #define HDMI_CORE_AV_AVI_CHSUM                  HDMI_REG(0x10C)
 100 #define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_REG(n * 4 + 0x110)
 101 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_REG(15)
 102 #define HDMI_CORE_AV_SPD_DBYTE                  HDMI_REG(0x190)
 103 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_REG(27)
 104 #define HDMI_CORE_AV_AUD_DBYTE(n)               HDMI_REG(n * 4 + 0x210)
 105 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS           HDMI_REG(10)
 106 #define HDMI_CORE_AV_MPEG_DBYTE                 HDMI_REG(0x290)
 107 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_REG(27)
 108 #define HDMI_CORE_AV_GEN_DBYTE                  HDMI_REG(0x300)
 109 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_REG(31)
 110 #define HDMI_CORE_AV_GEN2_DBYTE                 HDMI_REG(0x380)
 111 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_REG(31)
 112 #define HDMI_CORE_AV_ACR_CTRL                   HDMI_REG(0x4)
 113 #define HDMI_CORE_AV_FREQ_SVAL                  HDMI_REG(0x8)
 114 #define HDMI_CORE_AV_N_SVAL1                    HDMI_REG(0xC)
 115 #define HDMI_CORE_AV_N_SVAL2                    HDMI_REG(0x10)
 116 #define HDMI_CORE_AV_N_SVAL3                    HDMI_REG(0x14)
 117 #define HDMI_CORE_AV_CTS_SVAL1                  HDMI_REG(0x18)
 118 #define HDMI_CORE_AV_CTS_SVAL2                  HDMI_REG(0x1C)
 119 #define HDMI_CORE_AV_CTS_SVAL3                  HDMI_REG(0x20)
 120 #define HDMI_CORE_AV_CTS_HVAL1                  HDMI_REG(0x24)
 121 #define HDMI_CORE_AV_CTS_HVAL2                  HDMI_REG(0x28)
 122 #define HDMI_CORE_AV_CTS_HVAL3                  HDMI_REG(0x2C)
 123 #define HDMI_CORE_AV_AUD_MODE                   HDMI_REG(0x50)
 124 #define HDMI_CORE_AV_SPDIF_CTRL                 HDMI_REG(0x54)
 125 #define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_REG(0x60)
 126 #define HDMI_CORE_AV_SWAP_I2S                   HDMI_REG(0x64)
 127 #define HDMI_CORE_AV_SPDIF_ERTH                 HDMI_REG(0x6C)
 128 #define HDMI_CORE_AV_I2S_IN_MAP                 HDMI_REG(0x70)
 129 #define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_REG(0x74)
 130 #define HDMI_CORE_AV_I2S_CHST0                  HDMI_REG(0x78)
 131 #define HDMI_CORE_AV_I2S_CHST1                  HDMI_REG(0x7C)
 132 #define HDMI_CORE_AV_I2S_CHST2                  HDMI_REG(0x80)
 133 #define HDMI_CORE_AV_I2S_CHST4                  HDMI_REG(0x84)
 134 #define HDMI_CORE_AV_I2S_CHST5                  HDMI_REG(0x88)
 135 #define HDMI_CORE_AV_ASRC                       HDMI_REG(0x8C)
 136 #define HDMI_CORE_AV_I2S_IN_LEN                 HDMI_REG(0x90)
 137 #define HDMI_CORE_AV_HDMI_CTRL                  HDMI_REG(0xBC)
 138 #define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_REG(0xC0)
 139 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_REG(0xCC)
 140 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_REG(0xD0)
 141 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_REG(0xD4)
 142 #define HDMI_CORE_AV_TEST_TXCTRL                HDMI_REG(0xF0)
 143 #define HDMI_CORE_AV_DPD                        HDMI_REG(0xF4)
 144 #define HDMI_CORE_AV_PB_CTRL1                   HDMI_REG(0xF8)
 145 #define HDMI_CORE_AV_PB_CTRL2                   HDMI_REG(0xFC)
 146 #define HDMI_CORE_AV_AVI_TYPE                   HDMI_REG(0x100)
 147 #define HDMI_CORE_AV_AVI_VERS                   HDMI_REG(0x104)
 148 #define HDMI_CORE_AV_AVI_LEN                    HDMI_REG(0x108)
 149 #define HDMI_CORE_AV_AVI_CHSUM                  HDMI_REG(0x10C)
 150 #define HDMI_CORE_AV_SPD_TYPE                   HDMI_REG(0x180)
 151 #define HDMI_CORE_AV_SPD_VERS                   HDMI_REG(0x184)
 152 #define HDMI_CORE_AV_SPD_LEN                    HDMI_REG(0x188)
 153 #define HDMI_CORE_AV_SPD_CHSUM                  HDMI_REG(0x18C)
 154 #define HDMI_CORE_AV_AUDIO_TYPE                 HDMI_REG(0x200)
 155 #define HDMI_CORE_AV_AUDIO_VERS                 HDMI_REG(0x204)
 156 #define HDMI_CORE_AV_AUDIO_LEN                  HDMI_REG(0x208)
 157 #define HDMI_CORE_AV_AUDIO_CHSUM                HDMI_REG(0x20C)
 158 #define HDMI_CORE_AV_MPEG_TYPE                  HDMI_REG(0x280)
 159 #define HDMI_CORE_AV_MPEG_VERS                  HDMI_REG(0x284)
 160 #define HDMI_CORE_AV_MPEG_LEN                   HDMI_REG(0x288)
 161 #define HDMI_CORE_AV_MPEG_CHSUM                 HDMI_REG(0x28C)
 162 #define HDMI_CORE_AV_CP_BYTE1                   HDMI_REG(0x37C)
 163 #define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_REG(0x3FC)
 164 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
 165 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
 166 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
 167 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
 168
 169 /* PLL */
 170
 171 #define PLLCTRL_PLL_CONTROL                     HDMI_REG(0x0)
 172 #define PLLCTRL_PLL_STATUS                      HDMI_REG(0x4)
 173 #define PLLCTRL_PLL_GO                          HDMI_REG(0x8)
 174 #define PLLCTRL_CFG1                            HDMI_REG(0xC)
 175 #define PLLCTRL_CFG2                            HDMI_REG(0x10)
 176 #define PLLCTRL_CFG3                            HDMI_REG(0x14)
 177 #define PLLCTRL_CFG4                            HDMI_REG(0x20)
 178
 179 /* HDMI PHY */
 180
 181 #define HDMI_TXPHY_TX_CTRL                      HDMI_REG(0x0)
 182 #define HDMI_TXPHY_DIGITAL_CTRL                 HDMI_REG(0x4)
 183 #define HDMI_TXPHY_POWER_CTRL                   HDMI_REG(0x8)
 184 #define HDMI_TXPHY_PAD_CFG_CTRL                 HDMI_REG(0xC)
 185
 186 #define REG_FLD_MOD(base, idx, val, start, end) \
 187         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 188                                                         val, start, end))
 189 #define REG_GET(base, idx, start, end) \
 190         FLD_GET(hdmi_read_reg(base, idx), start, end)
 191
 192 enum hdmi_phy_pwr {
 193         HDMI_PHYPWRCMD_OFF = 0,
 194         HDMI_PHYPWRCMD_LDOON = 1,
 195         HDMI_PHYPWRCMD_TXON = 2
 196 };
 197
 198 enum hdmi_core_inputbus_width {
 199         HDMI_INPUT_8BIT = 0,
 200         HDMI_INPUT_10BIT = 1,
 201         HDMI_INPUT_12BIT = 2
 202 };
 203
 204 enum hdmi_core_dither_trunc {
 205         HDMI_OUTPUTTRUNCATION_8BIT = 0,
 206         HDMI_OUTPUTTRUNCATION_10BIT = 1,
 207         HDMI_OUTPUTTRUNCATION_12BIT = 2,
 208         HDMI_OUTPUTDITHER_8BIT = 3,
 209         HDMI_OUTPUTDITHER_10BIT = 4,
 210         HDMI_OUTPUTDITHER_12BIT = 5
 211 };
 212
 213 enum hdmi_core_deepcolor_ed {
 214         HDMI_DEEPCOLORPACKECTDISABLE = 0,
 215         HDMI_DEEPCOLORPACKECTENABLE = 1
 216 };
 217
 218 enum hdmi_core_packet_mode {
 219         HDMI_PACKETMODERESERVEDVALUE = 0,
 220         HDMI_PACKETMODE24BITPERPIXEL = 4,
 221         HDMI_PACKETMODE30BITPERPIXEL = 5,
 222         HDMI_PACKETMODE36BITPERPIXEL = 6,
 223         HDMI_PACKETMODE48BITPERPIXEL = 7
 224 };
 225
 226 enum hdmi_core_tclkselclkmult {
 227         HDMI_FPLL05IDCK = 0,
 228         HDMI_FPLL10IDCK = 1,
 229         HDMI_FPLL20IDCK = 2,
 230         HDMI_FPLL40IDCK = 3
 231 };
 232
 233 enum hdmi_core_packet_ctrl {
 234         HDMI_PACKETENABLE = 1,
 235         HDMI_PACKETDISABLE = 0,
 236         HDMI_PACKETREPEATON = 1,
 237         HDMI_PACKETREPEATOFF = 0
 238 };
 239
 240 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
 241 enum hdmi_core_infoframe {
 242         HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
 243         HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
 244         HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
 245         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
 246         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
 247         HDMI_INFOFRAME_AVI_DB1B_NO = 0,
 248         HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
 249         HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
 250         HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
 251         HDMI_INFOFRAME_AVI_DB1S_0 = 0,
 252         HDMI_INFOFRAME_AVI_DB1S_1 = 1,
 253         HDMI_INFOFRAME_AVI_DB1S_2 = 2,
 254         HDMI_INFOFRAME_AVI_DB2C_NO = 0,
 255         HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
 256         HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
 257         HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
 258         HDMI_INFOFRAME_AVI_DB2M_NO = 0,
 259         HDMI_INFOFRAME_AVI_DB2M_43 = 1,
 260         HDMI_INFOFRAME_AVI_DB2M_169 = 2,
 261         HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
 262         HDMI_INFOFRAME_AVI_DB2R_43 = 9,
 263         HDMI_INFOFRAME_AVI_DB2R_169 = 10,
 264         HDMI_INFOFRAME_AVI_DB2R_149 = 11,
 265         HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
 266         HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
 267         HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
 268         HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
 269         HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
 270         HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
 271         HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
 272         HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
 273         HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
 274         HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
 275         HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
 276         HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
 277         HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
 278         HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
 279         HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
 280         HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
 281         HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
 282         HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
 283         HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
 284         HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
 285         HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
 286         HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
 287         HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
 288         HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
 289         HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
 290         HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
 291         HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
 292         HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
 293         HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
 294         HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
 295         HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
 296         HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
 297         HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
 298         HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
 299         HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
 300         HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
 301         HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
 302         HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
 303         HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
 304         HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
 305         HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
 306         HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
 307         HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
 308         HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
 309         HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
 310         HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
 311         HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
 312         HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
 313         HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
 314         HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
 315 };
 316
 317 enum hdmi_packing_mode {
 318         HDMI_PACK_10b_RGB_YUV444 = 0,
 319         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 320         HDMI_PACK_20b_YUV422 = 2,
 321         HDMI_PACK_ALREADYPACKED = 7
 322 };
 323
 324 enum hdmi_core_audio_sample_freq {
 325         HDMI_AUDIO_FS_32000 = 0x3,
 326         HDMI_AUDIO_FS_44100 = 0x0,
 327         HDMI_AUDIO_FS_48000 = 0x2,
 328         HDMI_AUDIO_FS_88200 = 0x8,
 329         HDMI_AUDIO_FS_96000 = 0xA,
 330         HDMI_AUDIO_FS_176400 = 0xC,
 331         HDMI_AUDIO_FS_192000 = 0xE,
 332         HDMI_AUDIO_FS_NOT_INDICATED = 0x1
 333 };
 334
 335 enum hdmi_core_audio_layout {
 336         HDMI_AUDIO_LAYOUT_2CH = 0,
 337         HDMI_AUDIO_LAYOUT_8CH = 1
 338 };
 339
 340 enum hdmi_core_cts_mode {
 341         HDMI_AUDIO_CTS_MODE_HW = 0,
 342         HDMI_AUDIO_CTS_MODE_SW = 1
 343 };
 344
 345 enum hdmi_stereo_channels {
 346         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 347         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 348         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 349         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 350         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 351 };
 352
 353 enum hdmi_audio_type {
 354         HDMI_AUDIO_TYPE_LPCM = 0,
 355         HDMI_AUDIO_TYPE_IEC = 1
 356 };
 357
 358 enum hdmi_audio_justify {
 359         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 360         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 361 };
 362
 363 enum hdmi_audio_sample_order {
 364         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 365         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 366 };
 367
 368 enum hdmi_audio_samples_perword {
 369         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 370         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 371 };
 372
 373 enum hdmi_audio_sample_size {
 374         HDMI_AUDIO_SAMPLE_16BITS = 0,
 375         HDMI_AUDIO_SAMPLE_24BITS = 1
 376 };
 377
 378 enum hdmi_audio_transf_mode {
 379         HDMI_AUDIO_TRANSF_DMA = 0,
 380         HDMI_AUDIO_TRANSF_IRQ = 1
 381 };
 382
 383 enum hdmi_audio_blk_strt_end_sig {
 384         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 385         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 386 };
 387
 388 enum hdmi_audio_i2s_config {
 389         HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
 390         HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
 391         HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
 392         HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
 393         HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
 394         HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
 395         HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
 396         HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
 397         HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
 398         HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
 399         HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
 400         HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
 401         HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
 402         HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
 403         HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
 404         HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
 405         HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
 406         HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
 407         HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
 408         HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
 409         HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
 410         HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
 411         HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
 412         HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
 413         HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
 414         HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
 415         HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
 416         HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
 417         HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
 418         HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
 419         HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
 420         HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
 421         HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
 422         HDMI_AUDIO_I2S_SD0_EN = 1,
 423         HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
 424         HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
 425         HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
 426 };
 427
 428 enum hdmi_audio_mclk_mode {
 429         HDMI_AUDIO_MCLK_128FS = 0,
 430         HDMI_AUDIO_MCLK_256FS = 1,
 431         HDMI_AUDIO_MCLK_384FS = 2,
 432         HDMI_AUDIO_MCLK_512FS = 3,
 433         HDMI_AUDIO_MCLK_768FS = 4,
 434         HDMI_AUDIO_MCLK_1024FS = 5,
 435         HDMI_AUDIO_MCLK_1152FS = 6,
 436         HDMI_AUDIO_MCLK_192FS = 7
 437 };
 438
 439 struct hdmi_core_video_config {
 440         enum hdmi_core_inputbus_width   ip_bus_width;
 441         enum hdmi_core_dither_trunc     op_dither_truc;
 442         enum hdmi_core_deepcolor_ed     deep_color_pkt;
 443         enum hdmi_core_packet_mode      pkt_mode;
 444         enum hdmi_core_hdmi_dvi         hdmi_dvi;
 445         enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
 446 };
 447
 448 /*
 449  * Refer to section 8.2 in HDMI 1.3 specification for
 450  * details about infoframe databytes
 451  */
 452 struct hdmi_core_infoframe_avi {
 453         u8      db1_format;
 454                 /* Y0, Y1 rgb,yCbCr */
 455         u8      db1_active_info;
 456                 /* A0  Active information Present */
 457         u8      db1_bar_info_dv;
 458                 /* B0, B1 Bar info data valid */
 459         u8      db1_scan_info;
 460                 /* S0, S1 scan information */
 461         u8      db2_colorimetry;
 462                 /* C0, C1 colorimetry */
 463         u8      db2_aspect_ratio;
 464                 /* M0, M1 Aspect ratio (4:3, 16:9) */
 465         u8      db2_active_fmt_ar;
 466                 /* R0...R3 Active format aspect ratio */
 467         u8      db3_itc;
 468                 /* ITC IT content. */
 469         u8      db3_ec;
 470                 /* EC0, EC1, EC2 Extended colorimetry */
 471         u8      db3_q_range;
 472                 /* Q1, Q0 Quantization range */
 473         u8      db3_nup_scaling;
 474                 /* SC1, SC0 Non-uniform picture scaling */
 475         u8      db4_videocode;
 476                 /* VIC0..6 Video format identification */
 477         u8      db5_pixel_repeat;
 478                 /* PR0..PR3 Pixel repetition factor */
 479         u16     db6_7_line_eoftop;
 480                 /* Line number end of top bar */
 481         u16     db8_9_line_sofbottom;
 482                 /* Line number start of bottom bar */
 483         u16     db10_11_pixel_eofleft;
 484                 /* Pixel number end of left bar */
 485         u16     db12_13_pixel_sofright;
 486                 /* Pixel number start of right bar */
 487 };
 488 /*
 489  * Refer to section 8.2 in HDMI 1.3 specification for
 490  * details about infoframe databytes
 491  */
 492 struct hdmi_core_infoframe_audio {
 493         u8 db1_coding_type;
 494         u8 db1_channel_count;
 495         u8 db2_sample_freq;
 496         u8 db2_sample_size;
 497         u8 db4_channel_alloc;
 498         bool db5_downmix_inh;
 499         u8 db5_lsv;     /* Level shift values for downmix */
 500 };
 501
 502 struct hdmi_core_packet_enable_repeat {
 503         u32     audio_pkt;
 504         u32     audio_pkt_repeat;
 505         u32     avi_infoframe;
 506         u32     avi_infoframe_repeat;
 507         u32     gen_cntrl_pkt;
 508         u32     gen_cntrl_pkt_repeat;
 509         u32     generic_pkt;
 510         u32     generic_pkt_repeat;
 511 };
 512
 513 struct hdmi_video_format {
 514         enum hdmi_packing_mode  packing_mode;
 515         u32                     y_res;  /* Line per panel */
 516         u32                     x_res;  /* pixel per line */
 517 };
 518
 519 struct hdmi_video_interface {
 520         int     vsp;    /* Vsync polarity */
 521         int     hsp;    /* Hsync polarity */
 522         int     interlacing;
 523         int     tm;     /* Timing mode */
 524 };
 525
 526 struct hdmi_audio_format {
 527         enum hdmi_stereo_channels               stereo_channels;
 528         u8                                      active_chnnls_msk;
 529         enum hdmi_audio_type                    type;
 530         enum hdmi_audio_justify                 justification;
 531         enum hdmi_audio_sample_order            sample_order;
 532         enum hdmi_audio_samples_perword         samples_per_word;
 533         enum hdmi_audio_sample_size             sample_size;
 534         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 535 };
 536
 537 struct hdmi_audio_dma {
 538         u8                              transfer_size;
 539         u8                              block_size;
 540         enum hdmi_audio_transf_mode     mode;
 541         u16                             fifo_threshold;
 542 };
 543
 544 struct hdmi_core_audio_i2s_config {
 545         u8 word_max_length;
 546         u8 word_length;
 547         u8 in_length_bits;
 548         u8 justification;
 549         u8 en_high_bitrate_aud;
 550         u8 sck_edge_mode;
 551         u8 cbit_order;
 552         u8 vbit;
 553         u8 ws_polarity;
 554         u8 direction;
 555         u8 shift;
 556         u8 active_sds;
 557 };
 558
 559 struct hdmi_core_audio_config {
 560         struct hdmi_core_audio_i2s_config       i2s_cfg;
 561         enum hdmi_core_audio_sample_freq        freq_sample;
 562         bool                                    fs_override;
 563         u32                                     n;
 564         u32                                     cts;
 565         u32                                     aud_par_busclk;
 566         enum hdmi_core_audio_layout             layout;
 567         enum hdmi_core_cts_mode                 cts_mode;
 568         bool                                    use_mclk;
 569         enum hdmi_audio_mclk_mode               mclk_mode;
 570         bool                                    en_acr_pkt;
 571         bool                                    en_dsd_audio;
 572         bool                                    en_parallel_aud_input;
 573         bool                                    en_spdif;
 574 };
 575 #endif