drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c

   1 /*
   2  * ti_hdmi_4xxx_ip.c
   3  *
   4  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  * Authors: Yong Zhi
   7  *      Mythri pk <mythripk@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mutex.h>
  28 #include <linux/delay.h>
  29 #include <linux/string.h>
  30
  31 #include "ti_hdmi_4xxx_ip.h"
  32 #include "dss.h"
  33
  34 static inline void hdmi_write_reg(void __iomem *base_addr,
  35                                 const struct hdmi_reg idx, u32 val)
  36 {
  37         __raw_writel(val, base_addr + idx.idx);
  38 }
  39
  40 static inline u32 hdmi_read_reg(void __iomem *base_addr,
  41                                 const struct hdmi_reg idx)
  42 {
  43         return __raw_readl(base_addr + idx.idx);
  44 }
  45
  46 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
  47 {
  48         return ip_data->base_wp;
  49 }
  50
  51 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
  52 {
  53         return ip_data->base_wp + ip_data->phy_offset;
  54 }
  55
  56 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
  57 {
  58         return ip_data->base_wp + ip_data->pll_offset;
  59 }
  60
  61 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
  62 {
  63         return ip_data->base_wp + ip_data->core_av_offset;
  64 }
  65
  66 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
  67 {
  68         return ip_data->base_wp + ip_data->core_sys_offset;
  69 }
  70
  71 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
  72                                 const struct hdmi_reg idx,
  73                                 int b2, int b1, u32 val)
  74 {
  75         u32 t = 0;
  76         while (val != REG_GET(base_addr, idx, b2, b1)) {
  77                 udelay(1);
  78                 if (t++ > 10000)
  79                         return !val;
  80         }
  81         return val;
  82 }
  83
  84 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
  85 {
  86         u32 r;
  87         void __iomem *pll_base = hdmi_pll_base(ip_data);
  88         struct hdmi_pll_info *fmt = &ip_data->pll_data;
  89
  90         /* PLL start always use manual mode */
  91         REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
  92
  93         r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
  94         r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
  95         r = FLD_MOD(r, fmt->regn, 8, 1);  /* CFG1_PLL_REGN */
  96
  97         hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
  98
  99         r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
 100
 101         r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
 102         r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
 103         r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
 104         r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
 105
 106         if (fmt->dcofreq) {
 107                 /* divider programming for frequency beyond 1000Mhz */
 108                 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
 109                 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
 110         } else {
 111                 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
 112         }
 113
 114         hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
 115
 116         r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
 117         r = FLD_MOD(r, fmt->regm2, 24, 18);
 118         r = FLD_MOD(r, fmt->regmf, 17, 0);
 119
 120         hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
 121
 122         /* go now */
 123         REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
 124
 125         /* wait for bit change */
 126         if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
 127                                                         0, 0, 1) != 1) {
 128                 pr_err("PLL GO bit not set\n");
 129                 return -ETIMEDOUT;
 130         }
 131
 132         /* Wait till the lock bit is set in PLL status */
 133         if (hdmi_wait_for_bit_change(pll_base,
 134                                 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
 135                 pr_err("cannot lock PLL\n");
 136                 pr_err("CFG1 0x%x\n",
 137                         hdmi_read_reg(pll_base, PLLCTRL_CFG1));
 138                 pr_err("CFG2 0x%x\n",
 139                         hdmi_read_reg(pll_base, PLLCTRL_CFG2));
 140                 pr_err("CFG4 0x%x\n",
 141                         hdmi_read_reg(pll_base, PLLCTRL_CFG4));
 142                 return -ETIMEDOUT;
 143         }
 144
 145         pr_debug("PLL locked!\n");
 146
 147         return 0;
 148 }
 149
 150 /* PHY_PWR_CMD */
 151 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
 152 {
 153         /* Command for power control of HDMI PHY */
 154         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
 155
 156         /* Status of the power control of HDMI PHY */
 157         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
 158                                 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
 159                 pr_err("Failed to set PHY power mode to %d\n", val);
 160                 return -ETIMEDOUT;
 161         }
 162
 163         return 0;
 164 }
 165
 166 /* PLL_PWR_CMD */
 167 int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
 168 {
 169         /* Command for power control of HDMI PLL */
 170         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
 171
 172         /* wait till PHY_PWR_STATUS is set */
 173         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
 174                                                 1, 0, val) != val) {
 175                 pr_err("Failed to set PLL_PWR_STATUS\n");
 176                 return -ETIMEDOUT;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
 183 {
 184         /* SYSRESET  controlled by power FSM */
 185         REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
 186
 187         /* READ 0x0 reset is in progress */
 188         if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
 189                                 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
 190                 pr_err("Failed to sysreset PLL\n");
 191                 return -ETIMEDOUT;
 192         }
 193
 194         return 0;
 195 }
 196
 197 int hdmi_pll_program(struct hdmi_ip_data *ip_data)
 198 {
 199         u16 r = 0;
 200
 201         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 202         if (r)
 203                 return r;
 204
 205         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 206         if (r)
 207                 return r;
 208
 209         r = hdmi_pll_reset(ip_data);
 210         if (r)
 211                 return r;
 212
 213         r = hdmi_pll_init(ip_data);
 214         if (r)
 215                 return r;
 216
 217         return 0;
 218 }
 219
 220 int hdmi_phy_init(struct hdmi_ip_data *ip_data)
 221 {
 222         u16 r = 0;
 223         void __iomem *phy_base = hdmi_phy_base(ip_data);
 224
 225         r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
 226         if (r)
 227                 return r;
 228
 229         r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
 230         if (r)
 231                 return r;
 232
 233         /*
 234          * Read address 0 in order to get the SCP reset done completed
 235          * Dummy access performed to make sure reset is done
 236          */
 237         hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
 238
 239         /*
 240          * Write to phy address 0 to configure the clock
 241          * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
 242          */
 243         REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
 244
 245         /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
 246         hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
 247
 248         /* Setup max LDO voltage */
 249         REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
 250
 251         /* Write to phy address 3 to change the polarity control */
 252         REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
 253
 254         return 0;
 255 }
 256
 257 void hdmi_phy_off(struct hdmi_ip_data *ip_data)
 258 {
 259         hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 260 }
 261
 262 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
 263                                                 u8 *pedid, int ext)
 264 {
 265         u32 i, j;
 266         char checksum = 0;
 267         u32 offset = 0;
 268         void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
 269
 270         /* Turn on CLK for DDC */
 271         REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0);
 272
 273         /*
 274          * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
 275          * right shifted values( The behavior is not consistent and seen only
 276          * with some TV's)
 277          */
 278         usleep_range(800, 1000);
 279
 280         if (!ext) {
 281                 /* Clk SCL Devices */
 282                 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
 283
 284                 /* HDMI_CORE_DDC_STATUS_IN_PROG */
 285                 if (hdmi_wait_for_bit_change(core_sys_base,
 286                                         HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
 287                         pr_err("Failed to program DDC\n");
 288                         return -ETIMEDOUT;
 289                 }
 290
 291                 /* Clear FIFO */
 292                 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
 293
 294                 /* HDMI_CORE_DDC_STATUS_IN_PROG */
 295                 if (hdmi_wait_for_bit_change(core_sys_base,
 296                                         HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
 297                         pr_err("Failed to program DDC\n");
 298                         return -ETIMEDOUT;
 299                 }
 300
 301         } else {
 302                 if (ext % 2 != 0)
 303                         offset = 0x80;
 304         }
 305
 306         /* Load Segment Address Register */
 307         REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
 308
 309         /* Load Slave Address Register */
 310         REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
 311
 312         /* Load Offset Address Register */
 313         REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
 314
 315         /* Load Byte Count */
 316         REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
 317         REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
 318
 319         /* Set DDC_CMD */
 320         if (ext)
 321                 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
 322         else
 323                 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
 324
 325         /* HDMI_CORE_DDC_STATUS_BUS_LOW */
 326         if (REG_GET(core_sys_base,
 327                                         HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
 328                 pr_err("I2C Bus Low?\n");
 329                 return -EIO;
 330         }
 331         /* HDMI_CORE_DDC_STATUS_NO_ACK */
 332         if (REG_GET(core_sys_base,
 333                                         HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
 334                 pr_err("I2C No Ack\n");
 335                 return -EIO;
 336         }
 337
 338         i = ext * 128;
 339         j = 0;
 340         while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
 341                         (REG_GET(core_sys_base,
 342                         HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) {
 343
 344                 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
 345                         /* FIFO not empty */
 346                         pedid[i++] = REG_GET(core_sys_base,
 347                                                 HDMI_CORE_DDC_DATA, 7, 0);
 348                         j++;
 349                 }
 350         }
 351
 352         for (j = 0; j < 128; j++)
 353                 checksum += pedid[j];
 354
 355         if (checksum != 0) {
 356                 pr_err("E-EDID checksum failed!!\n");
 357                 return -EIO;
 358         }
 359
 360         return 0;
 361 }
 362
 363 int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length)
 364 {
 365         int r = 0, n = 0, i = 0;
 366         int max_ext_blocks = (max_length / 128) - 1;
 367
 368         r = hdmi_core_ddc_edid(ip_data, pedid, 0);
 369         if (r) {
 370                 return r;
 371         } else {
 372                 n = pedid[0x7e];
 373
 374                 /*
 375                  * README: need to comply with max_length set by the caller.
 376                  * Better implementation should be to allocate necessary
 377                  * memory to store EDID according to nb_block field found
 378                  * in first block
 379                  */
 380                 if (n > max_ext_blocks)
 381                         n = max_ext_blocks;
 382
 383                 for (i = 1; i <= n; i++) {
 384                         r = hdmi_core_ddc_edid(ip_data, pedid, i);
 385                         if (r)
 386                                 return r;
 387                 }
 388         }
 389         return 0;
 390 }
 391
 392 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
 393                         struct hdmi_core_infoframe_avi *avi_cfg,
 394                         struct hdmi_core_packet_enable_repeat *repeat_cfg)
 395 {
 396         pr_debug("Enter hdmi_core_init\n");
 397
 398         /* video core */
 399         video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
 400         video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
 401         video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
 402         video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
 403         video_cfg->hdmi_dvi = HDMI_DVI;
 404         video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
 405
 406         /* info frame */
 407         avi_cfg->db1_format = 0;
 408         avi_cfg->db1_active_info = 0;
 409         avi_cfg->db1_bar_info_dv = 0;
 410         avi_cfg->db1_scan_info = 0;
 411         avi_cfg->db2_colorimetry = 0;
 412         avi_cfg->db2_aspect_ratio = 0;
 413         avi_cfg->db2_active_fmt_ar = 0;
 414         avi_cfg->db3_itc = 0;
 415         avi_cfg->db3_ec = 0;
 416         avi_cfg->db3_q_range = 0;
 417         avi_cfg->db3_nup_scaling = 0;
 418         avi_cfg->db4_videocode = 0;
 419         avi_cfg->db5_pixel_repeat = 0;
 420         avi_cfg->db6_7_line_eoftop = 0 ;
 421         avi_cfg->db8_9_line_sofbottom = 0;
 422         avi_cfg->db10_11_pixel_eofleft = 0;
 423         avi_cfg->db12_13_pixel_sofright = 0;
 424
 425         /* packet enable and repeat */
 426         repeat_cfg->audio_pkt = 0;
 427         repeat_cfg->audio_pkt_repeat = 0;
 428         repeat_cfg->avi_infoframe = 0;
 429         repeat_cfg->avi_infoframe_repeat = 0;
 430         repeat_cfg->gen_cntrl_pkt = 0;
 431         repeat_cfg->gen_cntrl_pkt_repeat = 0;
 432         repeat_cfg->generic_pkt = 0;
 433         repeat_cfg->generic_pkt_repeat = 0;
 434 }
 435
 436 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
 437 {
 438         pr_debug("Enter hdmi_core_powerdown_disable\n");
 439         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
 440 }
 441
 442 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
 443 {
 444         pr_debug("Enter hdmi_core_swreset_release\n");
 445         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
 446 }
 447
 448 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
 449 {
 450         pr_debug("Enter hdmi_core_swreset_assert\n");
 451         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
 452 }
 453
 454 /* HDMI_CORE_VIDEO_CONFIG */
 455 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
 456                                 struct hdmi_core_video_config *cfg)
 457 {
 458         u32 r = 0;
 459         void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
 460
 461         /* sys_ctrl1 default configuration not tunable */
 462         r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
 463         r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
 464         r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
 465         r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
 466         r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
 467         hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
 468
 469         REG_FLD_MOD(core_sys_base,
 470                         HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
 471
 472         /* Vid_Mode */
 473         r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
 474
 475         /* dither truncation configuration */
 476         if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
 477                 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
 478                 r = FLD_MOD(r, 1, 5, 5);
 479         } else {
 480                 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
 481                 r = FLD_MOD(r, 0, 5, 5);
 482         }
 483         hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
 484
 485         /* HDMI_Ctrl */
 486         r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
 487         r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
 488         r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
 489         r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
 490         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
 491
 492         /* TMDS_CTRL */
 493         REG_FLD_MOD(core_sys_base,
 494                         HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
 495 }
 496
 497 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
 498                 struct hdmi_core_infoframe_avi info_avi)
 499 {
 500         u32 val;
 501         char sum = 0, checksum = 0;
 502         void __iomem *av_base = hdmi_av_base(ip_data);
 503
 504         sum += 0x82 + 0x002 + 0x00D;
 505         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
 506         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
 507         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
 508
 509         val = (info_avi.db1_format << 5) |
 510                 (info_avi.db1_active_info << 4) |
 511                 (info_avi.db1_bar_info_dv << 2) |
 512                 (info_avi.db1_scan_info);
 513         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
 514         sum += val;
 515
 516         val = (info_avi.db2_colorimetry << 6) |
 517                 (info_avi.db2_aspect_ratio << 4) |
 518                 (info_avi.db2_active_fmt_ar);
 519         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
 520         sum += val;
 521
 522         val = (info_avi.db3_itc << 7) |
 523                 (info_avi.db3_ec << 4) |
 524                 (info_avi.db3_q_range << 2) |
 525                 (info_avi.db3_nup_scaling);
 526         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
 527         sum += val;
 528
 529         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
 530                                         info_avi.db4_videocode);
 531         sum += info_avi.db4_videocode;
 532
 533         val = info_avi.db5_pixel_repeat;
 534         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
 535         sum += val;
 536
 537         val = info_avi.db6_7_line_eoftop & 0x00FF;
 538         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
 539         sum += val;
 540
 541         val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
 542         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
 543         sum += val;
 544
 545         val = info_avi.db8_9_line_sofbottom & 0x00FF;
 546         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
 547         sum += val;
 548
 549         val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
 550         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
 551         sum += val;
 552
 553         val = info_avi.db10_11_pixel_eofleft & 0x00FF;
 554         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
 555         sum += val;
 556
 557         val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
 558         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
 559         sum += val;
 560
 561         val = info_avi.db12_13_pixel_sofright & 0x00FF;
 562         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
 563         sum += val;
 564
 565         val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
 566         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
 567         sum += val;
 568
 569         checksum = 0x100 - sum;
 570         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
 571 }
 572
 573 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
 574                 struct hdmi_core_packet_enable_repeat repeat_cfg)
 575 {
 576         /* enable/repeat the infoframe */
 577         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
 578                 (repeat_cfg.audio_pkt << 5) |
 579                 (repeat_cfg.audio_pkt_repeat << 4) |
 580                 (repeat_cfg.avi_infoframe << 1) |
 581                 (repeat_cfg.avi_infoframe_repeat));
 582
 583         /* enable/repeat the packet */
 584         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
 585                 (repeat_cfg.gen_cntrl_pkt << 3) |
 586                 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
 587                 (repeat_cfg.generic_pkt << 1) |
 588                 (repeat_cfg.generic_pkt_repeat));
 589 }
 590
 591 static void hdmi_wp_init(struct omap_video_timings *timings,
 592                         struct hdmi_video_format *video_fmt,
 593                         struct hdmi_video_interface *video_int)
 594 {
 595         pr_debug("Enter hdmi_wp_init\n");
 596
 597         timings->hbp = 0;
 598         timings->hfp = 0;
 599         timings->hsw = 0;
 600         timings->vbp = 0;
 601         timings->vfp = 0;
 602         timings->vsw = 0;
 603
 604         video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
 605         video_fmt->y_res = 0;
 606         video_fmt->x_res = 0;
 607
 608         video_int->vsp = 0;
 609         video_int->hsp = 0;
 610
 611         video_int->interlacing = 0;
 612         video_int->tm = 0; /* HDMI_TIMING_SLAVE */
 613
 614 }
 615
 616 void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
 617 {
 618         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
 619 }
 620
 621 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
 622         struct omap_video_timings *timings, struct hdmi_config *param)
 623 {
 624         pr_debug("Enter hdmi_wp_video_init_format\n");
 625
 626         video_fmt->y_res = param->timings.timings.y_res;
 627         video_fmt->x_res = param->timings.timings.x_res;
 628
 629         timings->hbp = param->timings.timings.hbp;
 630         timings->hfp = param->timings.timings.hfp;
 631         timings->hsw = param->timings.timings.hsw;
 632         timings->vbp = param->timings.timings.vbp;
 633         timings->vfp = param->timings.timings.vfp;
 634         timings->vsw = param->timings.timings.vsw;
 635 }
 636
 637 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
 638                 struct hdmi_video_format *video_fmt)
 639 {
 640         u32 l = 0;
 641
 642         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
 643                         video_fmt->packing_mode, 10, 8);
 644
 645         l |= FLD_VAL(video_fmt->y_res, 31, 16);
 646         l |= FLD_VAL(video_fmt->x_res, 15, 0);
 647         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
 648 }
 649
 650 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
 651                 struct hdmi_video_interface *video_int)
 652 {
 653         u32 r;
 654         pr_debug("Enter hdmi_wp_video_config_interface\n");
 655
 656         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
 657         r = FLD_MOD(r, video_int->vsp, 7, 7);
 658         r = FLD_MOD(r, video_int->hsp, 6, 6);
 659         r = FLD_MOD(r, video_int->interlacing, 3, 3);
 660         r = FLD_MOD(r, video_int->tm, 1, 0);
 661         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
 662 }
 663
 664 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
 665                 struct omap_video_timings *timings)
 666 {
 667         u32 timing_h = 0;
 668         u32 timing_v = 0;
 669
 670         pr_debug("Enter hdmi_wp_video_config_timing\n");
 671
 672         timing_h |= FLD_VAL(timings->hbp, 31, 20);
 673         timing_h |= FLD_VAL(timings->hfp, 19, 8);
 674         timing_h |= FLD_VAL(timings->hsw, 7, 0);
 675         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
 676
 677         timing_v |= FLD_VAL(timings->vbp, 31, 20);
 678         timing_v |= FLD_VAL(timings->vfp, 19, 8);
 679         timing_v |= FLD_VAL(timings->vsw, 7, 0);
 680         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
 681 }
 682
 683 void hdmi_basic_configure(struct hdmi_ip_data *ip_data)
 684 {
 685         /* HDMI */
 686         struct omap_video_timings video_timing;
 687         struct hdmi_video_format video_format;
 688         struct hdmi_video_interface video_interface;
 689         /* HDMI core */
 690         struct hdmi_core_infoframe_avi avi_cfg;
 691         struct hdmi_core_video_config v_core_cfg;
 692         struct hdmi_core_packet_enable_repeat repeat_cfg;
 693         struct hdmi_config *cfg = &ip_data->cfg;
 694
 695         hdmi_wp_init(&video_timing, &video_format,
 696                 &video_interface);
 697
 698         hdmi_core_init(&v_core_cfg,
 699                 &avi_cfg,
 700                 &repeat_cfg);
 701
 702         hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
 703
 704         hdmi_wp_video_config_timing(ip_data, &video_timing);
 705
 706         /* video config */
 707         video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
 708
 709         hdmi_wp_video_config_format(ip_data, &video_format);
 710
 711         video_interface.vsp = cfg->timings.vsync_pol;
 712         video_interface.hsp = cfg->timings.hsync_pol;
 713         video_interface.interlacing = cfg->interlace;
 714         video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
 715
 716         hdmi_wp_video_config_interface(ip_data, &video_interface);
 717
 718         /*
 719          * configure core video part
 720          * set software reset in the core
 721          */
 722         hdmi_core_swreset_assert(ip_data);
 723
 724         /* power down off */
 725         hdmi_core_powerdown_disable(ip_data);
 726
 727         v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
 728         v_core_cfg.hdmi_dvi = cfg->cm.mode;
 729
 730         hdmi_core_video_config(ip_data, &v_core_cfg);
 731
 732         /* release software reset in the core */
 733         hdmi_core_swreset_release(ip_data);
 734
 735         /*
 736          * configure packet
 737          * info frame video see doc CEA861-D page 65
 738          */
 739         avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
 740         avi_cfg.db1_active_info =
 741                 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
 742         avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
 743         avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
 744         avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
 745         avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
 746         avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
 747         avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
 748         avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
 749         avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
 750         avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
 751         avi_cfg.db4_videocode = cfg->cm.code;
 752         avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
 753         avi_cfg.db6_7_line_eoftop = 0;
 754         avi_cfg.db8_9_line_sofbottom = 0;
 755         avi_cfg.db10_11_pixel_eofleft = 0;
 756         avi_cfg.db12_13_pixel_sofright = 0;
 757
 758         hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
 759
 760         /* enable/repeat the infoframe */
 761         repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
 762         repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
 763         /* wakeup */
 764         repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
 765         repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
 766         hdmi_core_av_packet_config(ip_data, repeat_cfg);
 767 }