drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c

   1 /*
   2  * ti_hdmi_4xxx_ip.c
   3  *
   4  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  * Authors: Yong Zhi
   7  *      Mythri pk <mythripk@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mutex.h>
  28 #include <linux/delay.h>
  29 #include <linux/string.h>
  30 #include <linux/seq_file.h>
  31
  32 #include "ti_hdmi_4xxx_ip.h"
  33 #include "dss.h"
  34
  35 static inline void hdmi_write_reg(void __iomem *base_addr,
  36                                 const u16 idx, u32 val)
  37 {
  38         __raw_writel(val, base_addr + idx);
  39 }
  40
  41 static inline u32 hdmi_read_reg(void __iomem *base_addr,
  42                                 const u16 idx)
  43 {
  44         return __raw_readl(base_addr + idx);
  45 }
  46
  47 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
  48 {
  49         return ip_data->base_wp;
  50 }
  51
  52 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
  53 {
  54         return ip_data->base_wp + ip_data->phy_offset;
  55 }
  56
  57 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
  58 {
  59         return ip_data->base_wp + ip_data->pll_offset;
  60 }
  61
  62 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
  63 {
  64         return ip_data->base_wp + ip_data->core_av_offset;
  65 }
  66
  67 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
  68 {
  69         return ip_data->base_wp + ip_data->core_sys_offset;
  70 }
  71
  72 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
  73                                 const u16 idx,
  74                                 int b2, int b1, u32 val)
  75 {
  76         u32 t = 0;
  77         while (val != REG_GET(base_addr, idx, b2, b1)) {
  78                 udelay(1);
  79                 if (t++ > 10000)
  80                         return !val;
  81         }
  82         return val;
  83 }
  84
  85 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
  86 {
  87         u32 r;
  88         void __iomem *pll_base = hdmi_pll_base(ip_data);
  89         struct hdmi_pll_info *fmt = &ip_data->pll_data;
  90
  91         /* PLL start always use manual mode */
  92         REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
  93
  94         r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
  95         r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
  96         r = FLD_MOD(r, fmt->regn - 1, 8, 1);  /* CFG1_PLL_REGN */
  97
  98         hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
  99
 100         r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
 101
 102         r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
 103         r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
 104         r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
 105         r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
 106
 107         if (fmt->dcofreq) {
 108                 /* divider programming for frequency beyond 1000Mhz */
 109                 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
 110                 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
 111         } else {
 112                 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
 113         }
 114
 115         hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
 116
 117         r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
 118         r = FLD_MOD(r, fmt->regm2, 24, 18);
 119         r = FLD_MOD(r, fmt->regmf, 17, 0);
 120
 121         hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
 122
 123         /* go now */
 124         REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
 125
 126         /* wait for bit change */
 127         if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
 128                                                         0, 0, 1) != 1) {
 129                 pr_err("PLL GO bit not set\n");
 130                 return -ETIMEDOUT;
 131         }
 132
 133         /* Wait till the lock bit is set in PLL status */
 134         if (hdmi_wait_for_bit_change(pll_base,
 135                                 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
 136                 pr_err("cannot lock PLL\n");
 137                 pr_err("CFG1 0x%x\n",
 138                         hdmi_read_reg(pll_base, PLLCTRL_CFG1));
 139                 pr_err("CFG2 0x%x\n",
 140                         hdmi_read_reg(pll_base, PLLCTRL_CFG2));
 141                 pr_err("CFG4 0x%x\n",
 142                         hdmi_read_reg(pll_base, PLLCTRL_CFG4));
 143                 return -ETIMEDOUT;
 144         }
 145
 146         pr_debug("PLL locked!\n");
 147
 148         return 0;
 149 }
 150
 151 /* PHY_PWR_CMD */
 152 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
 153 {
 154         /* Command for power control of HDMI PHY */
 155         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
 156
 157         /* Status of the power control of HDMI PHY */
 158         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
 159                                 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
 160                 pr_err("Failed to set PHY power mode to %d\n", val);
 161                 return -ETIMEDOUT;
 162         }
 163
 164         return 0;
 165 }
 166
 167 /* PLL_PWR_CMD */
 168 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
 169 {
 170         /* Command for power control of HDMI PLL */
 171         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
 172
 173         /* wait till PHY_PWR_STATUS is set */
 174         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
 175                                                 1, 0, val) != val) {
 176                 pr_err("Failed to set PLL_PWR_STATUS\n");
 177                 return -ETIMEDOUT;
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
 184 {
 185         /* SYSRESET  controlled by power FSM */
 186         REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
 187
 188         /* READ 0x0 reset is in progress */
 189         if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
 190                                 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
 191                 pr_err("Failed to sysreset PLL\n");
 192                 return -ETIMEDOUT;
 193         }
 194
 195         return 0;
 196 }
 197
 198 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
 199 {
 200         u16 r = 0;
 201
 202         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 203         if (r)
 204                 return r;
 205
 206         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 207         if (r)
 208                 return r;
 209
 210         r = hdmi_pll_reset(ip_data);
 211         if (r)
 212                 return r;
 213
 214         r = hdmi_pll_init(ip_data);
 215         if (r)
 216                 return r;
 217
 218         return 0;
 219 }
 220
 221 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
 222 {
 223         hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 224 }
 225
 226 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
 227 {
 228         u16 r = 0;
 229         void __iomem *phy_base = hdmi_phy_base(ip_data);
 230
 231         r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
 232         if (r)
 233                 return r;
 234
 235         r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
 236         if (r)
 237                 return r;
 238
 239         /*
 240          * Read address 0 in order to get the SCP reset done completed
 241          * Dummy access performed to make sure reset is done
 242          */
 243         hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
 244
 245         /*
 246          * Write to phy address 0 to configure the clock
 247          * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
 248          */
 249         REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
 250
 251         /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
 252         hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
 253
 254         /* Setup max LDO voltage */
 255         REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
 256
 257         /* Write to phy address 3 to change the polarity control */
 258         REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
 259
 260         return 0;
 261 }
 262
 263 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
 264 {
 265         hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 266 }
 267
 268 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
 269 {
 270         void __iomem *base = hdmi_core_sys_base(ip_data);
 271
 272         /* Turn on CLK for DDC */
 273         REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
 274
 275         /* IN_PROG */
 276         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
 277                 /* Abort transaction */
 278                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
 279                 /* IN_PROG */
 280                 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 281                                         4, 4, 0) != 0) {
 282                         DSSERR("Timeout aborting DDC transaction\n");
 283                         return -ETIMEDOUT;
 284                 }
 285         }
 286
 287         /* Clk SCL Devices */
 288         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
 289
 290         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 291         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 292                                 4, 4, 0) != 0) {
 293                 DSSERR("Timeout starting SCL clock\n");
 294                 return -ETIMEDOUT;
 295         }
 296
 297         /* Clear FIFO */
 298         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
 299
 300         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 301         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 302                                 4, 4, 0) != 0) {
 303                 DSSERR("Timeout clearing DDC fifo\n");
 304                 return -ETIMEDOUT;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
 311                 u8 *pedid, int ext)
 312 {
 313         void __iomem *base = hdmi_core_sys_base(ip_data);
 314         u32 i;
 315         char checksum;
 316         u32 offset = 0;
 317
 318         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 319         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 320                                 4, 4, 0) != 0) {
 321                 DSSERR("Timeout waiting DDC to be ready\n");
 322                 return -ETIMEDOUT;
 323         }
 324
 325         if (ext % 2 != 0)
 326                 offset = 0x80;
 327
 328         /* Load Segment Address Register */
 329         REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
 330
 331         /* Load Slave Address Register */
 332         REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
 333
 334         /* Load Offset Address Register */
 335         REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
 336
 337         /* Load Byte Count */
 338         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
 339         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
 340
 341         /* Set DDC_CMD */
 342         if (ext)
 343                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
 344         else
 345                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
 346
 347         /* HDMI_CORE_DDC_STATUS_BUS_LOW */
 348         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
 349                 pr_err("I2C Bus Low?\n");
 350                 return -EIO;
 351         }
 352         /* HDMI_CORE_DDC_STATUS_NO_ACK */
 353         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
 354                 pr_err("I2C No Ack\n");
 355                 return -EIO;
 356         }
 357
 358         for (i = 0; i < 0x80; ++i) {
 359                 int t;
 360
 361                 /* IN_PROG */
 362                 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
 363                         DSSERR("operation stopped when reading edid\n");
 364                         return -EIO;
 365                 }
 366
 367                 t = 0;
 368                 /* FIFO_EMPTY */
 369                 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
 370                         if (t++ > 10000) {
 371                                 DSSERR("timeout reading edid\n");
 372                                 return -ETIMEDOUT;
 373                         }
 374                         udelay(1);
 375                 }
 376
 377                 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
 378         }
 379
 380         checksum = 0;
 381         for (i = 0; i < 0x80; ++i)
 382                 checksum += pedid[i];
 383
 384         if (checksum != 0) {
 385                 pr_err("E-EDID checksum failed!!\n");
 386                 return -EIO;
 387         }
 388
 389         return 0;
 390 }
 391
 392 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
 393                                 u8 *edid, int len)
 394 {
 395         int r, l;
 396
 397         if (len < 128)
 398                 return -EINVAL;
 399
 400         r = hdmi_core_ddc_init(ip_data);
 401         if (r)
 402                 return r;
 403
 404         r = hdmi_core_ddc_edid(ip_data, edid, 0);
 405         if (r)
 406                 return r;
 407
 408         l = 128;
 409
 410         if (len >= 128 * 2 && edid[0x7e] > 0) {
 411                 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
 412                 if (r)
 413                         return r;
 414                 l += 128;
 415         }
 416
 417         return l;
 418 }
 419
 420 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
 421 {
 422         int r;
 423
 424         void __iomem *base = hdmi_core_sys_base(ip_data);
 425
 426         /* HPD */
 427         r = REG_GET(base, HDMI_CORE_SYS_SYS_STAT, 1, 1);
 428
 429         return r == 1;
 430 }
 431
 432 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
 433                         struct hdmi_core_infoframe_avi *avi_cfg,
 434                         struct hdmi_core_packet_enable_repeat *repeat_cfg)
 435 {
 436         pr_debug("Enter hdmi_core_init\n");
 437
 438         /* video core */
 439         video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
 440         video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
 441         video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
 442         video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
 443         video_cfg->hdmi_dvi = HDMI_DVI;
 444         video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
 445
 446         /* info frame */
 447         avi_cfg->db1_format = 0;
 448         avi_cfg->db1_active_info = 0;
 449         avi_cfg->db1_bar_info_dv = 0;
 450         avi_cfg->db1_scan_info = 0;
 451         avi_cfg->db2_colorimetry = 0;
 452         avi_cfg->db2_aspect_ratio = 0;
 453         avi_cfg->db2_active_fmt_ar = 0;
 454         avi_cfg->db3_itc = 0;
 455         avi_cfg->db3_ec = 0;
 456         avi_cfg->db3_q_range = 0;
 457         avi_cfg->db3_nup_scaling = 0;
 458         avi_cfg->db4_videocode = 0;
 459         avi_cfg->db5_pixel_repeat = 0;
 460         avi_cfg->db6_7_line_eoftop = 0 ;
 461         avi_cfg->db8_9_line_sofbottom = 0;
 462         avi_cfg->db10_11_pixel_eofleft = 0;
 463         avi_cfg->db12_13_pixel_sofright = 0;
 464
 465         /* packet enable and repeat */
 466         repeat_cfg->audio_pkt = 0;
 467         repeat_cfg->audio_pkt_repeat = 0;
 468         repeat_cfg->avi_infoframe = 0;
 469         repeat_cfg->avi_infoframe_repeat = 0;
 470         repeat_cfg->gen_cntrl_pkt = 0;
 471         repeat_cfg->gen_cntrl_pkt_repeat = 0;
 472         repeat_cfg->generic_pkt = 0;
 473         repeat_cfg->generic_pkt_repeat = 0;
 474 }
 475
 476 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
 477 {
 478         pr_debug("Enter hdmi_core_powerdown_disable\n");
 479         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
 480 }
 481
 482 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
 483 {
 484         pr_debug("Enter hdmi_core_swreset_release\n");
 485         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
 486 }
 487
 488 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
 489 {
 490         pr_debug("Enter hdmi_core_swreset_assert\n");
 491         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
 492 }
 493
 494 /* HDMI_CORE_VIDEO_CONFIG */
 495 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
 496                                 struct hdmi_core_video_config *cfg)
 497 {
 498         u32 r = 0;
 499         void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
 500
 501         /* sys_ctrl1 default configuration not tunable */
 502         r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
 503         r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
 504         r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
 505         r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
 506         r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
 507         hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
 508
 509         REG_FLD_MOD(core_sys_base,
 510                         HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
 511
 512         /* Vid_Mode */
 513         r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
 514
 515         /* dither truncation configuration */
 516         if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
 517                 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
 518                 r = FLD_MOD(r, 1, 5, 5);
 519         } else {
 520                 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
 521                 r = FLD_MOD(r, 0, 5, 5);
 522         }
 523         hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
 524
 525         /* HDMI_Ctrl */
 526         r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
 527         r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
 528         r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
 529         r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
 530         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
 531
 532         /* TMDS_CTRL */
 533         REG_FLD_MOD(core_sys_base,
 534                         HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
 535 }
 536
 537 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
 538                 struct hdmi_core_infoframe_avi info_avi)
 539 {
 540         u32 val;
 541         char sum = 0, checksum = 0;
 542         void __iomem *av_base = hdmi_av_base(ip_data);
 543
 544         sum += 0x82 + 0x002 + 0x00D;
 545         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
 546         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
 547         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
 548
 549         val = (info_avi.db1_format << 5) |
 550                 (info_avi.db1_active_info << 4) |
 551                 (info_avi.db1_bar_info_dv << 2) |
 552                 (info_avi.db1_scan_info);
 553         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
 554         sum += val;
 555
 556         val = (info_avi.db2_colorimetry << 6) |
 557                 (info_avi.db2_aspect_ratio << 4) |
 558                 (info_avi.db2_active_fmt_ar);
 559         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
 560         sum += val;
 561
 562         val = (info_avi.db3_itc << 7) |
 563                 (info_avi.db3_ec << 4) |
 564                 (info_avi.db3_q_range << 2) |
 565                 (info_avi.db3_nup_scaling);
 566         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
 567         sum += val;
 568
 569         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
 570                                         info_avi.db4_videocode);
 571         sum += info_avi.db4_videocode;
 572
 573         val = info_avi.db5_pixel_repeat;
 574         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
 575         sum += val;
 576
 577         val = info_avi.db6_7_line_eoftop & 0x00FF;
 578         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
 579         sum += val;
 580
 581         val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
 582         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
 583         sum += val;
 584
 585         val = info_avi.db8_9_line_sofbottom & 0x00FF;
 586         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
 587         sum += val;
 588
 589         val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
 590         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
 591         sum += val;
 592
 593         val = info_avi.db10_11_pixel_eofleft & 0x00FF;
 594         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
 595         sum += val;
 596
 597         val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
 598         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
 599         sum += val;
 600
 601         val = info_avi.db12_13_pixel_sofright & 0x00FF;
 602         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
 603         sum += val;
 604
 605         val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
 606         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
 607         sum += val;
 608
 609         checksum = 0x100 - sum;
 610         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
 611 }
 612
 613 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
 614                 struct hdmi_core_packet_enable_repeat repeat_cfg)
 615 {
 616         /* enable/repeat the infoframe */
 617         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
 618                 (repeat_cfg.audio_pkt << 5) |
 619                 (repeat_cfg.audio_pkt_repeat << 4) |
 620                 (repeat_cfg.avi_infoframe << 1) |
 621                 (repeat_cfg.avi_infoframe_repeat));
 622
 623         /* enable/repeat the packet */
 624         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
 625                 (repeat_cfg.gen_cntrl_pkt << 3) |
 626                 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
 627                 (repeat_cfg.generic_pkt << 1) |
 628                 (repeat_cfg.generic_pkt_repeat));
 629 }
 630
 631 static void hdmi_wp_init(struct omap_video_timings *timings,
 632                         struct hdmi_video_format *video_fmt,
 633                         struct hdmi_video_interface *video_int)
 634 {
 635         pr_debug("Enter hdmi_wp_init\n");
 636
 637         timings->hbp = 0;
 638         timings->hfp = 0;
 639         timings->hsw = 0;
 640         timings->vbp = 0;
 641         timings->vfp = 0;
 642         timings->vsw = 0;
 643
 644         video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
 645         video_fmt->y_res = 0;
 646         video_fmt->x_res = 0;
 647
 648         video_int->vsp = 0;
 649         video_int->hsp = 0;
 650
 651         video_int->interlacing = 0;
 652         video_int->tm = 0; /* HDMI_TIMING_SLAVE */
 653
 654 }
 655
 656 void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
 657 {
 658         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
 659 }
 660
 661 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
 662         struct omap_video_timings *timings, struct hdmi_config *param)
 663 {
 664         pr_debug("Enter hdmi_wp_video_init_format\n");
 665
 666         video_fmt->y_res = param->timings.timings.y_res;
 667         video_fmt->x_res = param->timings.timings.x_res;
 668
 669         timings->hbp = param->timings.timings.hbp;
 670         timings->hfp = param->timings.timings.hfp;
 671         timings->hsw = param->timings.timings.hsw;
 672         timings->vbp = param->timings.timings.vbp;
 673         timings->vfp = param->timings.timings.vfp;
 674         timings->vsw = param->timings.timings.vsw;
 675 }
 676
 677 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
 678                 struct hdmi_video_format *video_fmt)
 679 {
 680         u32 l = 0;
 681
 682         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
 683                         video_fmt->packing_mode, 10, 8);
 684
 685         l |= FLD_VAL(video_fmt->y_res, 31, 16);
 686         l |= FLD_VAL(video_fmt->x_res, 15, 0);
 687         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
 688 }
 689
 690 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
 691                 struct hdmi_video_interface *video_int)
 692 {
 693         u32 r;
 694         pr_debug("Enter hdmi_wp_video_config_interface\n");
 695
 696         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
 697         r = FLD_MOD(r, video_int->vsp, 7, 7);
 698         r = FLD_MOD(r, video_int->hsp, 6, 6);
 699         r = FLD_MOD(r, video_int->interlacing, 3, 3);
 700         r = FLD_MOD(r, video_int->tm, 1, 0);
 701         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
 702 }
 703
 704 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
 705                 struct omap_video_timings *timings)
 706 {
 707         u32 timing_h = 0;
 708         u32 timing_v = 0;
 709
 710         pr_debug("Enter hdmi_wp_video_config_timing\n");
 711
 712         timing_h |= FLD_VAL(timings->hbp, 31, 20);
 713         timing_h |= FLD_VAL(timings->hfp, 19, 8);
 714         timing_h |= FLD_VAL(timings->hsw, 7, 0);
 715         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
 716
 717         timing_v |= FLD_VAL(timings->vbp, 31, 20);
 718         timing_v |= FLD_VAL(timings->vfp, 19, 8);
 719         timing_v |= FLD_VAL(timings->vsw, 7, 0);
 720         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
 721 }
 722
 723 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
 724 {
 725         /* HDMI */
 726         struct omap_video_timings video_timing;
 727         struct hdmi_video_format video_format;
 728         struct hdmi_video_interface video_interface;
 729         /* HDMI core */
 730         struct hdmi_core_infoframe_avi avi_cfg;
 731         struct hdmi_core_video_config v_core_cfg;
 732         struct hdmi_core_packet_enable_repeat repeat_cfg;
 733         struct hdmi_config *cfg = &ip_data->cfg;
 734
 735         hdmi_wp_init(&video_timing, &video_format,
 736                 &video_interface);
 737
 738         hdmi_core_init(&v_core_cfg,
 739                 &avi_cfg,
 740                 &repeat_cfg);
 741
 742         hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
 743
 744         hdmi_wp_video_config_timing(ip_data, &video_timing);
 745
 746         /* video config */
 747         video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
 748
 749         hdmi_wp_video_config_format(ip_data, &video_format);
 750
 751         video_interface.vsp = cfg->timings.vsync_pol;
 752         video_interface.hsp = cfg->timings.hsync_pol;
 753         video_interface.interlacing = cfg->interlace;
 754         video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
 755
 756         hdmi_wp_video_config_interface(ip_data, &video_interface);
 757
 758         /*
 759          * configure core video part
 760          * set software reset in the core
 761          */
 762         hdmi_core_swreset_assert(ip_data);
 763
 764         /* power down off */
 765         hdmi_core_powerdown_disable(ip_data);
 766
 767         v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
 768         v_core_cfg.hdmi_dvi = cfg->cm.mode;
 769
 770         hdmi_core_video_config(ip_data, &v_core_cfg);
 771
 772         /* release software reset in the core */
 773         hdmi_core_swreset_release(ip_data);
 774
 775         /*
 776          * configure packet
 777          * info frame video see doc CEA861-D page 65
 778          */
 779         avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
 780         avi_cfg.db1_active_info =
 781                 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
 782         avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
 783         avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
 784         avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
 785         avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
 786         avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
 787         avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
 788         avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
 789         avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
 790         avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
 791         avi_cfg.db4_videocode = cfg->cm.code;
 792         avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
 793         avi_cfg.db6_7_line_eoftop = 0;
 794         avi_cfg.db8_9_line_sofbottom = 0;
 795         avi_cfg.db10_11_pixel_eofleft = 0;
 796         avi_cfg.db12_13_pixel_sofright = 0;
 797
 798         hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
 799
 800         /* enable/repeat the infoframe */
 801         repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
 802         repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
 803         /* wakeup */
 804         repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
 805         repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
 806         hdmi_core_av_packet_config(ip_data, repeat_cfg);
 807 }
 808
 809 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 810 {
 811 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
 812                 hdmi_read_reg(hdmi_wp_base(ip_data), r))
 813
 814         DUMPREG(HDMI_WP_REVISION);
 815         DUMPREG(HDMI_WP_SYSCONFIG);
 816         DUMPREG(HDMI_WP_IRQSTATUS_RAW);
 817         DUMPREG(HDMI_WP_IRQSTATUS);
 818         DUMPREG(HDMI_WP_PWR_CTRL);
 819         DUMPREG(HDMI_WP_IRQENABLE_SET);
 820         DUMPREG(HDMI_WP_VIDEO_CFG);
 821         DUMPREG(HDMI_WP_VIDEO_SIZE);
 822         DUMPREG(HDMI_WP_VIDEO_TIMING_H);
 823         DUMPREG(HDMI_WP_VIDEO_TIMING_V);
 824         DUMPREG(HDMI_WP_WP_CLK);
 825         DUMPREG(HDMI_WP_AUDIO_CFG);
 826         DUMPREG(HDMI_WP_AUDIO_CFG2);
 827         DUMPREG(HDMI_WP_AUDIO_CTRL);
 828         DUMPREG(HDMI_WP_AUDIO_DATA);
 829 }
 830
 831 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 832 {
 833 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
 834                 hdmi_read_reg(hdmi_pll_base(ip_data), r))
 835
 836         DUMPPLL(PLLCTRL_PLL_CONTROL);
 837         DUMPPLL(PLLCTRL_PLL_STATUS);
 838         DUMPPLL(PLLCTRL_PLL_GO);
 839         DUMPPLL(PLLCTRL_CFG1);
 840         DUMPPLL(PLLCTRL_CFG2);
 841         DUMPPLL(PLLCTRL_CFG3);
 842         DUMPPLL(PLLCTRL_CFG4);
 843 }
 844
 845 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 846 {
 847         int i;
 848
 849 #define CORE_REG(i, name) name(i)
 850 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
 851                 hdmi_read_reg(hdmi_pll_base(ip_data), r))
 852 #define DUMPCOREAV(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
 853                 (i < 10) ? 32 - strlen(#r) : 31 - strlen(#r), " ", \
 854                 hdmi_read_reg(hdmi_pll_base(ip_data), CORE_REG(i, r)))
 855
 856         DUMPCORE(HDMI_CORE_SYS_VND_IDL);
 857         DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
 858         DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
 859         DUMPCORE(HDMI_CORE_SYS_DEV_REV);
 860         DUMPCORE(HDMI_CORE_SYS_SRST);
 861         DUMPCORE(HDMI_CORE_CTRL1);
 862         DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
 863         DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
 864         DUMPCORE(HDMI_CORE_SYS_VID_MODE);
 865         DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
 866         DUMPCORE(HDMI_CORE_SYS_INTR1);
 867         DUMPCORE(HDMI_CORE_SYS_INTR2);
 868         DUMPCORE(HDMI_CORE_SYS_INTR3);
 869         DUMPCORE(HDMI_CORE_SYS_INTR4);
 870         DUMPCORE(HDMI_CORE_SYS_UMASK1);
 871         DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
 872         DUMPCORE(HDMI_CORE_SYS_DE_DLY);
 873         DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
 874         DUMPCORE(HDMI_CORE_SYS_DE_TOP);
 875         DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
 876         DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
 877         DUMPCORE(HDMI_CORE_SYS_DE_LINL);
 878         DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
 879
 880         DUMPCORE(HDMI_CORE_DDC_CMD);
 881         DUMPCORE(HDMI_CORE_DDC_STATUS);
 882         DUMPCORE(HDMI_CORE_DDC_ADDR);
 883         DUMPCORE(HDMI_CORE_DDC_OFFSET);
 884         DUMPCORE(HDMI_CORE_DDC_COUNT1);
 885         DUMPCORE(HDMI_CORE_DDC_COUNT2);
 886         DUMPCORE(HDMI_CORE_DDC_DATA);
 887         DUMPCORE(HDMI_CORE_DDC_SEGM);
 888
 889         DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
 890         DUMPCORE(HDMI_CORE_AV_DPD);
 891         DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
 892         DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
 893         DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
 894         DUMPCORE(HDMI_CORE_AV_AVI_VERS);
 895         DUMPCORE(HDMI_CORE_AV_AVI_LEN);
 896         DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
 897
 898         for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
 899                 DUMPCOREAV(i, HDMI_CORE_AV_AVI_DBYTE);
 900
 901         for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
 902                 DUMPCOREAV(i, HDMI_CORE_AV_SPD_DBYTE);
 903
 904         for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
 905                 DUMPCOREAV(i, HDMI_CORE_AV_AUD_DBYTE);
 906
 907         for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
 908                 DUMPCOREAV(i, HDMI_CORE_AV_MPEG_DBYTE);
 909
 910         for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
 911                 DUMPCOREAV(i, HDMI_CORE_AV_GEN_DBYTE);
 912
 913         for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
 914                 DUMPCOREAV(i, HDMI_CORE_AV_GEN2_DBYTE);
 915
 916         DUMPCORE(HDMI_CORE_AV_ACR_CTRL);
 917         DUMPCORE(HDMI_CORE_AV_FREQ_SVAL);
 918         DUMPCORE(HDMI_CORE_AV_N_SVAL1);
 919         DUMPCORE(HDMI_CORE_AV_N_SVAL2);
 920         DUMPCORE(HDMI_CORE_AV_N_SVAL3);
 921         DUMPCORE(HDMI_CORE_AV_CTS_SVAL1);
 922         DUMPCORE(HDMI_CORE_AV_CTS_SVAL2);
 923         DUMPCORE(HDMI_CORE_AV_CTS_SVAL3);
 924         DUMPCORE(HDMI_CORE_AV_CTS_HVAL1);
 925         DUMPCORE(HDMI_CORE_AV_CTS_HVAL2);
 926         DUMPCORE(HDMI_CORE_AV_CTS_HVAL3);
 927         DUMPCORE(HDMI_CORE_AV_AUD_MODE);
 928         DUMPCORE(HDMI_CORE_AV_SPDIF_CTRL);
 929         DUMPCORE(HDMI_CORE_AV_HW_SPDIF_FS);
 930         DUMPCORE(HDMI_CORE_AV_SWAP_I2S);
 931         DUMPCORE(HDMI_CORE_AV_SPDIF_ERTH);
 932         DUMPCORE(HDMI_CORE_AV_I2S_IN_MAP);
 933         DUMPCORE(HDMI_CORE_AV_I2S_IN_CTRL);
 934         DUMPCORE(HDMI_CORE_AV_I2S_CHST0);
 935         DUMPCORE(HDMI_CORE_AV_I2S_CHST1);
 936         DUMPCORE(HDMI_CORE_AV_I2S_CHST2);
 937         DUMPCORE(HDMI_CORE_AV_I2S_CHST4);
 938         DUMPCORE(HDMI_CORE_AV_I2S_CHST5);
 939         DUMPCORE(HDMI_CORE_AV_ASRC);
 940         DUMPCORE(HDMI_CORE_AV_I2S_IN_LEN);
 941         DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
 942         DUMPCORE(HDMI_CORE_AV_AUDO_TXSTAT);
 943         DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
 944         DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
 945         DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
 946         DUMPCORE(HDMI_CORE_AV_TEST_TXCTRL);
 947         DUMPCORE(HDMI_CORE_AV_DPD);
 948         DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
 949         DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
 950         DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
 951         DUMPCORE(HDMI_CORE_AV_AVI_VERS);
 952         DUMPCORE(HDMI_CORE_AV_AVI_LEN);
 953         DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
 954         DUMPCORE(HDMI_CORE_AV_SPD_TYPE);
 955         DUMPCORE(HDMI_CORE_AV_SPD_VERS);
 956         DUMPCORE(HDMI_CORE_AV_SPD_LEN);
 957         DUMPCORE(HDMI_CORE_AV_SPD_CHSUM);
 958         DUMPCORE(HDMI_CORE_AV_AUDIO_TYPE);
 959         DUMPCORE(HDMI_CORE_AV_AUDIO_VERS);
 960         DUMPCORE(HDMI_CORE_AV_AUDIO_LEN);
 961         DUMPCORE(HDMI_CORE_AV_AUDIO_CHSUM);
 962         DUMPCORE(HDMI_CORE_AV_MPEG_TYPE);
 963         DUMPCORE(HDMI_CORE_AV_MPEG_VERS);
 964         DUMPCORE(HDMI_CORE_AV_MPEG_LEN);
 965         DUMPCORE(HDMI_CORE_AV_MPEG_CHSUM);
 966         DUMPCORE(HDMI_CORE_AV_CP_BYTE1);
 967         DUMPCORE(HDMI_CORE_AV_CEC_ADDR_ID);
 968 }
 969
 970 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 971 {
 972 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
 973                 hdmi_read_reg(hdmi_phy_base(ip_data), r))
 974
 975         DUMPPHY(HDMI_TXPHY_TX_CTRL);
 976         DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
 977         DUMPPHY(HDMI_TXPHY_POWER_CTRL);
 978         DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
 979 }
 980
 981 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
 982         defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
 983 void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
 984                                         struct hdmi_audio_format *aud_fmt)
 985 {
 986         u32 r;
 987
 988         DSSDBG("Enter hdmi_wp_audio_config_format\n");
 989
 990         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
 991         r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
 992         r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
 993         r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
 994         r = FLD_MOD(r, aud_fmt->type, 4, 4);
 995         r = FLD_MOD(r, aud_fmt->justification, 3, 3);
 996         r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
 997         r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
 998         r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
 999         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1000 }
1001
1002 void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1003                                         struct hdmi_audio_dma *aud_dma)
1004 {
1005         u32 r;
1006
1007         DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1008
1009         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1010         r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1011         r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1012         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1013
1014         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1015         r = FLD_MOD(r, aud_dma->mode, 9, 9);
1016         r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1017         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1018 }
1019
1020 void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
1021                                         struct hdmi_core_audio_config *cfg)
1022 {
1023         u32 r;
1024         void __iomem *av_base = hdmi_av_base(ip_data);
1025
1026         /* audio clock recovery parameters */
1027         r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1028         r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1029         r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1030         r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1031         hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1032
1033         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1034         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1035         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1036
1037         if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1038                 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1039                 REG_FLD_MOD(av_base,
1040                                 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1041                 REG_FLD_MOD(av_base,
1042                                 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1043         } else {
1044                 /*
1045                  * HDMI IP uses this configuration to divide the MCLK to
1046                  * update CTS value.
1047                  */
1048                 REG_FLD_MOD(av_base,
1049                                 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1050
1051                 /* Configure clock for audio packets */
1052                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1053                                 cfg->aud_par_busclk, 7, 0);
1054                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1055                                 (cfg->aud_par_busclk >> 8), 7, 0);
1056                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1057                                 (cfg->aud_par_busclk >> 16), 7, 0);
1058         }
1059
1060         /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1061         REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1062                                                 cfg->fs_override, 1, 1);
1063
1064         /* I2S parameters */
1065         REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4,
1066                                                 cfg->freq_sample, 3, 0);
1067
1068         r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1069         r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1070         r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1071         r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1072         r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1073         r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1074         r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1075         r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1076         r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1077         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1078
1079         r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5);
1080         r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1081         r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1082         r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1083         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r);
1084
1085         REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1086                         cfg->i2s_cfg.in_length_bits, 3, 0);
1087
1088         /* Audio channels and mode parameters */
1089         REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1090         r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1091         r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1092         r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1093         r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1094         r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1095         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1096 }
1097
1098 void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
1099                 struct hdmi_core_infoframe_audio *info_aud)
1100 {
1101         u8 val;
1102         u8 sum = 0, checksum = 0;
1103         void __iomem *av_base = hdmi_av_base(ip_data);
1104
1105         /*
1106          * Set audio info frame type, version and length as
1107          * described in HDMI 1.4a Section 8.2.2 specification.
1108          * Checksum calculation is defined in Section 5.3.5.
1109          */
1110         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1111         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1112         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1113         sum += 0x84 + 0x001 + 0x00a;
1114
1115         val = (info_aud->db1_coding_type << 4)
1116                         | (info_aud->db1_channel_count - 1);
1117         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val);
1118         sum += val;
1119
1120         val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1121         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val);
1122         sum += val;
1123
1124         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1125
1126         val = info_aud->db4_channel_alloc;
1127         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val);
1128         sum += val;
1129
1130         val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1131         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val);
1132         sum += val;
1133
1134         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1135         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1136         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1137         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1138         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1139
1140         checksum = 0x100 - sum;
1141         hdmi_write_reg(av_base,
1142                                         HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1143
1144         /*
1145          * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1146          * is available.
1147          */
1148 }
1149
1150 int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
1151                                 u32 sample_freq, u32 *n, u32 *cts)
1152 {
1153         u32 r;
1154         u32 deep_color = 0;
1155         u32 pclk = ip_data->cfg.timings.timings.pixel_clock;
1156
1157         if (n == NULL || cts == NULL)
1158                 return -EINVAL;
1159         /*
1160          * Obtain current deep color configuration. This needed
1161          * to calculate the TMDS clock based on the pixel clock.
1162          */
1163         r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0);
1164         switch (r) {
1165         case 1: /* No deep color selected */
1166                 deep_color = 100;
1167                 break;
1168         case 2: /* 10-bit deep color selected */
1169                 deep_color = 125;
1170                 break;
1171         case 3: /* 12-bit deep color selected */
1172                 deep_color = 150;
1173                 break;
1174         default:
1175                 return -EINVAL;
1176         }
1177
1178         switch (sample_freq) {
1179         case 32000:
1180                 if ((deep_color == 125) && ((pclk == 54054)
1181                                 || (pclk == 74250)))
1182                         *n = 8192;
1183                 else
1184                         *n = 4096;
1185                 break;
1186         case 44100:
1187                 *n = 6272;
1188                 break;
1189         case 48000:
1190                 if ((deep_color == 125) && ((pclk == 54054)
1191                                 || (pclk == 74250)))
1192                         *n = 8192;
1193                 else
1194                         *n = 6144;
1195                 break;
1196         default:
1197                 *n = 0;
1198                 return -EINVAL;
1199         }
1200
1201         /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1202         *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1203
1204         return 0;
1205 }
1206
1207 void ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data, bool enable)
1208 {
1209         REG_FLD_MOD(hdmi_av_base(ip_data),
1210                                 HDMI_CORE_AV_AUD_MODE, enable, 0, 0);
1211         REG_FLD_MOD(hdmi_wp_base(ip_data),
1212                                 HDMI_WP_AUDIO_CTRL, enable, 31, 31);
1213         REG_FLD_MOD(hdmi_wp_base(ip_data),
1214                                 HDMI_WP_AUDIO_CTRL, enable, 30, 30);
1215 }
1216 #endif