drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum omap_parallel_interface_mode {
 101         OMAP_DSS_PARALLELMODE_BYPASS,           /* MIPI DPI */
 102         OMAP_DSS_PARALLELMODE_RFBI,             /* MIPI DBI */
 103         OMAP_DSS_PARALLELMODE_DSI,
 104 };
 105
 106 enum dss_hdmi_venc_clk_source_select {
 107         DSS_VENC_TV_CLK = 0,
 108         DSS_HDMI_M_PCLK = 1,
 109 };
 110
 111 struct dss_clock_info {
 112         /* rates that we get with dividers below */
 113         unsigned long fck;
 114
 115         /* dividers */
 116         u16 fck_div;
 117 };
 118
 119 struct dispc_clock_info {
 120         /* rates that we get with dividers below */
 121         unsigned long lck;
 122         unsigned long pck;
 123
 124         /* dividers */
 125         u16 lck_div;
 126         u16 pck_div;
 127 };
 128
 129 struct dsi_clock_info {
 130         /* rates that we get with dividers below */
 131         unsigned long fint;
 132         unsigned long clkin4ddr;
 133         unsigned long clkin;
 134         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 135                                                  * OMAP4: PLLx_CLK1 */
 136         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 137                                                  * OMAP4: PLLx_CLK2 */
 138         unsigned long lp_clk;
 139
 140         /* dividers */
 141         u16 regn;
 142         u16 regm;
 143         u16 regm_dispc; /* OMAP3: REGM3
 144                          * OMAP4: REGM4 */
 145         u16 regm_dsi;   /* OMAP3: REGM4
 146                          * OMAP4: REGM5 */
 147         u16 lp_clk_div;
 148
 149         u8 highfreq;
 150         bool use_sys_clk;
 151 };
 152
 153 /* HDMI PLL structure */
 154 struct hdmi_pll_info {
 155         u16 regn;
 156         u16 regm;
 157         u32 regmf;
 158         u16 regm2;
 159         u16 regsd;
 160         u16 dcofreq;
 161 };
 162
 163 struct seq_file;
 164 struct platform_device;
 165
 166 /* core */
 167 struct bus_type *dss_get_bus(void);
 168 struct regulator *dss_get_vdds_dsi(void);
 169 struct regulator *dss_get_vdds_sdi(void);
 170
 171 /* display */
 172 int dss_suspend_all_devices(void);
 173 int dss_resume_all_devices(void);
 174 void dss_disable_all_devices(void);
 175
 176 void dss_init_device(struct platform_device *pdev,
 177                 struct omap_dss_device *dssdev);
 178 void dss_uninit_device(struct platform_device *pdev,
 179                 struct omap_dss_device *dssdev);
 180 bool dss_use_replication(struct omap_dss_device *dssdev,
 181                 enum omap_color_mode mode);
 182 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 183                 u32 fifo_size, u32 burst_size,
 184                 u32 *fifo_low, u32 *fifo_high);
 185
 186 /* manager */
 187 int dss_init_overlay_managers(struct platform_device *pdev);
 188 void dss_uninit_overlay_managers(struct platform_device *pdev);
 189 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 190 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 191                                 u16 *x, u16 *y, u16 *w, u16 *h,
 192                                 bool enlarge_update_area);
 193 void dss_start_update(struct omap_dss_device *dssdev);
 194
 195 /* overlay */
 196 void dss_init_overlays(struct platform_device *pdev);
 197 void dss_uninit_overlays(struct platform_device *pdev);
 198 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 199 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 200 #ifdef L4_EXAMPLE
 201 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 202 #endif
 203 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 204
 205 /* DSS */
 206 int dss_init_platform_driver(void);
 207 void dss_uninit_platform_driver(void);
 208
 209 int dss_runtime_get(void);
 210 void dss_runtime_put(void);
 211
 212 struct clk *dss_get_ick(void);
 213
 214 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 215 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 216 void dss_dump_clocks(struct seq_file *s);
 217
 218 void dss_dump_regs(struct seq_file *s);
 219 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 220 void dss_debug_dump_clocks(struct seq_file *s);
 221 #endif
 222
 223 void dss_sdi_init(u8 datapairs);
 224 int dss_sdi_enable(void);
 225 void dss_sdi_disable(void);
 226
 227 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 228 void dss_select_dsi_clk_source(int dsi_module,
 229                 enum omap_dss_clk_source clk_src);
 230 void dss_select_lcd_clk_source(enum omap_channel channel,
 231                 enum omap_dss_clk_source clk_src);
 232 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 233 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 234 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 235
 236 void dss_set_venc_output(enum omap_dss_venc_type type);
 237 void dss_set_dac_pwrdn_bgz(bool enable);
 238
 239 unsigned long dss_get_dpll4_rate(void);
 240 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 241 int dss_set_clock_div(struct dss_clock_info *cinfo);
 242 int dss_get_clock_div(struct dss_clock_info *cinfo);
 243 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 244                 struct dss_clock_info *dss_cinfo,
 245                 struct dispc_clock_info *dispc_cinfo);
 246
 247 /* SDI */
 248 #ifdef CONFIG_OMAP2_DSS_SDI
 249 int sdi_init(void);
 250 void sdi_exit(void);
 251 int sdi_init_display(struct omap_dss_device *display);
 252 #else
 253 static inline int sdi_init(void)
 254 {
 255         return 0;
 256 }
 257 static inline void sdi_exit(void)
 258 {
 259 }
 260 #endif
 261
 262 /* DSI */
 263 #ifdef CONFIG_OMAP2_DSS_DSI
 264
 265 struct dentry;
 266 struct file_operations;
 267
 268 int dsi_init_platform_driver(void);
 269 void dsi_uninit_platform_driver(void);
 270
 271 int dsi_runtime_get(struct platform_device *dsidev);
 272 void dsi_runtime_put(struct platform_device *dsidev);
 273
 274 void dsi_dump_clocks(struct seq_file *s);
 275 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
 276                 const struct file_operations *debug_fops);
 277 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
 278                 const struct file_operations *debug_fops);
 279
 280 int dsi_init_display(struct omap_dss_device *display);
 281 void dsi_irq_handler(void);
 282 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 283 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 284                 struct dsi_clock_info *cinfo);
 285 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
 286                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 287                 struct dispc_clock_info *dispc_cinfo);
 288 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 289                 bool enable_hsdiv);
 290 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 291 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 292                 u32 fifo_size, u32 burst_size,
 293                 u32 *fifo_low, u32 *fifo_high);
 294 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 295 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 296 struct platform_device *dsi_get_dsidev_from_id(int module);
 297 #else
 298 static inline int dsi_init_platform_driver(void)
 299 {
 300         return 0;
 301 }
 302 static inline void dsi_uninit_platform_driver(void)
 303 {
 304 }
 305 static inline int dsi_runtime_get(struct platform_device *dsidev)
 306 {
 307         return 0;
 308 }
 309 static inline void dsi_runtime_put(struct platform_device *dsidev)
 310 {
 311 }
 312 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 313 {
 314         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 315         return 0;
 316 }
 317 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 318                 struct dsi_clock_info *cinfo)
 319 {
 320         WARN("%s: DSI not compiled in\n", __func__);
 321         return -ENODEV;
 322 }
 323 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 324                 bool is_tft, unsigned long req_pck,
 325                 struct dsi_clock_info *dsi_cinfo,
 326                 struct dispc_clock_info *dispc_cinfo)
 327 {
 328         WARN("%s: DSI not compiled in\n", __func__);
 329         return -ENODEV;
 330 }
 331 static inline int dsi_pll_init(struct platform_device *dsidev,
 332                 bool enable_hsclk, bool enable_hsdiv)
 333 {
 334         WARN("%s: DSI not compiled in\n", __func__);
 335         return -ENODEV;
 336 }
 337 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 338                 bool disconnect_lanes)
 339 {
 340 }
 341 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 342 {
 343 }
 344 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 345 {
 346 }
 347 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 348 {
 349         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
 350                         __func__);
 351         return NULL;
 352 }
 353 #endif
 354
 355 /* DPI */
 356 #ifdef CONFIG_OMAP2_DSS_DPI
 357 int dpi_init(void);
 358 void dpi_exit(void);
 359 int dpi_init_display(struct omap_dss_device *dssdev);
 360 #else
 361 static inline int dpi_init(void)
 362 {
 363         return 0;
 364 }
 365 static inline void dpi_exit(void)
 366 {
 367 }
 368 #endif
 369
 370 /* DISPC */
 371 int dispc_init_platform_driver(void);
 372 void dispc_uninit_platform_driver(void);
 373 void dispc_dump_clocks(struct seq_file *s);
 374 void dispc_dump_irqs(struct seq_file *s);
 375 void dispc_dump_regs(struct seq_file *s);
 376 void dispc_irq_handler(void);
 377 void dispc_fake_vsync_irq(void);
 378
 379 int dispc_runtime_get(void);
 380 void dispc_runtime_put(void);
 381
 382 void dispc_enable_sidle(void);
 383 void dispc_disable_sidle(void);
 384
 385 void dispc_lcd_enable_signal_polarity(bool act_high);
 386 void dispc_lcd_enable_signal(bool enable);
 387 void dispc_pck_free_enable(bool enable);
 388 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
 389
 390 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 391 void dispc_set_digit_size(u16 width, u16 height);
 392 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 393 void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 394 void dispc_enable_fifomerge(bool enable);
 395 u32 dispc_get_burst_size(enum omap_plane plane);
 396 void dispc_enable_cpr(enum omap_channel channel, bool enable);
 397 void dispc_set_cpr_coef(enum omap_channel channel,
 398                 struct omap_dss_cpr_coefs *coefs);
 399
 400 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
 401 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
 402 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
 403 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 404 void dispc_set_channel_out(enum omap_plane plane,
 405                 enum omap_channel channel_out);
 406
 407 void dispc_enable_gamma_table(bool enable);
 408 int dispc_setup_plane(enum omap_plane plane,
 409                       u32 paddr, u16 screen_width,
 410                       u16 pos_x, u16 pos_y,
 411                       u16 width, u16 height,
 412                       u16 out_width, u16 out_height,
 413                       enum omap_color_mode color_mode,
 414                       bool ilace,
 415                       enum omap_dss_rotation_type rotation_type,
 416                       u8 rotation, bool mirror,
 417                       u8 global_alpha, u8 pre_mult_alpha,
 418                       enum omap_channel channel,
 419                       u32 puv_addr);
 420
 421 bool dispc_go_busy(enum omap_channel channel);
 422 void dispc_go(enum omap_channel channel);
 423 void dispc_enable_channel(enum omap_channel channel, bool enable);
 424 bool dispc_is_channel_enabled(enum omap_channel channel);
 425 int dispc_enable_plane(enum omap_plane plane, bool enable);
 426 void dispc_enable_replication(enum omap_plane plane, bool enable);
 427
 428 void dispc_set_parallel_interface_mode(enum omap_channel channel,
 429                 enum omap_parallel_interface_mode mode);
 430 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 431 void dispc_set_lcd_display_type(enum omap_channel channel,
 432                 enum omap_lcd_display_type type);
 433 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 434
 435 void dispc_set_default_color(enum omap_channel channel, u32 color);
 436 u32 dispc_get_default_color(enum omap_channel channel);
 437 void dispc_set_trans_key(enum omap_channel ch,
 438                 enum omap_dss_trans_key_type type,
 439                 u32 trans_key);
 440 void dispc_get_trans_key(enum omap_channel ch,
 441                 enum omap_dss_trans_key_type *type,
 442                 u32 *trans_key);
 443 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
 444 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
 445 bool dispc_trans_key_enabled(enum omap_channel ch);
 446 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 447
 448 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 449 void dispc_set_lcd_timings(enum omap_channel channel,
 450                 struct omap_video_timings *timings);
 451 unsigned long dispc_fclk_rate(void);
 452 unsigned long dispc_lclk_rate(enum omap_channel channel);
 453 unsigned long dispc_pclk_rate(enum omap_channel channel);
 454 void dispc_set_pol_freq(enum omap_channel channel,
 455                 enum omap_panel_config config, u8 acbi, u8 acb);
 456 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 457                 struct dispc_clock_info *cinfo);
 458 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 459                 struct dispc_clock_info *cinfo);
 460 int dispc_set_clock_div(enum omap_channel channel,
 461                 struct dispc_clock_info *cinfo);
 462 int dispc_get_clock_div(enum omap_channel channel,
 463                 struct dispc_clock_info *cinfo);
 464
 465
 466 /* VENC */
 467 #ifdef CONFIG_OMAP2_DSS_VENC
 468 int venc_init_platform_driver(void);
 469 void venc_uninit_platform_driver(void);
 470 void venc_dump_regs(struct seq_file *s);
 471 int venc_init_display(struct omap_dss_device *display);
 472 #else
 473 static inline int venc_init_platform_driver(void)
 474 {
 475         return 0;
 476 }
 477 static inline void venc_uninit_platform_driver(void)
 478 {
 479 }
 480 #endif
 481
 482 /* HDMI */
 483 #ifdef CONFIG_OMAP4_DSS_HDMI
 484 int hdmi_init_platform_driver(void);
 485 void hdmi_uninit_platform_driver(void);
 486 int hdmi_init_display(struct omap_dss_device *dssdev);
 487 #else
 488 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 489 {
 490         return 0;
 491 }
 492 static inline int hdmi_init_platform_driver(void)
 493 {
 494         return 0;
 495 }
 496 static inline void hdmi_uninit_platform_driver(void)
 497 {
 498 }
 499 #endif
 500 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 501 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 502 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 503 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 504                                         struct omap_video_timings *timings);
 505 int hdmi_panel_init(void);
 506 void hdmi_panel_exit(void);
 507
 508 /* RFBI */
 509 #ifdef CONFIG_OMAP2_DSS_RFBI
 510 int rfbi_init_platform_driver(void);
 511 void rfbi_uninit_platform_driver(void);
 512 void rfbi_dump_regs(struct seq_file *s);
 513 int rfbi_init_display(struct omap_dss_device *display);
 514 #else
 515 static inline int rfbi_init_platform_driver(void)
 516 {
 517         return 0;
 518 }
 519 static inline void rfbi_uninit_platform_driver(void)
 520 {
 521 }
 522 #endif
 523
 524
 525 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 526 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 527 {
 528         int b;
 529         for (b = 0; b < 32; ++b) {
 530                 if (irqstatus & (1 << b))
 531                         irq_arr[b]++;
 532         }
 533 }
 534 #endif
 535
 536 #endif