drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/clk.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <video/omapdss.h>
  35 #include <plat/clock.h>
  36 #include "dss.h"
  37 #include "dss_features.h"
  38
  39 #define DSS_SZ_REGS                     SZ_512
  40
  41 struct dss_reg {
  42         u16 idx;
  43 };
  44
  45 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  46
  47 #define DSS_REVISION                    DSS_REG(0x0000)
  48 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  49 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  50 #define DSS_CONTROL                     DSS_REG(0x0040)
  51 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  52 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  53 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  54
  55 #define REG_GET(idx, start, end) \
  56         FLD_GET(dss_read_reg(idx), start, end)
  57
  58 #define REG_FLD_MOD(idx, val, start, end) \
  59         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  60
  61 static struct {
  62         struct platform_device *pdev;
  63         void __iomem    *base;
  64
  65         struct clk      *dpll4_m4_ck;
  66         struct clk      *dss_clk;
  67
  68         unsigned long   cache_req_pck;
  69         unsigned long   cache_prate;
  70         struct dss_clock_info cache_dss_cinfo;
  71         struct dispc_clock_info cache_dispc_cinfo;
  72
  73         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  74         enum omap_dss_clk_source dispc_clk_source;
  75         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  76
  77         bool            ctx_valid;
  78         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  79 } dss;
  80
  81 static const char * const dss_generic_clk_source_names[] = {
  82         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  83         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  84         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
  85 };
  86
  87 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  88 {
  89         __raw_writel(val, dss.base + idx.idx);
  90 }
  91
  92 static inline u32 dss_read_reg(const struct dss_reg idx)
  93 {
  94         return __raw_readl(dss.base + idx.idx);
  95 }
  96
  97 #define SR(reg) \
  98         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
  99 #define RR(reg) \
 100         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 101
 102 static void dss_save_context(void)
 103 {
 104         DSSDBG("dss_save_context\n");
 105
 106         SR(CONTROL);
 107
 108         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 109                         OMAP_DISPLAY_TYPE_SDI) {
 110                 SR(SDI_CONTROL);
 111                 SR(PLL_CONTROL);
 112         }
 113
 114         dss.ctx_valid = true;
 115
 116         DSSDBG("context saved\n");
 117 }
 118
 119 static void dss_restore_context(void)
 120 {
 121         DSSDBG("dss_restore_context\n");
 122
 123         if (!dss.ctx_valid)
 124                 return;
 125
 126         RR(CONTROL);
 127
 128         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 129                         OMAP_DISPLAY_TYPE_SDI) {
 130                 RR(SDI_CONTROL);
 131                 RR(PLL_CONTROL);
 132         }
 133
 134         DSSDBG("context restored\n");
 135 }
 136
 137 #undef SR
 138 #undef RR
 139
 140 void dss_sdi_init(u8 datapairs)
 141 {
 142         u32 l;
 143
 144         BUG_ON(datapairs > 3 || datapairs < 1);
 145
 146         l = dss_read_reg(DSS_SDI_CONTROL);
 147         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 148         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 149         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 150         dss_write_reg(DSS_SDI_CONTROL, l);
 151
 152         l = dss_read_reg(DSS_PLL_CONTROL);
 153         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 154         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 155         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 156         dss_write_reg(DSS_PLL_CONTROL, l);
 157 }
 158
 159 int dss_sdi_enable(void)
 160 {
 161         unsigned long timeout;
 162
 163         dispc_pck_free_enable(1);
 164
 165         /* Reset SDI PLL */
 166         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 167         udelay(1);      /* wait 2x PCLK */
 168
 169         /* Lock SDI PLL */
 170         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 171
 172         /* Waiting for PLL lock request to complete */
 173         timeout = jiffies + msecs_to_jiffies(500);
 174         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 175                 if (time_after_eq(jiffies, timeout)) {
 176                         DSSERR("PLL lock request timed out\n");
 177                         goto err1;
 178                 }
 179         }
 180
 181         /* Clearing PLL_GO bit */
 182         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 183
 184         /* Waiting for PLL to lock */
 185         timeout = jiffies + msecs_to_jiffies(500);
 186         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 187                 if (time_after_eq(jiffies, timeout)) {
 188                         DSSERR("PLL lock timed out\n");
 189                         goto err1;
 190                 }
 191         }
 192
 193         dispc_lcd_enable_signal(1);
 194
 195         /* Waiting for SDI reset to complete */
 196         timeout = jiffies + msecs_to_jiffies(500);
 197         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 198                 if (time_after_eq(jiffies, timeout)) {
 199                         DSSERR("SDI reset timed out\n");
 200                         goto err2;
 201                 }
 202         }
 203
 204         return 0;
 205
 206  err2:
 207         dispc_lcd_enable_signal(0);
 208  err1:
 209         /* Reset SDI PLL */
 210         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 211
 212         dispc_pck_free_enable(0);
 213
 214         return -ETIMEDOUT;
 215 }
 216
 217 void dss_sdi_disable(void)
 218 {
 219         dispc_lcd_enable_signal(0);
 220
 221         dispc_pck_free_enable(0);
 222
 223         /* Reset SDI PLL */
 224         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 225 }
 226
 227 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 228 {
 229         return dss_generic_clk_source_names[clk_src];
 230 }
 231
 232
 233 void dss_dump_clocks(struct seq_file *s)
 234 {
 235         unsigned long dpll4_ck_rate;
 236         unsigned long dpll4_m4_ck_rate;
 237         const char *fclk_name, *fclk_real_name;
 238         unsigned long fclk_rate;
 239
 240         if (dss_runtime_get())
 241                 return;
 242
 243         seq_printf(s, "- DSS -\n");
 244
 245         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 246         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 247         fclk_rate = clk_get_rate(dss.dss_clk);
 248
 249         if (dss.dpll4_m4_ck) {
 250                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 251                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 252
 253                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 254
 255                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 256                         seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
 257                                         fclk_name, fclk_real_name,
 258                                         dpll4_ck_rate,
 259                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 260                                         fclk_rate);
 261                 else
 262                         seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
 263                                         fclk_name, fclk_real_name,
 264                                         dpll4_ck_rate,
 265                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 266                                         fclk_rate);
 267         } else {
 268                 seq_printf(s, "%s (%s) = %lu\n",
 269                                 fclk_name, fclk_real_name,
 270                                 fclk_rate);
 271         }
 272
 273         dss_runtime_put();
 274 }
 275
 276 void dss_dump_regs(struct seq_file *s)
 277 {
 278 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 279
 280         if (dss_runtime_get())
 281                 return;
 282
 283         DUMPREG(DSS_REVISION);
 284         DUMPREG(DSS_SYSCONFIG);
 285         DUMPREG(DSS_SYSSTATUS);
 286         DUMPREG(DSS_CONTROL);
 287
 288         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 289                         OMAP_DISPLAY_TYPE_SDI) {
 290                 DUMPREG(DSS_SDI_CONTROL);
 291                 DUMPREG(DSS_PLL_CONTROL);
 292                 DUMPREG(DSS_SDI_STATUS);
 293         }
 294
 295         dss_runtime_put();
 296 #undef DUMPREG
 297 }
 298
 299 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 300 {
 301         struct platform_device *dsidev;
 302         int b;
 303         u8 start, end;
 304
 305         switch (clk_src) {
 306         case OMAP_DSS_CLK_SRC_FCK:
 307                 b = 0;
 308                 break;
 309         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 310                 b = 1;
 311                 dsidev = dsi_get_dsidev_from_id(0);
 312                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 313                 break;
 314         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 315                 b = 2;
 316                 dsidev = dsi_get_dsidev_from_id(1);
 317                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 318                 break;
 319         default:
 320                 BUG();
 321         }
 322
 323         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 324
 325         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 326
 327         dss.dispc_clk_source = clk_src;
 328 }
 329
 330 void dss_select_dsi_clk_source(int dsi_module,
 331                 enum omap_dss_clk_source clk_src)
 332 {
 333         struct platform_device *dsidev;
 334         int b;
 335
 336         switch (clk_src) {
 337         case OMAP_DSS_CLK_SRC_FCK:
 338                 b = 0;
 339                 break;
 340         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 341                 BUG_ON(dsi_module != 0);
 342                 b = 1;
 343                 dsidev = dsi_get_dsidev_from_id(0);
 344                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 345                 break;
 346         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 347                 BUG_ON(dsi_module != 1);
 348                 b = 1;
 349                 dsidev = dsi_get_dsidev_from_id(1);
 350                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 351                 break;
 352         default:
 353                 BUG();
 354         }
 355
 356         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 357
 358         dss.dsi_clk_source[dsi_module] = clk_src;
 359 }
 360
 361 void dss_select_lcd_clk_source(enum omap_channel channel,
 362                 enum omap_dss_clk_source clk_src)
 363 {
 364         struct platform_device *dsidev;
 365         int b, ix, pos;
 366
 367         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 368                 return;
 369
 370         switch (clk_src) {
 371         case OMAP_DSS_CLK_SRC_FCK:
 372                 b = 0;
 373                 break;
 374         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 375                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 376                 b = 1;
 377                 dsidev = dsi_get_dsidev_from_id(0);
 378                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 379                 break;
 380         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 381                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
 382                 b = 1;
 383                 dsidev = dsi_get_dsidev_from_id(1);
 384                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 385                 break;
 386         default:
 387                 BUG();
 388         }
 389
 390         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
 391         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 392
 393         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 394         dss.lcd_clk_source[ix] = clk_src;
 395 }
 396
 397 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 398 {
 399         return dss.dispc_clk_source;
 400 }
 401
 402 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 403 {
 404         return dss.dsi_clk_source[dsi_module];
 405 }
 406
 407 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 408 {
 409         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 410                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 411                 return dss.lcd_clk_source[ix];
 412         } else {
 413                 /* LCD_CLK source is the same as DISPC_FCLK source for
 414                  * OMAP2 and OMAP3 */
 415                 return dss.dispc_clk_source;
 416         }
 417 }
 418
 419 /* calculate clock rates using dividers in cinfo */
 420 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 421 {
 422         if (dss.dpll4_m4_ck) {
 423                 unsigned long prate;
 424                 u16 fck_div_max = 16;
 425
 426                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 427                         fck_div_max = 32;
 428
 429                 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
 430                         return -EINVAL;
 431
 432                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 433
 434                 cinfo->fck = prate / cinfo->fck_div;
 435         } else {
 436                 if (cinfo->fck_div != 0)
 437                         return -EINVAL;
 438                 cinfo->fck = clk_get_rate(dss.dss_clk);
 439         }
 440
 441         return 0;
 442 }
 443
 444 int dss_set_clock_div(struct dss_clock_info *cinfo)
 445 {
 446         if (dss.dpll4_m4_ck) {
 447                 unsigned long prate;
 448                 int r;
 449
 450                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 451                 DSSDBG("dpll4_m4 = %ld\n", prate);
 452
 453                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 454                 if (r)
 455                         return r;
 456         } else {
 457                 if (cinfo->fck_div != 0)
 458                         return -EINVAL;
 459         }
 460
 461         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 462
 463         return 0;
 464 }
 465
 466 int dss_get_clock_div(struct dss_clock_info *cinfo)
 467 {
 468         cinfo->fck = clk_get_rate(dss.dss_clk);
 469
 470         if (dss.dpll4_m4_ck) {
 471                 unsigned long prate;
 472
 473                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 474
 475                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 476                         cinfo->fck_div = prate / (cinfo->fck);
 477                 else
 478                         cinfo->fck_div = prate / (cinfo->fck / 2);
 479         } else {
 480                 cinfo->fck_div = 0;
 481         }
 482
 483         return 0;
 484 }
 485
 486 unsigned long dss_get_dpll4_rate(void)
 487 {
 488         if (dss.dpll4_m4_ck)
 489                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 490         else
 491                 return 0;
 492 }
 493
 494 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 495                 struct dss_clock_info *dss_cinfo,
 496                 struct dispc_clock_info *dispc_cinfo)
 497 {
 498         unsigned long prate;
 499         struct dss_clock_info best_dss;
 500         struct dispc_clock_info best_dispc;
 501
 502         unsigned long fck, max_dss_fck;
 503
 504         u16 fck_div, fck_div_max = 16;
 505
 506         int match = 0;
 507         int min_fck_per_pck;
 508
 509         prate = dss_get_dpll4_rate();
 510
 511         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 512
 513         fck = clk_get_rate(dss.dss_clk);
 514         if (req_pck == dss.cache_req_pck &&
 515                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 516                          dss.cache_dss_cinfo.fck == fck)) {
 517                 DSSDBG("dispc clock info found from cache.\n");
 518                 *dss_cinfo = dss.cache_dss_cinfo;
 519                 *dispc_cinfo = dss.cache_dispc_cinfo;
 520                 return 0;
 521         }
 522
 523         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 524
 525         if (min_fck_per_pck &&
 526                 req_pck * min_fck_per_pck > max_dss_fck) {
 527                 DSSERR("Requested pixel clock not possible with the current "
 528                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 529                                 "the constraint off.\n");
 530                 min_fck_per_pck = 0;
 531         }
 532
 533 retry:
 534         memset(&best_dss, 0, sizeof(best_dss));
 535         memset(&best_dispc, 0, sizeof(best_dispc));
 536
 537         if (dss.dpll4_m4_ck == NULL) {
 538                 struct dispc_clock_info cur_dispc;
 539                 /* XXX can we change the clock on omap2? */
 540                 fck = clk_get_rate(dss.dss_clk);
 541                 fck_div = 1;
 542
 543                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 544                 match = 1;
 545
 546                 best_dss.fck = fck;
 547                 best_dss.fck_div = fck_div;
 548
 549                 best_dispc = cur_dispc;
 550
 551                 goto found;
 552         } else {
 553                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 554                         fck_div_max = 32;
 555
 556                 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
 557                         struct dispc_clock_info cur_dispc;
 558
 559                         if (fck_div_max == 32)
 560                                 fck = prate / fck_div;
 561                         else
 562                                 fck = prate / fck_div * 2;
 563
 564                         if (fck > max_dss_fck)
 565                                 continue;
 566
 567                         if (min_fck_per_pck &&
 568                                         fck < req_pck * min_fck_per_pck)
 569                                 continue;
 570
 571                         match = 1;
 572
 573                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 574
 575                         if (abs(cur_dispc.pck - req_pck) <
 576                                         abs(best_dispc.pck - req_pck)) {
 577
 578                                 best_dss.fck = fck;
 579                                 best_dss.fck_div = fck_div;
 580
 581                                 best_dispc = cur_dispc;
 582
 583                                 if (cur_dispc.pck == req_pck)
 584                                         goto found;
 585                         }
 586                 }
 587         }
 588
 589 found:
 590         if (!match) {
 591                 if (min_fck_per_pck) {
 592                         DSSERR("Could not find suitable clock settings.\n"
 593                                         "Turning FCK/PCK constraint off and"
 594                                         "trying again.\n");
 595                         min_fck_per_pck = 0;
 596                         goto retry;
 597                 }
 598
 599                 DSSERR("Could not find suitable clock settings.\n");
 600
 601                 return -EINVAL;
 602         }
 603
 604         if (dss_cinfo)
 605                 *dss_cinfo = best_dss;
 606         if (dispc_cinfo)
 607                 *dispc_cinfo = best_dispc;
 608
 609         dss.cache_req_pck = req_pck;
 610         dss.cache_prate = prate;
 611         dss.cache_dss_cinfo = best_dss;
 612         dss.cache_dispc_cinfo = best_dispc;
 613
 614         return 0;
 615 }
 616
 617 void dss_set_venc_output(enum omap_dss_venc_type type)
 618 {
 619         int l = 0;
 620
 621         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 622                 l = 0;
 623         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 624                 l = 1;
 625         else
 626                 BUG();
 627
 628         /* venc out selection. 0 = comp, 1 = svideo */
 629         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 630 }
 631
 632 void dss_set_dac_pwrdn_bgz(bool enable)
 633 {
 634         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 635 }
 636
 637 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 638 {
 639         REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
 640 }
 641
 642 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 643 {
 644         enum omap_display_type displays;
 645
 646         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 647         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 648                 return DSS_VENC_TV_CLK;
 649
 650         return REG_GET(DSS_CONTROL, 15, 15);
 651 }
 652
 653 static int dss_get_clocks(void)
 654 {
 655         struct clk *clk;
 656         int r;
 657
 658         clk = clk_get(&dss.pdev->dev, "fck");
 659         if (IS_ERR(clk)) {
 660                 DSSERR("can't get clock fck\n");
 661                 r = PTR_ERR(clk);
 662                 goto err;
 663         }
 664
 665         dss.dss_clk = clk;
 666
 667         if (cpu_is_omap34xx()) {
 668                 clk = clk_get(NULL, "dpll4_m4_ck");
 669                 if (IS_ERR(clk)) {
 670                         DSSERR("Failed to get dpll4_m4_ck\n");
 671                         r = PTR_ERR(clk);
 672                         goto err;
 673                 }
 674         } else if (cpu_is_omap44xx()) {
 675                 clk = clk_get(NULL, "dpll_per_m5x2_ck");
 676                 if (IS_ERR(clk)) {
 677                         DSSERR("Failed to get dpll_per_m5x2_ck\n");
 678                         r = PTR_ERR(clk);
 679                         goto err;
 680                 }
 681         } else { /* omap24xx */
 682                 clk = NULL;
 683         }
 684
 685         dss.dpll4_m4_ck = clk;
 686
 687         return 0;
 688
 689 err:
 690         if (dss.dss_clk)
 691                 clk_put(dss.dss_clk);
 692         if (dss.dpll4_m4_ck)
 693                 clk_put(dss.dpll4_m4_ck);
 694
 695         return r;
 696 }
 697
 698 static void dss_put_clocks(void)
 699 {
 700         if (dss.dpll4_m4_ck)
 701                 clk_put(dss.dpll4_m4_ck);
 702         clk_put(dss.dss_clk);
 703 }
 704
 705 int dss_runtime_get(void)
 706 {
 707         int r;
 708
 709         DSSDBG("dss_runtime_get\n");
 710
 711         r = pm_runtime_get_sync(&dss.pdev->dev);
 712         WARN_ON(r < 0);
 713         return r < 0 ? r : 0;
 714 }
 715
 716 void dss_runtime_put(void)
 717 {
 718         int r;
 719
 720         DSSDBG("dss_runtime_put\n");
 721
 722         r = pm_runtime_put(&dss.pdev->dev);
 723         WARN_ON(r < 0);
 724 }
 725
 726 /* DEBUGFS */
 727 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 728 void dss_debug_dump_clocks(struct seq_file *s)
 729 {
 730         dss_dump_clocks(s);
 731         dispc_dump_clocks(s);
 732 #ifdef CONFIG_OMAP2_DSS_DSI
 733         dsi_dump_clocks(s);
 734 #endif
 735 }
 736 #endif
 737
 738 /* DSS HW IP initialisation */
 739 static int omap_dsshw_probe(struct platform_device *pdev)
 740 {
 741         struct resource *dss_mem;
 742         u32 rev;
 743         int r;
 744
 745         dss.pdev = pdev;
 746
 747         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 748         if (!dss_mem) {
 749                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 750                 r = -EINVAL;
 751                 goto err_ioremap;
 752         }
 753         dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
 754         if (!dss.base) {
 755                 DSSERR("can't ioremap DSS\n");
 756                 r = -ENOMEM;
 757                 goto err_ioremap;
 758         }
 759
 760         r = dss_get_clocks();
 761         if (r)
 762                 goto err_clocks;
 763
 764         pm_runtime_enable(&pdev->dev);
 765
 766         r = dss_runtime_get();
 767         if (r)
 768                 goto err_runtime_get;
 769
 770         /* Select DPLL */
 771         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 772
 773 #ifdef CONFIG_OMAP2_DSS_VENC
 774         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 775         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 776         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 777 #endif
 778         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 779         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 780         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 781         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 782         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 783
 784         r = dpi_init();
 785         if (r) {
 786                 DSSERR("Failed to initialize DPI\n");
 787                 goto err_dpi;
 788         }
 789
 790         r = sdi_init();
 791         if (r) {
 792                 DSSERR("Failed to initialize SDI\n");
 793                 goto err_sdi;
 794         }
 795
 796         rev = dss_read_reg(DSS_REVISION);
 797         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 798                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 799
 800         dss_runtime_put();
 801
 802         return 0;
 803 err_sdi:
 804         dpi_exit();
 805 err_dpi:
 806         dss_runtime_put();
 807 err_runtime_get:
 808         pm_runtime_disable(&pdev->dev);
 809         dss_put_clocks();
 810 err_clocks:
 811         iounmap(dss.base);
 812 err_ioremap:
 813         return r;
 814 }
 815
 816 static int omap_dsshw_remove(struct platform_device *pdev)
 817 {
 818         dpi_exit();
 819         sdi_exit();
 820
 821         iounmap(dss.base);
 822
 823         pm_runtime_disable(&pdev->dev);
 824
 825         dss_put_clocks();
 826
 827         return 0;
 828 }
 829
 830 static int dss_runtime_suspend(struct device *dev)
 831 {
 832         dss_save_context();
 833         return 0;
 834 }
 835
 836 static int dss_runtime_resume(struct device *dev)
 837 {
 838         dss_restore_context();
 839         return 0;
 840 }
 841
 842 static const struct dev_pm_ops dss_pm_ops = {
 843         .runtime_suspend = dss_runtime_suspend,
 844         .runtime_resume = dss_runtime_resume,
 845 };
 846
 847 static struct platform_driver omap_dsshw_driver = {
 848         .probe          = omap_dsshw_probe,
 849         .remove         = omap_dsshw_remove,
 850         .driver         = {
 851                 .name   = "omapdss_dss",
 852                 .owner  = THIS_MODULE,
 853                 .pm     = &dss_pm_ops,
 854         },
 855 };
 856
 857 int dss_init_platform_driver(void)
 858 {
 859         return platform_driver_register(&omap_dsshw_driver);
 860 }
 861
 862 void dss_uninit_platform_driver(void)
 863 {
 864         return platform_driver_unregister(&omap_dsshw_driver);
 865 }