drivers/video/omap/hwa742.c

   1 /*
   2  * Epson HWA742 LCD controller driver
   3  *
   4  * Copyright (C) 2004-2005 Nokia Corporation
   5  * Authors:     Juha Yrjölä   <juha.yrjola@nokia.com>
   6  *              Imre Deak     <imre.deak@nokia.com>
   7  * YUV support: Jussi Laako   <jussi.laako@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23 #include <linux/module.h>
  24 #include <linux/mm.h>
  25 #include <linux/fb.h>
  26 #include <linux/delay.h>
  27 #include <linux/clk.h>
  28 #include <linux/interrupt.h>
  29
  30 #include <plat/dma.h>
  31 #include <plat/hwa742.h>
  32 #include "omapfb.h"
  33
  34 #define HWA742_REV_CODE_REG       0x0
  35 #define HWA742_CONFIG_REG         0x2
  36 #define HWA742_PLL_DIV_REG        0x4
  37 #define HWA742_PLL_0_REG          0x6
  38 #define HWA742_PLL_1_REG          0x8
  39 #define HWA742_PLL_2_REG          0xa
  40 #define HWA742_PLL_3_REG          0xc
  41 #define HWA742_PLL_4_REG          0xe
  42 #define HWA742_CLK_SRC_REG        0x12
  43 #define HWA742_PANEL_TYPE_REG     0x14
  44 #define HWA742_H_DISP_REG         0x16
  45 #define HWA742_H_NDP_REG          0x18
  46 #define HWA742_V_DISP_1_REG       0x1a
  47 #define HWA742_V_DISP_2_REG       0x1c
  48 #define HWA742_V_NDP_REG          0x1e
  49 #define HWA742_HS_W_REG           0x20
  50 #define HWA742_HP_S_REG           0x22
  51 #define HWA742_VS_W_REG           0x24
  52 #define HWA742_VP_S_REG           0x26
  53 #define HWA742_PCLK_POL_REG       0x28
  54 #define HWA742_INPUT_MODE_REG     0x2a
  55 #define HWA742_TRANSL_MODE_REG1   0x2e
  56 #define HWA742_DISP_MODE_REG      0x34
  57 #define HWA742_WINDOW_TYPE        0x36
  58 #define HWA742_WINDOW_X_START_0   0x38
  59 #define HWA742_WINDOW_X_START_1   0x3a
  60 #define HWA742_WINDOW_Y_START_0   0x3c
  61 #define HWA742_WINDOW_Y_START_1   0x3e
  62 #define HWA742_WINDOW_X_END_0     0x40
  63 #define HWA742_WINDOW_X_END_1     0x42
  64 #define HWA742_WINDOW_Y_END_0     0x44
  65 #define HWA742_WINDOW_Y_END_1     0x46
  66 #define HWA742_MEMORY_WRITE_LSB   0x48
  67 #define HWA742_MEMORY_WRITE_MSB   0x49
  68 #define HWA742_MEMORY_READ_0      0x4a
  69 #define HWA742_MEMORY_READ_1      0x4c
  70 #define HWA742_MEMORY_READ_2      0x4e
  71 #define HWA742_POWER_SAVE         0x56
  72 #define HWA742_NDP_CTRL           0x58
  73
  74 #define HWA742_AUTO_UPDATE_TIME         (HZ / 20)
  75
  76 /* Reserve 4 request slots for requests in irq context */
  77 #define REQ_POOL_SIZE                   24
  78 #define IRQ_REQ_POOL_SIZE               4
  79
  80 #define REQ_FROM_IRQ_POOL 0x01
  81
  82 #define REQ_COMPLETE    0
  83 #define REQ_PENDING     1
  84
  85 struct update_param {
  86         int     x, y, width, height;
  87         int     color_mode;
  88         int     flags;
  89 };
  90
  91 struct hwa742_request {
  92         struct list_head entry;
  93         unsigned int     flags;
  94
  95         int              (*handler)(struct hwa742_request *req);
  96         void             (*complete)(void *data);
  97         void             *complete_data;
  98
  99         union {
 100                 struct update_param     update;
 101                 struct completion       *sync;
 102         } par;
 103 };
 104
 105 struct {
 106         enum omapfb_update_mode update_mode;
 107         enum omapfb_update_mode update_mode_before_suspend;
 108
 109         struct timer_list       auto_update_timer;
 110         int                     stop_auto_update;
 111         struct omapfb_update_window     auto_update_window;
 112         unsigned                te_connected:1;
 113         unsigned                vsync_only:1;
 114
 115         struct hwa742_request   req_pool[REQ_POOL_SIZE];
 116         struct list_head        pending_req_list;
 117         struct list_head        free_req_list;
 118         struct semaphore        req_sema;
 119         spinlock_t              req_lock;
 120
 121         struct extif_timings    reg_timings, lut_timings;
 122
 123         int                     prev_color_mode;
 124         int                     prev_flags;
 125         int                     window_type;
 126
 127         u32                     max_transmit_size;
 128         u32                     extif_clk_period;
 129         unsigned long           pix_tx_time;
 130         unsigned long           line_upd_time;
 131
 132
 133         struct omapfb_device    *fbdev;
 134         struct lcd_ctrl_extif   *extif;
 135         const struct lcd_ctrl   *int_ctrl;
 136
 137         struct clk              *sys_ck;
 138 } hwa742;
 139
 140 struct lcd_ctrl hwa742_ctrl;
 141
 142 static u8 hwa742_read_reg(u8 reg)
 143 {
 144         u8 data;
 145
 146         hwa742.extif->set_bits_per_cycle(8);
 147         hwa742.extif->write_command(&reg, 1);
 148         hwa742.extif->read_data(&data, 1);
 149
 150         return data;
 151 }
 152
 153 static void hwa742_write_reg(u8 reg, u8 data)
 154 {
 155         hwa742.extif->set_bits_per_cycle(8);
 156         hwa742.extif->write_command(&reg, 1);
 157         hwa742.extif->write_data(&data, 1);
 158 }
 159
 160 static void set_window_regs(int x_start, int y_start, int x_end, int y_end)
 161 {
 162         u8 tmp[8];
 163         u8 cmd;
 164
 165         x_end--;
 166         y_end--;
 167         tmp[0] = x_start;
 168         tmp[1] = x_start >> 8;
 169         tmp[2] = y_start;
 170         tmp[3] = y_start >> 8;
 171         tmp[4] = x_end;
 172         tmp[5] = x_end >> 8;
 173         tmp[6] = y_end;
 174         tmp[7] = y_end >> 8;
 175
 176         hwa742.extif->set_bits_per_cycle(8);
 177         cmd = HWA742_WINDOW_X_START_0;
 178
 179         hwa742.extif->write_command(&cmd, 1);
 180
 181         hwa742.extif->write_data(tmp, 8);
 182 }
 183
 184 static void set_format_regs(int conv, int transl, int flags)
 185 {
 186         if (flags & OMAPFB_FORMAT_FLAG_DOUBLE) {
 187                 hwa742.window_type = ((hwa742.window_type & 0xfc) | 0x01);
 188 #ifdef VERBOSE
 189                 dev_dbg(hwa742.fbdev->dev, "hwa742: enabled pixel doubling\n");
 190 #endif
 191         } else {
 192                 hwa742.window_type = (hwa742.window_type & 0xfc);
 193 #ifdef VERBOSE
 194                 dev_dbg(hwa742.fbdev->dev, "hwa742: disabled pixel doubling\n");
 195 #endif
 196         }
 197
 198         hwa742_write_reg(HWA742_INPUT_MODE_REG, conv);
 199         hwa742_write_reg(HWA742_TRANSL_MODE_REG1, transl);
 200         hwa742_write_reg(HWA742_WINDOW_TYPE, hwa742.window_type);
 201 }
 202
 203 static void enable_tearsync(int y, int width, int height, int screen_height,
 204                             int force_vsync)
 205 {
 206         u8 b;
 207
 208         b = hwa742_read_reg(HWA742_NDP_CTRL);
 209         b |= 1 << 2;
 210         hwa742_write_reg(HWA742_NDP_CTRL, b);
 211
 212         if (likely(hwa742.vsync_only || force_vsync)) {
 213                 hwa742.extif->enable_tearsync(1, 0);
 214                 return;
 215         }
 216
 217         if (width * hwa742.pix_tx_time < hwa742.line_upd_time) {
 218                 hwa742.extif->enable_tearsync(1, 0);
 219                 return;
 220         }
 221
 222         if ((width * hwa742.pix_tx_time / 1000) * height <
 223             (y + height) * (hwa742.line_upd_time / 1000)) {
 224                 hwa742.extif->enable_tearsync(1, 0);
 225                 return;
 226         }
 227
 228         hwa742.extif->enable_tearsync(1, y + 1);
 229 }
 230
 231 static void disable_tearsync(void)
 232 {
 233         u8 b;
 234
 235         hwa742.extif->enable_tearsync(0, 0);
 236
 237         b = hwa742_read_reg(HWA742_NDP_CTRL);
 238         b &= ~(1 << 2);
 239         hwa742_write_reg(HWA742_NDP_CTRL, b);
 240 }
 241
 242 static inline struct hwa742_request *alloc_req(void)
 243 {
 244         unsigned long flags;
 245         struct hwa742_request *req;
 246         int req_flags = 0;
 247
 248         if (!in_interrupt())
 249                 down(&hwa742.req_sema);
 250         else
 251                 req_flags = REQ_FROM_IRQ_POOL;
 252
 253         spin_lock_irqsave(&hwa742.req_lock, flags);
 254         BUG_ON(list_empty(&hwa742.free_req_list));
 255         req = list_entry(hwa742.free_req_list.next,
 256                          struct hwa742_request, entry);
 257         list_del(&req->entry);
 258         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 259
 260         INIT_LIST_HEAD(&req->entry);
 261         req->flags = req_flags;
 262
 263         return req;
 264 }
 265
 266 static inline void free_req(struct hwa742_request *req)
 267 {
 268         unsigned long flags;
 269
 270         spin_lock_irqsave(&hwa742.req_lock, flags);
 271
 272         list_move(&req->entry, &hwa742.free_req_list);
 273         if (!(req->flags & REQ_FROM_IRQ_POOL))
 274                 up(&hwa742.req_sema);
 275
 276         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 277 }
 278
 279 static void process_pending_requests(void)
 280 {
 281         unsigned long flags;
 282
 283         spin_lock_irqsave(&hwa742.req_lock, flags);
 284
 285         while (!list_empty(&hwa742.pending_req_list)) {
 286                 struct hwa742_request *req;
 287                 void (*complete)(void *);
 288                 void *complete_data;
 289
 290                 req = list_entry(hwa742.pending_req_list.next,
 291                                  struct hwa742_request, entry);
 292                 spin_unlock_irqrestore(&hwa742.req_lock, flags);
 293
 294                 if (req->handler(req) == REQ_PENDING)
 295                         return;
 296
 297                 complete = req->complete;
 298                 complete_data = req->complete_data;
 299                 free_req(req);
 300
 301                 if (complete)
 302                         complete(complete_data);
 303
 304                 spin_lock_irqsave(&hwa742.req_lock, flags);
 305         }
 306
 307         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 308 }
 309
 310 static void submit_req_list(struct list_head *head)
 311 {
 312         unsigned long flags;
 313         int process = 1;
 314
 315         spin_lock_irqsave(&hwa742.req_lock, flags);
 316         if (likely(!list_empty(&hwa742.pending_req_list)))
 317                 process = 0;
 318         list_splice_init(head, hwa742.pending_req_list.prev);
 319         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 320
 321         if (process)
 322                 process_pending_requests();
 323 }
 324
 325 static void request_complete(void *data)
 326 {
 327         struct hwa742_request   *req = (struct hwa742_request *)data;
 328         void                    (*complete)(void *);
 329         void                    *complete_data;
 330
 331         complete = req->complete;
 332         complete_data = req->complete_data;
 333
 334         free_req(req);
 335
 336         if (complete)
 337                 complete(complete_data);
 338
 339         process_pending_requests();
 340 }
 341
 342 static int send_frame_handler(struct hwa742_request *req)
 343 {
 344         struct update_param *par = &req->par.update;
 345         int x = par->x;
 346         int y = par->y;
 347         int w = par->width;
 348         int h = par->height;
 349         int bpp;
 350         int conv, transl;
 351         unsigned long offset;
 352         int color_mode = par->color_mode;
 353         int flags = par->flags;
 354         int scr_width = hwa742.fbdev->panel->x_res;
 355         int scr_height = hwa742.fbdev->panel->y_res;
 356
 357 #ifdef VERBOSE
 358         dev_dbg(hwa742.fbdev->dev, "x %d y %d w %d h %d scr_width %d "
 359                 "color_mode %d flags %d\n",
 360                 x, y, w, h, scr_width, color_mode, flags);
 361 #endif
 362
 363         switch (color_mode) {
 364         case OMAPFB_COLOR_YUV422:
 365                 bpp = 16;
 366                 conv = 0x08;
 367                 transl = 0x25;
 368                 break;
 369         case OMAPFB_COLOR_YUV420:
 370                 bpp = 12;
 371                 conv = 0x09;
 372                 transl = 0x25;
 373                 break;
 374         case OMAPFB_COLOR_RGB565:
 375                 bpp = 16;
 376                 conv = 0x01;
 377                 transl = 0x05;
 378                 break;
 379         default:
 380                 return -EINVAL;
 381         }
 382
 383         if (hwa742.prev_flags != flags ||
 384             hwa742.prev_color_mode != color_mode) {
 385                 set_format_regs(conv, transl, flags);
 386                 hwa742.prev_color_mode = color_mode;
 387                 hwa742.prev_flags = flags;
 388         }
 389         flags = req->par.update.flags;
 390         if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
 391                 enable_tearsync(y, scr_width, h, scr_height,
 392                                 flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
 393         else
 394                 disable_tearsync();
 395
 396         set_window_regs(x, y, x + w, y + h);
 397
 398         offset = (scr_width * y + x) * bpp / 8;
 399
 400         hwa742.int_ctrl->setup_plane(OMAPFB_PLANE_GFX,
 401                         OMAPFB_CHANNEL_OUT_LCD, offset, scr_width, 0, 0, w, h,
 402                         color_mode);
 403
 404         hwa742.extif->set_bits_per_cycle(16);
 405
 406         hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 1);
 407         hwa742.extif->transfer_area(w, h, request_complete, req);
 408
 409         return REQ_PENDING;
 410 }
 411
 412 static void send_frame_complete(void *data)
 413 {
 414         hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 0);
 415 }
 416
 417 #define ADD_PREQ(_x, _y, _w, _h) do {           \
 418         req = alloc_req();                      \
 419         req->handler    = send_frame_handler;   \
 420         req->complete   = send_frame_complete;  \
 421         req->par.update.x = _x;                 \
 422         req->par.update.y = _y;                 \
 423         req->par.update.width  = _w;            \
 424         req->par.update.height = _h;            \
 425         req->par.update.color_mode = color_mode;\
 426         req->par.update.flags     = flags;      \
 427         list_add_tail(&req->entry, req_head);   \
 428 } while(0)
 429
 430 static void create_req_list(struct omapfb_update_window *win,
 431                             struct list_head *req_head)
 432 {
 433         struct hwa742_request *req;
 434         int x = win->x;
 435         int y = win->y;
 436         int width = win->width;
 437         int height = win->height;
 438         int color_mode;
 439         int flags;
 440
 441         flags = win->format & ~OMAPFB_FORMAT_MASK;
 442         color_mode = win->format & OMAPFB_FORMAT_MASK;
 443
 444         if (x & 1) {
 445                 ADD_PREQ(x, y, 1, height);
 446                 width--;
 447                 x++;
 448                 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
 449         }
 450         if (width & ~1) {
 451                 unsigned int xspan = width & ~1;
 452                 unsigned int ystart = y;
 453                 unsigned int yspan = height;
 454
 455                 if (xspan * height * 2 > hwa742.max_transmit_size) {
 456                         yspan = hwa742.max_transmit_size / (xspan * 2);
 457                         ADD_PREQ(x, ystart, xspan, yspan);
 458                         ystart += yspan;
 459                         yspan = height - yspan;
 460                         flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
 461                 }
 462
 463                 ADD_PREQ(x, ystart, xspan, yspan);
 464                 x += xspan;
 465                 width -= xspan;
 466                 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
 467         }
 468         if (width)
 469                 ADD_PREQ(x, y, 1, height);
 470 }
 471
 472 static void auto_update_complete(void *data)
 473 {
 474         if (!hwa742.stop_auto_update)
 475                 mod_timer(&hwa742.auto_update_timer,
 476                           jiffies + HWA742_AUTO_UPDATE_TIME);
 477 }
 478
 479 static void hwa742_update_window_auto(unsigned long arg)
 480 {
 481         LIST_HEAD(req_list);
 482         struct hwa742_request *last;
 483
 484         create_req_list(&hwa742.auto_update_window, &req_list);
 485         last = list_entry(req_list.prev, struct hwa742_request, entry);
 486
 487         last->complete = auto_update_complete;
 488         last->complete_data = NULL;
 489
 490         submit_req_list(&req_list);
 491 }
 492
 493 int hwa742_update_window_async(struct fb_info *fbi,
 494                                  struct omapfb_update_window *win,
 495                                  void (*complete_callback)(void *arg),
 496                                  void *complete_callback_data)
 497 {
 498         LIST_HEAD(req_list);
 499         struct hwa742_request *last;
 500         int r = 0;
 501
 502         if (hwa742.update_mode != OMAPFB_MANUAL_UPDATE) {
 503                 dev_dbg(hwa742.fbdev->dev, "invalid update mode\n");
 504                 r = -EINVAL;
 505                 goto out;
 506         }
 507         if (unlikely(win->format &
 508             ~(0x03 | OMAPFB_FORMAT_FLAG_DOUBLE |
 509             OMAPFB_FORMAT_FLAG_TEARSYNC | OMAPFB_FORMAT_FLAG_FORCE_VSYNC))) {
 510                 dev_dbg(hwa742.fbdev->dev, "invalid window flag\n");
 511                 r = -EINVAL;
 512                 goto out;
 513         }
 514
 515         create_req_list(win, &req_list);
 516         last = list_entry(req_list.prev, struct hwa742_request, entry);
 517
 518         last->complete = complete_callback;
 519         last->complete_data = (void *)complete_callback_data;
 520
 521         submit_req_list(&req_list);
 522
 523 out:
 524         return r;
 525 }
 526 EXPORT_SYMBOL(hwa742_update_window_async);
 527
 528 static int hwa742_setup_plane(int plane, int channel_out,
 529                                   unsigned long offset, int screen_width,
 530                                   int pos_x, int pos_y, int width, int height,
 531                                   int color_mode)
 532 {
 533         if (plane != OMAPFB_PLANE_GFX ||
 534             channel_out != OMAPFB_CHANNEL_OUT_LCD)
 535                 return -EINVAL;
 536
 537         return 0;
 538 }
 539
 540 static int hwa742_enable_plane(int plane, int enable)
 541 {
 542         if (plane != 0)
 543                 return -EINVAL;
 544
 545         hwa742.int_ctrl->enable_plane(plane, enable);
 546
 547         return 0;
 548 }
 549
 550 static int sync_handler(struct hwa742_request *req)
 551 {
 552         complete(req->par.sync);
 553         return REQ_COMPLETE;
 554 }
 555
 556 static void hwa742_sync(void)
 557 {
 558         LIST_HEAD(req_list);
 559         struct hwa742_request *req;
 560         struct completion comp;
 561
 562         req = alloc_req();
 563
 564         req->handler = sync_handler;
 565         req->complete = NULL;
 566         init_completion(&comp);
 567         req->par.sync = &comp;
 568
 569         list_add(&req->entry, &req_list);
 570         submit_req_list(&req_list);
 571
 572         wait_for_completion(&comp);
 573 }
 574
 575 static void hwa742_bind_client(struct omapfb_notifier_block *nb)
 576 {
 577         dev_dbg(hwa742.fbdev->dev, "update_mode %d\n", hwa742.update_mode);
 578         if (hwa742.update_mode == OMAPFB_MANUAL_UPDATE) {
 579                 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
 580         }
 581 }
 582
 583 static int hwa742_set_update_mode(enum omapfb_update_mode mode)
 584 {
 585         if (mode != OMAPFB_MANUAL_UPDATE && mode != OMAPFB_AUTO_UPDATE &&
 586             mode != OMAPFB_UPDATE_DISABLED)
 587                 return -EINVAL;
 588
 589         if (mode == hwa742.update_mode)
 590                 return 0;
 591
 592         dev_info(hwa742.fbdev->dev, "HWA742: setting update mode to %s\n",
 593                         mode == OMAPFB_UPDATE_DISABLED ? "disabled" :
 594                         (mode == OMAPFB_AUTO_UPDATE ? "auto" : "manual"));
 595
 596         switch (hwa742.update_mode) {
 597         case OMAPFB_MANUAL_UPDATE:
 598                 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_DISABLED);
 599                 break;
 600         case OMAPFB_AUTO_UPDATE:
 601                 hwa742.stop_auto_update = 1;
 602                 del_timer_sync(&hwa742.auto_update_timer);
 603                 break;
 604         case OMAPFB_UPDATE_DISABLED:
 605                 break;
 606         }
 607
 608         hwa742.update_mode = mode;
 609         hwa742_sync();
 610         hwa742.stop_auto_update = 0;
 611
 612         switch (mode) {
 613         case OMAPFB_MANUAL_UPDATE:
 614                 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
 615                 break;
 616         case OMAPFB_AUTO_UPDATE:
 617                 hwa742_update_window_auto(0);
 618                 break;
 619         case OMAPFB_UPDATE_DISABLED:
 620                 break;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static enum omapfb_update_mode hwa742_get_update_mode(void)
 627 {
 628         return hwa742.update_mode;
 629 }
 630
 631 static unsigned long round_to_extif_ticks(unsigned long ps, int div)
 632 {
 633         int bus_tick = hwa742.extif_clk_period * div;
 634         return (ps + bus_tick - 1) / bus_tick * bus_tick;
 635 }
 636
 637 static int calc_reg_timing(unsigned long sysclk, int div)
 638 {
 639         struct extif_timings *t;
 640         unsigned long systim;
 641
 642         /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
 643          * AccessTime 2 ns + 12.2 ns (regs),
 644          * WEOffTime = WEOnTime + 1 ns,
 645          * REOffTime = REOnTime + 16 ns (regs),
 646          * CSOffTime = REOffTime + 1 ns
 647          * ReadCycle = 2ns + 2*SYSCLK  (regs),
 648          * WriteCycle = 2*SYSCLK + 2 ns,
 649          * CSPulseWidth = 10 ns */
 650         systim = 1000000000 / (sysclk / 1000);
 651         dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
 652                   "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
 653
 654         t = &hwa742.reg_timings;
 655         memset(t, 0, sizeof(*t));
 656         t->clk_div = div;
 657         t->cs_on_time = 0;
 658         t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 659         t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 660         t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div);
 661         t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
 662         t->re_off_time = round_to_extif_ticks(t->re_on_time + 16000, div);
 663         t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
 664         t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
 665         if (t->we_cycle_time < t->we_off_time)
 666                 t->we_cycle_time = t->we_off_time;
 667         t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
 668         if (t->re_cycle_time < t->re_off_time)
 669                 t->re_cycle_time = t->re_off_time;
 670         t->cs_pulse_width = 0;
 671
 672         dev_dbg(hwa742.fbdev->dev, "[reg]cson %d csoff %d reon %d reoff %d\n",
 673                  t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
 674         dev_dbg(hwa742.fbdev->dev, "[reg]weon %d weoff %d recyc %d wecyc %d\n",
 675                  t->we_on_time, t->we_off_time, t->re_cycle_time,
 676                  t->we_cycle_time);
 677         dev_dbg(hwa742.fbdev->dev, "[reg]rdaccess %d cspulse %d\n",
 678                  t->access_time, t->cs_pulse_width);
 679
 680         return hwa742.extif->convert_timings(t);
 681 }
 682
 683 static int calc_lut_timing(unsigned long sysclk, int div)
 684 {
 685         struct extif_timings *t;
 686         unsigned long systim;
 687
 688         /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
 689          * AccessTime 2 ns + 4 * SYSCLK + 26 (lut),
 690          * WEOffTime = WEOnTime + 1 ns,
 691          * REOffTime = REOnTime + 4*SYSCLK + 26 ns (lut),
 692          * CSOffTime = REOffTime + 1 ns
 693          * ReadCycle = 2ns + 4*SYSCLK + 26 ns (lut),
 694          * WriteCycle = 2*SYSCLK + 2 ns,
 695          * CSPulseWidth = 10 ns
 696          */
 697         systim = 1000000000 / (sysclk / 1000);
 698         dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
 699                   "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
 700
 701         t = &hwa742.lut_timings;
 702         memset(t, 0, sizeof(*t));
 703
 704         t->clk_div = div;
 705
 706         t->cs_on_time = 0;
 707         t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 708         t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 709         t->access_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
 710                                               26000, div);
 711         t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
 712         t->re_off_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
 713                                               26000, div);
 714         t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
 715         t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
 716         if (t->we_cycle_time < t->we_off_time)
 717                 t->we_cycle_time = t->we_off_time;
 718         t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div);
 719         if (t->re_cycle_time < t->re_off_time)
 720                 t->re_cycle_time = t->re_off_time;
 721         t->cs_pulse_width = 0;
 722
 723         dev_dbg(hwa742.fbdev->dev, "[lut]cson %d csoff %d reon %d reoff %d\n",
 724                  t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
 725         dev_dbg(hwa742.fbdev->dev, "[lut]weon %d weoff %d recyc %d wecyc %d\n",
 726                  t->we_on_time, t->we_off_time, t->re_cycle_time,
 727                  t->we_cycle_time);
 728         dev_dbg(hwa742.fbdev->dev, "[lut]rdaccess %d cspulse %d\n",
 729                  t->access_time, t->cs_pulse_width);
 730
 731         return hwa742.extif->convert_timings(t);
 732 }
 733
 734 static int calc_extif_timings(unsigned long sysclk, int *extif_mem_div)
 735 {
 736         int max_clk_div;
 737         int div;
 738
 739         hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);
 740         for (div = 1; div < max_clk_div; div++) {
 741                 if (calc_reg_timing(sysclk, div) == 0)
 742                         break;
 743         }
 744         if (div >= max_clk_div)
 745                 goto err;
 746
 747         *extif_mem_div = div;
 748
 749         for (div = 1; div < max_clk_div; div++) {
 750                 if (calc_lut_timing(sysclk, div) == 0)
 751                         break;
 752         }
 753
 754         if (div >= max_clk_div)
 755                 goto err;
 756
 757         return 0;
 758
 759 err:
 760         dev_err(hwa742.fbdev->dev, "can't setup timings\n");
 761         return -1;
 762 }
 763
 764 static void calc_hwa742_clk_rates(unsigned long ext_clk,
 765                                 unsigned long *sys_clk, unsigned long *pix_clk)
 766 {
 767         int pix_clk_src;
 768         int sys_div = 0, sys_mul = 0;
 769         int pix_div;
 770
 771         pix_clk_src = hwa742_read_reg(HWA742_CLK_SRC_REG);
 772         pix_div = ((pix_clk_src >> 3) & 0x1f) + 1;
 773         if ((pix_clk_src & (0x3 << 1)) == 0) {
 774                 /* Source is the PLL */
 775                 sys_div = (hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x3f) + 1;
 776                 sys_mul = (hwa742_read_reg(HWA742_PLL_4_REG) & 0x7f) + 1;
 777                 *sys_clk = ext_clk * sys_mul / sys_div;
 778         } else  /* else source is ext clk, or oscillator */
 779                 *sys_clk = ext_clk;
 780
 781         *pix_clk = *sys_clk / pix_div;                  /* HZ */
 782         dev_dbg(hwa742.fbdev->dev,
 783                 "ext_clk %ld pix_src %d pix_div %d sys_div %d sys_mul %d\n",
 784                 ext_clk, pix_clk_src & (0x3 << 1), pix_div, sys_div, sys_mul);
 785         dev_dbg(hwa742.fbdev->dev, "sys_clk %ld pix_clk %ld\n",
 786                 *sys_clk, *pix_clk);
 787 }
 788
 789
 790 static int setup_tearsync(unsigned long pix_clk, int extif_div)
 791 {
 792         int hdisp, vdisp;
 793         int hndp, vndp;
 794         int hsw, vsw;
 795         int hs, vs;
 796         int hs_pol_inv, vs_pol_inv;
 797         int use_hsvs, use_ndp;
 798         u8  b;
 799
 800         hsw = hwa742_read_reg(HWA742_HS_W_REG);
 801         vsw = hwa742_read_reg(HWA742_VS_W_REG);
 802         hs_pol_inv = !(hsw & 0x80);
 803         vs_pol_inv = !(vsw & 0x80);
 804         hsw = hsw & 0x7f;
 805         vsw = vsw & 0x3f;
 806
 807         hdisp = (hwa742_read_reg(HWA742_H_DISP_REG) & 0x7f) * 8;
 808         vdisp = hwa742_read_reg(HWA742_V_DISP_1_REG) +
 809                 ((hwa742_read_reg(HWA742_V_DISP_2_REG) & 0x3) << 8);
 810
 811         hndp = hwa742_read_reg(HWA742_H_NDP_REG) & 0x7f;
 812         vndp = hwa742_read_reg(HWA742_V_NDP_REG);
 813
 814         /* time to transfer one pixel (16bpp) in ps */
 815         hwa742.pix_tx_time = hwa742.reg_timings.we_cycle_time;
 816         if (hwa742.extif->get_max_tx_rate != NULL) {
 817                 /*
 818                  * The external interface might have a rate limitation,
 819                  * if so, we have to maximize our transfer rate.
 820                  */
 821                 unsigned long min_tx_time;
 822                 unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();
 823
 824                 dev_dbg(hwa742.fbdev->dev, "max_tx_rate %ld HZ\n",
 825                         max_tx_rate);
 826                 min_tx_time = 1000000000 / (max_tx_rate / 1000);  /* ps */
 827                 if (hwa742.pix_tx_time < min_tx_time)
 828                         hwa742.pix_tx_time = min_tx_time;
 829         }
 830
 831         /* time to update one line in ps */
 832         hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000);
 833         hwa742.line_upd_time *= 1000;
 834         if (hdisp * hwa742.pix_tx_time > hwa742.line_upd_time)
 835                 /*
 836                  * transfer speed too low, we might have to use both
 837                  * HS and VS
 838                  */
 839                 use_hsvs = 1;
 840         else
 841                 /* decent transfer speed, we'll always use only VS */
 842                 use_hsvs = 0;
 843
 844         if (use_hsvs && (hs_pol_inv || vs_pol_inv)) {
 845                 /*
 846                  * HS or'ed with VS doesn't work, use the active high
 847                  * TE signal based on HNDP / VNDP
 848                  */
 849                 use_ndp = 1;
 850                 hs_pol_inv = 0;
 851                 vs_pol_inv = 0;
 852                 hs = hndp;
 853                 vs = vndp;
 854         } else {
 855                 /*
 856                  * Use HS or'ed with VS as a TE signal if both are needed
 857                  * or VNDP if only vsync is needed.
 858                  */
 859                 use_ndp = 0;
 860                 hs = hsw;
 861                 vs = vsw;
 862                 if (!use_hsvs) {
 863                         hs_pol_inv = 0;
 864                         vs_pol_inv = 0;
 865                 }
 866         }
 867
 868         hs = hs * 1000000 / (pix_clk / 1000);                   /* ps */
 869         hs *= 1000;
 870
 871         vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000);  /* ps */
 872         vs *= 1000;
 873
 874         if (vs <= hs)
 875                 return -EDOM;
 876         /* set VS to 120% of HS to minimize VS detection time */
 877         vs = hs * 12 / 10;
 878         /* minimize HS too */
 879         hs = 10000;
 880
 881         b = hwa742_read_reg(HWA742_NDP_CTRL);
 882         b &= ~0x3;
 883         b |= use_hsvs ? 1 : 0;
 884         b |= (use_ndp && use_hsvs) ? 0 : 2;
 885         hwa742_write_reg(HWA742_NDP_CTRL, b);
 886
 887         hwa742.vsync_only = !use_hsvs;
 888
 889         dev_dbg(hwa742.fbdev->dev,
 890                 "pix_clk %ld HZ pix_tx_time %ld ps line_upd_time %ld ps\n",
 891                 pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time);
 892         dev_dbg(hwa742.fbdev->dev,
 893                 "hs %d ps vs %d ps mode %d vsync_only %d\n",
 894                 hs, vs, (b & 0x3), !use_hsvs);
 895
 896         return hwa742.extif->setup_tearsync(1, hs, vs,
 897                                             hs_pol_inv, vs_pol_inv, extif_div);
 898 }
 899
 900 static void hwa742_get_caps(int plane, struct omapfb_caps *caps)
 901 {
 902         hwa742.int_ctrl->get_caps(plane, caps);
 903         caps->ctrl |= OMAPFB_CAPS_MANUAL_UPDATE |
 904                       OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE;
 905         if (hwa742.te_connected)
 906                 caps->ctrl |= OMAPFB_CAPS_TEARSYNC;
 907         caps->wnd_color |= (1 << OMAPFB_COLOR_RGB565) |
 908                            (1 << OMAPFB_COLOR_YUV420);
 909 }
 910
 911 static void hwa742_suspend(void)
 912 {
 913         hwa742.update_mode_before_suspend = hwa742.update_mode;
 914         hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
 915         /* Enable sleep mode */
 916         hwa742_write_reg(HWA742_POWER_SAVE, 1 << 1);
 917         clk_disable(hwa742.sys_ck);
 918 }
 919
 920 static void hwa742_resume(void)
 921 {
 922         clk_enable(hwa742.sys_ck);
 923
 924         /* Disable sleep mode */
 925         hwa742_write_reg(HWA742_POWER_SAVE, 0);
 926         while (1) {
 927                 /* Loop until PLL output is stabilized */
 928                 if (hwa742_read_reg(HWA742_PLL_DIV_REG) & (1 << 7))
 929                         break;
 930                 set_current_state(TASK_UNINTERRUPTIBLE);
 931                 schedule_timeout(msecs_to_jiffies(5));
 932         }
 933         hwa742_set_update_mode(hwa742.update_mode_before_suspend);
 934 }
 935
 936 static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
 937                        struct omapfb_mem_desc *req_vram)
 938 {
 939         int r = 0, i;
 940         u8 rev, conf;
 941         unsigned long ext_clk;
 942         unsigned long sys_clk, pix_clk;
 943         int extif_mem_div;
 944         struct omapfb_platform_data *omapfb_conf;
 945         struct hwa742_platform_data *ctrl_conf;
 946
 947         BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
 948
 949         hwa742.fbdev = fbdev;
 950         hwa742.extif = fbdev->ext_if;
 951         hwa742.int_ctrl = fbdev->int_ctrl;
 952
 953         omapfb_conf = fbdev->dev->platform_data;
 954         ctrl_conf = omapfb_conf->ctrl_platform_data;
 955
 956         if (ctrl_conf == NULL) {
 957                 dev_err(fbdev->dev, "HWA742: missing platform data\n");
 958                 r = -ENOENT;
 959                 goto err1;
 960         }
 961
 962         hwa742.sys_ck = clk_get(NULL, "hwa_sys_ck");
 963
 964         spin_lock_init(&hwa742.req_lock);
 965
 966         if ((r = hwa742.int_ctrl->init(fbdev, 1, req_vram)) < 0)
 967                 goto err1;
 968
 969         if ((r = hwa742.extif->init(fbdev)) < 0)
 970                 goto err2;
 971
 972         ext_clk = clk_get_rate(hwa742.sys_ck);
 973         if ((r = calc_extif_timings(ext_clk, &extif_mem_div)) < 0)
 974                 goto err3;
 975         hwa742.extif->set_timings(&hwa742.reg_timings);
 976         clk_enable(hwa742.sys_ck);
 977
 978         calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk);
 979         if ((r = calc_extif_timings(sys_clk, &extif_mem_div)) < 0)
 980                 goto err4;
 981         hwa742.extif->set_timings(&hwa742.reg_timings);
 982
 983         rev = hwa742_read_reg(HWA742_REV_CODE_REG);
 984         if ((rev & 0xfc) != 0x80) {
 985                 dev_err(fbdev->dev, "HWA742: invalid revision %02x\n", rev);
 986                 r = -ENODEV;
 987                 goto err4;
 988         }
 989
 990
 991         if (!(hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x80)) {
 992                 dev_err(fbdev->dev,
 993                       "HWA742: controller not initialized by the bootloader\n");
 994                 r = -ENODEV;
 995                 goto err4;
 996         }
 997
 998         if (ctrl_conf->te_connected) {
 999                 if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
1000                         dev_err(hwa742.fbdev->dev,
1001                                "HWA742: can't setup tearing synchronization\n");
1002                         goto err4;
1003                 }
1004                 hwa742.te_connected = 1;
1005         }
1006
1007         hwa742.max_transmit_size = hwa742.extif->max_transmit_size;
1008
1009         hwa742.update_mode = OMAPFB_UPDATE_DISABLED;
1010
1011         hwa742.auto_update_window.x = 0;
1012         hwa742.auto_update_window.y = 0;
1013         hwa742.auto_update_window.width = fbdev->panel->x_res;
1014         hwa742.auto_update_window.height = fbdev->panel->y_res;
1015         hwa742.auto_update_window.format = 0;
1016
1017         init_timer(&hwa742.auto_update_timer);
1018         hwa742.auto_update_timer.function = hwa742_update_window_auto;
1019         hwa742.auto_update_timer.data = 0;
1020
1021         hwa742.prev_color_mode = -1;
1022         hwa742.prev_flags = 0;
1023
1024         hwa742.fbdev = fbdev;
1025
1026         INIT_LIST_HEAD(&hwa742.free_req_list);
1027         INIT_LIST_HEAD(&hwa742.pending_req_list);
1028         for (i = 0; i < ARRAY_SIZE(hwa742.req_pool); i++)
1029                 list_add(&hwa742.req_pool[i].entry, &hwa742.free_req_list);
1030         BUG_ON(i <= IRQ_REQ_POOL_SIZE);
1031         sema_init(&hwa742.req_sema, i - IRQ_REQ_POOL_SIZE);
1032
1033         conf = hwa742_read_reg(HWA742_CONFIG_REG);
1034         dev_info(fbdev->dev, ": Epson HWA742 LCD controller rev %d "
1035                         "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
1036
1037         return 0;
1038 err4:
1039         clk_disable(hwa742.sys_ck);
1040 err3:
1041         hwa742.extif->cleanup();
1042 err2:
1043         hwa742.int_ctrl->cleanup();
1044 err1:
1045         return r;
1046 }
1047
1048 static void hwa742_cleanup(void)
1049 {
1050         hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
1051         hwa742.extif->cleanup();
1052         hwa742.int_ctrl->cleanup();
1053         clk_disable(hwa742.sys_ck);
1054 }
1055
1056 struct lcd_ctrl hwa742_ctrl = {
1057         .name                   = "hwa742",
1058         .init                   = hwa742_init,
1059         .cleanup                = hwa742_cleanup,
1060         .bind_client            = hwa742_bind_client,
1061         .get_caps               = hwa742_get_caps,
1062         .set_update_mode        = hwa742_set_update_mode,
1063         .get_update_mode        = hwa742_get_update_mode,
1064         .setup_plane            = hwa742_setup_plane,
1065         .enable_plane           = hwa742_enable_plane,
1066         .update_window          = hwa742_update_window_async,
1067         .sync                   = hwa742_sync,
1068         .suspend                = hwa742_suspend,
1069         .resume                 = hwa742_resume,
1070 };
1071