drivers/video/mbx/mbxfb.c

   1 /*
   2  *  linux/drivers/video/mbx/mbxfb.c
   3  *
   4  *  Copyright (C) 2006 Compulab, Ltd.
   5  *  Mike Rapoport <mike@compulab.co.il>
   6  *
   7  *   Based on pxafb.c
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file COPYING in the main directory of this archive for
  11  * more details.
  12  *
  13  *   Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
  14  *
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/fb.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22
  23 #include <asm/io.h>
  24
  25 #include <video/mbxfb.h>
  26
  27 #include "regs.h"
  28 #include "reg_bits.h"
  29
  30 static unsigned long virt_base_2700;
  31
  32 #define MIN_XRES        16
  33 #define MIN_YRES        16
  34 #define MAX_XRES        2048
  35 #define MAX_YRES        2048
  36
  37 #define MAX_PALETTES    16
  38
  39 /* FIXME: take care of different chip revisions with different sizes
  40    of ODFB */
  41 #define MEMORY_OFFSET   0x60000
  42
  43 struct mbxfb_info {
  44         struct device *dev;
  45
  46         struct resource *fb_res;
  47         struct resource *fb_req;
  48
  49         struct resource *reg_res;
  50         struct resource *reg_req;
  51
  52         void __iomem *fb_virt_addr;
  53         unsigned long fb_phys_addr;
  54
  55         void __iomem *reg_virt_addr;
  56         unsigned long reg_phys_addr;
  57
  58         int (*platform_probe) (struct fb_info * fb);
  59         int (*platform_remove) (struct fb_info * fb);
  60
  61         u32 pseudo_palette[MAX_PALETTES];
  62 #ifdef CONFIG_FB_MBX_DEBUG
  63         void *debugfs_data;
  64 #endif
  65
  66 };
  67
  68 static struct fb_var_screeninfo mbxfb_default __devinitdata = {
  69         .xres = 640,
  70         .yres = 480,
  71         .xres_virtual = 640,
  72         .yres_virtual = 480,
  73         .bits_per_pixel = 16,
  74         .red = {11, 5, 0},
  75         .green = {5, 6, 0},
  76         .blue = {0, 5, 0},
  77         .activate = FB_ACTIVATE_TEST,
  78         .height = -1,
  79         .width = -1,
  80         .pixclock = 40000,
  81         .left_margin = 48,
  82         .right_margin = 16,
  83         .upper_margin = 33,
  84         .lower_margin = 10,
  85         .hsync_len = 96,
  86         .vsync_len = 2,
  87         .vmode = FB_VMODE_NONINTERLACED,
  88         .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  89 };
  90
  91 static struct fb_fix_screeninfo mbxfb_fix  __devinitdata = {
  92         .id = "MBX",
  93         .type = FB_TYPE_PACKED_PIXELS,
  94         .visual = FB_VISUAL_TRUECOLOR,
  95         .xpanstep = 0,
  96         .ypanstep = 0,
  97         .ywrapstep = 0,
  98         .accel = FB_ACCEL_NONE,
  99 };
 100
 101 struct pixclock_div {
 102         u8 m;
 103         u8 n;
 104         u8 p;
 105 };
 106
 107 static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps,
 108                                        struct pixclock_div *div)
 109 {
 110         u8 m, n, p;
 111         unsigned int err = 0;
 112         unsigned int min_err = ~0x0;
 113         unsigned int clk;
 114         unsigned int best_clk = 0;
 115         unsigned int ref_clk = 13000;   /* FIXME: take from platform data */
 116         unsigned int pixclock;
 117
 118         /* convert pixclock to KHz */
 119         pixclock = PICOS2KHZ(pixclock_ps);
 120
 121         /* PLL output freq = (ref_clk * M) / (N * 2^P)
 122          *
 123          * M: 1 to 63
 124          * N: 1 to 7
 125          * P: 0 to 7
 126          */
 127
 128         /* RAPH: When N==1, the resulting pixel clock appears to
 129          * get divided by 2. Preventing N=1 by starting the following
 130          * loop at 2 prevents this. Is this a bug with my chip
 131          * revision or something I dont understand? */
 132         for (m = 1; m < 64; m++) {
 133                 for (n = 2; n < 8; n++) {
 134                         for (p = 0; p < 8; p++) {
 135                                 clk = (ref_clk * m) / (n * (1 << p));
 136                                 err = (clk > pixclock) ? (clk - pixclock) :
 137                                         (pixclock - clk);
 138                                 if (err < min_err) {
 139                                         min_err = err;
 140                                         best_clk = clk;
 141                                         div->m = m;
 142                                         div->n = n;
 143                                         div->p = p;
 144                                 }
 145                         }
 146                 }
 147         }
 148         return KHZ2PICOS(best_clk);
 149 }
 150
 151 static int mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 152                            u_int trans, struct fb_info *info)
 153 {
 154         u32 val, ret = 1;
 155
 156         if (regno < MAX_PALETTES) {
 157                 u32 *pal = info->pseudo_palette;
 158
 159                 val = (red & 0xf800) | ((green & 0xfc00) >> 5) |
 160                         ((blue & 0xf800) >> 11);
 161                 pal[regno] = val;
 162                 ret = 0;
 163         }
 164
 165         return ret;
 166 }
 167
 168 static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 169 {
 170         struct pixclock_div div;
 171
 172         var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
 173
 174         if (var->xres < MIN_XRES)
 175                 var->xres = MIN_XRES;
 176         if (var->yres < MIN_YRES)
 177                 var->yres = MIN_YRES;
 178         if (var->xres > MAX_XRES)
 179                 return -EINVAL;
 180         if (var->yres > MAX_YRES)
 181                 return -EINVAL;
 182         var->xres_virtual = max(var->xres_virtual, var->xres);
 183         var->yres_virtual = max(var->yres_virtual, var->yres);
 184
 185         switch (var->bits_per_pixel) {
 186                 /* 8 bits-per-pixel is not supported yet */
 187         case 8:
 188                 return -EINVAL;
 189         case 16:
 190                 var->green.length = (var->green.length == 5) ? 5 : 6;
 191                 var->red.length = 5;
 192                 var->blue.length = 5;
 193                 var->transp.length = 6 - var->green.length;
 194                 var->blue.offset = 0;
 195                 var->green.offset = 5;
 196                 var->red.offset = 5 + var->green.length;
 197                 var->transp.offset = (5 + var->red.offset) & 15;
 198                 break;
 199         case 24:                /* RGB 888   */
 200         case 32:                /* RGBA 8888 */
 201                 var->red.offset = 16;
 202                 var->red.length = 8;
 203                 var->green.offset = 8;
 204                 var->green.length = 8;
 205                 var->blue.offset = 0;
 206                 var->blue.length = 8;
 207                 var->transp.length = var->bits_per_pixel - 24;
 208                 var->transp.offset = (var->transp.length) ? 24 : 0;
 209                 break;
 210         }
 211         var->red.msb_right = 0;
 212         var->green.msb_right = 0;
 213         var->blue.msb_right = 0;
 214         var->transp.msb_right = 0;
 215
 216         return 0;
 217 }
 218
 219 static int mbxfb_set_par(struct fb_info *info)
 220 {
 221         struct fb_var_screeninfo *var = &info->var;
 222         struct pixclock_div div;
 223         ushort hbps, ht, hfps, has;
 224         ushort vbps, vt, vfps, vas;
 225         u32 gsctrl = readl(GSCTRL);
 226         u32 gsadr = readl(GSADR);
 227
 228         info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
 229
 230         /* setup color mode */
 231         gsctrl &= ~(FMsk(GSCTRL_GPIXFMT));
 232         /* FIXME: add *WORKING* support for 8-bits per color */
 233         if (info->var.bits_per_pixel == 8) {
 234                 return -EINVAL;
 235         } else {
 236                 fb_dealloc_cmap(&info->cmap);
 237                 gsctrl &= ~GSCTRL_LUT_EN;
 238
 239                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 240                 switch (info->var.bits_per_pixel) {
 241                 case 16:
 242                         if (info->var.green.length == 5)
 243                                 gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
 244                         else
 245                                 gsctrl |= GSCTRL_GPIXFMT_RGB565;
 246                         break;
 247                 case 24:
 248                         gsctrl |= GSCTRL_GPIXFMT_RGB888;
 249                         break;
 250                 case 32:
 251                         gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
 252                         break;
 253                 }
 254         }
 255
 256         /* setup resolution */
 257         gsctrl &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
 258         gsctrl |= Gsctrl_Width(info->var.xres) |
 259                 Gsctrl_Height(info->var.yres);
 260         writel(gsctrl, GSCTRL);
 261         udelay(1000);
 262
 263         gsadr &= ~(FMsk(GSADR_SRCSTRIDE));
 264         gsadr |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel /
 265                                  (8 * 16) - 1);
 266         writel(gsadr, GSADR);
 267         udelay(1000);
 268
 269         /* setup timings */
 270         var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
 271
 272         writel((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
 273                 Disp_Pll_P(div.p) | DISP_PLL_EN), DISPPLL);
 274
 275         hbps = var->hsync_len;
 276         has = hbps + var->left_margin;
 277         hfps = has + var->xres;
 278         ht = hfps + var->right_margin;
 279
 280         vbps = var->vsync_len;
 281         vas = vbps + var->upper_margin;
 282         vfps = vas + var->yres;
 283         vt = vfps + var->lower_margin;
 284
 285         writel((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
 286         writel((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
 287         writel((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
 288         writel((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
 289
 290         writel((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
 291         writel((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
 292         writel((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
 293         writel((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
 294         writel((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
 295
 296         writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
 297
 298         return 0;
 299 }
 300
 301 static int mbxfb_blank(int blank, struct fb_info *info)
 302 {
 303         switch (blank) {
 304         case FB_BLANK_POWERDOWN:
 305         case FB_BLANK_VSYNC_SUSPEND:
 306         case FB_BLANK_HSYNC_SUSPEND:
 307         case FB_BLANK_NORMAL:
 308                 writel((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
 309                 udelay(1000);
 310                 writel((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
 311                 udelay(1000);
 312                 writel((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
 313                 udelay(1000);
 314                 break;
 315         case FB_BLANK_UNBLANK:
 316                 writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
 317                 udelay(1000);
 318                 writel((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
 319                 udelay(1000);
 320                 break;
 321         }
 322         return 0;
 323 }
 324
 325 static struct fb_ops mbxfb_ops = {
 326         .owner = THIS_MODULE,
 327         .fb_check_var = mbxfb_check_var,
 328         .fb_set_par = mbxfb_set_par,
 329         .fb_setcolreg = mbxfb_setcolreg,
 330         .fb_fillrect = cfb_fillrect,
 331         .fb_copyarea = cfb_copyarea,
 332         .fb_imageblit = cfb_imageblit,
 333         .fb_blank = mbxfb_blank,
 334 };
 335
 336 /*
 337   Enable external SDRAM controller. Assume that all clocks are active
 338   by now.
 339 */
 340 static void __devinit setup_memc(struct fb_info *fbi)
 341 {
 342         struct mbxfb_info *mfbi = fbi->par;
 343         unsigned long tmp;
 344         int i;
 345
 346         /* FIXME: use platfrom specific parameters */
 347         /* setup SDRAM controller */
 348         writel((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
 349                 LMCFG_LMA_TS),
 350                LMCFG);
 351         udelay(1000);
 352
 353         writel(LMPWR_MC_PWR_ACT, LMPWR);
 354         udelay(1000);
 355
 356         /* setup SDRAM timings */
 357         writel((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
 358                 Lmtim_Trc(9) | Lmtim_Tdpl(2)),
 359                LMTIM);
 360         udelay(1000);
 361         /* setup SDRAM refresh rate */
 362         writel(0xc2b, LMREFRESH);
 363         udelay(1000);
 364         /* setup SDRAM type parameters */
 365         writel((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
 366                 LMTYPE_COLSZ_8),
 367                LMTYPE);
 368         udelay(1000);
 369         /* enable memory controller */
 370         writel(LMPWR_MC_PWR_ACT, LMPWR);
 371         udelay(1000);
 372
 373         /* perform dummy reads */
 374         for ( i = 0; i < 16; i++ ) {
 375                 tmp = readl(fbi->screen_base);
 376         }
 377 }
 378
 379 static void enable_clocks(struct fb_info *fbi)
 380 {
 381         /* enable clocks */
 382         writel(SYSCLKSRC_PLL_2, SYSCLKSRC);
 383         udelay(1000);
 384         writel(PIXCLKSRC_PLL_1, PIXCLKSRC);
 385         udelay(1000);
 386         writel(0x00000000, CLKSLEEP);
 387         udelay(1000);
 388         writel((Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) |
 389                 CORE_PLL_EN),
 390                COREPLL);
 391         udelay(1000);
 392         writel((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
 393                 DISP_PLL_EN),
 394                DISPPLL);
 395
 396         writel(0x00000000, VOVRCLK);
 397         udelay(1000);
 398         writel(PIXCLK_EN, PIXCLK);
 399         udelay(1000);
 400         writel(MEMCLK_EN, MEMCLK);
 401         udelay(1000);
 402         writel(0x00000006, M24CLK);
 403         udelay(1000);
 404         writel(0x00000006, MBXCLK);
 405         udelay(1000);
 406         writel(SDCLK_EN, SDCLK);
 407         udelay(1000);
 408         writel(0x00000001, PIXCLKDIV);
 409         udelay(1000);
 410 }
 411
 412 static void __devinit setup_graphics(struct fb_info *fbi)
 413 {
 414         unsigned long gsctrl;
 415
 416         gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres) |
 417                 Gsctrl_Height(fbi->var.yres);
 418         switch (fbi->var.bits_per_pixel) {
 419         case 16:
 420                 if (fbi->var.green.length == 5)
 421                         gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
 422                 else
 423                         gsctrl |= GSCTRL_GPIXFMT_RGB565;
 424                 break;
 425         case 24:
 426                 gsctrl |= GSCTRL_GPIXFMT_RGB888;
 427                 break;
 428         case 32:
 429                 gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
 430                 break;
 431         }
 432
 433         writel(gsctrl, GSCTRL);
 434         udelay(1000);
 435         writel(0x00000000, GBBASE);
 436         udelay(1000);
 437         writel(0x00ffffff, GDRCTRL);
 438         udelay(1000);
 439         writel((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
 440         udelay(1000);
 441         writel(0x00000000, GPLUT);
 442         udelay(1000);
 443 }
 444
 445 static void __devinit setup_display(struct fb_info *fbi)
 446 {
 447         unsigned long dsctrl = 0;
 448
 449         dsctrl = DSCTRL_BLNK_POL;
 450         if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
 451                 dsctrl |= DSCTRL_HS_POL;
 452         if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
 453                 dsctrl |= DSCTRL_VS_POL;
 454         writel(dsctrl, DSCTRL);
 455         udelay(1000);
 456         writel(0xd0303010, DMCTRL);
 457         udelay(1000);
 458         writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
 459 }
 460
 461 static void __devinit enable_controller(struct fb_info *fbi)
 462 {
 463         writel(SYSRST_RST, SYSRST);
 464         udelay(1000);
 465
 466
 467         enable_clocks(fbi);
 468         setup_memc(fbi);
 469         setup_graphics(fbi);
 470         setup_display(fbi);
 471 }
 472
 473 #ifdef CONFIG_PM
 474 /*
 475  * Power management hooks.  Note that we won't be called from IRQ context,
 476  * unlike the blank functions above, so we may sleep.
 477  */
 478 static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
 479 {
 480         /* make frame buffer memory enter self-refresh mode */
 481         writel(LMPWR_MC_PWR_SRM, LMPWR);
 482         while (LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM)
 483                 ; /* empty statement */
 484
 485         /* reset the device, since it's initial state is 'mostly sleeping' */
 486         writel(SYSRST_RST, SYSRST);
 487         return 0;
 488 }
 489
 490 static int mbxfb_resume(struct platform_device *dev)
 491 {
 492         struct fb_info *fbi = platform_get_drvdata(dev);
 493
 494         enable_clocks(fbi);
 495 /*      setup_graphics(fbi); */
 496 /*      setup_display(fbi); */
 497
 498         writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
 499         return 0;
 500 }
 501 #else
 502 #define mbxfb_suspend   NULL
 503 #define mbxfb_resume    NULL
 504 #endif
 505
 506 /* debugfs entries */
 507 #ifndef CONFIG_FB_MBX_DEBUG
 508 #define mbxfb_debugfs_init(x)   do {} while(0)
 509 #define mbxfb_debugfs_remove(x) do {} while(0)
 510 #endif
 511
 512 #define res_size(_r) (((_r)->end - (_r)->start) + 1)
 513
 514 static int __devinit mbxfb_probe(struct platform_device *dev)
 515 {
 516         int ret;
 517         struct fb_info *fbi;
 518         struct mbxfb_info *mfbi;
 519         struct mbxfb_platform_data *pdata;
 520
 521         dev_dbg(dev, "mbxfb_probe\n");
 522
 523         fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
 524         if (fbi == NULL) {
 525                 dev_err(&dev->dev, "framebuffer_alloc failed\n");
 526                 return -ENOMEM;
 527         }
 528
 529         mfbi = fbi->par;
 530         fbi->pseudo_palette = mfbi->pseudo_palette;
 531         pdata = dev->dev.platform_data;
 532         if (pdata->probe)
 533                 mfbi->platform_probe = pdata->probe;
 534         if (pdata->remove)
 535                 mfbi->platform_remove = pdata->remove;
 536
 537         mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 538         mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
 539
 540         if (!mfbi->fb_res || !mfbi->reg_res) {
 541                 dev_err(&dev->dev, "no resources found\n");
 542                 ret = -ENODEV;
 543                 goto err1;
 544         }
 545
 546         mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
 547                                           res_size(mfbi->fb_res), dev->name);
 548         if (mfbi->fb_req == NULL) {
 549                 dev_err(&dev->dev, "failed to claim framebuffer memory\n");
 550                 ret = -EINVAL;
 551                 goto err1;
 552         }
 553         mfbi->fb_phys_addr = mfbi->fb_res->start;
 554
 555         mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
 556                                            res_size(mfbi->reg_res), dev->name);
 557         if (mfbi->reg_req == NULL) {
 558                 dev_err(&dev->dev, "failed to claim Marathon registers\n");
 559                 ret = -EINVAL;
 560                 goto err2;
 561         }
 562         mfbi->reg_phys_addr = mfbi->reg_res->start;
 563
 564         mfbi->reg_virt_addr = ioremap_nocache(mfbi->reg_phys_addr,
 565                                               res_size(mfbi->reg_req));
 566         if (!mfbi->reg_virt_addr) {
 567                 dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
 568                 ret = -EINVAL;
 569                 goto err3;
 570         }
 571         virt_base_2700 = (unsigned long)mfbi->reg_virt_addr;
 572
 573         mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
 574                                              res_size(mfbi->fb_req));
 575         if (!mfbi->reg_virt_addr) {
 576                 dev_err(&dev->dev, "failed to ioremap frame buffer\n");
 577                 ret = -EINVAL;
 578                 goto err4;
 579         }
 580
 581         /* FIXME: get from platform */
 582         fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000);
 583         fbi->screen_size = 8 * 1024 * 1024;     /* 8 Megs */
 584         fbi->fbops = &mbxfb_ops;
 585
 586         fbi->var = mbxfb_default;
 587         fbi->fix = mbxfb_fix;
 588         fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
 589         fbi->fix.smem_len = 8 * 1024 * 1024;
 590         fbi->fix.line_length = 640 * 2;
 591
 592         ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
 593         if (ret < 0) {
 594                 dev_err(&dev->dev, "fb_alloc_cmap failed\n");
 595                 ret = -EINVAL;
 596                 goto err5;
 597         }
 598
 599         platform_set_drvdata(dev, fbi);
 600
 601         printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node);
 602
 603         if (mfbi->platform_probe)
 604                 mfbi->platform_probe(fbi);
 605
 606         enable_controller(fbi);
 607
 608         mbxfb_debugfs_init(fbi);
 609
 610         ret = register_framebuffer(fbi);
 611         if (ret < 0) {
 612                 dev_err(&dev->dev, "register_framebuffer failed\n");
 613                 ret = -EINVAL;
 614                 goto err6;
 615         }
 616
 617         return 0;
 618
 619 err6:
 620         fb_dealloc_cmap(&fbi->cmap);
 621 err5:
 622         iounmap(mfbi->fb_virt_addr);
 623 err4:
 624         iounmap(mfbi->reg_virt_addr);
 625 err3:
 626         release_mem_region(mfbi->reg_res->start, res_size(mfbi->reg_res));
 627 err2:
 628         release_mem_region(mfbi->fb_res->start, res_size(mfbi->fb_res));
 629 err1:
 630         framebuffer_release(fbi);
 631
 632         return ret;
 633 }
 634
 635 static int __devexit mbxfb_remove(struct platform_device *dev)
 636 {
 637         struct fb_info *fbi = platform_get_drvdata(dev);
 638
 639         writel(SYSRST_RST, SYSRST);
 640         udelay(1000);
 641
 642         mbxfb_debugfs_remove(fbi);
 643
 644         if (fbi) {
 645                 struct mbxfb_info *mfbi = fbi->par;
 646
 647                 unregister_framebuffer(fbi);
 648                 if (mfbi) {
 649                         if (mfbi->platform_remove)
 650                                 mfbi->platform_remove(fbi);
 651
 652                         if (mfbi->fb_virt_addr)
 653                                 iounmap(mfbi->fb_virt_addr);
 654                         if (mfbi->reg_virt_addr)
 655                                 iounmap(mfbi->reg_virt_addr);
 656                         if (mfbi->reg_req)
 657                                 release_mem_region(mfbi->reg_req->start,
 658                                                    res_size(mfbi->reg_req));
 659                         if (mfbi->fb_req)
 660                                 release_mem_region(mfbi->fb_req->start,
 661                                                    res_size(mfbi->fb_req));
 662                 }
 663                 framebuffer_release(fbi);
 664         }
 665
 666         return 0;
 667 }
 668
 669 static struct platform_driver mbxfb_driver = {
 670         .probe = mbxfb_probe,
 671         .remove = mbxfb_remove,
 672         .suspend = mbxfb_suspend,
 673         .resume = mbxfb_resume,
 674         .driver = {
 675                 .name = "mbx-fb",
 676         },
 677 };
 678
 679 int __devinit mbxfb_init(void)
 680 {
 681         return platform_driver_register(&mbxfb_driver);
 682 }
 683
 684 static void __devexit mbxfb_exit(void)
 685 {
 686         platform_driver_unregister(&mbxfb_driver);
 687 }
 688
 689 module_init(mbxfb_init);
 690 module_exit(mbxfb_exit);
 691
 692 MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
 693 MODULE_AUTHOR("Mike Rapoport, Compulab");
 694 MODULE_LICENSE("GPL");