drivers/video/da8xx-fb.c

   1 /*
   2  * Copyright (C) 2008-2009 MontaVista Software Inc.
   3  * Copyright (C) 2008-2009 Texas Instruments Inc
   4  *
   5  * Based on the LCD driver for TI Avalanche processors written by
   6  * Ajay Singh and Shalom Hai.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option)any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/fb.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/clk.h>
  31 #include <linux/cpufreq.h>
  32 #include <linux/console.h>
  33 #include <linux/slab.h>
  34 #include <video/da8xx-fb.h>
  35 #include <asm/div64.h>
  36
  37 #define DRIVER_NAME "da8xx_lcdc"
  38
  39 #define LCD_VERSION_1   1
  40 #define LCD_VERSION_2   2
  41
  42 /* LCD Status Register */
  43 #define LCD_END_OF_FRAME1               BIT(9)
  44 #define LCD_END_OF_FRAME0               BIT(8)
  45 #define LCD_PL_LOAD_DONE                BIT(6)
  46 #define LCD_FIFO_UNDERFLOW              BIT(5)
  47 #define LCD_SYNC_LOST                   BIT(2)
  48
  49 /* LCD DMA Control Register */
  50 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  51 #define LCD_DMA_BURST_1                 0x0
  52 #define LCD_DMA_BURST_2                 0x1
  53 #define LCD_DMA_BURST_4                 0x2
  54 #define LCD_DMA_BURST_8                 0x3
  55 #define LCD_DMA_BURST_16                0x4
  56 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
  57 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
  58 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
  59 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  60
  61 /* LCD Control Register */
  62 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  63 #define LCD_RASTER_MODE                 0x01
  64
  65 /* LCD Raster Control Register */
  66 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  67 #define PALETTE_AND_DATA                0x00
  68 #define PALETTE_ONLY                    0x01
  69 #define DATA_ONLY                       0x02
  70
  71 #define LCD_MONO_8BIT_MODE              BIT(9)
  72 #define LCD_RASTER_ORDER                BIT(8)
  73 #define LCD_TFT_MODE                    BIT(7)
  74 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
  75 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
  76 #define LCD_V1_PL_INT_ENA               BIT(4)
  77 #define LCD_V2_PL_INT_ENA               BIT(6)
  78 #define LCD_MONOCHROME_MODE             BIT(1)
  79 #define LCD_RASTER_ENABLE               BIT(0)
  80 #define LCD_TFT_ALT_ENABLE              BIT(23)
  81 #define LCD_STN_565_ENABLE              BIT(24)
  82 #define LCD_V2_DMA_CLK_EN               BIT(2)
  83 #define LCD_V2_LIDD_CLK_EN              BIT(1)
  84 #define LCD_V2_CORE_CLK_EN              BIT(0)
  85 #define LCD_V2_LPP_B10                  26
  86
  87 /* LCD Raster Timing 2 Register */
  88 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  89 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  90 #define LCD_SYNC_CTRL                           BIT(25)
  91 #define LCD_SYNC_EDGE                           BIT(24)
  92 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
  93 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
  94 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
  95
  96 /* LCD Block */
  97 #define  LCD_PID_REG                            0x0
  98 #define  LCD_CTRL_REG                           0x4
  99 #define  LCD_STAT_REG                           0x8
 100 #define  LCD_RASTER_CTRL_REG                    0x28
 101 #define  LCD_RASTER_TIMING_0_REG                0x2C
 102 #define  LCD_RASTER_TIMING_1_REG                0x30
 103 #define  LCD_RASTER_TIMING_2_REG                0x34
 104 #define  LCD_DMA_CTRL_REG                       0x40
 105 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
 106 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
 107 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
 108 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
 109
 110 /* Interrupt Registers available only in Version 2 */
 111 #define  LCD_RAW_STAT_REG                       0x58
 112 #define  LCD_MASKED_STAT_REG                    0x5c
 113 #define  LCD_INT_ENABLE_SET_REG                 0x60
 114 #define  LCD_INT_ENABLE_CLR_REG                 0x64
 115 #define  LCD_END_OF_INT_IND_REG                 0x68
 116
 117 /* Clock registers available only on Version 2 */
 118 #define  LCD_CLK_ENABLE_REG                     0x6c
 119 #define  LCD_CLK_RESET_REG                      0x70
 120 #define  LCD_CLK_MAIN_RESET                     BIT(3)
 121
 122 #define LCD_NUM_BUFFERS 2
 123
 124 #define WSI_TIMEOUT     50
 125 #define PALETTE_SIZE    256
 126 #define LEFT_MARGIN     64
 127 #define RIGHT_MARGIN    64
 128 #define UPPER_MARGIN    32
 129 #define LOWER_MARGIN    32
 130
 131 static resource_size_t da8xx_fb_reg_base;
 132 static struct resource *lcdc_regs;
 133 static unsigned int lcd_revision;
 134 static irq_handler_t lcdc_irq_handler;
 135
 136 static inline unsigned int lcdc_read(unsigned int addr)
 137 {
 138         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 139 }
 140
 141 static inline void lcdc_write(unsigned int val, unsigned int addr)
 142 {
 143         __raw_writel(val, da8xx_fb_reg_base + (addr));
 144 }
 145
 146 struct da8xx_fb_par {
 147         resource_size_t p_palette_base;
 148         unsigned char *v_palette_base;
 149         dma_addr_t              vram_phys;
 150         unsigned long           vram_size;
 151         void                    *vram_virt;
 152         unsigned int            dma_start;
 153         unsigned int            dma_end;
 154         struct clk *lcdc_clk;
 155         int irq;
 156         unsigned short pseudo_palette[16];
 157         unsigned int palette_sz;
 158         unsigned int pxl_clk;
 159         int blank;
 160         wait_queue_head_t       vsync_wait;
 161         int                     vsync_flag;
 162         int                     vsync_timeout;
 163 #ifdef CONFIG_CPU_FREQ
 164         struct notifier_block   freq_transition;
 165         unsigned int            lcd_fck_rate;
 166 #endif
 167         void (*panel_power_ctrl)(int);
 168 };
 169
 170 /* Variable Screen Information */
 171 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
 172         .xoffset = 0,
 173         .yoffset = 0,
 174         .transp = {0, 0, 0},
 175         .nonstd = 0,
 176         .activate = 0,
 177         .height = -1,
 178         .width = -1,
 179         .accel_flags = 0,
 180         .left_margin = LEFT_MARGIN,
 181         .right_margin = RIGHT_MARGIN,
 182         .upper_margin = UPPER_MARGIN,
 183         .lower_margin = LOWER_MARGIN,
 184         .sync = 0,
 185         .vmode = FB_VMODE_NONINTERLACED
 186 };
 187
 188 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
 189         .id = "DA8xx FB Drv",
 190         .type = FB_TYPE_PACKED_PIXELS,
 191         .type_aux = 0,
 192         .visual = FB_VISUAL_PSEUDOCOLOR,
 193         .xpanstep = 0,
 194         .ypanstep = 1,
 195         .ywrapstep = 0,
 196         .accel = FB_ACCEL_NONE
 197 };
 198
 199 struct da8xx_panel {
 200         const char      name[25];       /* Full name <vendor>_<model> */
 201         unsigned short  width;
 202         unsigned short  height;
 203         int             hfp;            /* Horizontal front porch */
 204         int             hbp;            /* Horizontal back porch */
 205         int             hsw;            /* Horizontal Sync Pulse Width */
 206         int             vfp;            /* Vertical front porch */
 207         int             vbp;            /* Vertical back porch */
 208         int             vsw;            /* Vertical Sync Pulse Width */
 209         unsigned int    pxl_clk;        /* Pixel clock */
 210         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
 211 };
 212
 213 static struct da8xx_panel known_lcd_panels[] = {
 214         /* Sharp LCD035Q3DG01 */
 215         [0] = {
 216                 .name = "Sharp_LCD035Q3DG01",
 217                 .width = 320,
 218                 .height = 240,
 219                 .hfp = 8,
 220                 .hbp = 6,
 221                 .hsw = 0,
 222                 .vfp = 2,
 223                 .vbp = 2,
 224                 .vsw = 0,
 225                 .pxl_clk = 4608000,
 226                 .invert_pxl_clk = 1,
 227         },
 228         /* Sharp LK043T1DG01 */
 229         [1] = {
 230                 .name = "Sharp_LK043T1DG01",
 231                 .width = 480,
 232                 .height = 272,
 233                 .hfp = 2,
 234                 .hbp = 2,
 235                 .hsw = 41,
 236                 .vfp = 2,
 237                 .vbp = 2,
 238                 .vsw = 10,
 239                 .pxl_clk = 7833600,
 240                 .invert_pxl_clk = 0,
 241         },
 242         [2] = {
 243                 /* Hitachi SP10Q010 */
 244                 .name = "SP10Q010",
 245                 .width = 320,
 246                 .height = 240,
 247                 .hfp = 10,
 248                 .hbp = 10,
 249                 .hsw = 10,
 250                 .vfp = 10,
 251                 .vbp = 10,
 252                 .vsw = 10,
 253                 .pxl_clk = 7833600,
 254                 .invert_pxl_clk = 0,
 255         },
 256 };
 257
 258 /* Enable the Raster Engine of the LCD Controller */
 259 static inline void lcd_enable_raster(void)
 260 {
 261         u32 reg;
 262
 263         /* Bring LCDC out of reset */
 264         if (lcd_revision == LCD_VERSION_2)
 265                 lcdc_write(0, LCD_CLK_RESET_REG);
 266
 267         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 268         if (!(reg & LCD_RASTER_ENABLE))
 269                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 270 }
 271
 272 /* Disable the Raster Engine of the LCD Controller */
 273 static inline void lcd_disable_raster(void)
 274 {
 275         u32 reg;
 276
 277         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 278         if (reg & LCD_RASTER_ENABLE)
 279                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 280
 281         if (lcd_revision == LCD_VERSION_2)
 282                 /* Write 1 to reset LCDC */
 283                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 284 }
 285
 286 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 287 {
 288         u32 start;
 289         u32 end;
 290         u32 reg_ras;
 291         u32 reg_dma;
 292         u32 reg_int;
 293
 294         /* init reg to clear PLM (loading mode) fields */
 295         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
 296         reg_ras &= ~(3 << 20);
 297
 298         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
 299
 300         if (load_mode == LOAD_DATA) {
 301                 start    = par->dma_start;
 302                 end      = par->dma_end;
 303
 304                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 305                 if (lcd_revision == LCD_VERSION_1) {
 306                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 307                 } else {
 308                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 309                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 310                                 LCD_V2_END_OF_FRAME1_INT_ENA;
 311                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 312                 }
 313                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 314
 315                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 316                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 317                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 318                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 319         } else if (load_mode == LOAD_PALETTE) {
 320                 start    = par->p_palette_base;
 321                 end      = start + par->palette_sz - 1;
 322
 323                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 324
 325                 if (lcd_revision == LCD_VERSION_1) {
 326                         reg_ras |= LCD_V1_PL_INT_ENA;
 327                 } else {
 328                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 329                                 LCD_V2_PL_INT_ENA;
 330                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 331                 }
 332
 333                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 334                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 335         }
 336
 337         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
 338         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 339
 340         /*
 341          * The Raster enable bit must be set after all other control fields are
 342          * set.
 343          */
 344         lcd_enable_raster();
 345 }
 346
 347 /* Configure the Burst Size of DMA */
 348 static int lcd_cfg_dma(int burst_size)
 349 {
 350         u32 reg;
 351
 352         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 353         switch (burst_size) {
 354         case 1:
 355                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 356                 break;
 357         case 2:
 358                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 359                 break;
 360         case 4:
 361                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 362                 break;
 363         case 8:
 364                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 365                 break;
 366         case 16:
 367                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 368                 break;
 369         default:
 370                 return -EINVAL;
 371         }
 372         lcdc_write(reg, LCD_DMA_CTRL_REG);
 373
 374         return 0;
 375 }
 376
 377 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 378 {
 379         u32 reg;
 380
 381         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 382         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 383         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 384                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 385         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 386 }
 387
 388 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 389                 int front_porch)
 390 {
 391         u32 reg;
 392
 393         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
 394         reg |= ((back_porch & 0xff) << 24)
 395             | ((front_porch & 0xff) << 16)
 396             | ((pulse_width & 0x3f) << 10);
 397         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 398 }
 399
 400 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 401                 int front_porch)
 402 {
 403         u32 reg;
 404
 405         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 406         reg |= ((back_porch & 0xff) << 24)
 407             | ((front_porch & 0xff) << 16)
 408             | ((pulse_width & 0x3f) << 10);
 409         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 410 }
 411
 412 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 413 {
 414         u32 reg;
 415         u32 reg_int;
 416
 417         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 418                                                 LCD_MONO_8BIT_MODE |
 419                                                 LCD_MONOCHROME_MODE);
 420
 421         switch (cfg->p_disp_panel->panel_shade) {
 422         case MONOCHROME:
 423                 reg |= LCD_MONOCHROME_MODE;
 424                 if (cfg->mono_8bit_mode)
 425                         reg |= LCD_MONO_8BIT_MODE;
 426                 break;
 427         case COLOR_ACTIVE:
 428                 reg |= LCD_TFT_MODE;
 429                 if (cfg->tft_alt_mode)
 430                         reg |= LCD_TFT_ALT_ENABLE;
 431                 break;
 432
 433         case COLOR_PASSIVE:
 434                 if (cfg->stn_565_mode)
 435                         reg |= LCD_STN_565_ENABLE;
 436                 break;
 437
 438         default:
 439                 return -EINVAL;
 440         }
 441
 442         /* enable additional interrupts here */
 443         if (lcd_revision == LCD_VERSION_1) {
 444                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 445         } else {
 446                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 447                         LCD_V2_UNDERFLOW_INT_ENA;
 448                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 449         }
 450
 451         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 452
 453         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 454
 455         if (cfg->sync_ctrl)
 456                 reg |= LCD_SYNC_CTRL;
 457         else
 458                 reg &= ~LCD_SYNC_CTRL;
 459
 460         if (cfg->sync_edge)
 461                 reg |= LCD_SYNC_EDGE;
 462         else
 463                 reg &= ~LCD_SYNC_EDGE;
 464
 465         if (cfg->invert_line_clock)
 466                 reg |= LCD_INVERT_LINE_CLOCK;
 467         else
 468                 reg &= ~LCD_INVERT_LINE_CLOCK;
 469
 470         if (cfg->invert_frm_clock)
 471                 reg |= LCD_INVERT_FRAME_CLOCK;
 472         else
 473                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 474
 475         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 476
 477         return 0;
 478 }
 479
 480 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 481                 u32 bpp, u32 raster_order)
 482 {
 483         u32 reg;
 484
 485         /* Set the Panel Width */
 486         /* Pixels per line = (PPL + 1)*16 */
 487         if (lcd_revision == LCD_VERSION_1) {
 488                 /*
 489                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 490                  * pixels.
 491                  */
 492                 width &= 0x3f0;
 493         } else {
 494                 /*
 495                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 496                  * pixels.
 497                  */
 498                 width &= 0x7f0;
 499         }
 500
 501         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 502         reg &= 0xfffffc00;
 503         if (lcd_revision == LCD_VERSION_1) {
 504                 reg |= ((width >> 4) - 1) << 4;
 505         } else {
 506                 width = (width >> 4) - 1;
 507                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 508         }
 509         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 510
 511         /* Set the Panel Height */
 512         /* Set bits 9:0 of Lines Per Pixel */
 513         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 514         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 515         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 516
 517         /* Set bit 10 of Lines Per Pixel */
 518         if (lcd_revision == LCD_VERSION_2) {
 519                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 520                 reg |= ((height - 1) & 0x400) << 16;
 521                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 522         }
 523
 524         /* Set the Raster Order of the Frame Buffer */
 525         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 526         if (raster_order)
 527                 reg |= LCD_RASTER_ORDER;
 528         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 529
 530         switch (bpp) {
 531         case 1:
 532         case 2:
 533         case 4:
 534         case 16:
 535                 par->palette_sz = 16 * 2;
 536                 break;
 537
 538         case 8:
 539                 par->palette_sz = 256 * 2;
 540                 break;
 541
 542         default:
 543                 return -EINVAL;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 550                               unsigned blue, unsigned transp,
 551                               struct fb_info *info)
 552 {
 553         struct da8xx_fb_par *par = info->par;
 554         unsigned short *palette = (unsigned short *) par->v_palette_base;
 555         u_short pal;
 556         int update_hw = 0;
 557
 558         if (regno > 255)
 559                 return 1;
 560
 561         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 562                 return 1;
 563
 564         if (info->var.bits_per_pixel == 4) {
 565                 if (regno > 15)
 566                         return 1;
 567
 568                 if (info->var.grayscale) {
 569                         pal = regno;
 570                 } else {
 571                         red >>= 4;
 572                         green >>= 8;
 573                         blue >>= 12;
 574
 575                         pal = (red & 0x0f00);
 576                         pal |= (green & 0x00f0);
 577                         pal |= (blue & 0x000f);
 578                 }
 579                 if (regno == 0)
 580                         pal |= 0x2000;
 581                 palette[regno] = pal;
 582
 583         } else if (info->var.bits_per_pixel == 8) {
 584                 red >>= 4;
 585                 green >>= 8;
 586                 blue >>= 12;
 587
 588                 pal = (red & 0x0f00);
 589                 pal |= (green & 0x00f0);
 590                 pal |= (blue & 0x000f);
 591
 592                 if (palette[regno] != pal) {
 593                         update_hw = 1;
 594                         palette[regno] = pal;
 595                 }
 596         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
 597                 red >>= (16 - info->var.red.length);
 598                 red <<= info->var.red.offset;
 599
 600                 green >>= (16 - info->var.green.length);
 601                 green <<= info->var.green.offset;
 602
 603                 blue >>= (16 - info->var.blue.length);
 604                 blue <<= info->var.blue.offset;
 605
 606                 par->pseudo_palette[regno] = red | green | blue;
 607
 608                 if (palette[0] != 0x4000) {
 609                         update_hw = 1;
 610                         palette[0] = 0x4000;
 611                 }
 612         }
 613
 614         /* Update the palette in the h/w as needed. */
 615         if (update_hw)
 616                 lcd_blit(LOAD_PALETTE, par);
 617
 618         return 0;
 619 }
 620
 621 static void lcd_reset(struct da8xx_fb_par *par)
 622 {
 623         /* Disable the Raster if previously Enabled */
 624         lcd_disable_raster();
 625
 626         /* DMA has to be disabled */
 627         lcdc_write(0, LCD_DMA_CTRL_REG);
 628         lcdc_write(0, LCD_RASTER_CTRL_REG);
 629
 630         if (lcd_revision == LCD_VERSION_2) {
 631                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
 632                 /* Write 1 to reset */
 633                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 634                 lcdc_write(0, LCD_CLK_RESET_REG);
 635         }
 636 }
 637
 638 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
 639 {
 640         unsigned int lcd_clk, div;
 641
 642         lcd_clk = clk_get_rate(par->lcdc_clk);
 643         div = lcd_clk / par->pxl_clk;
 644
 645         /* Configure the LCD clock divisor. */
 646         lcdc_write(LCD_CLK_DIVISOR(div) |
 647                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 648
 649         if (lcd_revision == LCD_VERSION_2)
 650                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 651                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
 652
 653 }
 654
 655 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 656                 struct da8xx_panel *panel)
 657 {
 658         u32 bpp;
 659         int ret = 0;
 660
 661         lcd_reset(par);
 662
 663         /* Calculate the divider */
 664         lcd_calc_clk_divider(par);
 665
 666         if (panel->invert_pxl_clk)
 667                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 668                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 669         else
 670                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 671                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 672
 673         /* Configure the DMA burst size. */
 674         ret = lcd_cfg_dma(cfg->dma_burst_sz);
 675         if (ret < 0)
 676                 return ret;
 677
 678         /* Configure the AC bias properties. */
 679         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 680
 681         /* Configure the vertical and horizontal sync properties. */
 682         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 683         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 684
 685         /* Configure for disply */
 686         ret = lcd_cfg_display(cfg);
 687         if (ret < 0)
 688                 return ret;
 689
 690         if (QVGA != cfg->p_disp_panel->panel_type)
 691                 return -EINVAL;
 692
 693         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
 694             cfg->bpp >= cfg->p_disp_panel->min_bpp)
 695                 bpp = cfg->bpp;
 696         else
 697                 bpp = cfg->p_disp_panel->max_bpp;
 698         if (bpp == 12)
 699                 bpp = 16;
 700         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
 701                                 (unsigned int)panel->height, bpp,
 702                                 cfg->raster_order);
 703         if (ret < 0)
 704                 return ret;
 705
 706         /* Configure FDD */
 707         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 708                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 709
 710         return 0;
 711 }
 712
 713 /* IRQ handler for version 2 of LCDC */
 714 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
 715 {
 716         struct da8xx_fb_par *par = arg;
 717         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
 718         u32 reg_int;
 719
 720         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 721                 lcd_disable_raster();
 722                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 723                 lcd_enable_raster();
 724         } else if (stat & LCD_PL_LOAD_DONE) {
 725                 /*
 726                  * Must disable raster before changing state of any control bit.
 727                  * And also must be disabled before clearing the PL loading
 728                  * interrupt via the following write to the status register. If
 729                  * this is done after then one gets multiple PL done interrupts.
 730                  */
 731                 lcd_disable_raster();
 732
 733                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 734
 735                 /* Disable PL completion inerrupt */
 736                 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
 737                        (LCD_V2_PL_INT_ENA);
 738                 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
 739
 740                 /* Setup and start data loading mode */
 741                 lcd_blit(LOAD_DATA, par);
 742         } else {
 743                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 744
 745                 if (stat & LCD_END_OF_FRAME0) {
 746                         lcdc_write(par->dma_start,
 747                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 748                         lcdc_write(par->dma_end,
 749                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 750                         par->vsync_flag = 1;
 751                         wake_up_interruptible(&par->vsync_wait);
 752                 }
 753
 754                 if (stat & LCD_END_OF_FRAME1) {
 755                         lcdc_write(par->dma_start,
 756                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 757                         lcdc_write(par->dma_end,
 758                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 759                         par->vsync_flag = 1;
 760                         wake_up_interruptible(&par->vsync_wait);
 761                 }
 762         }
 763
 764         lcdc_write(0, LCD_END_OF_INT_IND_REG);
 765         return IRQ_HANDLED;
 766 }
 767
 768 /* IRQ handler for version 1 LCDC */
 769 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
 770 {
 771         struct da8xx_fb_par *par = arg;
 772         u32 stat = lcdc_read(LCD_STAT_REG);
 773         u32 reg_ras;
 774
 775         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 776                 lcd_disable_raster();
 777                 lcdc_write(stat, LCD_STAT_REG);
 778                 lcd_enable_raster();
 779         } else if (stat & LCD_PL_LOAD_DONE) {
 780                 /*
 781                  * Must disable raster before changing state of any control bit.
 782                  * And also must be disabled before clearing the PL loading
 783                  * interrupt via the following write to the status register. If
 784                  * this is done after then one gets multiple PL done interrupts.
 785                  */
 786                 lcd_disable_raster();
 787
 788                 lcdc_write(stat, LCD_STAT_REG);
 789
 790                 /* Disable PL completion inerrupt */
 791                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
 792                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 793                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 794
 795                 /* Setup and start data loading mode */
 796                 lcd_blit(LOAD_DATA, par);
 797         } else {
 798                 lcdc_write(stat, LCD_STAT_REG);
 799
 800                 if (stat & LCD_END_OF_FRAME0) {
 801                         lcdc_write(par->dma_start,
 802                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 803                         lcdc_write(par->dma_end,
 804                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 805                         par->vsync_flag = 1;
 806                         wake_up_interruptible(&par->vsync_wait);
 807                 }
 808
 809                 if (stat & LCD_END_OF_FRAME1) {
 810                         lcdc_write(par->dma_start,
 811                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 812                         lcdc_write(par->dma_end,
 813                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 814                         par->vsync_flag = 1;
 815                         wake_up_interruptible(&par->vsync_wait);
 816                 }
 817         }
 818
 819         return IRQ_HANDLED;
 820 }
 821
 822 static int fb_check_var(struct fb_var_screeninfo *var,
 823                         struct fb_info *info)
 824 {
 825         int err = 0;
 826
 827         switch (var->bits_per_pixel) {
 828         case 1:
 829         case 8:
 830                 var->red.offset = 0;
 831                 var->red.length = 8;
 832                 var->green.offset = 0;
 833                 var->green.length = 8;
 834                 var->blue.offset = 0;
 835                 var->blue.length = 8;
 836                 var->transp.offset = 0;
 837                 var->transp.length = 0;
 838                 var->nonstd = 0;
 839                 break;
 840         case 4:
 841                 var->red.offset = 0;
 842                 var->red.length = 4;
 843                 var->green.offset = 0;
 844                 var->green.length = 4;
 845                 var->blue.offset = 0;
 846                 var->blue.length = 4;
 847                 var->transp.offset = 0;
 848                 var->transp.length = 0;
 849                 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
 850                 break;
 851         case 16:                /* RGB 565 */
 852                 var->red.offset = 11;
 853                 var->red.length = 5;
 854                 var->green.offset = 5;
 855                 var->green.length = 6;
 856                 var->blue.offset = 0;
 857                 var->blue.length = 5;
 858                 var->transp.offset = 0;
 859                 var->transp.length = 0;
 860                 var->nonstd = 0;
 861                 break;
 862         default:
 863                 err = -EINVAL;
 864         }
 865
 866         var->red.msb_right = 0;
 867         var->green.msb_right = 0;
 868         var->blue.msb_right = 0;
 869         var->transp.msb_right = 0;
 870         return err;
 871 }
 872
 873 #ifdef CONFIG_CPU_FREQ
 874 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
 875                                      unsigned long val, void *data)
 876 {
 877         struct da8xx_fb_par *par;
 878
 879         par = container_of(nb, struct da8xx_fb_par, freq_transition);
 880         if (val == CPUFREQ_POSTCHANGE) {
 881                 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
 882                         par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
 883                         lcd_disable_raster();
 884                         lcd_calc_clk_divider(par);
 885                         lcd_enable_raster();
 886                 }
 887         }
 888
 889         return 0;
 890 }
 891
 892 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
 893 {
 894         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
 895
 896         return cpufreq_register_notifier(&par->freq_transition,
 897                                          CPUFREQ_TRANSITION_NOTIFIER);
 898 }
 899
 900 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
 901 {
 902         cpufreq_unregister_notifier(&par->freq_transition,
 903                                     CPUFREQ_TRANSITION_NOTIFIER);
 904 }
 905 #endif
 906
 907 static int __devexit fb_remove(struct platform_device *dev)
 908 {
 909         struct fb_info *info = dev_get_drvdata(&dev->dev);
 910
 911         if (info) {
 912                 struct da8xx_fb_par *par = info->par;
 913
 914 #ifdef CONFIG_CPU_FREQ
 915                 lcd_da8xx_cpufreq_deregister(par);
 916 #endif
 917                 if (par->panel_power_ctrl)
 918                         par->panel_power_ctrl(0);
 919
 920                 lcd_disable_raster();
 921                 lcdc_write(0, LCD_RASTER_CTRL_REG);
 922
 923                 /* disable DMA  */
 924                 lcdc_write(0, LCD_DMA_CTRL_REG);
 925
 926                 unregister_framebuffer(info);
 927                 fb_dealloc_cmap(&info->cmap);
 928                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
 929                                   par->p_palette_base);
 930                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
 931                                   par->vram_phys);
 932                 free_irq(par->irq, par);
 933                 clk_disable(par->lcdc_clk);
 934                 clk_put(par->lcdc_clk);
 935                 framebuffer_release(info);
 936                 iounmap((void __iomem *)da8xx_fb_reg_base);
 937                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
 938
 939         }
 940         return 0;
 941 }
 942
 943 /*
 944  * Function to wait for vertical sync which for this LCD peripheral
 945  * translates into waiting for the current raster frame to complete.
 946  */
 947 static int fb_wait_for_vsync(struct fb_info *info)
 948 {
 949         struct da8xx_fb_par *par = info->par;
 950         int ret;
 951
 952         /*
 953          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
 954          * race condition here where the ISR could have occurred just before or
 955          * just after this set. But since we are just coarsely waiting for
 956          * a frame to complete then that's OK. i.e. if the frame completed
 957          * just before this code executed then we have to wait another full
 958          * frame time but there is no way to avoid such a situation. On the
 959          * other hand if the frame completed just after then we don't need
 960          * to wait long at all. Either way we are guaranteed to return to the
 961          * user immediately after a frame completion which is all that is
 962          * required.
 963          */
 964         par->vsync_flag = 0;
 965         ret = wait_event_interruptible_timeout(par->vsync_wait,
 966                                                par->vsync_flag != 0,
 967                                                par->vsync_timeout);
 968         if (ret < 0)
 969                 return ret;
 970         if (ret == 0)
 971                 return -ETIMEDOUT;
 972
 973         return 0;
 974 }
 975
 976 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
 977                           unsigned long arg)
 978 {
 979         struct lcd_sync_arg sync_arg;
 980
 981         switch (cmd) {
 982         case FBIOGET_CONTRAST:
 983         case FBIOPUT_CONTRAST:
 984         case FBIGET_BRIGHTNESS:
 985         case FBIPUT_BRIGHTNESS:
 986         case FBIGET_COLOR:
 987         case FBIPUT_COLOR:
 988                 return -ENOTTY;
 989         case FBIPUT_HSYNC:
 990                 if (copy_from_user(&sync_arg, (char *)arg,
 991                                 sizeof(struct lcd_sync_arg)))
 992                         return -EFAULT;
 993                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
 994                                         sync_arg.pulse_width,
 995                                         sync_arg.front_porch);
 996                 break;
 997         case FBIPUT_VSYNC:
 998                 if (copy_from_user(&sync_arg, (char *)arg,
 999                                 sizeof(struct lcd_sync_arg)))
1000                         return -EFAULT;
1001                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1002                                         sync_arg.pulse_width,
1003                                         sync_arg.front_porch);
1004                 break;
1005         case FBIO_WAITFORVSYNC:
1006                 return fb_wait_for_vsync(info);
1007         default:
1008                 return -EINVAL;
1009         }
1010         return 0;
1011 }
1012
1013 static int cfb_blank(int blank, struct fb_info *info)
1014 {
1015         struct da8xx_fb_par *par = info->par;
1016         int ret = 0;
1017
1018         if (par->blank == blank)
1019                 return 0;
1020
1021         par->blank = blank;
1022         switch (blank) {
1023         case FB_BLANK_UNBLANK:
1024                 if (par->panel_power_ctrl)
1025                         par->panel_power_ctrl(1);
1026
1027                 lcd_enable_raster();
1028                 break;
1029         case FB_BLANK_POWERDOWN:
1030                 if (par->panel_power_ctrl)
1031                         par->panel_power_ctrl(0);
1032
1033                 lcd_disable_raster();
1034                 break;
1035         default:
1036                 ret = -EINVAL;
1037         }
1038
1039         return ret;
1040 }
1041
1042 /*
1043  * Set new x,y offsets in the virtual display for the visible area and switch
1044  * to the new mode.
1045  */
1046 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1047                              struct fb_info *fbi)
1048 {
1049         int ret = 0;
1050         struct fb_var_screeninfo new_var;
1051         struct da8xx_fb_par         *par = fbi->par;
1052         struct fb_fix_screeninfo    *fix = &fbi->fix;
1053         unsigned int end;
1054         unsigned int start;
1055
1056         if (var->xoffset != fbi->var.xoffset ||
1057                         var->yoffset != fbi->var.yoffset) {
1058                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1059                 new_var.xoffset = var->xoffset;
1060                 new_var.yoffset = var->yoffset;
1061                 if (fb_check_var(&new_var, fbi))
1062                         ret = -EINVAL;
1063                 else {
1064                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1065
1066                         start   = fix->smem_start +
1067                                 new_var.yoffset * fix->line_length +
1068                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1069                         end     = start + fbi->var.yres * fix->line_length - 1;
1070                         par->dma_start  = start;
1071                         par->dma_end    = end;
1072                 }
1073         }
1074
1075         return ret;
1076 }
1077
1078 static struct fb_ops da8xx_fb_ops = {
1079         .owner = THIS_MODULE,
1080         .fb_check_var = fb_check_var,
1081         .fb_setcolreg = fb_setcolreg,
1082         .fb_pan_display = da8xx_pan_display,
1083         .fb_ioctl = fb_ioctl,
1084         .fb_fillrect = cfb_fillrect,
1085         .fb_copyarea = cfb_copyarea,
1086         .fb_imageblit = cfb_imageblit,
1087         .fb_blank = cfb_blank,
1088 };
1089
1090 /* Calculate and return pixel clock period in pico seconds */
1091 static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
1092 {
1093         unsigned int lcd_clk, div;
1094         unsigned int configured_pix_clk;
1095         unsigned long long pix_clk_period_picosec = 1000000000000ULL;
1096
1097         lcd_clk = clk_get_rate(par->lcdc_clk);
1098         div = lcd_clk / par->pxl_clk;
1099         configured_pix_clk = (lcd_clk / div);
1100
1101         do_div(pix_clk_period_picosec, configured_pix_clk);
1102
1103         return pix_clk_period_picosec;
1104 }
1105
1106 static int __devinit fb_probe(struct platform_device *device)
1107 {
1108         struct da8xx_lcdc_platform_data *fb_pdata =
1109                                                 device->dev.platform_data;
1110         struct lcd_ctrl_config *lcd_cfg;
1111         struct da8xx_panel *lcdc_info;
1112         struct fb_info *da8xx_fb_info;
1113         struct clk *fb_clk = NULL;
1114         struct da8xx_fb_par *par;
1115         resource_size_t len;
1116         int ret, i;
1117
1118         if (fb_pdata == NULL) {
1119                 dev_err(&device->dev, "Can not get platform data\n");
1120                 return -ENOENT;
1121         }
1122
1123         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1124         if (!lcdc_regs) {
1125                 dev_err(&device->dev,
1126                         "Can not get memory resource for LCD controller\n");
1127                 return -ENOENT;
1128         }
1129
1130         len = resource_size(lcdc_regs);
1131
1132         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1133         if (!lcdc_regs)
1134                 return -EBUSY;
1135
1136         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1137         if (!da8xx_fb_reg_base) {
1138                 ret = -EBUSY;
1139                 goto err_request_mem;
1140         }
1141
1142         fb_clk = clk_get(&device->dev, NULL);
1143         if (IS_ERR(fb_clk)) {
1144                 dev_err(&device->dev, "Can not get device clock\n");
1145                 ret = -ENODEV;
1146                 goto err_ioremap;
1147         }
1148         ret = clk_enable(fb_clk);
1149         if (ret)
1150                 goto err_clk_put;
1151
1152         /* Determine LCD IP Version */
1153         switch (lcdc_read(LCD_PID_REG)) {
1154         case 0x4C100102:
1155                 lcd_revision = LCD_VERSION_1;
1156                 break;
1157         case 0x4F200800:
1158                 lcd_revision = LCD_VERSION_2;
1159                 break;
1160         default:
1161                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1162                                 "defaulting to LCD revision 1\n",
1163                                 lcdc_read(LCD_PID_REG));
1164                 lcd_revision = LCD_VERSION_1;
1165                 break;
1166         }
1167
1168         for (i = 0, lcdc_info = known_lcd_panels;
1169                 i < ARRAY_SIZE(known_lcd_panels);
1170                 i++, lcdc_info++) {
1171                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1172                         break;
1173         }
1174
1175         if (i == ARRAY_SIZE(known_lcd_panels)) {
1176                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1177                 ret = -ENODEV;
1178                 goto err_clk_disable;
1179         } else
1180                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1181                                         fb_pdata->type);
1182
1183         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1184
1185         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1186                                         &device->dev);
1187         if (!da8xx_fb_info) {
1188                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1189                 ret = -ENOMEM;
1190                 goto err_clk_disable;
1191         }
1192
1193         par = da8xx_fb_info->par;
1194         par->lcdc_clk = fb_clk;
1195 #ifdef CONFIG_CPU_FREQ
1196         par->lcd_fck_rate = clk_get_rate(fb_clk);
1197 #endif
1198         par->pxl_clk = lcdc_info->pxl_clk;
1199         if (fb_pdata->panel_power_ctrl) {
1200                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1201                 par->panel_power_ctrl(1);
1202         }
1203
1204         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1205                 dev_err(&device->dev, "lcd_init failed\n");
1206                 ret = -EFAULT;
1207                 goto err_release_fb;
1208         }
1209
1210         /* allocate frame buffer */
1211         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1212         par->vram_size = PAGE_ALIGN(par->vram_size/8);
1213         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1214
1215         par->vram_virt = dma_alloc_coherent(NULL,
1216                                             par->vram_size,
1217                                             (resource_size_t *) &par->vram_phys,
1218                                             GFP_KERNEL | GFP_DMA);
1219         if (!par->vram_virt) {
1220                 dev_err(&device->dev,
1221                         "GLCD: kmalloc for frame buffer failed\n");
1222                 ret = -EINVAL;
1223                 goto err_release_fb;
1224         }
1225
1226         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1227         da8xx_fb_fix.smem_start    = par->vram_phys;
1228         da8xx_fb_fix.smem_len      = par->vram_size;
1229         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1230
1231         par->dma_start = par->vram_phys;
1232         par->dma_end   = par->dma_start + lcdc_info->height *
1233                 da8xx_fb_fix.line_length - 1;
1234
1235         /* allocate palette buffer */
1236         par->v_palette_base = dma_alloc_coherent(NULL,
1237                                                PALETTE_SIZE,
1238                                                (resource_size_t *)
1239                                                &par->p_palette_base,
1240                                                GFP_KERNEL | GFP_DMA);
1241         if (!par->v_palette_base) {
1242                 dev_err(&device->dev,
1243                         "GLCD: kmalloc for palette buffer failed\n");
1244                 ret = -EINVAL;
1245                 goto err_release_fb_mem;
1246         }
1247         memset(par->v_palette_base, 0, PALETTE_SIZE);
1248
1249         par->irq = platform_get_irq(device, 0);
1250         if (par->irq < 0) {
1251                 ret = -ENOENT;
1252                 goto err_release_pl_mem;
1253         }
1254
1255         /* Initialize par */
1256         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1257
1258         da8xx_fb_var.xres = lcdc_info->width;
1259         da8xx_fb_var.xres_virtual = lcdc_info->width;
1260
1261         da8xx_fb_var.yres         = lcdc_info->height;
1262         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1263
1264         da8xx_fb_var.grayscale =
1265             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1266         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1267
1268         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1269         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1270         da8xx_fb_var.right_margin = lcdc_info->hfp;
1271         da8xx_fb_var.left_margin  = lcdc_info->hbp;
1272         da8xx_fb_var.lower_margin = lcdc_info->vfp;
1273         da8xx_fb_var.upper_margin = lcdc_info->vbp;
1274         da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
1275
1276         /* Initialize fbinfo */
1277         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1278         da8xx_fb_info->fix = da8xx_fb_fix;
1279         da8xx_fb_info->var = da8xx_fb_var;
1280         da8xx_fb_info->fbops = &da8xx_fb_ops;
1281         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1282         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1283                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1284
1285         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1286         if (ret)
1287                 goto err_release_pl_mem;
1288         da8xx_fb_info->cmap.len = par->palette_sz;
1289
1290         /* initialize var_screeninfo */
1291         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1292         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1293
1294         dev_set_drvdata(&device->dev, da8xx_fb_info);
1295
1296         /* initialize the vsync wait queue */
1297         init_waitqueue_head(&par->vsync_wait);
1298         par->vsync_timeout = HZ / 5;
1299
1300         /* Register the Frame Buffer  */
1301         if (register_framebuffer(da8xx_fb_info) < 0) {
1302                 dev_err(&device->dev,
1303                         "GLCD: Frame Buffer Registration Failed!\n");
1304                 ret = -EINVAL;
1305                 goto err_dealloc_cmap;
1306         }
1307
1308 #ifdef CONFIG_CPU_FREQ
1309         ret = lcd_da8xx_cpufreq_register(par);
1310         if (ret) {
1311                 dev_err(&device->dev, "failed to register cpufreq\n");
1312                 goto err_cpu_freq;
1313         }
1314 #endif
1315
1316         if (lcd_revision == LCD_VERSION_1)
1317                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1318         else
1319                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1320
1321         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1322                         DRIVER_NAME, par);
1323         if (ret)
1324                 goto irq_freq;
1325         return 0;
1326
1327 irq_freq:
1328 #ifdef CONFIG_CPU_FREQ
1329         lcd_da8xx_cpufreq_deregister(par);
1330 err_cpu_freq:
1331 #endif
1332         unregister_framebuffer(da8xx_fb_info);
1333
1334 err_dealloc_cmap:
1335         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1336
1337 err_release_pl_mem:
1338         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1339                           par->p_palette_base);
1340
1341 err_release_fb_mem:
1342         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1343
1344 err_release_fb:
1345         framebuffer_release(da8xx_fb_info);
1346
1347 err_clk_disable:
1348         clk_disable(fb_clk);
1349
1350 err_clk_put:
1351         clk_put(fb_clk);
1352
1353 err_ioremap:
1354         iounmap((void __iomem *)da8xx_fb_reg_base);
1355
1356 err_request_mem:
1357         release_mem_region(lcdc_regs->start, len);
1358
1359         return ret;
1360 }
1361
1362 #ifdef CONFIG_PM
1363 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1364 {
1365         struct fb_info *info = platform_get_drvdata(dev);
1366         struct da8xx_fb_par *par = info->par;
1367
1368         console_lock();
1369         if (par->panel_power_ctrl)
1370                 par->panel_power_ctrl(0);
1371
1372         fb_set_suspend(info, 1);
1373         lcd_disable_raster();
1374         clk_disable(par->lcdc_clk);
1375         console_unlock();
1376
1377         return 0;
1378 }
1379 static int fb_resume(struct platform_device *dev)
1380 {
1381         struct fb_info *info = platform_get_drvdata(dev);
1382         struct da8xx_fb_par *par = info->par;
1383
1384         console_lock();
1385         if (par->panel_power_ctrl)
1386                 par->panel_power_ctrl(1);
1387
1388         clk_enable(par->lcdc_clk);
1389         lcd_enable_raster();
1390         fb_set_suspend(info, 0);
1391         console_unlock();
1392
1393         return 0;
1394 }
1395 #else
1396 #define fb_suspend NULL
1397 #define fb_resume NULL
1398 #endif
1399
1400 static struct platform_driver da8xx_fb_driver = {
1401         .probe = fb_probe,
1402         .remove = __devexit_p(fb_remove),
1403         .suspend = fb_suspend,
1404         .resume = fb_resume,
1405         .driver = {
1406                    .name = DRIVER_NAME,
1407                    .owner = THIS_MODULE,
1408                    },
1409 };
1410
1411 static int __init da8xx_fb_init(void)
1412 {
1413         return platform_driver_register(&da8xx_fb_driver);
1414 }
1415
1416 static void __exit da8xx_fb_cleanup(void)
1417 {
1418         platform_driver_unregister(&da8xx_fb_driver);
1419 }
1420
1421 module_init(da8xx_fb_init);
1422 module_exit(da8xx_fb_cleanup);
1423
1424 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1425 MODULE_AUTHOR("Texas Instruments");
1426 MODULE_LICENSE("GPL");