drivers/video/cg3.c

   1 /* cg3.c: CGTHREE frame buffer driver
   2  *
   3  * Copyright (C) 2003 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
   5  * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
   6  * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
   7  *
   8  * Driver layout based loosely on tgafb.c, see that file for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/errno.h>
  14 #include <linux/string.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/fb.h>
  19 #include <linux/mm.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/sbus.h>
  23 #include <asm/oplib.h>
  24 #include <asm/fbio.h>
  25
  26 #include "sbuslib.h"
  27
  28 /*
  29  * Local functions.
  30  */
  31
  32 static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
  33                          unsigned, struct fb_info *);
  34 static int cg3_blank(int, struct fb_info *);
  35
  36 static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
  37 static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
  38
  39 /*
  40  *  Frame buffer operations
  41  */
  42
  43 static struct fb_ops cg3_ops = {
  44         .owner                  = THIS_MODULE,
  45         .fb_setcolreg           = cg3_setcolreg,
  46         .fb_blank               = cg3_blank,
  47         .fb_fillrect            = cfb_fillrect,
  48         .fb_copyarea            = cfb_copyarea,
  49         .fb_imageblit           = cfb_imageblit,
  50         .fb_mmap                = cg3_mmap,
  51         .fb_ioctl               = cg3_ioctl,
  52 #ifdef CONFIG_COMPAT
  53         .fb_compat_ioctl        = sbusfb_compat_ioctl,
  54 #endif
  55 };
  56
  57
  58 /* Control Register Constants */
  59 #define CG3_CR_ENABLE_INTS      0x80
  60 #define CG3_CR_ENABLE_VIDEO     0x40
  61 #define CG3_CR_ENABLE_TIMING    0x20
  62 #define CG3_CR_ENABLE_CURCMP    0x10
  63 #define CG3_CR_XTAL_MASK        0x0c
  64 #define CG3_CR_DIVISOR_MASK     0x03
  65
  66 /* Status Register Constants */
  67 #define CG3_SR_PENDING_INT      0x80
  68 #define CG3_SR_RES_MASK         0x70
  69 #define CG3_SR_1152_900_76_A    0x40
  70 #define CG3_SR_1152_900_76_B    0x60
  71 #define CG3_SR_ID_MASK          0x0f
  72 #define CG3_SR_ID_COLOR         0x01
  73 #define CG3_SR_ID_MONO          0x02
  74 #define CG3_SR_ID_MONO_ECL      0x03
  75
  76 enum cg3_type {
  77         CG3_AT_66HZ = 0,
  78         CG3_AT_76HZ,
  79         CG3_RDI
  80 };
  81
  82 struct bt_regs {
  83         volatile u32 addr;
  84         volatile u32 color_map;
  85         volatile u32 control;
  86         volatile u32 cursor;
  87 };
  88
  89 struct cg3_regs {
  90         struct bt_regs  cmap;
  91         volatile u8     control;
  92         volatile u8     status;
  93         volatile u8     cursor_start;
  94         volatile u8     cursor_end;
  95         volatile u8     h_blank_start;
  96         volatile u8     h_blank_end;
  97         volatile u8     h_sync_start;
  98         volatile u8     h_sync_end;
  99         volatile u8     comp_sync_end;
 100         volatile u8     v_blank_start_high;
 101         volatile u8     v_blank_start_low;
 102         volatile u8     v_blank_end;
 103         volatile u8     v_sync_start;
 104         volatile u8     v_sync_end;
 105         volatile u8     xfer_holdoff_start;
 106         volatile u8     xfer_holdoff_end;
 107 };
 108
 109 /* Offset of interesting structures in the OBIO space */
 110 #define CG3_REGS_OFFSET      0x400000UL
 111 #define CG3_RAM_OFFSET       0x800000UL
 112
 113 struct cg3_par {
 114         spinlock_t              lock;
 115         struct cg3_regs         __iomem *regs;
 116         u32                     sw_cmap[((256 * 3) + 3) / 4];
 117
 118         u32                     flags;
 119 #define CG3_FLAG_BLANKED        0x00000001
 120 #define CG3_FLAG_RDI            0x00000002
 121
 122         unsigned long           physbase;
 123         unsigned long           fbsize;
 124
 125         struct sbus_dev         *sdev;
 126 };
 127
 128 /**
 129  *      cg3_setcolreg - Optional function. Sets a color register.
 130  *      @regno: boolean, 0 copy local, 1 get_user() function
 131  *      @red: frame buffer colormap structure
 132  *      @green: The green value which can be up to 16 bits wide
 133  *      @blue:  The blue value which can be up to 16 bits wide.
 134  *      @transp: If supported the alpha value which can be up to 16 bits wide.
 135  *      @info: frame buffer info structure
 136  *
 137  * The cg3 palette is loaded with 4 color values at each time
 138  * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
 139  * We keep a sw copy of the hw cmap to assist us in this esoteric
 140  * loading procedure.
 141  */
 142 static int cg3_setcolreg(unsigned regno,
 143                          unsigned red, unsigned green, unsigned blue,
 144                          unsigned transp, struct fb_info *info)
 145 {
 146         struct cg3_par *par = (struct cg3_par *) info->par;
 147         struct bt_regs __iomem *bt = &par->regs->cmap;
 148         unsigned long flags;
 149         u32 *p32;
 150         u8 *p8;
 151         int count;
 152
 153         if (regno >= 256)
 154                 return 1;
 155
 156         red >>= 8;
 157         green >>= 8;
 158         blue >>= 8;
 159
 160         spin_lock_irqsave(&par->lock, flags);
 161
 162         p8 = (u8 *)par->sw_cmap + (regno * 3);
 163         p8[0] = red;
 164         p8[1] = green;
 165         p8[2] = blue;
 166
 167 #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2))      /* (x/4)*3 */
 168 #define D4M4(x) ((x)&~0x3)                      /* (x/4)*4 */
 169
 170         count = 3;
 171         p32 = &par->sw_cmap[D4M3(regno)];
 172         sbus_writel(D4M4(regno), &bt->addr);
 173         while (count--)
 174                 sbus_writel(*p32++, &bt->color_map);
 175
 176 #undef D4M3
 177 #undef D4M4
 178
 179         spin_unlock_irqrestore(&par->lock, flags);
 180
 181         return 0;
 182 }
 183
 184 /**
 185  *      cg3_blank - Optional function.  Blanks the display.
 186  *      @blank_mode: the blank mode we want.
 187  *      @info: frame buffer structure that represents a single frame buffer
 188  */
 189 static int
 190 cg3_blank(int blank, struct fb_info *info)
 191 {
 192         struct cg3_par *par = (struct cg3_par *) info->par;
 193         struct cg3_regs __iomem *regs = par->regs;
 194         unsigned long flags;
 195         u8 val;
 196
 197         spin_lock_irqsave(&par->lock, flags);
 198
 199         switch (blank) {
 200         case FB_BLANK_UNBLANK: /* Unblanking */
 201                 val = sbus_readb(&regs->control);
 202                 val |= CG3_CR_ENABLE_VIDEO;
 203                 sbus_writeb(val, &regs->control);
 204                 par->flags &= ~CG3_FLAG_BLANKED;
 205                 break;
 206
 207         case FB_BLANK_NORMAL: /* Normal blanking */
 208         case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
 209         case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
 210         case FB_BLANK_POWERDOWN: /* Poweroff */
 211                 val = sbus_readb(&regs->control);
 212                 val &= ~CG3_CR_ENABLE_VIDEO;
 213                 sbus_writeb(val, &regs->control);
 214                 par->flags |= CG3_FLAG_BLANKED;
 215                 break;
 216         }
 217
 218         spin_unlock_irqrestore(&par->lock, flags);
 219
 220         return 0;
 221 }
 222
 223 static struct sbus_mmap_map cg3_mmap_map[] = {
 224         {
 225                 .voff   = CG3_MMAP_OFFSET,
 226                 .poff   = CG3_RAM_OFFSET,
 227                 .size   = SBUS_MMAP_FBSIZE(1)
 228         },
 229         { .size = 0 }
 230 };
 231
 232 static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
 233 {
 234         struct cg3_par *par = (struct cg3_par *)info->par;
 235
 236         return sbusfb_mmap_helper(cg3_mmap_map,
 237                                   par->physbase, par->fbsize,
 238                                   par->sdev->reg_addrs[0].which_io,
 239                                   vma);
 240 }
 241
 242 static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
 243 {
 244         struct cg3_par *par = (struct cg3_par *) info->par;
 245
 246         return sbusfb_ioctl_helper(cmd, arg, info,
 247                                    FBTYPE_SUN3COLOR, 8, par->fbsize);
 248 }
 249
 250 /*
 251  *  Initialisation
 252  */
 253
 254 static void
 255 cg3_init_fix(struct fb_info *info, int linebytes)
 256 {
 257         struct cg3_par *par = (struct cg3_par *)info->par;
 258
 259         strlcpy(info->fix.id, par->sdev->prom_name, sizeof(info->fix.id));
 260
 261         info->fix.type = FB_TYPE_PACKED_PIXELS;
 262         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 263
 264         info->fix.line_length = linebytes;
 265
 266         info->fix.accel = FB_ACCEL_SUN_CGTHREE;
 267 }
 268
 269 static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
 270                                     struct sbus_dev *sdev)
 271 {
 272         char buffer[40];
 273         char *p;
 274         int ww, hh;
 275
 276         *buffer = 0;
 277         prom_getstring(sdev->prom_node, "params", buffer, sizeof(buffer));
 278         if (*buffer) {
 279                 ww = simple_strtoul(buffer, &p, 10);
 280                 if (ww && *p == 'x') {
 281                         hh = simple_strtoul(p + 1, &p, 10);
 282                         if (hh && *p == '-') {
 283                                 if (var->xres != ww ||
 284                                     var->yres != hh) {
 285                                         var->xres = var->xres_virtual = ww;
 286                                         var->yres = var->yres_virtual = hh;
 287                                 }
 288                         }
 289                 }
 290         }
 291 }
 292
 293 static u8 cg3regvals_66hz[] __initdata = {      /* 1152 x 900, 66 Hz */
 294         0x14, 0xbb,     0x15, 0x2b,     0x16, 0x04,     0x17, 0x14,
 295         0x18, 0xae,     0x19, 0x03,     0x1a, 0xa8,     0x1b, 0x24,
 296         0x1c, 0x01,     0x1d, 0x05,     0x1e, 0xff,     0x1f, 0x01,
 297         0x10, 0x20,     0
 298 };
 299
 300 static u8 cg3regvals_76hz[] __initdata = {      /* 1152 x 900, 76 Hz */
 301         0x14, 0xb7,     0x15, 0x27,     0x16, 0x03,     0x17, 0x0f,
 302         0x18, 0xae,     0x19, 0x03,     0x1a, 0xae,     0x1b, 0x2a,
 303         0x1c, 0x01,     0x1d, 0x09,     0x1e, 0xff,     0x1f, 0x01,
 304         0x10, 0x24,     0
 305 };
 306
 307 static u8 cg3regvals_rdi[] __initdata = {       /* 640 x 480, cgRDI */
 308         0x14, 0x70,     0x15, 0x20,     0x16, 0x08,     0x17, 0x10,
 309         0x18, 0x06,     0x19, 0x02,     0x1a, 0x31,     0x1b, 0x51,
 310         0x1c, 0x06,     0x1d, 0x0c,     0x1e, 0xff,     0x1f, 0x01,
 311         0x10, 0x22,     0
 312 };
 313
 314 static u8 *cg3_regvals[] __initdata = {
 315         cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
 316 };
 317
 318 static u_char cg3_dacvals[] __initdata = {
 319         4, 0xff,        5, 0x00,        6, 0x70,        7, 0x00,        0
 320 };
 321
 322 static void cg3_do_default_mode(struct cg3_par *par)
 323 {
 324         enum cg3_type type;
 325         u8 *p;
 326
 327         if (par->flags & CG3_FLAG_RDI)
 328                 type = CG3_RDI;
 329         else {
 330                 u8 status = sbus_readb(&par->regs->status), mon;
 331                 if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
 332                         mon = status & CG3_SR_RES_MASK;
 333                         if (mon == CG3_SR_1152_900_76_A ||
 334                             mon == CG3_SR_1152_900_76_B)
 335                                 type = CG3_AT_76HZ;
 336                         else
 337                                 type = CG3_AT_66HZ;
 338                 } else {
 339                         prom_printf("cgthree: can't handle SR %02x\n",
 340                                     status);
 341                         prom_halt();
 342                         return;
 343                 }
 344         }
 345
 346         for (p = cg3_regvals[type]; *p; p += 2) {
 347                 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
 348                 sbus_writeb(p[1], regp);
 349         }
 350         for (p = cg3_dacvals; *p; p += 2) {
 351                 volatile u8 __iomem *regp;
 352
 353                 regp = (volatile u8 __iomem *)&par->regs->cmap.addr;
 354                 sbus_writeb(p[0], regp);
 355                 regp = (volatile u8 __iomem *)&par->regs->cmap.control;
 356                 sbus_writeb(p[1], regp);
 357         }
 358 }
 359
 360 struct all_info {
 361         struct fb_info info;
 362         struct cg3_par par;
 363         struct list_head list;
 364 };
 365 static LIST_HEAD(cg3_list);
 366
 367 static void cg3_init_one(struct sbus_dev *sdev)
 368 {
 369         struct all_info *all;
 370         int linebytes;
 371
 372         all = kmalloc(sizeof(*all), GFP_KERNEL);
 373         if (!all) {
 374                 printk(KERN_ERR "cg3: Cannot allocate memory.\n");
 375                 return;
 376         }
 377         memset(all, 0, sizeof(*all));
 378
 379         INIT_LIST_HEAD(&all->list);
 380
 381         spin_lock_init(&all->par.lock);
 382         all->par.sdev = sdev;
 383
 384         all->par.physbase = sdev->reg_addrs[0].phys_addr;
 385
 386         sbusfb_fill_var(&all->info.var, sdev->prom_node, 8);
 387         all->info.var.red.length = 8;
 388         all->info.var.green.length = 8;
 389         all->info.var.blue.length = 8;
 390         if (!strcmp(sdev->prom_name, "cgRDI"))
 391                 all->par.flags |= CG3_FLAG_RDI;
 392         if (all->par.flags & CG3_FLAG_RDI)
 393                 cg3_rdi_maybe_fixup_var(&all->info.var, sdev);
 394
 395         linebytes = prom_getintdefault(sdev->prom_node, "linebytes",
 396                                        all->info.var.xres);
 397         all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
 398
 399         all->par.regs = sbus_ioremap(&sdev->resource[0], CG3_REGS_OFFSET,
 400                              sizeof(struct cg3_regs), "cg3 regs");
 401
 402         all->info.flags = FBINFO_DEFAULT;
 403         all->info.fbops = &cg3_ops;
 404 #ifdef CONFIG_SPARC32
 405         all->info.screen_base = (char __iomem *)
 406                 prom_getintdefault(sdev->prom_node, "address", 0);
 407 #endif
 408         if (!all->info.screen_base)
 409                 all->info.screen_base =
 410                         sbus_ioremap(&sdev->resource[0], CG3_RAM_OFFSET,
 411                                      all->par.fbsize, "cg3 ram");
 412         all->info.par = &all->par;
 413
 414         cg3_blank(0, &all->info);
 415
 416         if (!prom_getbool(sdev->prom_node, "width"))
 417                 cg3_do_default_mode(&all->par);
 418
 419         if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
 420                 printk(KERN_ERR "cg3: Could not allocate color map.\n");
 421                 kfree(all);
 422                 return;
 423         }
 424         fb_set_cmap(&all->info.cmap, &all->info);
 425
 426         cg3_init_fix(&all->info, linebytes);
 427
 428         if (register_framebuffer(&all->info) < 0) {
 429                 printk(KERN_ERR "cg3: Could not register framebuffer.\n");
 430                 fb_dealloc_cmap(&all->info.cmap);
 431                 kfree(all);
 432                 return;
 433         }
 434
 435         list_add(&all->list, &cg3_list);
 436
 437         printk("cg3: %s at %lx:%lx\n",
 438                sdev->prom_name,
 439                (long) sdev->reg_addrs[0].which_io,
 440                (long) sdev->reg_addrs[0].phys_addr);
 441 }
 442
 443 int __init cg3_init(void)
 444 {
 445         struct sbus_bus *sbus;
 446         struct sbus_dev *sdev;
 447
 448         if (fb_get_options("cg3fb", NULL))
 449                 return -ENODEV;
 450
 451         for_all_sbusdev(sdev, sbus) {
 452                 if (!strcmp(sdev->prom_name, "cgthree") ||
 453                     !strcmp(sdev->prom_name, "cgRDI"))
 454                         cg3_init_one(sdev);
 455         }
 456
 457         return 0;
 458 }
 459
 460 void __exit cg3_exit(void)
 461 {
 462         struct list_head *pos, *tmp;
 463
 464         list_for_each_safe(pos, tmp, &cg3_list) {
 465                 struct all_info *all = list_entry(pos, typeof(*all), list);
 466
 467                 unregister_framebuffer(&all->info);
 468                 fb_dealloc_cmap(&all->info.cmap);
 469                 kfree(all);
 470         }
 471 }
 472
 473 int __init
 474 cg3_setup(char *arg)
 475 {
 476         /* No cmdline options yet... */
 477         return 0;
 478 }
 479
 480 module_init(cg3_init);
 481
 482 #ifdef MODULE
 483 module_exit(cg3_exit);
 484 #endif
 485
 486 MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
 487 MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
 488 MODULE_LICENSE("GPL");