drivers/usb/otg/twl4030-usb.c

   1 /*
   2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
   3  *
   4  * Copyright (C) 2004-2007 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Current status:
  23  *      - HS USB ULPI mode works.
  24  *      - 3-pin mode support may be added in future.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/io.h>
  34 #include <linux/delay.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/ulpi.h>
  37 #include <linux/i2c/twl.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/err.h>
  40 #include <linux/notifier.h>
  41 #include <linux/slab.h>
  42
  43 /* Register defines */
  44
  45 #define MCPC_CTRL                       0x30
  46 #define MCPC_CTRL_RTSOL                 (1 << 7)
  47 #define MCPC_CTRL_EXTSWR                (1 << 6)
  48 #define MCPC_CTRL_EXTSWC                (1 << 5)
  49 #define MCPC_CTRL_VOICESW               (1 << 4)
  50 #define MCPC_CTRL_OUT64K                (1 << 3)
  51 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
  52 #define MCPC_CTRL_HS_UART               (1 << 0)
  53
  54 #define MCPC_IO_CTRL                    0x33
  55 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
  56 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
  57 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
  58 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
  59 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
  60 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
  61
  62 #define MCPC_CTRL2                      0x36
  63 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
  64
  65 #define OTHER_FUNC_CTRL                 0x80
  66 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
  67 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
  68
  69 #define OTHER_IFC_CTRL                  0x83
  70 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
  71 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
  72 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
  73 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
  74 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
  75 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
  76
  77 #define OTHER_INT_EN_RISE               0x86
  78 #define OTHER_INT_EN_FALL               0x89
  79 #define OTHER_INT_STS                   0x8C
  80 #define OTHER_INT_LATCH                 0x8D
  81 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
  82 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
  83 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
  84 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
  85 #define OTHER_INT_MANU                  (1 << 1)
  86 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
  87
  88 #define ID_STATUS                       0x96
  89 #define ID_RES_FLOAT                    (1 << 4)
  90 #define ID_RES_440K                     (1 << 3)
  91 #define ID_RES_200K                     (1 << 2)
  92 #define ID_RES_102K                     (1 << 1)
  93 #define ID_RES_GND                      (1 << 0)
  94
  95 #define POWER_CTRL                      0xAC
  96 #define POWER_CTRL_OTG_ENAB             (1 << 5)
  97
  98 #define OTHER_IFC_CTRL2                 0xAF
  99 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
 100 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
 101 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
 102 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
 103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
 104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
 105
 106 #define REG_CTRL_EN                     0xB2
 107 #define REG_CTRL_ERROR                  0xB5
 108 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
 109
 110 #define OTHER_FUNC_CTRL2                0xB8
 111 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
 112
 113 /* following registers do not have separate _clr and _set registers */
 114 #define VBUS_DEBOUNCE                   0xC0
 115 #define ID_DEBOUNCE                     0xC1
 116 #define VBAT_TIMER                      0xD3
 117 #define PHY_PWR_CTRL                    0xFD
 118 #define PHY_PWR_PHYPWD                  (1 << 0)
 119 #define PHY_CLK_CTRL                    0xFE
 120 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
 121 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
 122 #define REQ_PHY_DPLL_CLK                (1 << 0)
 123 #define PHY_CLK_CTRL_STS                0xFF
 124 #define PHY_DPLL_CLK                    (1 << 0)
 125
 126 /* In module TWL4030_MODULE_PM_MASTER */
 127 #define PROTECT_KEY                     0x0E
 128 #define STS_HW_CONDITIONS               0x0F
 129
 130 /* In module TWL4030_MODULE_PM_RECEIVER */
 131 #define VUSB_DEDICATED1                 0x7D
 132 #define VUSB_DEDICATED2                 0x7E
 133 #define VUSB1V5_DEV_GRP                 0x71
 134 #define VUSB1V5_TYPE                    0x72
 135 #define VUSB1V5_REMAP                   0x73
 136 #define VUSB1V8_DEV_GRP                 0x74
 137 #define VUSB1V8_TYPE                    0x75
 138 #define VUSB1V8_REMAP                   0x76
 139 #define VUSB3V1_DEV_GRP                 0x77
 140 #define VUSB3V1_TYPE                    0x78
 141 #define VUSB3V1_REMAP                   0x79
 142
 143 /* In module TWL4030_MODULE_INTBR */
 144 #define PMBR1                           0x0D
 145 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
 146
 147 struct twl4030_usb {
 148         struct otg_transceiver  otg;
 149         struct device           *dev;
 150
 151         /* TWL4030 internal USB regulator supplies */
 152         struct regulator        *usb1v5;
 153         struct regulator        *usb1v8;
 154         struct regulator        *usb3v1;
 155
 156         /* for vbus reporting with irqs disabled */
 157         spinlock_t              lock;
 158
 159         /* pin configuration */
 160         enum twl4030_usb_mode   usb_mode;
 161
 162         int                     irq;
 163         u8                      linkstat;
 164         u8                      asleep;
 165         bool                    irq_enabled;
 166 };
 167
 168 /* internal define on top of container_of */
 169 #define xceiv_to_twl(x)         container_of((x), struct twl4030_usb, otg);
 170
 171 /*-------------------------------------------------------------------------*/
 172
 173 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
 174                 u8 module, u8 data, u8 address)
 175 {
 176         u8 check;
 177
 178         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 179             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 180                                                 (check == data))
 181                 return 0;
 182         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 183                         1, module, address, check, data);
 184
 185         /* Failed once: Try again */
 186         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 187             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 188                                                 (check == data))
 189                 return 0;
 190         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 191                         2, module, address, check, data);
 192
 193         /* Failed again: Return error */
 194         return -EBUSY;
 195 }
 196
 197 #define twl4030_usb_write_verify(twl, address, data)    \
 198         twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
 199
 200 static inline int twl4030_usb_write(struct twl4030_usb *twl,
 201                 u8 address, u8 data)
 202 {
 203         int ret = 0;
 204
 205         ret = twl_i2c_write_u8(TWL4030_MODULE_USB, data, address);
 206         if (ret < 0)
 207                 dev_dbg(twl->dev,
 208                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 209         return ret;
 210 }
 211
 212 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
 213 {
 214         u8 data;
 215         int ret = 0;
 216
 217         ret = twl_i2c_read_u8(module, &data, address);
 218         if (ret >= 0)
 219                 ret = data;
 220         else
 221                 dev_dbg(twl->dev,
 222                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
 223                                         module, address, ret);
 224
 225         return ret;
 226 }
 227
 228 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
 229 {
 230         return twl4030_readb(twl, TWL4030_MODULE_USB, address);
 231 }
 232
 233 /*-------------------------------------------------------------------------*/
 234
 235 static inline int
 236 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 237 {
 238         return twl4030_usb_write(twl, ULPI_SET(reg), bits);
 239 }
 240
 241 static inline int
 242 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 243 {
 244         return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
 245 }
 246
 247 /*-------------------------------------------------------------------------*/
 248
 249 static enum usb_xceiv_events twl4030_usb_linkstat(struct twl4030_usb *twl)
 250 {
 251         int     status;
 252         int     linkstat = USB_EVENT_NONE;
 253
 254         /*
 255          * For ID/VBUS sensing, see manual section 15.4.8 ...
 256          * except when using only battery backup power, two
 257          * comparators produce VBUS_PRES and ID_PRES signals,
 258          * which don't match docs elsewhere.  But ... BIT(7)
 259          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
 260          * seem to match up.  If either is true the USB_PRES
 261          * signal is active, the OTG module is activated, and
 262          * its interrupt may be raised (may wake the system).
 263          */
 264         status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
 265                         STS_HW_CONDITIONS);
 266         if (status < 0)
 267                 dev_err(twl->dev, "USB link status err %d\n", status);
 268         else if (status & (BIT(7) | BIT(2))) {
 269                 if (status & BIT(2))
 270                         linkstat = USB_EVENT_ID;
 271                 else
 272                         linkstat = USB_EVENT_VBUS;
 273         } else
 274                 linkstat = USB_EVENT_NONE;
 275
 276         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
 277                         status, status, linkstat);
 278
 279         /* REVISIT this assumes host and peripheral controllers
 280          * are registered, and that both are active...
 281          */
 282
 283         spin_lock_irq(&twl->lock);
 284         twl->linkstat = linkstat;
 285         if (linkstat == USB_EVENT_ID) {
 286                 twl->otg.default_a = true;
 287                 twl->otg.state = OTG_STATE_A_IDLE;
 288         } else {
 289                 twl->otg.default_a = false;
 290                 twl->otg.state = OTG_STATE_B_IDLE;
 291         }
 292         spin_unlock_irq(&twl->lock);
 293
 294         return linkstat;
 295 }
 296
 297 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
 298 {
 299         twl->usb_mode = mode;
 300
 301         switch (mode) {
 302         case T2_USB_MODE_ULPI:
 303                 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
 304                                         ULPI_IFC_CTRL_CARKITMODE);
 305                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 306                 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
 307                                         ULPI_FUNC_CTRL_XCVRSEL_MASK |
 308                                         ULPI_FUNC_CTRL_OPMODE_MASK);
 309                 break;
 310         case -1:
 311                 /* FIXME: power on defaults */
 312                 break;
 313         default:
 314                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
 315                                 mode);
 316                 break;
 317         };
 318 }
 319
 320 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
 321 {
 322         unsigned long timeout;
 323         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 324
 325         if (val >= 0) {
 326                 if (on) {
 327                         /* enable DPLL to access PHY registers over I2C */
 328                         val |= REQ_PHY_DPLL_CLK;
 329                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 330                                                 (u8)val) < 0);
 331
 332                         timeout = jiffies + HZ;
 333                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 334                                                         PHY_DPLL_CLK)
 335                                 && time_before(jiffies, timeout))
 336                                         udelay(10);
 337                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 338                                                         PHY_DPLL_CLK))
 339                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
 340                                                 "PHY DPLL clock\n");
 341                 } else {
 342                         /* let ULPI control the DPLL clock */
 343                         val &= ~REQ_PHY_DPLL_CLK;
 344                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 345                                                 (u8)val) < 0);
 346                 }
 347         }
 348 }
 349
 350 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
 351 {
 352         u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
 353
 354         if (on)
 355                 pwr &= ~PHY_PWR_PHYPWD;
 356         else
 357                 pwr |= PHY_PWR_PHYPWD;
 358
 359         WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 360 }
 361
 362 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
 363 {
 364         if (on) {
 365                 regulator_enable(twl->usb3v1);
 366                 regulator_enable(twl->usb1v8);
 367                 /*
 368                  * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
 369                  * in twl4030) resets the VUSB_DEDICATED2 register. This reset
 370                  * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
 371                  * SLEEP. We work around this by clearing the bit after usv3v1
 372                  * is re-activated. This ensures that VUSB3V1 is really active.
 373                  */
 374                 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0,
 375                                                         VUSB_DEDICATED2);
 376                 regulator_enable(twl->usb1v5);
 377                 __twl4030_phy_power(twl, 1);
 378                 twl4030_usb_write(twl, PHY_CLK_CTRL,
 379                                   twl4030_usb_read(twl, PHY_CLK_CTRL) |
 380                                         (PHY_CLK_CTRL_CLOCKGATING_EN |
 381                                                 PHY_CLK_CTRL_CLK32K_EN));
 382         } else {
 383                 __twl4030_phy_power(twl, 0);
 384                 regulator_disable(twl->usb1v5);
 385                 regulator_disable(twl->usb1v8);
 386                 regulator_disable(twl->usb3v1);
 387         }
 388 }
 389
 390 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
 391 {
 392         if (twl->asleep)
 393                 return;
 394
 395         twl4030_phy_power(twl, 0);
 396         twl->asleep = 1;
 397         dev_dbg(twl->dev, "%s\n", __func__);
 398 }
 399
 400 static void __twl4030_phy_resume(struct twl4030_usb *twl)
 401 {
 402         twl4030_phy_power(twl, 1);
 403         twl4030_i2c_access(twl, 1);
 404         twl4030_usb_set_mode(twl, twl->usb_mode);
 405         if (twl->usb_mode == T2_USB_MODE_ULPI)
 406                 twl4030_i2c_access(twl, 0);
 407 }
 408
 409 static void twl4030_phy_resume(struct twl4030_usb *twl)
 410 {
 411         if (!twl->asleep)
 412                 return;
 413         __twl4030_phy_resume(twl);
 414         twl->asleep = 0;
 415         dev_dbg(twl->dev, "%s\n", __func__);
 416 }
 417
 418 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
 419 {
 420         /* Enable writing to power configuration registers */
 421         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0xC0, PROTECT_KEY);
 422         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x0C, PROTECT_KEY);
 423
 424         /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
 425         /*twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
 426
 427         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
 428         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
 429
 430         /* Initialize 3.1V regulator */
 431         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
 432
 433         twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
 434         if (IS_ERR(twl->usb3v1))
 435                 return -ENODEV;
 436
 437         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
 438
 439         /* Initialize 1.5V regulator */
 440         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
 441
 442         twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
 443         if (IS_ERR(twl->usb1v5))
 444                 goto fail1;
 445
 446         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
 447
 448         /* Initialize 1.8V regulator */
 449         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
 450
 451         twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
 452         if (IS_ERR(twl->usb1v8))
 453                 goto fail2;
 454
 455         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
 456
 457         /* disable access to power configuration registers */
 458         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY);
 459
 460         return 0;
 461
 462 fail2:
 463         regulator_put(twl->usb1v5);
 464         twl->usb1v5 = NULL;
 465 fail1:
 466         regulator_put(twl->usb3v1);
 467         twl->usb3v1 = NULL;
 468         return -ENODEV;
 469 }
 470
 471 static ssize_t twl4030_usb_vbus_show(struct device *dev,
 472                 struct device_attribute *attr, char *buf)
 473 {
 474         struct twl4030_usb *twl = dev_get_drvdata(dev);
 475         unsigned long flags;
 476         int ret = -EINVAL;
 477
 478         spin_lock_irqsave(&twl->lock, flags);
 479         ret = sprintf(buf, "%s\n",
 480                         (twl->linkstat == USB_EVENT_VBUS) ? "on" : "off");
 481         spin_unlock_irqrestore(&twl->lock, flags);
 482
 483         return ret;
 484 }
 485 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
 486
 487 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
 488 {
 489         struct twl4030_usb *twl = _twl;
 490         int status;
 491
 492         status = twl4030_usb_linkstat(twl);
 493         if (status >= 0) {
 494                 /* FIXME add a set_power() method so that B-devices can
 495                  * configure the charger appropriately.  It's not always
 496                  * correct to consume VBUS power, and how much current to
 497                  * consume is a function of the USB configuration chosen
 498                  * by the host.
 499                  *
 500                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
 501                  * its disconnect() sibling, when changing to/from the
 502                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
 503                  * starts to handle softconnect right.
 504                  */
 505                 if (status == USB_EVENT_NONE)
 506                         twl4030_phy_suspend(twl, 0);
 507                 else
 508                         twl4030_phy_resume(twl);
 509
 510                 blocking_notifier_call_chain(&twl->otg.notifier, status,
 511                                 twl->otg.gadget);
 512         }
 513         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 514
 515         return IRQ_HANDLED;
 516 }
 517
 518 static void twl4030_usb_phy_init(struct twl4030_usb *twl)
 519 {
 520         int status;
 521
 522         status = twl4030_usb_linkstat(twl);
 523         if (status >= 0) {
 524                 if (status == USB_EVENT_NONE) {
 525                         __twl4030_phy_power(twl, 0);
 526                         twl->asleep = 1;
 527                 } else {
 528                         __twl4030_phy_resume(twl);
 529                         twl->asleep = 0;
 530                 }
 531
 532                 blocking_notifier_call_chain(&twl->otg.notifier, status,
 533                                 twl->otg.gadget);
 534         }
 535         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 536 }
 537
 538 static int twl4030_set_suspend(struct otg_transceiver *x, int suspend)
 539 {
 540         struct twl4030_usb *twl = xceiv_to_twl(x);
 541
 542         if (suspend)
 543                 twl4030_phy_suspend(twl, 1);
 544         else
 545                 twl4030_phy_resume(twl);
 546
 547         return 0;
 548 }
 549
 550 static int twl4030_set_peripheral(struct otg_transceiver *x,
 551                 struct usb_gadget *gadget)
 552 {
 553         struct twl4030_usb *twl;
 554
 555         if (!x)
 556                 return -ENODEV;
 557
 558         twl = xceiv_to_twl(x);
 559         twl->otg.gadget = gadget;
 560         if (!gadget)
 561                 twl->otg.state = OTG_STATE_UNDEFINED;
 562
 563         return 0;
 564 }
 565
 566 static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
 567 {
 568         struct twl4030_usb *twl;
 569
 570         if (!x)
 571                 return -ENODEV;
 572
 573         twl = xceiv_to_twl(x);
 574         twl->otg.host = host;
 575         if (!host)
 576                 twl->otg.state = OTG_STATE_UNDEFINED;
 577
 578         return 0;
 579 }
 580
 581 static int __devinit twl4030_usb_probe(struct platform_device *pdev)
 582 {
 583         struct twl4030_usb_data *pdata = pdev->dev.platform_data;
 584         struct twl4030_usb      *twl;
 585         int                     status, err;
 586
 587         if (!pdata) {
 588                 dev_dbg(&pdev->dev, "platform_data not available\n");
 589                 return -EINVAL;
 590         }
 591
 592         twl = kzalloc(sizeof *twl, GFP_KERNEL);
 593         if (!twl)
 594                 return -ENOMEM;
 595
 596         twl->dev                = &pdev->dev;
 597         twl->irq                = platform_get_irq(pdev, 0);
 598         twl->otg.dev            = twl->dev;
 599         twl->otg.label          = "twl4030";
 600         twl->otg.set_host       = twl4030_set_host;
 601         twl->otg.set_peripheral = twl4030_set_peripheral;
 602         twl->otg.set_suspend    = twl4030_set_suspend;
 603         twl->usb_mode           = pdata->usb_mode;
 604         twl->asleep = 1;
 605
 606         /* init spinlock for workqueue */
 607         spin_lock_init(&twl->lock);
 608
 609         err = twl4030_usb_ldo_init(twl);
 610         if (err) {
 611                 dev_err(&pdev->dev, "ldo init failed\n");
 612                 kfree(twl);
 613                 return err;
 614         }
 615         otg_set_transceiver(&twl->otg);
 616
 617         platform_set_drvdata(pdev, twl);
 618         if (device_create_file(&pdev->dev, &dev_attr_vbus))
 619                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 620
 621         BLOCKING_INIT_NOTIFIER_HEAD(&twl->otg.notifier);
 622
 623         /* Our job is to use irqs and status from the power module
 624          * to keep the transceiver disabled when nothing's connected.
 625          *
 626          * FIXME we actually shouldn't start enabling it until the
 627          * USB controller drivers have said they're ready, by calling
 628          * set_host() and/or set_peripheral() ... OTG_capable boards
 629          * need both handles, otherwise just one suffices.
 630          */
 631         twl->irq_enabled = true;
 632         status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq,
 633                         IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 634                         "twl4030_usb", twl);
 635         if (status < 0) {
 636                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
 637                         twl->irq, status);
 638                 kfree(twl);
 639                 return status;
 640         }
 641
 642         /* Power down phy or make it work according to
 643          * current link state.
 644          */
 645         twl4030_usb_phy_init(twl);
 646
 647         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
 648         return 0;
 649 }
 650
 651 static int __exit twl4030_usb_remove(struct platform_device *pdev)
 652 {
 653         struct twl4030_usb *twl = platform_get_drvdata(pdev);
 654         int val;
 655
 656         free_irq(twl->irq, twl);
 657         device_remove_file(twl->dev, &dev_attr_vbus);
 658
 659         /* set transceiver mode to power on defaults */
 660         twl4030_usb_set_mode(twl, -1);
 661
 662         /* autogate 60MHz ULPI clock,
 663          * clear dpll clock request for i2c access,
 664          * disable 32KHz
 665          */
 666         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 667         if (val >= 0) {
 668                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
 669                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
 670                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
 671         }
 672
 673         /* disable complete OTG block */
 674         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 675
 676         twl4030_phy_power(twl, 0);
 677         regulator_put(twl->usb1v5);
 678         regulator_put(twl->usb1v8);
 679         regulator_put(twl->usb3v1);
 680
 681         kfree(twl);
 682
 683         return 0;
 684 }
 685
 686 static struct platform_driver twl4030_usb_driver = {
 687         .probe          = twl4030_usb_probe,
 688         .remove         = __exit_p(twl4030_usb_remove),
 689         .driver         = {
 690                 .name   = "twl4030_usb",
 691                 .owner  = THIS_MODULE,
 692         },
 693 };
 694
 695 static int __init twl4030_usb_init(void)
 696 {
 697         return platform_driver_register(&twl4030_usb_driver);
 698 }
 699 subsys_initcall(twl4030_usb_init);
 700
 701 static void __exit twl4030_usb_exit(void)
 702 {
 703         platform_driver_unregister(&twl4030_usb_driver);
 704 }
 705 module_exit(twl4030_usb_exit);
 706
 707 MODULE_ALIAS("platform:twl4030_usb");
 708 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
 709 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
 710 MODULE_LICENSE("GPL");