2 * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
4 * Copyright (C) 2006 Nokia Corporation
5 * Jarkko Nikula <jarkko.nikula@nokia.com>
6 * Tony Lindgren <tony@atomide.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __TUSB6010_H__
14 #define __TUSB6010_H__
16 extern u8 tusb_get_revision(struct musb *musb);
18 #ifdef CONFIG_USB_TUSB6010
19 #define musb_in_tusb() 1
21 #define musb_in_tusb() 0
24 #ifdef CONFIG_USB_TUSB_OMAP_DMA
25 #define tusb_dma_omap() 1
27 #define tusb_dma_omap() 0
30 /* VLYNQ control register. 32-bit at offset 0x000 */
31 #define TUSB_VLYNQ_CTRL 0x004
33 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
34 #define TUSB_BASE_OFFSET 0x400
36 /* FIFO registers 32-bit at offset 0x600 */
37 #define TUSB_FIFO_BASE 0x600
39 /* Device System & Control registers. 32-bit at offset 0x800 */
40 #define TUSB_SYS_REG_BASE 0x800
42 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
43 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
44 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
45 #define TUSB_DEV_CONF_SOFT_ID (1 << 1)
46 #define TUSB_DEV_CONF_ID_SEL (1 << 0)
48 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
49 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
50 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
51 #define TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP (1 << 23)
52 #define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19)
53 #define TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN (1 << 18)
54 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
55 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
56 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
57 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
58 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
59 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
60 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
61 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
62 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
63 #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7)
64 #define TUSB_PHY_OTG_CTRL_PD (1 << 6)
65 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
66 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
67 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
68 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
69 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
70 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
72 /*OTG status register */
73 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
74 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
75 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
76 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
77 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
78 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
79 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
80 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
81 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
82 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
83 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
85 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
86 # define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
87 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
88 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
90 /* PRCM configuration register */
91 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
92 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
93 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
95 /* PRCM management register */
96 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
97 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25)
98 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
99 #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20)
100 #define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19)
101 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
102 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
103 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
104 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
105 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
106 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
107 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
108 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
109 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
110 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
112 /* Wake-up source clear and mask registers */
113 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
114 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
115 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
116 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
117 #define TUSB_PRCM_WGPIO_7 (1 << 12)
118 #define TUSB_PRCM_WGPIO_6 (1 << 11)
119 #define TUSB_PRCM_WGPIO_5 (1 << 10)
120 #define TUSB_PRCM_WGPIO_4 (1 << 9)
121 #define TUSB_PRCM_WGPIO_3 (1 << 8)
122 #define TUSB_PRCM_WGPIO_2 (1 << 7)
123 #define TUSB_PRCM_WGPIO_1 (1 << 6)
124 #define TUSB_PRCM_WGPIO_0 (1 << 5)
125 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */
126 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */
127 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */
128 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */
129 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
131 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
132 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
133 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
134 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
135 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
136 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
137 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
138 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
139 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
140 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
141 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
142 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
143 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
144 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
145 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
146 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
148 /* NOR flash interrupt source registers */
149 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
150 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
151 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
152 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
153 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
154 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
155 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
156 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
157 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
158 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
159 #define TUSB_INT_SRC_DEV_READY (1 << 12)
160 #define TUSB_INT_SRC_USB_IP_TX (1 << 9)
161 #define TUSB_INT_SRC_USB_IP_RX (1 << 8)
162 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
163 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
164 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
165 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
166 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
167 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
168 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
169 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
171 /* NOR flash interrupt registers reserved bits. Must be written as 0 */
172 #define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17)
173 #define TUSB_INT_MASK_RESERVED_13 (1 << 13)
174 #define TUSB_INT_MASK_RESERVED_8 (0xf << 8)
175 #define TUSB_INT_SRC_RESERVED_26 (0x1f << 26)
176 #define TUSB_INT_SRC_RESERVED_18 (0x3f << 18)
177 #define TUSB_INT_SRC_RESERVED_10 (0x03 << 10)
179 /* Reserved bits for NOR flash interrupt mask and clear register */
180 #define TUSB_INT_MASK_RESERVED_BITS (TUSB_INT_MASK_RESERVED_17 | \
181 TUSB_INT_MASK_RESERVED_13 | \
182 TUSB_INT_MASK_RESERVED_8)
184 /* Reserved bits for NOR flash interrupt status register */
185 #define TUSB_INT_SRC_RESERVED_BITS (TUSB_INT_SRC_RESERVED_26 | \
186 TUSB_INT_SRC_RESERVED_18 | \
187 TUSB_INT_SRC_RESERVED_10)
189 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
190 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
191 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
192 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
193 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
194 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
196 /* Offsets from each ep base register */
197 #define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */
198 #define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */
199 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188
201 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
202 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
203 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
205 /* Device System & Control register bitfields */
206 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18)
207 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
208 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
209 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
210 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
211 #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20)
212 #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16)
213 #define TUSB_EP0_CONFIG_SW_EN (1 << 8)
214 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
215 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
216 #define TUSB_EP_CONFIG_SW_EN (1 << 31)
217 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
218 #define TUSB_PROD_TEST_RESET_VAL 0xa596
219 #define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20)
221 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
222 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
223 #define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf)
224 #define TUSB_DIDR1_HI_REV_20 0
225 #define TUSB_DIDR1_HI_REV_30 1
226 #define TUSB_DIDR1_HI_REV_31 2
228 #define TUSB_REV_10 0x10
229 #define TUSB_REV_20 0x20
230 #define TUSB_REV_30 0x30
231 #define TUSB_REV_31 0x31
233 /*----------------------------------------------------------------------------*/
235 #ifdef CONFIG_USB_TUSB6010
237 /* configuration parameters specific to this silicon */
239 /* Number of Tx endpoints. Legal values are 1 - 16 (this value includes EP0) */
240 #define MUSB_C_NUM_EPT 16
242 /* Number of Rx endpoints. Legal values are 1 - 16 (this value includes EP0) */
243 #define MUSB_C_NUM_EPR 16
245 /* Endpoint 1 to 15 direction types. C_EP1_DEF is defined if either Tx endpoint
246 * 1 or Rx endpoint 1 are used.
248 #define MUSB_C_EP1_DEF
250 /* C_EP1_TX_DEF is defined if Tx endpoint 1 is used */
251 #define MUSB_C_EP1_TX_DEF
253 /* C_EP1_RX_DEF is defined if Rx endpoint 1 is used */
254 #define MUSB_C_EP1_RX_DEF
256 /* C_EP1_TOR_DEF is defined if Tx endpoint 1 and Rx endpoint 1 share a FIFO */
257 /* #define C_EP1_TOR_DEF */
259 /* C_EP1_TAR_DEF is defined if both Tx endpoint 1 and Rx endpoint 1 are used
260 * and do not share a FIFO.
262 #define MUSB_C_EP1_TAR_DEF
264 /* Similarly for all other used endpoints */
265 #define MUSB_C_EP2_DEF
266 #define MUSB_C_EP2_TX_DEF
267 #define MUSB_C_EP2_RX_DEF
268 #define MUSB_C_EP2_TAR_DEF
269 #define MUSB_C_EP3_DEF
270 #define MUSB_C_EP3_TX_DEF
271 #define MUSB_C_EP3_RX_DEF
272 #define MUSB_C_EP3_TAR_DEF
273 #define MUSB_C_EP4_DEF
274 #define MUSB_C_EP4_TX_DEF
275 #define MUSB_C_EP4_RX_DEF
276 #define MUSB_C_EP4_TAR_DEF
278 /* Endpoint 1 to 15 FIFO address bits. Legal values are 3 to 13 - corresponding
279 * to FIFO sizes of 8 to 8192 bytes. If an Tx endpoint shares a FIFO with an Rx
280 * endpoint then the Rx FIFO size must be the same as the Tx FIFO size. All
281 * endpoints 1 to 15 must be defined, unused endpoints should be set to 2.
283 #define MUSB_C_EP1T_BITS 5
284 #define MUSB_C_EP1R_BITS 5
285 #define MUSB_C_EP2T_BITS 5
286 #define MUSB_C_EP2R_BITS 5
287 #define MUSB_C_EP3T_BITS 3
288 #define MUSB_C_EP3R_BITS 3
289 #define MUSB_C_EP4T_BITS 3
290 #define MUSB_C_EP4R_BITS 3
292 #define MUSB_C_EP5T_BITS 2
293 #define MUSB_C_EP5R_BITS 2
294 #define MUSB_C_EP6T_BITS 2
295 #define MUSB_C_EP6R_BITS 2
296 #define MUSB_C_EP7T_BITS 2
297 #define MUSB_C_EP7R_BITS 2
298 #define MUSB_C_EP8T_BITS 2
299 #define MUSB_C_EP8R_BITS 2
300 #define MUSB_C_EP9T_BITS 2
301 #define MUSB_C_EP9R_BITS 2
302 #define MUSB_C_EP10T_BITS 2
303 #define MUSB_C_EP10R_BITS 2
304 #define MUSB_C_EP11T_BITS 2
305 #define MUSB_C_EP11R_BITS 2
306 #define MUSB_C_EP12T_BITS 2
307 #define MUSB_C_EP12R_BITS 2
308 #define MUSB_C_EP13T_BITS 2
309 #define MUSB_C_EP13R_BITS 2
310 #define MUSB_C_EP14T_BITS 2
311 #define MUSB_C_EP14R_BITS 2
312 #define MUSB_C_EP15T_BITS 2
313 #define MUSB_C_EP15R_BITS 2
315 /* Define the following constant if the USB2.0 Transceiver Macrocell data width
318 /* #define C_UTM_16 */
320 /* Define this constant if the CPU uses big-endian byte ordering. */
321 /* #define C_BIGEND */
323 /* Define the following constant if any Tx endpoint is required to support
324 * multiple bulk packets.
326 /* #define C_MP_TX */
328 /* Define the following constant if any Rx endpoint is required to support
329 * multiple bulk packets.
331 /* #define C_MP_RX */
333 /* Define the following constant if any Tx endpoint is required to support high
336 /* #define C_HB_TX */
338 /* Define the following constant if any Rx endpoint is required to support high
341 /* #define C_HB_RX */
343 /* Define the following constant if software connect/disconnect control is
346 #define MUSB_C_SOFT_CON
348 /* Define the following constant if Vendor Control Registers are required. */
349 /* #define C_VEND_REG */
351 /* Vendor control register widths. */
352 #define MUSB_C_VCTL_BITS 4
353 #define MUSB_C_VSTAT_BITS 8
355 /* Define the following constant to include a DMA controller. */
358 /* Define the following constant if 2 or more DMA channels are required. */
361 /* Define the following constant if 3 or more DMA channels are required. */
364 /* Define the following constant if 4 or more DMA channels are required. */
367 /* Define the following constant if 5 or more DMA channels are required. */
370 /* Define the following constant if 6 or more DMA channels are required. */
373 /* Define the following constant if 7 or more DMA channels are required. */
376 /* Define the following constant if 8 or more DMA channels are required. */
379 /* Enable Dynamic FIFO Sizing */
380 #define MUSB_C_DYNFIFO_DEF
382 /* Derived constants. The following constants are derived from the previous
383 * configuration constants
386 /* Total number of endpoints. Legal values are 2 - 16. This must be equal to
387 * the larger of C_NUM_EPT, C_NUM_EPR
389 /* #define MUSB_C_NUM_EPS 5 */
391 /* C_EPMAX_BITS is equal to the largest endpoint FIFO word address bits */
392 #define MUSB_C_EPMAX_BITS 11
394 /* C_RAM_BITS is the number of address bits required to address the RAM (32-bit
395 * addresses). It is defined as log2 of the sum of 2** of all the endpoint FIFO
396 * dword address bits (rounded up).
398 #define MUSB_C_RAM_BITS 12
400 #endif /* CONFIG_USB_TUSB6010 */
402 #endif /* __TUSB6010_H__ */
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