drivers/usb/musb/musb_gadget_ep0.c

   1 /*
   2  * MUSB OTG peripheral driver ep0 handling
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2006 by Texas Instruments
   6  * Copyright (C) 2006-2007 Nokia Corporation
   7  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  26  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/list.h>
  38 #include <linux/timer.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/init.h>
  41 #include <linux/device.h>
  42 #include <linux/interrupt.h>
  43
  44 #include "musb_core.h"
  45
  46 /* ep0 is always musb->endpoints[0].ep_in */
  47 #define next_ep0_request(musb)  next_in_request(&(musb)->endpoints[0])
  48
  49 /*
  50  * locking note:  we use only the controller lock, for simpler correctness.
  51  * It's always held with IRQs blocked.
  52  *
  53  * It protects the ep0 request queue as well as ep0_state, not just the
  54  * controller and indexed registers.  And that lock stays held unless it
  55  * needs to be dropped to allow reentering this driver ... like upcalls to
  56  * the gadget driver, or adjusting endpoint halt status.
  57  */
  58
  59 static char *decode_ep0stage(u8 stage)
  60 {
  61         switch (stage) {
  62         case MUSB_EP0_STAGE_IDLE:       return "idle";
  63         case MUSB_EP0_STAGE_SETUP:      return "setup";
  64         case MUSB_EP0_STAGE_TX:         return "in";
  65         case MUSB_EP0_STAGE_RX:         return "out";
  66         case MUSB_EP0_STAGE_ACKWAIT:    return "wait";
  67         case MUSB_EP0_STAGE_STATUSIN:   return "in/status";
  68         case MUSB_EP0_STAGE_STATUSOUT:  return "out/status";
  69         default:                        return "?";
  70         }
  71 }
  72
  73 /* handle a standard GET_STATUS request
  74  * Context:  caller holds controller lock
  75  */
  76 static int service_tx_status_request(
  77         struct musb *musb,
  78         const struct usb_ctrlrequest *ctrlrequest)
  79 {
  80         void __iomem    *mbase = musb->mregs;
  81         int handled = 1;
  82         u8 result[2], epnum = 0;
  83         const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  84
  85         result[1] = 0;
  86
  87         switch (recip) {
  88         case USB_RECIP_DEVICE:
  89                 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  90                 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  91 #ifdef CONFIG_USB_MUSB_OTG
  92                 if (musb->g.is_otg) {
  93                         result[0] |= musb->g.b_hnp_enable
  94                                 << USB_DEVICE_B_HNP_ENABLE;
  95                         result[0] |= musb->g.a_alt_hnp_support
  96                                 << USB_DEVICE_A_ALT_HNP_SUPPORT;
  97                         result[0] |= musb->g.a_hnp_support
  98                                 << USB_DEVICE_A_HNP_SUPPORT;
  99                 }
 100 #endif
 101                 break;
 102
 103         case USB_RECIP_INTERFACE:
 104                 result[0] = 0;
 105                 break;
 106
 107         case USB_RECIP_ENDPOINT: {
 108                 int             is_in;
 109                 struct musb_ep  *ep;
 110                 u16             tmp;
 111                 void __iomem    *regs;
 112
 113                 epnum = (u8) ctrlrequest->wIndex;
 114                 if (!epnum) {
 115                         result[0] = 0;
 116                         break;
 117                 }
 118
 119                 is_in = epnum & USB_DIR_IN;
 120                 if (is_in) {
 121                         epnum &= 0x0f;
 122                         ep = &musb->endpoints[epnum].ep_in;
 123                 } else {
 124                         ep = &musb->endpoints[epnum].ep_out;
 125                 }
 126                 regs = musb->endpoints[epnum].regs;
 127
 128                 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
 129                         handled = -EINVAL;
 130                         break;
 131                 }
 132
 133                 musb_ep_select(mbase, epnum);
 134                 if (is_in)
 135                         tmp = musb_readw(regs, MUSB_TXCSR)
 136                                                 & MUSB_TXCSR_P_SENDSTALL;
 137                 else
 138                         tmp = musb_readw(regs, MUSB_RXCSR)
 139                                                 & MUSB_RXCSR_P_SENDSTALL;
 140                 musb_ep_select(mbase, 0);
 141
 142                 result[0] = tmp ? 1 : 0;
 143                 } break;
 144
 145         default:
 146                 /* class, vendor, etc ... delegate */
 147                 handled = 0;
 148                 break;
 149         }
 150
 151         /* fill up the fifo; caller updates csr0 */
 152         if (handled > 0) {
 153                 u16     len = le16_to_cpu(ctrlrequest->wLength);
 154
 155                 if (len > 2)
 156                         len = 2;
 157                 musb_write_fifo(&musb->endpoints[0], len, result);
 158         }
 159
 160         return handled;
 161 }
 162
 163 /*
 164  * handle a control-IN request, the end0 buffer contains the current request
 165  * that is supposed to be a standard control request. Assumes the fifo to
 166  * be at least 2 bytes long.
 167  *
 168  * @return 0 if the request was NOT HANDLED,
 169  * < 0 when error
 170  * > 0 when the request is processed
 171  *
 172  * Context:  caller holds controller lock
 173  */
 174 static int
 175 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 176 {
 177         int handled = 0;        /* not handled */
 178
 179         if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
 180                         == USB_TYPE_STANDARD) {
 181                 switch (ctrlrequest->bRequest) {
 182                 case USB_REQ_GET_STATUS:
 183                         handled = service_tx_status_request(musb,
 184                                         ctrlrequest);
 185                         break;
 186
 187                 /* case USB_REQ_SYNC_FRAME: */
 188
 189                 default:
 190                         break;
 191                 }
 192         }
 193         return handled;
 194 }
 195
 196 /*
 197  * Context:  caller holds controller lock
 198  */
 199 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 200 {
 201         musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
 202 }
 203
 204 /*
 205  * Tries to start B-device HNP negotiation if enabled via sysfs
 206  */
 207 static inline void musb_try_b_hnp_enable(struct musb *musb)
 208 {
 209         void __iomem    *mbase = musb->mregs;
 210         u8              devctl;
 211
 212         dev_dbg(musb->controller, "HNP: Setting HR\n");
 213         devctl = musb_readb(mbase, MUSB_DEVCTL);
 214         musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
 215 }
 216
 217 /*
 218  * Handle all control requests with no DATA stage, including standard
 219  * requests such as:
 220  * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
 221  *      always delegated to the gadget driver
 222  * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
 223  *      always handled here, except for class/vendor/... features
 224  *
 225  * Context:  caller holds controller lock
 226  */
 227 static int
 228 service_zero_data_request(struct musb *musb,
 229                 struct usb_ctrlrequest *ctrlrequest)
 230 __releases(musb->lock)
 231 __acquires(musb->lock)
 232 {
 233         int handled = -EINVAL;
 234         void __iomem *mbase = musb->mregs;
 235         const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
 236
 237         /* the gadget driver handles everything except what we MUST handle */
 238         if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
 239                         == USB_TYPE_STANDARD) {
 240                 switch (ctrlrequest->bRequest) {
 241                 case USB_REQ_SET_ADDRESS:
 242                         /* change it after the status stage */
 243                         musb->set_address = true;
 244                         musb->address = (u8) (ctrlrequest->wValue & 0x7f);
 245                         handled = 1;
 246                         break;
 247
 248                 case USB_REQ_CLEAR_FEATURE:
 249                         switch (recip) {
 250                         case USB_RECIP_DEVICE:
 251                                 if (ctrlrequest->wValue
 252                                                 != USB_DEVICE_REMOTE_WAKEUP)
 253                                         break;
 254                                 musb->may_wakeup = 0;
 255                                 handled = 1;
 256                                 break;
 257                         case USB_RECIP_INTERFACE:
 258                                 break;
 259                         case USB_RECIP_ENDPOINT:{
 260                                 const u8                epnum =
 261                                         ctrlrequest->wIndex & 0x0f;
 262                                 struct musb_ep          *musb_ep;
 263                                 struct musb_hw_ep       *ep;
 264                                 struct musb_request     *request;
 265                                 void __iomem            *regs;
 266                                 int                     is_in;
 267                                 u16                     csr;
 268
 269                                 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
 270                                     ctrlrequest->wValue != USB_ENDPOINT_HALT)
 271                                         break;
 272
 273                                 ep = musb->endpoints + epnum;
 274                                 regs = ep->regs;
 275                                 is_in = ctrlrequest->wIndex & USB_DIR_IN;
 276                                 if (is_in)
 277                                         musb_ep = &ep->ep_in;
 278                                 else
 279                                         musb_ep = &ep->ep_out;
 280                                 if (!musb_ep->desc)
 281                                         break;
 282
 283                                 handled = 1;
 284                                 /* Ignore request if endpoint is wedged */
 285                                 if (musb_ep->wedged)
 286                                         break;
 287
 288                                 musb_ep_select(mbase, epnum);
 289                                 if (is_in) {
 290                                         csr  = musb_readw(regs, MUSB_TXCSR);
 291                                         csr |= MUSB_TXCSR_CLRDATATOG |
 292                                                MUSB_TXCSR_P_WZC_BITS;
 293                                         csr &= ~(MUSB_TXCSR_P_SENDSTALL |
 294                                                  MUSB_TXCSR_P_SENTSTALL |
 295                                                  MUSB_TXCSR_TXPKTRDY);
 296                                         musb_writew(regs, MUSB_TXCSR, csr);
 297                                 } else {
 298                                         csr  = musb_readw(regs, MUSB_RXCSR);
 299                                         csr |= MUSB_RXCSR_CLRDATATOG |
 300                                                MUSB_RXCSR_P_WZC_BITS;
 301                                         csr &= ~(MUSB_RXCSR_P_SENDSTALL |
 302                                                  MUSB_RXCSR_P_SENTSTALL);
 303                                         musb_writew(regs, MUSB_RXCSR, csr);
 304                                 }
 305
 306                                 /* Maybe start the first request in the queue */
 307                                 request = next_request(musb_ep);
 308                                 if (!musb_ep->busy && request) {
 309                                         dev_dbg(musb->controller, "restarting the request\n");
 310                                         musb_ep_restart(musb, request);
 311                                 }
 312
 313                                 /* select ep0 again */
 314                                 musb_ep_select(mbase, 0);
 315                                 } break;
 316                         default:
 317                                 /* class, vendor, etc ... delegate */
 318                                 handled = 0;
 319                                 break;
 320                         }
 321                         break;
 322
 323                 case USB_REQ_SET_FEATURE:
 324                         switch (recip) {
 325                         case USB_RECIP_DEVICE:
 326                                 handled = 1;
 327                                 switch (ctrlrequest->wValue) {
 328                                 case USB_DEVICE_REMOTE_WAKEUP:
 329                                         musb->may_wakeup = 1;
 330                                         break;
 331                                 case USB_DEVICE_TEST_MODE:
 332                                         if (musb->g.speed != USB_SPEED_HIGH)
 333                                                 goto stall;
 334                                         if (ctrlrequest->wIndex & 0xff)
 335                                                 goto stall;
 336
 337                                         switch (ctrlrequest->wIndex >> 8) {
 338                                         case 1:
 339                                                 pr_debug("TEST_J\n");
 340                                                 /* TEST_J */
 341                                                 musb->test_mode_nr =
 342                                                         MUSB_TEST_J;
 343                                                 break;
 344                                         case 2:
 345                                                 /* TEST_K */
 346                                                 pr_debug("TEST_K\n");
 347                                                 musb->test_mode_nr =
 348                                                         MUSB_TEST_K;
 349                                                 break;
 350                                         case 3:
 351                                                 /* TEST_SE0_NAK */
 352                                                 pr_debug("TEST_SE0_NAK\n");
 353                                                 musb->test_mode_nr =
 354                                                         MUSB_TEST_SE0_NAK;
 355                                                 break;
 356                                         case 4:
 357                                                 /* TEST_PACKET */
 358                                                 pr_debug("TEST_PACKET\n");
 359                                                 musb->test_mode_nr =
 360                                                         MUSB_TEST_PACKET;
 361                                                 break;
 362
 363                                         case 0xc0:
 364                                                 /* TEST_FORCE_HS */
 365                                                 pr_debug("TEST_FORCE_HS\n");
 366                                                 musb->test_mode_nr =
 367                                                         MUSB_TEST_FORCE_HS;
 368                                                 break;
 369                                         case 0xc1:
 370                                                 /* TEST_FORCE_FS */
 371                                                 pr_debug("TEST_FORCE_FS\n");
 372                                                 musb->test_mode_nr =
 373                                                         MUSB_TEST_FORCE_FS;
 374                                                 break;
 375                                         case 0xc2:
 376                                                 /* TEST_FIFO_ACCESS */
 377                                                 pr_debug("TEST_FIFO_ACCESS\n");
 378                                                 musb->test_mode_nr =
 379                                                         MUSB_TEST_FIFO_ACCESS;
 380                                                 break;
 381                                         case 0xc3:
 382                                                 /* TEST_FORCE_HOST */
 383                                                 pr_debug("TEST_FORCE_HOST\n");
 384                                                 musb->test_mode_nr =
 385                                                         MUSB_TEST_FORCE_HOST;
 386                                                 break;
 387                                         default:
 388                                                 goto stall;
 389                                         }
 390
 391                                         /* enter test mode after irq */
 392                                         if (handled > 0)
 393                                                 musb->test_mode = true;
 394                                         break;
 395 #ifdef CONFIG_USB_MUSB_OTG
 396                                 case USB_DEVICE_B_HNP_ENABLE:
 397                                         if (!musb->g.is_otg)
 398                                                 goto stall;
 399                                         musb->g.b_hnp_enable = 1;
 400                                         musb_try_b_hnp_enable(musb);
 401                                         break;
 402                                 case USB_DEVICE_A_HNP_SUPPORT:
 403                                         if (!musb->g.is_otg)
 404                                                 goto stall;
 405                                         musb->g.a_hnp_support = 1;
 406                                         break;
 407                                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
 408                                         if (!musb->g.is_otg)
 409                                                 goto stall;
 410                                         musb->g.a_alt_hnp_support = 1;
 411                                         break;
 412 #endif
 413                                 case USB_DEVICE_DEBUG_MODE:
 414                                         handled = 0;
 415                                         break;
 416 stall:
 417                                 default:
 418                                         handled = -EINVAL;
 419                                         break;
 420                                 }
 421                                 break;
 422
 423                         case USB_RECIP_INTERFACE:
 424                                 break;
 425
 426                         case USB_RECIP_ENDPOINT:{
 427                                 const u8                epnum =
 428                                         ctrlrequest->wIndex & 0x0f;
 429                                 struct musb_ep          *musb_ep;
 430                                 struct musb_hw_ep       *ep;
 431                                 void __iomem            *regs;
 432                                 int                     is_in;
 433                                 u16                     csr;
 434
 435                                 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
 436                                     ctrlrequest->wValue != USB_ENDPOINT_HALT)
 437                                         break;
 438
 439                                 ep = musb->endpoints + epnum;
 440                                 regs = ep->regs;
 441                                 is_in = ctrlrequest->wIndex & USB_DIR_IN;
 442                                 if (is_in)
 443                                         musb_ep = &ep->ep_in;
 444                                 else
 445                                         musb_ep = &ep->ep_out;
 446                                 if (!musb_ep->desc)
 447                                         break;
 448
 449                                 musb_ep_select(mbase, epnum);
 450                                 if (is_in) {
 451                                         csr = musb_readw(regs, MUSB_TXCSR);
 452                                         if (csr & MUSB_TXCSR_FIFONOTEMPTY)
 453                                                 csr |= MUSB_TXCSR_FLUSHFIFO;
 454                                         csr |= MUSB_TXCSR_P_SENDSTALL
 455                                                 | MUSB_TXCSR_CLRDATATOG
 456                                                 | MUSB_TXCSR_P_WZC_BITS;
 457                                         musb_writew(regs, MUSB_TXCSR, csr);
 458                                 } else {
 459                                         csr = musb_readw(regs, MUSB_RXCSR);
 460                                         csr |= MUSB_RXCSR_P_SENDSTALL
 461                                                 | MUSB_RXCSR_FLUSHFIFO
 462                                                 | MUSB_RXCSR_CLRDATATOG
 463                                                 | MUSB_RXCSR_P_WZC_BITS;
 464                                         musb_writew(regs, MUSB_RXCSR, csr);
 465                                 }
 466
 467                                 /* select ep0 again */
 468                                 musb_ep_select(mbase, 0);
 469                                 handled = 1;
 470                                 } break;
 471
 472                         default:
 473                                 /* class, vendor, etc ... delegate */
 474                                 handled = 0;
 475                                 break;
 476                         }
 477                         break;
 478                 default:
 479                         /* delegate SET_CONFIGURATION, etc */
 480                         handled = 0;
 481                 }
 482         } else
 483                 handled = 0;
 484         return handled;
 485 }
 486
 487 /* we have an ep0out data packet
 488  * Context:  caller holds controller lock
 489  */
 490 static void ep0_rxstate(struct musb *musb)
 491 {
 492         void __iomem            *regs = musb->control_ep->regs;
 493         struct musb_request     *request;
 494         struct usb_request      *req;
 495         u16                     count, csr;
 496
 497         request = next_ep0_request(musb);
 498         req = &request->request;
 499
 500         /* read packet and ack; or stall because of gadget driver bug:
 501          * should have provided the rx buffer before setup() returned.
 502          */
 503         if (req) {
 504                 void            *buf = req->buf + req->actual;
 505                 unsigned        len = req->length - req->actual;
 506
 507                 /* read the buffer */
 508                 count = musb_readb(regs, MUSB_COUNT0);
 509                 if (count > len) {
 510                         req->status = -EOVERFLOW;
 511                         count = len;
 512                 }
 513                 musb_read_fifo(&musb->endpoints[0], count, buf);
 514                 req->actual += count;
 515                 csr = MUSB_CSR0_P_SVDRXPKTRDY;
 516                 if (count < 64 || req->actual == req->length) {
 517                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 518                         csr |= MUSB_CSR0_P_DATAEND;
 519                 } else
 520                         req = NULL;
 521         } else
 522                 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
 523
 524
 525         /* Completion handler may choose to stall, e.g. because the
 526          * message just received holds invalid data.
 527          */
 528         if (req) {
 529                 musb->ackpend = csr;
 530                 musb_g_ep0_giveback(musb, req);
 531                 if (!musb->ackpend)
 532                         return;
 533                 musb->ackpend = 0;
 534         }
 535         musb_ep_select(musb->mregs, 0);
 536         musb_writew(regs, MUSB_CSR0, csr);
 537 }
 538
 539 /*
 540  * transmitting to the host (IN), this code might be called from IRQ
 541  * and from kernel thread.
 542  *
 543  * Context:  caller holds controller lock
 544  */
 545 static void ep0_txstate(struct musb *musb)
 546 {
 547         void __iomem            *regs = musb->control_ep->regs;
 548         struct musb_request     *req = next_ep0_request(musb);
 549         struct usb_request      *request;
 550         u16                     csr = MUSB_CSR0_TXPKTRDY;
 551         u8                      *fifo_src;
 552         u8                      fifo_count;
 553
 554         if (!req) {
 555                 /* WARN_ON(1); */
 556                 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
 557                 return;
 558         }
 559
 560         request = &req->request;
 561
 562         /* load the data */
 563         fifo_src = (u8 *) request->buf + request->actual;
 564         fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
 565                 request->length - request->actual);
 566         musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
 567         request->actual += fifo_count;
 568
 569         /* update the flags */
 570         if (fifo_count < MUSB_MAX_END0_PACKET
 571                         || (request->actual == request->length
 572                                 && !request->zero)) {
 573                 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 574                 csr |= MUSB_CSR0_P_DATAEND;
 575         } else
 576                 request = NULL;
 577
 578         /* report completions as soon as the fifo's loaded; there's no
 579          * win in waiting till this last packet gets acked.  (other than
 580          * very precise fault reporting, needed by USB TMC; possible with
 581          * this hardware, but not usable from portable gadget drivers.)
 582          */
 583         if (request) {
 584                 musb->ackpend = csr;
 585                 musb_g_ep0_giveback(musb, request);
 586                 if (!musb->ackpend)
 587                         return;
 588                 musb->ackpend = 0;
 589         }
 590
 591         /* send it out, triggering a "txpktrdy cleared" irq */
 592         musb_ep_select(musb->mregs, 0);
 593         musb_writew(regs, MUSB_CSR0, csr);
 594 }
 595
 596 /*
 597  * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
 598  * Fields are left in USB byte-order.
 599  *
 600  * Context:  caller holds controller lock.
 601  */
 602 static void
 603 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
 604 {
 605         struct musb_request     *r;
 606         void __iomem            *regs = musb->control_ep->regs;
 607
 608         musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
 609
 610         /* NOTE:  earlier 2.6 versions changed setup packets to host
 611          * order, but now USB packets always stay in USB byte order.
 612          */
 613         dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
 614                 req->bRequestType,
 615                 req->bRequest,
 616                 le16_to_cpu(req->wValue),
 617                 le16_to_cpu(req->wIndex),
 618                 le16_to_cpu(req->wLength));
 619
 620         /* clean up any leftover transfers */
 621         r = next_ep0_request(musb);
 622         if (r)
 623                 musb_g_ep0_giveback(musb, &r->request);
 624
 625         /* For zero-data requests we want to delay the STATUS stage to
 626          * avoid SETUPEND errors.  If we read data (OUT), delay accepting
 627          * packets until there's a buffer to store them in.
 628          *
 629          * If we write data, the controller acts happier if we enable
 630          * the TX FIFO right away, and give the controller a moment
 631          * to switch modes...
 632          */
 633         musb->set_address = false;
 634         musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
 635         if (req->wLength == 0) {
 636                 if (req->bRequestType & USB_DIR_IN)
 637                         musb->ackpend |= MUSB_CSR0_TXPKTRDY;
 638                 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
 639         } else if (req->bRequestType & USB_DIR_IN) {
 640                 musb->ep0_state = MUSB_EP0_STAGE_TX;
 641                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
 642                 while ((musb_readw(regs, MUSB_CSR0)
 643                                 & MUSB_CSR0_RXPKTRDY) != 0)
 644                         cpu_relax();
 645                 musb->ackpend = 0;
 646         } else
 647                 musb->ep0_state = MUSB_EP0_STAGE_RX;
 648 }
 649
 650 static int
 651 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 652 __releases(musb->lock)
 653 __acquires(musb->lock)
 654 {
 655         int retval;
 656         if (!musb->gadget_driver)
 657                 return -EOPNOTSUPP;
 658         spin_unlock(&musb->lock);
 659         retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
 660         spin_lock(&musb->lock);
 661         return retval;
 662 }
 663
 664 /*
 665  * Handle peripheral ep0 interrupt
 666  *
 667  * Context: irq handler; we won't re-enter the driver that way.
 668  */
 669 irqreturn_t musb_g_ep0_irq(struct musb *musb)
 670 {
 671         u16             csr;
 672         u16             len;
 673         void __iomem    *mbase = musb->mregs;
 674         void __iomem    *regs = musb->endpoints[0].regs;
 675         irqreturn_t     retval = IRQ_NONE;
 676
 677         musb_ep_select(mbase, 0);       /* select ep0 */
 678         csr = musb_readw(regs, MUSB_CSR0);
 679         len = musb_readb(regs, MUSB_COUNT0);
 680
 681         dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
 682                         csr, len,
 683                         musb_readb(mbase, MUSB_FADDR),
 684                         decode_ep0stage(musb->ep0_state));
 685
 686         /* I sent a stall.. need to acknowledge it now.. */
 687         if (csr & MUSB_CSR0_P_SENTSTALL) {
 688                 musb_writew(regs, MUSB_CSR0,
 689                                 csr & ~MUSB_CSR0_P_SENTSTALL);
 690                 retval = IRQ_HANDLED;
 691                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 692                 csr = musb_readw(regs, MUSB_CSR0);
 693         }
 694
 695         /* request ended "early" */
 696         if (csr & MUSB_CSR0_P_SETUPEND) {
 697                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
 698                 retval = IRQ_HANDLED;
 699                 /* Transition into the early status phase */
 700                 switch (musb->ep0_state) {
 701                 case MUSB_EP0_STAGE_TX:
 702                         musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 703                         break;
 704                 case MUSB_EP0_STAGE_RX:
 705                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 706                         break;
 707                 default:
 708                         ERR("SetupEnd came in a wrong ep0stage %s\n",
 709                             decode_ep0stage(musb->ep0_state));
 710                 }
 711                 csr = musb_readw(regs, MUSB_CSR0);
 712                 /* NOTE:  request may need completion */
 713         }
 714
 715         /* docs from Mentor only describe tx, rx, and idle/setup states.
 716          * we need to handle nuances around status stages, and also the
 717          * case where status and setup stages come back-to-back ...
 718          */
 719         switch (musb->ep0_state) {
 720
 721         case MUSB_EP0_STAGE_TX:
 722                 /* irq on clearing txpktrdy */
 723                 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
 724                         ep0_txstate(musb);
 725                         retval = IRQ_HANDLED;
 726                 }
 727                 break;
 728
 729         case MUSB_EP0_STAGE_RX:
 730                 /* irq on set rxpktrdy */
 731                 if (csr & MUSB_CSR0_RXPKTRDY) {
 732                         ep0_rxstate(musb);
 733                         retval = IRQ_HANDLED;
 734                 }
 735                 break;
 736
 737         case MUSB_EP0_STAGE_STATUSIN:
 738                 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
 739
 740                 /* update address (if needed) only @ the end of the
 741                  * status phase per usb spec, which also guarantees
 742                  * we get 10 msec to receive this irq... until this
 743                  * is done we won't see the next packet.
 744                  */
 745                 if (musb->set_address) {
 746                         musb->set_address = false;
 747                         musb_writeb(mbase, MUSB_FADDR, musb->address);
 748                 }
 749
 750                 /* enter test mode if needed (exit by reset) */
 751                 else if (musb->test_mode) {
 752                         dev_dbg(musb->controller, "entering TESTMODE\n");
 753
 754                         if (MUSB_TEST_PACKET == musb->test_mode_nr)
 755                                 musb_load_testpacket(musb);
 756
 757                         musb_writeb(mbase, MUSB_TESTMODE,
 758                                         musb->test_mode_nr);
 759                 }
 760                 /* FALLTHROUGH */
 761
 762         case MUSB_EP0_STAGE_STATUSOUT:
 763                 /* end of sequence #1: write to host (TX state) */
 764                 {
 765                         struct musb_request     *req;
 766
 767                         req = next_ep0_request(musb);
 768                         if (req)
 769                                 musb_g_ep0_giveback(musb, &req->request);
 770                 }
 771
 772                 /*
 773                  * In case when several interrupts can get coalesced,
 774                  * check to see if we've already received a SETUP packet...
 775                  */
 776                 if (csr & MUSB_CSR0_RXPKTRDY)
 777                         goto setup;
 778
 779                 retval = IRQ_HANDLED;
 780                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 781                 break;
 782
 783         case MUSB_EP0_STAGE_IDLE:
 784                 /*
 785                  * This state is typically (but not always) indiscernible
 786                  * from the status states since the corresponding interrupts
 787                  * tend to happen within too little period of time (with only
 788                  * a zero-length packet in between) and so get coalesced...
 789                  */
 790                 retval = IRQ_HANDLED;
 791                 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
 792                 /* FALLTHROUGH */
 793
 794         case MUSB_EP0_STAGE_SETUP:
 795 setup:
 796                 if (csr & MUSB_CSR0_RXPKTRDY) {
 797                         struct usb_ctrlrequest  setup;
 798                         int                     handled = 0;
 799
 800                         if (len != 8) {
 801                                 ERR("SETUP packet len %d != 8 ?\n", len);
 802                                 break;
 803                         }
 804                         musb_read_setup(musb, &setup);
 805                         retval = IRQ_HANDLED;
 806
 807                         /* sometimes the RESET won't be reported */
 808                         if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
 809                                 u8      power;
 810
 811                                 printk(KERN_NOTICE "%s: peripheral reset "
 812                                                 "irq lost!\n",
 813                                                 musb_driver_name);
 814                                 power = musb_readb(mbase, MUSB_POWER);
 815                                 musb->g.speed = (power & MUSB_POWER_HSMODE)
 816                                         ? USB_SPEED_HIGH : USB_SPEED_FULL;
 817
 818                         }
 819
 820                         switch (musb->ep0_state) {
 821
 822                         /* sequence #3 (no data stage), includes requests
 823                          * we can't forward (notably SET_ADDRESS and the
 824                          * device/endpoint feature set/clear operations)
 825                          * plus SET_CONFIGURATION and others we must
 826                          */
 827                         case MUSB_EP0_STAGE_ACKWAIT:
 828                                 handled = service_zero_data_request(
 829                                                 musb, &setup);
 830
 831                                 /*
 832                                  * We're expecting no data in any case, so
 833                                  * always set the DATAEND bit -- doing this
 834                                  * here helps avoid SetupEnd interrupt coming
 835                                  * in the idle stage when we're stalling...
 836                                  */
 837                                 musb->ackpend |= MUSB_CSR0_P_DATAEND;
 838
 839                                 /* status stage might be immediate */
 840                                 if (handled > 0)
 841                                         musb->ep0_state =
 842                                                 MUSB_EP0_STAGE_STATUSIN;
 843                                 break;
 844
 845                         /* sequence #1 (IN to host), includes GET_STATUS
 846                          * requests that we can't forward, GET_DESCRIPTOR
 847                          * and others that we must
 848                          */
 849                         case MUSB_EP0_STAGE_TX:
 850                                 handled = service_in_request(musb, &setup);
 851                                 if (handled > 0) {
 852                                         musb->ackpend = MUSB_CSR0_TXPKTRDY
 853                                                 | MUSB_CSR0_P_DATAEND;
 854                                         musb->ep0_state =
 855                                                 MUSB_EP0_STAGE_STATUSOUT;
 856                                 }
 857                                 break;
 858
 859                         /* sequence #2 (OUT from host), always forward */
 860                         default:                /* MUSB_EP0_STAGE_RX */
 861                                 break;
 862                         }
 863
 864                         dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
 865                                 handled, csr,
 866                                 decode_ep0stage(musb->ep0_state));
 867
 868                         /* unless we need to delegate this to the gadget
 869                          * driver, we know how to wrap this up:  csr0 has
 870                          * not yet been written.
 871                          */
 872                         if (handled < 0)
 873                                 goto stall;
 874                         else if (handled > 0)
 875                                 goto finish;
 876
 877                         handled = forward_to_driver(musb, &setup);
 878                         if (handled < 0) {
 879                                 musb_ep_select(mbase, 0);
 880 stall:
 881                                 dev_dbg(musb->controller, "stall (%d)\n", handled);
 882                                 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
 883                                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 884 finish:
 885                                 musb_writew(regs, MUSB_CSR0,
 886                                                 musb->ackpend);
 887                                 musb->ackpend = 0;
 888                         }
 889                 }
 890                 break;
 891
 892         case MUSB_EP0_STAGE_ACKWAIT:
 893                 /* This should not happen. But happens with tusb6010 with
 894                  * g_file_storage and high speed. Do nothing.
 895                  */
 896                 retval = IRQ_HANDLED;
 897                 break;
 898
 899         default:
 900                 /* "can't happen" */
 901                 WARN_ON(1);
 902                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
 903                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 904                 break;
 905         }
 906
 907         return retval;
 908 }
 909
 910
 911 static int
 912 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
 913 {
 914         /* always enabled */
 915         return -EINVAL;
 916 }
 917
 918 static int musb_g_ep0_disable(struct usb_ep *e)
 919 {
 920         /* always enabled */
 921         return -EINVAL;
 922 }
 923
 924 static int
 925 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
 926 {
 927         struct musb_ep          *ep;
 928         struct musb_request     *req;
 929         struct musb             *musb;
 930         int                     status;
 931         unsigned long           lockflags;
 932         void __iomem            *regs;
 933
 934         if (!e || !r)
 935                 return -EINVAL;
 936
 937         ep = to_musb_ep(e);
 938         musb = ep->musb;
 939         regs = musb->control_ep->regs;
 940
 941         req = to_musb_request(r);
 942         req->musb = musb;
 943         req->request.actual = 0;
 944         req->request.status = -EINPROGRESS;
 945         req->tx = ep->is_in;
 946
 947         spin_lock_irqsave(&musb->lock, lockflags);
 948
 949         if (!list_empty(&ep->req_list)) {
 950                 status = -EBUSY;
 951                 goto cleanup;
 952         }
 953
 954         switch (musb->ep0_state) {
 955         case MUSB_EP0_STAGE_RX:         /* control-OUT data */
 956         case MUSB_EP0_STAGE_TX:         /* control-IN data */
 957         case MUSB_EP0_STAGE_ACKWAIT:    /* zero-length data */
 958                 status = 0;
 959                 break;
 960         default:
 961                 dev_dbg(musb->controller, "ep0 request queued in state %d\n",
 962                                 musb->ep0_state);
 963                 status = -EINVAL;
 964                 goto cleanup;
 965         }
 966
 967         /* add request to the list */
 968         list_add_tail(&req->list, &ep->req_list);
 969
 970         dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
 971                         ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
 972                         req->request.length);
 973
 974         musb_ep_select(musb->mregs, 0);
 975
 976         /* sequence #1, IN ... start writing the data */
 977         if (musb->ep0_state == MUSB_EP0_STAGE_TX)
 978                 ep0_txstate(musb);
 979
 980         /* sequence #3, no-data ... issue IN status */
 981         else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
 982                 if (req->request.length)
 983                         status = -EINVAL;
 984                 else {
 985                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 986                         musb_writew(regs, MUSB_CSR0,
 987                                         musb->ackpend | MUSB_CSR0_P_DATAEND);
 988                         musb->ackpend = 0;
 989                         musb_g_ep0_giveback(ep->musb, r);
 990                 }
 991
 992         /* else for sequence #2 (OUT), caller provides a buffer
 993          * before the next packet arrives.  deferred responses
 994          * (after SETUP is acked) are racey.
 995          */
 996         } else if (musb->ackpend) {
 997                 musb_writew(regs, MUSB_CSR0, musb->ackpend);
 998                 musb->ackpend = 0;
 999         }
1000
1001 cleanup:
1002         spin_unlock_irqrestore(&musb->lock, lockflags);
1003         return status;
1004 }
1005
1006 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
1007 {
1008         /* we just won't support this */
1009         return -EINVAL;
1010 }
1011
1012 static int musb_g_ep0_halt(struct usb_ep *e, int value)
1013 {
1014         struct musb_ep          *ep;
1015         struct musb             *musb;
1016         void __iomem            *base, *regs;
1017         unsigned long           flags;
1018         int                     status;
1019         u16                     csr;
1020
1021         if (!e || !value)
1022                 return -EINVAL;
1023
1024         ep = to_musb_ep(e);
1025         musb = ep->musb;
1026         base = musb->mregs;
1027         regs = musb->control_ep->regs;
1028         status = 0;
1029
1030         spin_lock_irqsave(&musb->lock, flags);
1031
1032         if (!list_empty(&ep->req_list)) {
1033                 status = -EBUSY;
1034                 goto cleanup;
1035         }
1036
1037         musb_ep_select(base, 0);
1038         csr = musb->ackpend;
1039
1040         switch (musb->ep0_state) {
1041
1042         /* Stalls are usually issued after parsing SETUP packet, either
1043          * directly in irq context from setup() or else later.
1044          */
1045         case MUSB_EP0_STAGE_TX:         /* control-IN data */
1046         case MUSB_EP0_STAGE_ACKWAIT:    /* STALL for zero-length data */
1047         case MUSB_EP0_STAGE_RX:         /* control-OUT data */
1048                 csr = musb_readw(regs, MUSB_CSR0);
1049                 /* FALLTHROUGH */
1050
1051         /* It's also OK to issue stalls during callbacks when a non-empty
1052          * DATA stage buffer has been read (or even written).
1053          */
1054         case MUSB_EP0_STAGE_STATUSIN:   /* control-OUT status */
1055         case MUSB_EP0_STAGE_STATUSOUT:  /* control-IN status */
1056
1057                 csr |= MUSB_CSR0_P_SENDSTALL;
1058                 musb_writew(regs, MUSB_CSR0, csr);
1059                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1060                 musb->ackpend = 0;
1061                 break;
1062         default:
1063                 dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
1064                 status = -EINVAL;
1065         }
1066
1067 cleanup:
1068         spin_unlock_irqrestore(&musb->lock, flags);
1069         return status;
1070 }
1071
1072 const struct usb_ep_ops musb_g_ep0_ops = {
1073         .enable         = musb_g_ep0_enable,
1074         .disable        = musb_g_ep0_disable,
1075         .alloc_request  = musb_alloc_request,
1076         .free_request   = musb_free_request,
1077         .queue          = musb_g_ep0_queue,
1078         .dequeue        = musb_g_ep0_dequeue,
1079         .set_halt       = musb_g_ep0_halt,
1080 };