2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
95 #define is_buffer_mapped(req) (is_dma_capable() && \
96 (req->map_state != UN_MAPPED))
98 /* Maps the buffer to dma */
100 static inline void map_dma_buffer(struct musb_request *request,
101 struct musb *musb, struct musb_ep *musb_ep)
103 int compatible = true;
104 struct dma_controller *dma = musb->dma_controller;
106 request->map_state = UN_MAPPED;
108 if (!is_dma_capable() || !musb_ep->dma)
111 /* Check if DMA engine can handle this request.
112 * DMA code must reject the USB request explicitly.
113 * Default behaviour is to map the request.
115 if (dma->is_compatible)
116 compatible = dma->is_compatible(musb_ep->dma,
117 musb_ep->packet_sz, request->request.buf,
118 request->request.length);
122 if (request->request.dma == DMA_ADDR_INVALID) {
123 request->request.dma = dma_map_single(
125 request->request.buf,
126 request->request.length,
130 request->map_state = MUSB_MAPPED;
132 dma_sync_single_for_device(musb->controller,
133 request->request.dma,
134 request->request.length,
138 request->map_state = PRE_MAPPED;
142 /* Unmap the buffer from dma and maps it back to cpu */
143 static inline void unmap_dma_buffer(struct musb_request *request,
146 if (!is_buffer_mapped(request))
149 if (request->request.dma == DMA_ADDR_INVALID) {
150 dev_vdbg(musb->controller,
151 "not unmapping a never mapped buffer\n");
154 if (request->map_state == MUSB_MAPPED) {
155 dma_unmap_single(musb->controller,
156 request->request.dma,
157 request->request.length,
161 request->request.dma = DMA_ADDR_INVALID;
162 } else { /* PRE_MAPPED */
163 dma_sync_single_for_cpu(musb->controller,
164 request->request.dma,
165 request->request.length,
170 request->map_state = UN_MAPPED;
174 * Immediately complete a request.
176 * @param request the request to complete
177 * @param status the status to complete the request with
178 * Context: controller locked, IRQs blocked.
180 void musb_g_giveback(
182 struct usb_request *request,
184 __releases(ep->musb->lock)
185 __acquires(ep->musb->lock)
187 struct musb_request *req;
191 req = to_musb_request(request);
193 list_del(&req->list);
194 if (req->request.status == -EINPROGRESS)
195 req->request.status = status;
199 spin_unlock(&musb->lock);
200 unmap_dma_buffer(req, musb);
201 if (request->status == 0)
202 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
203 ep->end_point.name, request,
204 req->request.actual, req->request.length);
206 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
207 ep->end_point.name, request,
208 req->request.actual, req->request.length,
210 req->request.complete(&req->ep->end_point, &req->request);
211 spin_lock(&musb->lock);
215 /* ----------------------------------------------------------------------- */
218 * Abort requests queued to an endpoint using the status. Synchronous.
219 * caller locked controller and blocked irqs, and selected this ep.
221 static void nuke(struct musb_ep *ep, const int status)
223 struct musb *musb = ep->musb;
224 struct musb_request *req = NULL;
225 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
229 if (is_dma_capable() && ep->dma) {
230 struct dma_controller *c = ep->musb->dma_controller;
235 * The programming guide says that we must not clear
236 * the DMAMODE bit before DMAENAB, so we only
237 * clear it in the second write...
239 musb_writew(epio, MUSB_TXCSR,
240 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
241 musb_writew(epio, MUSB_TXCSR,
242 0 | MUSB_TXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
246 musb_writew(epio, MUSB_RXCSR,
247 0 | MUSB_RXCSR_FLUSHFIFO);
250 value = c->channel_abort(ep->dma);
251 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
253 c->channel_release(ep->dma);
257 while (!list_empty(&ep->req_list)) {
258 req = list_first_entry(&ep->req_list, struct musb_request, list);
259 musb_g_giveback(ep, &req->request, status);
263 /* ----------------------------------------------------------------------- */
265 /* Data transfers - pure PIO, pure DMA, or mixed mode */
268 * This assumes the separate CPPI engine is responding to DMA requests
269 * from the usb core ... sequenced a bit differently from mentor dma.
272 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
274 if (can_bulk_split(musb, ep->type))
275 return ep->hw_ep->max_packet_sz_tx;
277 return ep->packet_sz;
281 #ifdef CONFIG_USB_INVENTRA_DMA
283 /* Peripheral tx (IN) using Mentor DMA works as follows:
284 Only mode 0 is used for transfers <= wPktSize,
285 mode 1 is used for larger transfers,
287 One of the following happens:
288 - Host sends IN token which causes an endpoint interrupt
290 -> if DMA is currently busy, exit.
291 -> if queue is non-empty, txstate().
293 - Request is queued by the gadget driver.
294 -> if queue was previously empty, txstate()
299 | (data is transferred to the FIFO, then sent out when
300 | IN token(s) are recd from Host.
301 | -> DMA interrupt on completion
303 | -> stop DMA, ~DMAENAB,
304 | -> set TxPktRdy for last short pkt or zlp
305 | -> Complete Request
306 | -> Continue next request (call txstate)
307 |___________________________________|
309 * Non-Mentor DMA engines can of course work differently, such as by
310 * upleveling from irq-per-packet to irq-per-buffer.
316 * An endpoint is transmitting data. This can be called either from
317 * the IRQ routine or from ep.queue() to kickstart a request on an
320 * Context: controller locked, IRQs blocked, endpoint selected
322 static void txstate(struct musb *musb, struct musb_request *req)
324 u8 epnum = req->epnum;
325 struct musb_ep *musb_ep;
326 void __iomem *epio = musb->endpoints[epnum].regs;
327 struct usb_request *request;
328 u16 fifo_count = 0, csr;
333 /* we shouldn't get here while DMA is active ... but we do ... */
334 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
335 dev_dbg(musb->controller, "dma pending...\n");
339 /* read TXCSR before */
340 csr = musb_readw(epio, MUSB_TXCSR);
342 request = &req->request;
343 fifo_count = min(max_ep_writesize(musb, musb_ep),
344 (int)(request->length - request->actual));
346 if (csr & MUSB_TXCSR_TXPKTRDY) {
347 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
348 musb_ep->end_point.name, csr);
352 if (csr & MUSB_TXCSR_P_SENDSTALL) {
353 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
354 musb_ep->end_point.name, csr);
358 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
359 epnum, musb_ep->packet_sz, fifo_count,
362 #ifndef CONFIG_MUSB_PIO_ONLY
363 if (is_buffer_mapped(req)) {
364 struct dma_controller *c = musb->dma_controller;
367 /* setup DMA, then program endpoint CSR */
368 request_size = min_t(size_t, request->length - request->actual,
369 musb_ep->dma->max_len);
371 use_dma = (request->dma != DMA_ADDR_INVALID);
373 /* MUSB_TXCSR_P_ISO is still set correctly */
375 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
377 if (request_size < musb_ep->packet_sz)
378 musb_ep->dma->desired_mode = 0;
380 musb_ep->dma->desired_mode = 1;
382 use_dma = use_dma && c->channel_program(
383 musb_ep->dma, musb_ep->packet_sz,
384 musb_ep->dma->desired_mode,
385 request->dma + request->actual, request_size);
387 if (musb_ep->dma->desired_mode == 0) {
389 * We must not clear the DMAMODE bit
390 * before the DMAENAB bit -- and the
391 * latter doesn't always get cleared
392 * before we get here...
394 csr &= ~(MUSB_TXCSR_AUTOSET
395 | MUSB_TXCSR_DMAENAB);
396 musb_writew(epio, MUSB_TXCSR, csr
397 | MUSB_TXCSR_P_WZC_BITS);
398 csr &= ~MUSB_TXCSR_DMAMODE;
399 csr |= (MUSB_TXCSR_DMAENAB |
401 /* against programming guide */
403 csr |= (MUSB_TXCSR_DMAENAB
406 if (!musb_ep->hb_mult)
407 csr |= MUSB_TXCSR_AUTOSET;
409 csr &= ~MUSB_TXCSR_P_UNDERRUN;
411 musb_writew(epio, MUSB_TXCSR, csr);
415 #elif defined(CONFIG_USB_TI_CPPI_DMA)
416 /* program endpoint CSR first, then setup DMA */
417 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
418 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
420 musb_writew(epio, MUSB_TXCSR,
421 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
424 /* ensure writebuffer is empty */
425 csr = musb_readw(epio, MUSB_TXCSR);
427 /* NOTE host side sets DMAENAB later than this; both are
428 * OK since the transfer dma glue (between CPPI and Mentor
429 * fifos) just tells CPPI it could start. Data only moves
430 * to the USB TX fifo when both fifos are ready.
433 /* "mode" is irrelevant here; handle terminating ZLPs like
434 * PIO does, since the hardware RNDIS mode seems unreliable
435 * except for the last-packet-is-already-short case.
437 use_dma = use_dma && c->channel_program(
438 musb_ep->dma, musb_ep->packet_sz,
440 request->dma + request->actual,
443 c->channel_release(musb_ep->dma);
445 csr &= ~MUSB_TXCSR_DMAENAB;
446 musb_writew(epio, MUSB_TXCSR, csr);
447 /* invariant: prequest->buf is non-null */
449 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
450 use_dma = use_dma && c->channel_program(
451 musb_ep->dma, musb_ep->packet_sz,
453 request->dma + request->actual,
461 * Unmap the dma buffer back to cpu if dma channel
464 unmap_dma_buffer(req, musb);
466 musb_write_fifo(musb_ep->hw_ep, fifo_count,
467 (u8 *) (request->buf + request->actual));
468 request->actual += fifo_count;
469 csr |= MUSB_TXCSR_TXPKTRDY;
470 csr &= ~MUSB_TXCSR_P_UNDERRUN;
471 musb_writew(epio, MUSB_TXCSR, csr);
474 /* host may already have the data when this message shows... */
475 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
476 musb_ep->end_point.name, use_dma ? "dma" : "pio",
477 request->actual, request->length,
478 musb_readw(epio, MUSB_TXCSR),
480 musb_readw(epio, MUSB_TXMAXP));
484 * FIFO state update (e.g. data ready).
485 * Called from IRQ, with controller locked.
487 void musb_g_tx(struct musb *musb, u8 epnum)
490 struct musb_request *req;
491 struct usb_request *request;
492 u8 __iomem *mbase = musb->mregs;
493 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
494 void __iomem *epio = musb->endpoints[epnum].regs;
495 struct dma_channel *dma;
497 musb_ep_select(mbase, epnum);
498 req = next_request(musb_ep);
499 request = &req->request;
501 csr = musb_readw(epio, MUSB_TXCSR);
502 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
504 dma = is_dma_capable() ? musb_ep->dma : NULL;
507 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
508 * probably rates reporting as a host error.
510 if (csr & MUSB_TXCSR_P_SENTSTALL) {
511 csr |= MUSB_TXCSR_P_WZC_BITS;
512 csr &= ~MUSB_TXCSR_P_SENTSTALL;
513 musb_writew(epio, MUSB_TXCSR, csr);
517 if (csr & MUSB_TXCSR_P_UNDERRUN) {
518 /* We NAKed, no big deal... little reason to care. */
519 csr |= MUSB_TXCSR_P_WZC_BITS;
520 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
521 musb_writew(epio, MUSB_TXCSR, csr);
522 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
526 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
528 * SHOULD NOT HAPPEN... has with CPPI though, after
529 * changing SENDSTALL (and other cases); harmless?
531 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
538 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
540 csr |= MUSB_TXCSR_P_WZC_BITS;
541 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
542 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
543 musb_writew(epio, MUSB_TXCSR, csr);
544 /* Ensure writebuffer is empty. */
545 csr = musb_readw(epio, MUSB_TXCSR);
546 request->actual += musb_ep->dma->actual_len;
547 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
548 epnum, csr, musb_ep->dma->actual_len, request);
552 * First, maybe a terminating short packet. Some DMA
553 * engines might handle this by themselves.
555 if ((request->zero && request->length
556 && (request->length % musb_ep->packet_sz == 0)
557 && (request->actual == request->length))
558 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
559 || (is_dma && (!dma->desired_mode ||
561 (musb_ep->packet_sz - 1))))
565 * On DMA completion, FIFO may not be
568 if (csr & MUSB_TXCSR_TXPKTRDY)
571 dev_dbg(musb->controller, "sending zero pkt\n");
572 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
573 | MUSB_TXCSR_TXPKTRDY);
577 if (request->actual == request->length) {
578 musb_g_giveback(musb_ep, request, 0);
580 * In the giveback function the MUSB lock is
581 * released and acquired after sometime. During
582 * this time period the INDEX register could get
583 * changed by the gadget_queue function especially
584 * on SMP systems. Reselect the INDEX to be sure
585 * we are reading/modifying the right registers
587 musb_ep_select(mbase, epnum);
588 req = musb_ep->desc ? next_request(musb_ep) : NULL;
590 dev_dbg(musb->controller, "%s idle now\n",
591 musb_ep->end_point.name);
600 /* ------------------------------------------------------------ */
602 #ifdef CONFIG_USB_INVENTRA_DMA
604 /* Peripheral rx (OUT) using Mentor DMA works as follows:
605 - Only mode 0 is used.
607 - Request is queued by the gadget class driver.
608 -> if queue was previously empty, rxstate()
610 - Host sends OUT token which causes an endpoint interrupt
612 | -> if request queued, call rxstate
614 | | -> DMA interrupt on completion
618 | | -> if data recd = max expected
619 | | by the request, or host
620 | | sent a short packet,
621 | | complete the request,
622 | | and start the next one.
623 | |_____________________________________|
624 | else just wait for the host
625 | to send the next OUT token.
626 |__________________________________________________|
628 * Non-Mentor DMA engines can of course work differently.
634 * Context: controller locked, IRQs blocked, endpoint selected
636 static void rxstate(struct musb *musb, struct musb_request *req)
638 const u8 epnum = req->epnum;
639 struct usb_request *request = &req->request;
640 struct musb_ep *musb_ep;
641 void __iomem *epio = musb->endpoints[epnum].regs;
642 unsigned fifo_count = 0;
644 u16 csr = musb_readw(epio, MUSB_RXCSR);
645 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
648 if (hw_ep->is_shared_fifo)
649 musb_ep = &hw_ep->ep_in;
651 musb_ep = &hw_ep->ep_out;
653 len = musb_ep->packet_sz;
655 /* We shouldn't get here while DMA is active, but we do... */
656 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
657 dev_dbg(musb->controller, "DMA pending...\n");
661 if (csr & MUSB_RXCSR_P_SENDSTALL) {
662 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
663 musb_ep->end_point.name, csr);
667 if (is_cppi_enabled() && is_buffer_mapped(req)) {
668 struct dma_controller *c = musb->dma_controller;
669 struct dma_channel *channel = musb_ep->dma;
671 /* NOTE: CPPI won't actually stop advancing the DMA
672 * queue after short packet transfers, so this is almost
673 * always going to run as IRQ-per-packet DMA so that
674 * faults will be handled correctly.
676 if (c->channel_program(channel,
678 !request->short_not_ok,
679 request->dma + request->actual,
680 request->length - request->actual)) {
682 /* make sure that if an rxpkt arrived after the irq,
683 * the cppi engine will be ready to take it as soon
686 csr &= ~(MUSB_RXCSR_AUTOCLEAR
687 | MUSB_RXCSR_DMAMODE);
688 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
689 musb_writew(epio, MUSB_RXCSR, csr);
694 if (csr & MUSB_RXCSR_RXPKTRDY) {
695 len = musb_readw(epio, MUSB_RXCOUNT);
698 * Enable Mode 1 on RX transfers only when short_not_ok flag
699 * is set. Currently short_not_ok flag is set only from
700 * file_storage and f_mass_storage drivers
703 if (request->short_not_ok && len == musb_ep->packet_sz)
708 if (request->actual < request->length) {
709 #ifdef CONFIG_USB_INVENTRA_DMA
710 if (is_buffer_mapped(req)) {
711 struct dma_controller *c;
712 struct dma_channel *channel;
715 c = musb->dma_controller;
716 channel = musb_ep->dma;
718 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
719 * mode 0 only. So we do not get endpoint interrupts due to DMA
720 * completion. We only get interrupts from DMA controller.
722 * We could operate in DMA mode 1 if we knew the size of the tranfer
723 * in advance. For mass storage class, request->length = what the host
724 * sends, so that'd work. But for pretty much everything else,
725 * request->length is routinely more than what the host sends. For
726 * most these gadgets, end of is signified either by a short packet,
727 * or filling the last byte of the buffer. (Sending extra data in
728 * that last pckate should trigger an overflow fault.) But in mode 1,
729 * we don't get DMA completion interrupt for short packets.
731 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
732 * to get endpoint interrupt on every DMA req, but that didn't seem
735 * REVISIT an updated g_file_storage can set req->short_not_ok, which
736 * then becomes usable as a runtime "use mode 1" hint...
739 /* Experimental: Mode1 works with mass storage use cases */
741 csr |= MUSB_RXCSR_AUTOCLEAR;
742 musb_writew(epio, MUSB_RXCSR, csr);
743 csr |= MUSB_RXCSR_DMAENAB;
744 musb_writew(epio, MUSB_RXCSR, csr);
747 * this special sequence (enabling and then
748 * disabling MUSB_RXCSR_DMAMODE) is required
749 * to get DMAReq to activate
751 musb_writew(epio, MUSB_RXCSR,
752 csr | MUSB_RXCSR_DMAMODE);
753 musb_writew(epio, MUSB_RXCSR, csr);
756 if (!musb_ep->hb_mult &&
757 musb_ep->hw_ep->rx_double_buffered)
758 csr |= MUSB_RXCSR_AUTOCLEAR;
759 csr |= MUSB_RXCSR_DMAENAB;
760 musb_writew(epio, MUSB_RXCSR, csr);
763 if (request->actual < request->length) {
764 int transfer_size = 0;
766 transfer_size = min(request->length - request->actual,
768 musb_ep->dma->desired_mode = 1;
770 transfer_size = min(request->length - request->actual,
772 musb_ep->dma->desired_mode = 0;
775 use_dma = c->channel_program(
778 channel->desired_mode,
787 #elif defined(CONFIG_USB_UX500_DMA)
788 if ((is_buffer_mapped(req)) &&
789 (request->actual < request->length)) {
791 struct dma_controller *c;
792 struct dma_channel *channel;
793 int transfer_size = 0;
795 c = musb->dma_controller;
796 channel = musb_ep->dma;
798 /* In case first packet is short */
799 if (len < musb_ep->packet_sz)
801 else if (request->short_not_ok)
802 transfer_size = min(request->length -
806 transfer_size = min(request->length -
810 csr &= ~MUSB_RXCSR_DMAMODE;
811 csr |= (MUSB_RXCSR_DMAENAB |
812 MUSB_RXCSR_AUTOCLEAR);
814 musb_writew(epio, MUSB_RXCSR, csr);
816 if (transfer_size <= musb_ep->packet_sz) {
817 musb_ep->dma->desired_mode = 0;
819 musb_ep->dma->desired_mode = 1;
820 /* Mode must be set after DMAENAB */
821 csr |= MUSB_RXCSR_DMAMODE;
822 musb_writew(epio, MUSB_RXCSR, csr);
825 if (c->channel_program(channel,
827 channel->desired_mode,
834 #endif /* Mentor's DMA */
836 fifo_count = request->length - request->actual;
837 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
838 musb_ep->end_point.name,
842 fifo_count = min_t(unsigned, len, fifo_count);
844 #ifdef CONFIG_USB_TUSB_OMAP_DMA
845 if (tusb_dma_omap() && is_buffer_mapped(req)) {
846 struct dma_controller *c = musb->dma_controller;
847 struct dma_channel *channel = musb_ep->dma;
848 u32 dma_addr = request->dma + request->actual;
851 ret = c->channel_program(channel,
853 channel->desired_mode,
861 * Unmap the dma buffer back to cpu if dma channel
862 * programming fails. This buffer is mapped if the
863 * channel allocation is successful
865 if (is_buffer_mapped(req)) {
866 unmap_dma_buffer(req, musb);
869 * Clear DMAENAB and AUTOCLEAR for the
872 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
873 musb_writew(epio, MUSB_RXCSR, csr);
876 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
877 (request->buf + request->actual));
878 request->actual += fifo_count;
880 /* REVISIT if we left anything in the fifo, flush
881 * it and report -EOVERFLOW
885 csr |= MUSB_RXCSR_P_WZC_BITS;
886 csr &= ~MUSB_RXCSR_RXPKTRDY;
887 musb_writew(epio, MUSB_RXCSR, csr);
891 /* reach the end or short packet detected */
892 if (request->actual == request->length || len < musb_ep->packet_sz)
893 musb_g_giveback(musb_ep, request, 0);
897 * Data ready for a request; called from IRQ
899 void musb_g_rx(struct musb *musb, u8 epnum)
902 struct musb_request *req;
903 struct usb_request *request;
904 void __iomem *mbase = musb->mregs;
905 struct musb_ep *musb_ep;
906 void __iomem *epio = musb->endpoints[epnum].regs;
907 struct dma_channel *dma;
908 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
910 if (hw_ep->is_shared_fifo)
911 musb_ep = &hw_ep->ep_in;
913 musb_ep = &hw_ep->ep_out;
915 musb_ep_select(mbase, epnum);
917 req = next_request(musb_ep);
921 request = &req->request;
923 csr = musb_readw(epio, MUSB_RXCSR);
924 dma = is_dma_capable() ? musb_ep->dma : NULL;
926 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
927 csr, dma ? " (dma)" : "", request);
929 if (csr & MUSB_RXCSR_P_SENTSTALL) {
930 csr |= MUSB_RXCSR_P_WZC_BITS;
931 csr &= ~MUSB_RXCSR_P_SENTSTALL;
932 musb_writew(epio, MUSB_RXCSR, csr);
936 if (csr & MUSB_RXCSR_P_OVERRUN) {
937 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
938 csr &= ~MUSB_RXCSR_P_OVERRUN;
939 musb_writew(epio, MUSB_RXCSR, csr);
941 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
942 if (request->status == -EINPROGRESS)
943 request->status = -EOVERFLOW;
945 if (csr & MUSB_RXCSR_INCOMPRX) {
946 /* REVISIT not necessarily an error */
947 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
950 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
951 /* "should not happen"; likely RXPKTRDY pending for DMA */
952 dev_dbg(musb->controller, "%s busy, csr %04x\n",
953 musb_ep->end_point.name, csr);
957 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
958 csr &= ~(MUSB_RXCSR_AUTOCLEAR
960 | MUSB_RXCSR_DMAMODE);
961 musb_writew(epio, MUSB_RXCSR,
962 MUSB_RXCSR_P_WZC_BITS | csr);
964 request->actual += musb_ep->dma->actual_len;
966 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
968 musb_readw(epio, MUSB_RXCSR),
969 musb_ep->dma->actual_len, request);
971 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
972 defined(CONFIG_USB_UX500_DMA)
973 /* Autoclear doesn't clear RxPktRdy for short packets */
974 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
976 & (musb_ep->packet_sz - 1))) {
978 csr &= ~MUSB_RXCSR_RXPKTRDY;
979 musb_writew(epio, MUSB_RXCSR, csr);
982 /* incomplete, and not short? wait for next IN packet */
983 if ((request->actual < request->length)
984 && (musb_ep->dma->actual_len
985 == musb_ep->packet_sz)) {
986 /* In double buffer case, continue to unload fifo if
987 * there is Rx packet in FIFO.
989 csr = musb_readw(epio, MUSB_RXCSR);
990 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
991 hw_ep->rx_double_buffered)
996 musb_g_giveback(musb_ep, request, 0);
998 * In the giveback function the MUSB lock is
999 * released and acquired after sometime. During
1000 * this time period the INDEX register could get
1001 * changed by the gadget_queue function especially
1002 * on SMP systems. Reselect the INDEX to be sure
1003 * we are reading/modifying the right registers
1005 musb_ep_select(mbase, epnum);
1007 req = next_request(musb_ep);
1011 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
1012 defined(CONFIG_USB_UX500_DMA)
1015 /* Analyze request */
1019 /* ------------------------------------------------------------ */
1021 static int musb_gadget_enable(struct usb_ep *ep,
1022 const struct usb_endpoint_descriptor *desc)
1024 unsigned long flags;
1025 struct musb_ep *musb_ep;
1026 struct musb_hw_ep *hw_ep;
1029 void __iomem *mbase;
1033 int status = -EINVAL;
1038 musb_ep = to_musb_ep(ep);
1039 hw_ep = musb_ep->hw_ep;
1041 musb = musb_ep->musb;
1042 mbase = musb->mregs;
1043 epnum = musb_ep->current_epnum;
1045 spin_lock_irqsave(&musb->lock, flags);
1047 if (musb_ep->desc) {
1051 musb_ep->type = usb_endpoint_type(desc);
1053 /* check direction and (later) maxpacket size against endpoint */
1054 if (usb_endpoint_num(desc) != epnum)
1057 /* REVISIT this rules out high bandwidth periodic transfers */
1058 tmp = usb_endpoint_maxp(desc);
1059 if (tmp & ~0x07ff) {
1062 if (usb_endpoint_dir_in(desc))
1063 ok = musb->hb_iso_tx;
1065 ok = musb->hb_iso_rx;
1068 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1071 musb_ep->hb_mult = (tmp >> 11) & 3;
1073 musb_ep->hb_mult = 0;
1076 musb_ep->packet_sz = tmp & 0x7ff;
1077 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1079 /* enable the interrupts for the endpoint, set the endpoint
1080 * packet size (or fail), set the mode, clear the fifo
1082 musb_ep_select(mbase, epnum);
1083 if (usb_endpoint_dir_in(desc)) {
1084 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1086 if (hw_ep->is_shared_fifo)
1088 if (!musb_ep->is_in)
1091 if (tmp > hw_ep->max_packet_sz_tx) {
1092 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1096 int_txe |= (1 << epnum);
1097 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1099 /* REVISIT if can_bulk_split(), use by updating "tmp";
1100 * likewise high bandwidth periodic tx
1102 /* Set TXMAXP with the FIFO size of the endpoint
1103 * to disable double buffering mode.
1105 if (musb->double_buffer_not_ok)
1106 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1108 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1109 | (musb_ep->hb_mult << 11));
1111 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1112 if (musb_readw(regs, MUSB_TXCSR)
1113 & MUSB_TXCSR_FIFONOTEMPTY)
1114 csr |= MUSB_TXCSR_FLUSHFIFO;
1115 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1116 csr |= MUSB_TXCSR_P_ISO;
1118 /* set twice in case of double buffering */
1119 musb_writew(regs, MUSB_TXCSR, csr);
1120 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1121 musb_writew(regs, MUSB_TXCSR, csr);
1124 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1126 if (hw_ep->is_shared_fifo)
1131 if (tmp > hw_ep->max_packet_sz_rx) {
1132 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1136 int_rxe |= (1 << epnum);
1137 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1139 /* REVISIT if can_bulk_combine() use by updating "tmp"
1140 * likewise high bandwidth periodic rx
1142 /* Set RXMAXP with the FIFO size of the endpoint
1143 * to disable double buffering mode.
1145 if (musb->double_buffer_not_ok)
1146 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1148 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1149 | (musb_ep->hb_mult << 11));
1151 /* force shared fifo to OUT-only mode */
1152 if (hw_ep->is_shared_fifo) {
1153 csr = musb_readw(regs, MUSB_TXCSR);
1154 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1155 musb_writew(regs, MUSB_TXCSR, csr);
1158 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1159 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1160 csr |= MUSB_RXCSR_P_ISO;
1161 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1162 csr |= MUSB_RXCSR_DISNYET;
1164 /* set twice in case of double buffering */
1165 musb_writew(regs, MUSB_RXCSR, csr);
1166 musb_writew(regs, MUSB_RXCSR, csr);
1169 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1170 * for some reason you run out of channels here.
1172 if (is_dma_capable() && musb->dma_controller) {
1173 struct dma_controller *c = musb->dma_controller;
1175 musb_ep->dma = c->channel_alloc(c, hw_ep,
1176 (desc->bEndpointAddress & USB_DIR_IN));
1178 musb_ep->dma = NULL;
1180 musb_ep->desc = desc;
1182 musb_ep->wedged = 0;
1185 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1186 musb_driver_name, musb_ep->end_point.name,
1187 ({ char *s; switch (musb_ep->type) {
1188 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1189 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1190 default: s = "iso"; break;
1192 musb_ep->is_in ? "IN" : "OUT",
1193 musb_ep->dma ? "dma, " : "",
1194 musb_ep->packet_sz);
1196 schedule_work(&musb->irq_work);
1199 spin_unlock_irqrestore(&musb->lock, flags);
1204 * Disable an endpoint flushing all requests queued.
1206 static int musb_gadget_disable(struct usb_ep *ep)
1208 unsigned long flags;
1211 struct musb_ep *musb_ep;
1215 musb_ep = to_musb_ep(ep);
1216 musb = musb_ep->musb;
1217 epnum = musb_ep->current_epnum;
1218 epio = musb->endpoints[epnum].regs;
1220 spin_lock_irqsave(&musb->lock, flags);
1221 musb_ep_select(musb->mregs, epnum);
1223 /* zero the endpoint sizes */
1224 if (musb_ep->is_in) {
1225 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1226 int_txe &= ~(1 << epnum);
1227 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1228 musb_writew(epio, MUSB_TXMAXP, 0);
1230 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1231 int_rxe &= ~(1 << epnum);
1232 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1233 musb_writew(epio, MUSB_RXMAXP, 0);
1236 musb_ep->desc = NULL;
1237 musb_ep->end_point.desc = NULL;
1239 /* abort all pending DMA and requests */
1240 nuke(musb_ep, -ESHUTDOWN);
1242 schedule_work(&musb->irq_work);
1244 spin_unlock_irqrestore(&(musb->lock), flags);
1246 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1252 * Allocate a request for an endpoint.
1253 * Reused by ep0 code.
1255 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1257 struct musb_ep *musb_ep = to_musb_ep(ep);
1258 struct musb *musb = musb_ep->musb;
1259 struct musb_request *request = NULL;
1261 request = kzalloc(sizeof *request, gfp_flags);
1263 dev_dbg(musb->controller, "not enough memory\n");
1267 request->request.dma = DMA_ADDR_INVALID;
1268 request->epnum = musb_ep->current_epnum;
1269 request->ep = musb_ep;
1271 return &request->request;
1276 * Reused by ep0 code.
1278 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1280 kfree(to_musb_request(req));
1283 static LIST_HEAD(buffers);
1285 struct free_record {
1286 struct list_head list;
1293 * Context: controller locked, IRQs blocked.
1295 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1297 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1298 req->tx ? "TX/IN" : "RX/OUT",
1299 &req->request, req->request.length, req->epnum);
1301 musb_ep_select(musb->mregs, req->epnum);
1308 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1311 struct musb_ep *musb_ep;
1312 struct musb_request *request;
1315 unsigned long lockflags;
1322 musb_ep = to_musb_ep(ep);
1323 musb = musb_ep->musb;
1325 request = to_musb_request(req);
1326 request->musb = musb;
1328 if (request->ep != musb_ep)
1331 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1333 /* request is mine now... */
1334 request->request.actual = 0;
1335 request->request.status = -EINPROGRESS;
1336 request->epnum = musb_ep->current_epnum;
1337 request->tx = musb_ep->is_in;
1339 map_dma_buffer(request, musb, musb_ep);
1341 spin_lock_irqsave(&musb->lock, lockflags);
1343 /* don't queue if the ep is down */
1344 if (!musb_ep->desc) {
1345 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1346 req, ep->name, "disabled");
1347 status = -ESHUTDOWN;
1351 /* add request to the list */
1352 list_add_tail(&request->list, &musb_ep->req_list);
1354 /* it this is the head of the queue, start i/o ... */
1355 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1356 musb_ep_restart(musb, request);
1359 spin_unlock_irqrestore(&musb->lock, lockflags);
1363 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1365 struct musb_ep *musb_ep = to_musb_ep(ep);
1366 struct musb_request *req = to_musb_request(request);
1367 struct musb_request *r;
1368 unsigned long flags;
1370 struct musb *musb = musb_ep->musb;
1372 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1375 spin_lock_irqsave(&musb->lock, flags);
1377 list_for_each_entry(r, &musb_ep->req_list, list) {
1382 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1387 /* if the hardware doesn't have the request, easy ... */
1388 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1389 musb_g_giveback(musb_ep, request, -ECONNRESET);
1391 /* ... else abort the dma transfer ... */
1392 else if (is_dma_capable() && musb_ep->dma) {
1393 struct dma_controller *c = musb->dma_controller;
1395 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1396 if (c->channel_abort)
1397 status = c->channel_abort(musb_ep->dma);
1401 musb_g_giveback(musb_ep, request, -ECONNRESET);
1403 /* NOTE: by sticking to easily tested hardware/driver states,
1404 * we leave counting of in-flight packets imprecise.
1406 musb_g_giveback(musb_ep, request, -ECONNRESET);
1410 spin_unlock_irqrestore(&musb->lock, flags);
1415 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1416 * data but will queue requests.
1418 * exported to ep0 code
1420 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1422 struct musb_ep *musb_ep = to_musb_ep(ep);
1423 u8 epnum = musb_ep->current_epnum;
1424 struct musb *musb = musb_ep->musb;
1425 void __iomem *epio = musb->endpoints[epnum].regs;
1426 void __iomem *mbase;
1427 unsigned long flags;
1429 struct musb_request *request;
1434 mbase = musb->mregs;
1436 spin_lock_irqsave(&musb->lock, flags);
1438 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1443 musb_ep_select(mbase, epnum);
1445 request = next_request(musb_ep);
1448 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1453 /* Cannot portably stall with non-empty FIFO */
1454 if (musb_ep->is_in) {
1455 csr = musb_readw(epio, MUSB_TXCSR);
1456 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1457 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1463 musb_ep->wedged = 0;
1465 /* set/clear the stall and toggle bits */
1466 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1467 if (musb_ep->is_in) {
1468 csr = musb_readw(epio, MUSB_TXCSR);
1469 csr |= MUSB_TXCSR_P_WZC_BITS
1470 | MUSB_TXCSR_CLRDATATOG;
1472 csr |= MUSB_TXCSR_P_SENDSTALL;
1474 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1475 | MUSB_TXCSR_P_SENTSTALL);
1476 csr &= ~MUSB_TXCSR_TXPKTRDY;
1477 musb_writew(epio, MUSB_TXCSR, csr);
1479 csr = musb_readw(epio, MUSB_RXCSR);
1480 csr |= MUSB_RXCSR_P_WZC_BITS
1481 | MUSB_RXCSR_FLUSHFIFO
1482 | MUSB_RXCSR_CLRDATATOG;
1484 csr |= MUSB_RXCSR_P_SENDSTALL;
1486 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1487 | MUSB_RXCSR_P_SENTSTALL);
1488 musb_writew(epio, MUSB_RXCSR, csr);
1491 /* maybe start the first request in the queue */
1492 if (!musb_ep->busy && !value && request) {
1493 dev_dbg(musb->controller, "restarting the request\n");
1494 musb_ep_restart(musb, request);
1498 spin_unlock_irqrestore(&musb->lock, flags);
1503 * Sets the halt feature with the clear requests ignored
1505 static int musb_gadget_set_wedge(struct usb_ep *ep)
1507 struct musb_ep *musb_ep = to_musb_ep(ep);
1512 musb_ep->wedged = 1;
1514 return usb_ep_set_halt(ep);
1517 static int musb_gadget_fifo_status(struct usb_ep *ep)
1519 struct musb_ep *musb_ep = to_musb_ep(ep);
1520 void __iomem *epio = musb_ep->hw_ep->regs;
1521 int retval = -EINVAL;
1523 if (musb_ep->desc && !musb_ep->is_in) {
1524 struct musb *musb = musb_ep->musb;
1525 int epnum = musb_ep->current_epnum;
1526 void __iomem *mbase = musb->mregs;
1527 unsigned long flags;
1529 spin_lock_irqsave(&musb->lock, flags);
1531 musb_ep_select(mbase, epnum);
1532 /* FIXME return zero unless RXPKTRDY is set */
1533 retval = musb_readw(epio, MUSB_RXCOUNT);
1535 spin_unlock_irqrestore(&musb->lock, flags);
1540 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1542 struct musb_ep *musb_ep = to_musb_ep(ep);
1543 struct musb *musb = musb_ep->musb;
1544 u8 epnum = musb_ep->current_epnum;
1545 void __iomem *epio = musb->endpoints[epnum].regs;
1546 void __iomem *mbase;
1547 unsigned long flags;
1550 mbase = musb->mregs;
1552 spin_lock_irqsave(&musb->lock, flags);
1553 musb_ep_select(mbase, (u8) epnum);
1555 /* disable interrupts */
1556 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1557 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1559 if (musb_ep->is_in) {
1560 csr = musb_readw(epio, MUSB_TXCSR);
1561 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1562 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1564 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1565 * to interrupt current FIFO loading, but not flushing
1566 * the already loaded ones.
1568 csr &= ~MUSB_TXCSR_TXPKTRDY;
1569 musb_writew(epio, MUSB_TXCSR, csr);
1570 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1571 musb_writew(epio, MUSB_TXCSR, csr);
1574 csr = musb_readw(epio, MUSB_RXCSR);
1575 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1576 musb_writew(epio, MUSB_RXCSR, csr);
1577 musb_writew(epio, MUSB_RXCSR, csr);
1580 /* re-enable interrupt */
1581 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1582 spin_unlock_irqrestore(&musb->lock, flags);
1585 static const struct usb_ep_ops musb_ep_ops = {
1586 .enable = musb_gadget_enable,
1587 .disable = musb_gadget_disable,
1588 .alloc_request = musb_alloc_request,
1589 .free_request = musb_free_request,
1590 .queue = musb_gadget_queue,
1591 .dequeue = musb_gadget_dequeue,
1592 .set_halt = musb_gadget_set_halt,
1593 .set_wedge = musb_gadget_set_wedge,
1594 .fifo_status = musb_gadget_fifo_status,
1595 .fifo_flush = musb_gadget_fifo_flush
1598 /* ----------------------------------------------------------------------- */
1600 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1602 struct musb *musb = gadget_to_musb(gadget);
1604 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1607 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1609 struct musb *musb = gadget_to_musb(gadget);
1610 void __iomem *mregs = musb->mregs;
1611 unsigned long flags;
1612 int status = -EINVAL;
1616 spin_lock_irqsave(&musb->lock, flags);
1618 switch (musb->xceiv->state) {
1619 case OTG_STATE_B_PERIPHERAL:
1620 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1621 * that's part of the standard usb 1.1 state machine, and
1622 * doesn't affect OTG transitions.
1624 if (musb->may_wakeup && musb->is_suspended)
1627 case OTG_STATE_B_IDLE:
1628 /* Start SRP ... OTG not required. */
1629 devctl = musb_readb(mregs, MUSB_DEVCTL);
1630 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1631 devctl |= MUSB_DEVCTL_SESSION;
1632 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1633 devctl = musb_readb(mregs, MUSB_DEVCTL);
1635 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1636 devctl = musb_readb(mregs, MUSB_DEVCTL);
1641 while (devctl & MUSB_DEVCTL_SESSION) {
1642 devctl = musb_readb(mregs, MUSB_DEVCTL);
1647 spin_unlock_irqrestore(&musb->lock, flags);
1648 otg_start_srp(musb->xceiv);
1649 spin_lock_irqsave(&musb->lock, flags);
1651 /* Block idling for at least 1s */
1652 musb_platform_try_idle(musb,
1653 jiffies + msecs_to_jiffies(1 * HZ));
1658 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1659 otg_state_string(musb->xceiv->state));
1665 power = musb_readb(mregs, MUSB_POWER);
1666 power |= MUSB_POWER_RESUME;
1667 musb_writeb(mregs, MUSB_POWER, power);
1668 dev_dbg(musb->controller, "issue wakeup\n");
1670 /* FIXME do this next chunk in a timer callback, no udelay */
1673 power = musb_readb(mregs, MUSB_POWER);
1674 power &= ~MUSB_POWER_RESUME;
1675 musb_writeb(mregs, MUSB_POWER, power);
1677 spin_unlock_irqrestore(&musb->lock, flags);
1682 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1684 struct musb *musb = gadget_to_musb(gadget);
1686 musb->is_self_powered = !!is_selfpowered;
1690 static void musb_pullup(struct musb *musb, int is_on)
1694 power = musb_readb(musb->mregs, MUSB_POWER);
1696 power |= MUSB_POWER_SOFTCONN;
1698 power &= ~MUSB_POWER_SOFTCONN;
1700 /* FIXME if on, HdrcStart; if off, HdrcStop */
1702 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1703 is_on ? "on" : "off");
1704 musb_writeb(musb->mregs, MUSB_POWER, power);
1708 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1710 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1713 * FIXME iff driver's softconnect flag is set (as it is during probe,
1714 * though that can clear it), just musb_pullup().
1721 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1723 struct musb *musb = gadget_to_musb(gadget);
1725 if (!musb->xceiv->set_power)
1727 return otg_set_power(musb->xceiv, mA);
1730 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1732 struct musb *musb = gadget_to_musb(gadget);
1733 unsigned long flags;
1737 pm_runtime_get_sync(musb->controller);
1739 /* NOTE: this assumes we are sensing vbus; we'd rather
1740 * not pullup unless the B-session is active.
1742 spin_lock_irqsave(&musb->lock, flags);
1743 if (is_on != musb->softconnect) {
1744 musb->softconnect = is_on;
1745 musb_pullup(musb, is_on);
1747 spin_unlock_irqrestore(&musb->lock, flags);
1749 pm_runtime_put(musb->controller);
1754 static int musb_gadget_start(struct usb_gadget *g,
1755 struct usb_gadget_driver *driver);
1756 static int musb_gadget_stop(struct usb_gadget *g,
1757 struct usb_gadget_driver *driver);
1759 static const struct usb_gadget_ops musb_gadget_operations = {
1760 .get_frame = musb_gadget_get_frame,
1761 .wakeup = musb_gadget_wakeup,
1762 .set_selfpowered = musb_gadget_set_self_powered,
1763 /* .vbus_session = musb_gadget_vbus_session, */
1764 .vbus_draw = musb_gadget_vbus_draw,
1765 .pullup = musb_gadget_pullup,
1766 .udc_start = musb_gadget_start,
1767 .udc_stop = musb_gadget_stop,
1770 /* ----------------------------------------------------------------------- */
1774 /* Only this registration code "knows" the rule (from USB standards)
1775 * about there being only one external upstream port. It assumes
1776 * all peripheral ports are external...
1779 static void musb_gadget_release(struct device *dev)
1781 /* kref_put(WHAT) */
1782 dev_dbg(dev, "%s\n", __func__);
1787 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1789 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1791 memset(ep, 0, sizeof *ep);
1793 ep->current_epnum = epnum;
1798 INIT_LIST_HEAD(&ep->req_list);
1800 sprintf(ep->name, "ep%d%s", epnum,
1801 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1802 is_in ? "in" : "out"));
1803 ep->end_point.name = ep->name;
1804 INIT_LIST_HEAD(&ep->end_point.ep_list);
1806 ep->end_point.maxpacket = 64;
1807 ep->end_point.ops = &musb_g_ep0_ops;
1808 musb->g.ep0 = &ep->end_point;
1811 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1813 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1814 ep->end_point.ops = &musb_ep_ops;
1815 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1820 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1821 * to the rest of the driver state.
1823 static inline void __init musb_g_init_endpoints(struct musb *musb)
1826 struct musb_hw_ep *hw_ep;
1829 /* initialize endpoint list just once */
1830 INIT_LIST_HEAD(&(musb->g.ep_list));
1832 for (epnum = 0, hw_ep = musb->endpoints;
1833 epnum < musb->nr_endpoints;
1835 if (hw_ep->is_shared_fifo /* || !epnum */) {
1836 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1839 if (hw_ep->max_packet_sz_tx) {
1840 init_peripheral_ep(musb, &hw_ep->ep_in,
1844 if (hw_ep->max_packet_sz_rx) {
1845 init_peripheral_ep(musb, &hw_ep->ep_out,
1853 /* called once during driver setup to initialize and link into
1854 * the driver model; memory is zeroed.
1856 int __init musb_gadget_setup(struct musb *musb)
1860 /* REVISIT minor race: if (erroneously) setting up two
1861 * musb peripherals at the same time, only the bus lock
1865 musb->g.ops = &musb_gadget_operations;
1866 musb->g.is_dualspeed = 1;
1867 musb->g.speed = USB_SPEED_UNKNOWN;
1869 /* this "gadget" abstracts/virtualizes the controller */
1870 dev_set_name(&musb->g.dev, "gadget");
1871 musb->g.dev.parent = musb->controller;
1872 musb->g.dev.dma_mask = musb->controller->dma_mask;
1873 musb->g.dev.release = musb_gadget_release;
1874 musb->g.name = musb_driver_name;
1876 if (is_otg_enabled(musb))
1879 musb_g_init_endpoints(musb);
1881 musb->is_active = 0;
1882 musb_platform_try_idle(musb, 0);
1884 status = device_register(&musb->g.dev);
1886 put_device(&musb->g.dev);
1889 status = usb_add_gadget_udc(musb->controller, &musb->g);
1895 musb->g.dev.parent = NULL;
1896 device_unregister(&musb->g.dev);
1900 void musb_gadget_cleanup(struct musb *musb)
1902 usb_del_gadget_udc(&musb->g);
1903 if (musb->g.dev.parent)
1904 device_unregister(&musb->g.dev);
1908 * Register the gadget driver. Used by gadget drivers when
1909 * registering themselves with the controller.
1911 * -EINVAL something went wrong (not driver)
1912 * -EBUSY another gadget is already using the controller
1913 * -ENOMEM no memory to perform the operation
1915 * @param driver the gadget driver
1916 * @return <0 if error, 0 if everything is fine
1918 static int musb_gadget_start(struct usb_gadget *g,
1919 struct usb_gadget_driver *driver)
1921 struct musb *musb = gadget_to_musb(g);
1922 unsigned long flags;
1923 int retval = -EINVAL;
1925 if (driver->speed < USB_SPEED_HIGH)
1928 pm_runtime_get_sync(musb->controller);
1930 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1932 musb->softconnect = 0;
1933 musb->gadget_driver = driver;
1935 spin_lock_irqsave(&musb->lock, flags);
1936 musb->is_active = 1;
1938 otg_set_peripheral(musb->xceiv, &musb->g);
1939 musb->xceiv->state = OTG_STATE_B_IDLE;
1942 * FIXME this ignores the softconnect flag. Drivers are
1943 * allowed hold the peripheral inactive until for example
1944 * userspace hooks up printer hardware or DSP codecs, so
1945 * hosts only see fully functional devices.
1948 if (!is_otg_enabled(musb))
1951 spin_unlock_irqrestore(&musb->lock, flags);
1953 if (is_otg_enabled(musb)) {
1954 struct usb_hcd *hcd = musb_to_hcd(musb);
1956 dev_dbg(musb->controller, "OTG startup...\n");
1958 /* REVISIT: funcall to other code, which also
1959 * handles power budgeting ... this way also
1960 * ensures HdrcStart is indirectly called.
1962 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1964 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1968 if (musb->xceiv->last_event == USB_EVENT_ID)
1969 musb_platform_set_vbus(musb, 1);
1971 hcd->self.uses_pio_for_control = 1;
1973 if (musb->xceiv->last_event == USB_EVENT_NONE)
1974 pm_runtime_put(musb->controller);
1979 if (!is_otg_enabled(musb))
1985 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1988 struct musb_hw_ep *hw_ep;
1990 /* don't disconnect if it's not connected */
1991 if (musb->g.speed == USB_SPEED_UNKNOWN)
1994 musb->g.speed = USB_SPEED_UNKNOWN;
1996 /* deactivate the hardware */
1997 if (musb->softconnect) {
1998 musb->softconnect = 0;
1999 musb_pullup(musb, 0);
2003 /* killing any outstanding requests will quiesce the driver;
2004 * then report disconnect
2007 for (i = 0, hw_ep = musb->endpoints;
2008 i < musb->nr_endpoints;
2010 musb_ep_select(musb->mregs, i);
2011 if (hw_ep->is_shared_fifo /* || !epnum */) {
2012 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2014 if (hw_ep->max_packet_sz_tx)
2015 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2016 if (hw_ep->max_packet_sz_rx)
2017 nuke(&hw_ep->ep_out, -ESHUTDOWN);
2024 * Unregister the gadget driver. Used by gadget drivers when
2025 * unregistering themselves from the controller.
2027 * @param driver the gadget driver to unregister
2029 static int musb_gadget_stop(struct usb_gadget *g,
2030 struct usb_gadget_driver *driver)
2032 struct musb *musb = gadget_to_musb(g);
2033 unsigned long flags;
2035 if (musb->xceiv->last_event == USB_EVENT_NONE)
2036 pm_runtime_get_sync(musb->controller);
2039 * REVISIT always use otg_set_peripheral() here too;
2040 * this needs to shut down the OTG engine.
2043 spin_lock_irqsave(&musb->lock, flags);
2045 musb_hnp_stop(musb);
2047 (void) musb_gadget_vbus_draw(&musb->g, 0);
2049 musb->xceiv->state = OTG_STATE_UNDEFINED;
2050 stop_activity(musb, driver);
2051 otg_set_peripheral(musb->xceiv, NULL);
2053 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2055 musb->is_active = 0;
2056 musb->gadget_driver = NULL;
2057 musb_platform_try_idle(musb, 0);
2058 spin_unlock_irqrestore(&musb->lock, flags);
2060 if (is_otg_enabled(musb)) {
2061 usb_remove_hcd(musb_to_hcd(musb));
2062 /* FIXME we need to be able to register another
2063 * gadget driver here and have everything work;
2064 * that currently misbehaves.
2068 if (!is_otg_enabled(musb))
2071 pm_runtime_put(musb->controller);
2076 /* ----------------------------------------------------------------------- */
2078 /* lifecycle operations called through plat_uds.c */
2080 void musb_g_resume(struct musb *musb)
2082 musb->is_suspended = 0;
2083 switch (musb->xceiv->state) {
2084 case OTG_STATE_B_IDLE:
2086 case OTG_STATE_B_WAIT_ACON:
2087 case OTG_STATE_B_PERIPHERAL:
2088 musb->is_active = 1;
2089 if (musb->gadget_driver && musb->gadget_driver->resume) {
2090 spin_unlock(&musb->lock);
2091 musb->gadget_driver->resume(&musb->g);
2092 spin_lock(&musb->lock);
2096 WARNING("unhandled RESUME transition (%s)\n",
2097 otg_state_string(musb->xceiv->state));
2101 /* called when SOF packets stop for 3+ msec */
2102 void musb_g_suspend(struct musb *musb)
2106 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2107 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2109 switch (musb->xceiv->state) {
2110 case OTG_STATE_B_IDLE:
2111 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2112 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2114 case OTG_STATE_B_PERIPHERAL:
2115 musb->is_suspended = 1;
2116 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2117 spin_unlock(&musb->lock);
2118 musb->gadget_driver->suspend(&musb->g);
2119 spin_lock(&musb->lock);
2123 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2124 * A_PERIPHERAL may need care too
2126 WARNING("unhandled SUSPEND transition (%s)\n",
2127 otg_state_string(musb->xceiv->state));
2131 /* Called during SRP */
2132 void musb_g_wakeup(struct musb *musb)
2134 musb_gadget_wakeup(&musb->g);
2137 /* called when VBUS drops below session threshold, and in other cases */
2138 void musb_g_disconnect(struct musb *musb)
2140 void __iomem *mregs = musb->mregs;
2141 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2143 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2146 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2148 /* don't draw vbus until new b-default session */
2149 (void) musb_gadget_vbus_draw(&musb->g, 0);
2151 musb->g.speed = USB_SPEED_UNKNOWN;
2152 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2153 spin_unlock(&musb->lock);
2154 musb->gadget_driver->disconnect(&musb->g);
2155 spin_lock(&musb->lock);
2158 switch (musb->xceiv->state) {
2160 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2161 otg_state_string(musb->xceiv->state));
2162 musb->xceiv->state = OTG_STATE_A_IDLE;
2163 MUSB_HST_MODE(musb);
2165 case OTG_STATE_A_PERIPHERAL:
2166 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2167 MUSB_HST_MODE(musb);
2169 case OTG_STATE_B_WAIT_ACON:
2170 case OTG_STATE_B_HOST:
2171 case OTG_STATE_B_PERIPHERAL:
2172 case OTG_STATE_B_IDLE:
2173 musb->xceiv->state = OTG_STATE_B_IDLE;
2175 case OTG_STATE_B_SRP_INIT:
2179 musb->is_active = 0;
2182 void musb_g_reset(struct musb *musb)
2183 __releases(musb->lock)
2184 __acquires(musb->lock)
2186 void __iomem *mbase = musb->mregs;
2187 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2190 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2191 (devctl & MUSB_DEVCTL_BDEVICE)
2192 ? "B-Device" : "A-Device",
2193 musb_readb(mbase, MUSB_FADDR),
2195 ? musb->gadget_driver->driver.name
2199 /* report disconnect, if we didn't already (flushing EP state) */
2200 if (musb->g.speed != USB_SPEED_UNKNOWN)
2201 musb_g_disconnect(musb);
2204 else if (devctl & MUSB_DEVCTL_HR)
2205 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2208 /* what speed did we negotiate? */
2209 power = musb_readb(mbase, MUSB_POWER);
2210 musb->g.speed = (power & MUSB_POWER_HSMODE)
2211 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2213 /* start in USB_STATE_DEFAULT */
2214 musb->is_active = 1;
2215 musb->is_suspended = 0;
2216 MUSB_DEV_MODE(musb);
2218 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2220 musb->may_wakeup = 0;
2221 musb->g.b_hnp_enable = 0;
2222 musb->g.a_alt_hnp_support = 0;
2223 musb->g.a_hnp_support = 0;
2225 /* Normal reset, as B-Device;
2226 * or else after HNP, as A-Device
2228 if (devctl & MUSB_DEVCTL_BDEVICE) {
2229 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2230 musb->g.is_a_peripheral = 0;
2231 } else if (is_otg_enabled(musb)) {
2232 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2233 musb->g.is_a_peripheral = 1;
2237 /* start with default limits on VBUS power draw */
2238 (void) musb_gadget_vbus_draw(&musb->g,
2239 is_otg_enabled(musb) ? 8 : 100);