2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
125 #define MUSB_VERSION "6.0"
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
138 /*-------------------------------------------------------------------------*/
140 static inline struct musb *dev_to_musb(struct device *dev)
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
146 return dev_get_drvdata(dev);
150 /*-------------------------------------------------------------------------*/
152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
155 * Load an endpoint's FIFO
157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
159 void __iomem *fifo = hw_ep->fifo;
163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 'T', hw_ep->epnum, fifo, len, src);
166 /* we can't assume unaligned reads work */
167 if (likely((0x01 & (unsigned long) src) == 0)) {
170 /* best case is 32bit-aligned source address */
171 if ((0x02 & (unsigned long) src) == 0) {
173 writesl(fifo, src + index, len >> 2);
174 index += len & ~0x03;
177 musb_writew(fifo, 0, *(u16 *)&src[index]);
182 writesw(fifo, src + index, len >> 1);
183 index += len & ~0x01;
187 musb_writeb(fifo, 0, src[index]);
190 writesb(fifo, src, len);
195 * Unload an endpoint's FIFO
197 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
199 void __iomem *fifo = hw_ep->fifo;
201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 'R', hw_ep->epnum, fifo, len, dst);
204 /* we can't assume unaligned writes work */
205 if (likely((0x01 & (unsigned long) dst) == 0)) {
208 /* best case is 32bit-aligned destination address */
209 if ((0x02 & (unsigned long) dst) == 0) {
211 readsl(fifo, dst, len >> 2);
215 *(u16 *)&dst[index] = musb_readw(fifo, 0);
220 readsw(fifo, dst, len >> 1);
225 dst[index] = musb_readb(fifo, 0);
228 readsb(fifo, dst, len);
232 #endif /* normal PIO */
235 /*-------------------------------------------------------------------------*/
237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
238 static const u8 musb_test_packet[53] = {
239 /* implicit SYNC then DATA0 to start */
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 /* JJJJJJJKKKKKKK x8 */
248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 /* JKKKKKKK x10, JK */
252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
254 /* implicit CRC16 then EOP to end */
257 void musb_load_testpacket(struct musb *musb)
259 void __iomem *regs = musb->endpoints[0].regs;
261 musb_ep_select(musb->mregs, 0);
262 musb_write_fifo(musb->control_ep,
263 sizeof(musb_test_packet), musb_test_packet);
264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
267 /*-------------------------------------------------------------------------*/
269 const char *otg_state_string(struct musb *musb)
271 switch (musb->xceiv->state) {
272 case OTG_STATE_A_IDLE: return "a_idle";
273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
275 case OTG_STATE_A_HOST: return "a_host";
276 case OTG_STATE_A_SUSPEND: return "a_suspend";
277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
280 case OTG_STATE_B_IDLE: return "b_idle";
281 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
284 case OTG_STATE_B_HOST: return "b_host";
285 default: return "UNDEFINED";
289 #ifdef CONFIG_USB_MUSB_OTG
292 * Handles OTG hnp timeouts, such as b_ase0_brst
294 void musb_otg_timer_func(unsigned long data)
296 struct musb *musb = (struct musb *)data;
299 spin_lock_irqsave(&musb->lock, flags);
300 switch (musb->xceiv->state) {
301 case OTG_STATE_B_WAIT_ACON:
302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 musb_g_disconnect(musb);
304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
307 case OTG_STATE_A_SUSPEND:
308 case OTG_STATE_A_WAIT_BCON:
309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
310 musb_set_vbus(musb, 0);
311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
316 musb->ignore_disconnect = 0;
317 spin_unlock_irqrestore(&musb->lock, flags);
321 * Stops the HNP transition. Caller must take care of locking.
323 void musb_hnp_stop(struct musb *musb)
325 struct usb_hcd *hcd = musb_to_hcd(musb);
326 void __iomem *mbase = musb->mregs;
329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
331 switch (musb->xceiv->state) {
332 case OTG_STATE_A_PERIPHERAL:
333 musb_g_disconnect(musb);
334 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
336 case OTG_STATE_B_HOST:
337 DBG(1, "HNP: Disabling HR\n");
338 hcd->self.is_b_host = 0;
339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
341 reg = musb_readb(mbase, MUSB_POWER);
342 reg |= MUSB_POWER_SUSPENDM;
343 musb_writeb(mbase, MUSB_POWER, reg);
344 /* REVISIT: Start SESSION_REQUEST here? */
347 DBG(1, "HNP: Stopping in unknown state %s\n",
348 otg_state_string(musb));
352 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 * which cause occasional OPT A "Did not receive reset after connect"
356 musb->port1_status &=
357 ~(1 << USB_PORT_FEAT_C_CONNECTION);
363 * Interrupt Service Routine to record USB "global" interrupts.
364 * Since these do not happen often and signify things of
365 * paramount importance, it seems OK to check them individually;
366 * the order of the tests is specified in the manual
368 * @param musb instance pointer
369 * @param int_usb register contents
374 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
378 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
381 irqreturn_t handled = IRQ_NONE;
383 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
386 /* in host mode, the peripheral may issue remote wakeup.
387 * in peripheral mode, the host may resume the link.
388 * spurious RESUME irqs happen too, paired with SUSPEND.
390 if (int_usb & MUSB_INTR_RESUME) {
391 handled = IRQ_HANDLED;
392 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
394 if (devctl & MUSB_DEVCTL_HM) {
395 #ifdef CONFIG_USB_MUSB_HDRC_HCD
396 void __iomem *mbase = musb->mregs;
398 switch (musb->xceiv->state) {
399 case OTG_STATE_A_SUSPEND:
400 /* remote wakeup? later, GetPortStatus
401 * will stop RESUME signaling
404 if (power & MUSB_POWER_SUSPENDM) {
406 musb->int_usb &= ~MUSB_INTR_SUSPEND;
407 DBG(2, "Spurious SUSPENDM\n");
411 power &= ~MUSB_POWER_SUSPENDM;
412 musb_writeb(mbase, MUSB_POWER,
413 power | MUSB_POWER_RESUME);
415 musb->port1_status |=
416 (USB_PORT_STAT_C_SUSPEND << 16)
417 | MUSB_PORT_STAT_RESUME;
418 musb->rh_timer = jiffies
419 + msecs_to_jiffies(20);
421 musb->xceiv->state = OTG_STATE_A_HOST;
423 usb_hcd_resume_root_hub(musb_to_hcd(musb));
425 case OTG_STATE_B_WAIT_ACON:
426 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
431 WARNING("bogus %s RESUME (%s)\n",
433 otg_state_string(musb));
437 switch (musb->xceiv->state) {
438 #ifdef CONFIG_USB_MUSB_HDRC_HCD
439 case OTG_STATE_A_SUSPEND:
440 /* possibly DISCONNECT is upcoming */
441 musb->xceiv->state = OTG_STATE_A_HOST;
442 usb_hcd_resume_root_hub(musb_to_hcd(musb));
445 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
446 case OTG_STATE_B_WAIT_ACON:
447 case OTG_STATE_B_PERIPHERAL:
448 /* disconnect while suspended? we may
449 * not get a disconnect irq...
451 if ((devctl & MUSB_DEVCTL_VBUS)
452 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
454 musb->int_usb |= MUSB_INTR_DISCONNECT;
455 musb->int_usb &= ~MUSB_INTR_SUSPEND;
460 case OTG_STATE_B_IDLE:
461 musb->int_usb &= ~MUSB_INTR_SUSPEND;
465 WARNING("bogus %s RESUME (%s)\n",
467 otg_state_string(musb));
472 #ifdef CONFIG_USB_MUSB_HDRC_HCD
473 /* see manual for the order of the tests */
474 if (int_usb & MUSB_INTR_SESSREQ) {
475 void __iomem *mbase = musb->mregs;
477 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
479 /* IRQ arrives from ID pin sense or (later, if VBUS power
480 * is removed) SRP. responses are time critical:
481 * - turn on VBUS (with silicon-specific mechanism)
482 * - go through A_WAIT_VRISE
483 * - ... to A_WAIT_BCON.
484 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
486 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
487 musb->ep0_stage = MUSB_EP0_START;
488 musb->xceiv->state = OTG_STATE_A_IDLE;
490 musb_set_vbus(musb, 1);
492 handled = IRQ_HANDLED;
495 if (int_usb & MUSB_INTR_VBUSERROR) {
498 /* During connection as an A-Device, we may see a short
499 * current spikes causing voltage drop, because of cable
500 * and peripheral capacitance combined with vbus draw.
501 * (So: less common with truly self-powered devices, where
502 * vbus doesn't act like a power supply.)
504 * Such spikes are short; usually less than ~500 usec, max
505 * of ~2 msec. That is, they're not sustained overcurrent
506 * errors, though they're reported using VBUSERROR irqs.
508 * Workarounds: (a) hardware: use self powered devices.
509 * (b) software: ignore non-repeated VBUS errors.
511 * REVISIT: do delays from lots of DEBUG_KERNEL checks
512 * make trouble here, keeping VBUS < 4.4V ?
514 switch (musb->xceiv->state) {
515 case OTG_STATE_A_HOST:
516 /* recovery is dicey once we've gotten past the
517 * initial stages of enumeration, but if VBUS
518 * stayed ok at the other end of the link, and
519 * another reset is due (at least for high speed,
520 * to redo the chirp etc), it might work OK...
522 case OTG_STATE_A_WAIT_BCON:
523 case OTG_STATE_A_WAIT_VRISE:
524 if (musb->vbuserr_retry) {
525 void __iomem *mbase = musb->mregs;
527 musb->vbuserr_retry--;
529 devctl |= MUSB_DEVCTL_SESSION;
530 musb_writeb(mbase, MUSB_DEVCTL, devctl);
532 musb->port1_status |=
533 (1 << USB_PORT_FEAT_OVER_CURRENT)
534 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
541 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
542 otg_state_string(musb),
545 switch (devctl & MUSB_DEVCTL_VBUS) {
546 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
547 s = "<SessEnd"; break;
548 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
549 s = "<AValid"; break;
550 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
551 s = "<VBusValid"; break;
552 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
556 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
559 /* go through A_WAIT_VFALL then start a new session */
561 musb_set_vbus(musb, 0);
562 handled = IRQ_HANDLED;
566 if (int_usb & MUSB_INTR_SUSPEND) {
567 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
568 otg_state_string(musb), devctl, power);
569 handled = IRQ_HANDLED;
571 switch (musb->xceiv->state) {
572 #ifdef CONFIG_USB_MUSB_OTG
573 case OTG_STATE_A_PERIPHERAL:
574 /* We also come here if the cable is removed, since
575 * this silicon doesn't report ID-no-longer-grounded.
577 * We depend on T(a_wait_bcon) to shut us down, and
578 * hope users don't do anything dicey during this
579 * undesired detour through A_WAIT_BCON.
582 usb_hcd_resume_root_hub(musb_to_hcd(musb));
583 musb_root_disconnect(musb);
584 musb_platform_try_idle(musb, jiffies
585 + msecs_to_jiffies(musb->a_wait_bcon
586 ? : OTG_TIME_A_WAIT_BCON));
590 case OTG_STATE_B_IDLE:
591 if (!musb->is_active)
593 case OTG_STATE_B_PERIPHERAL:
594 musb_g_suspend(musb);
595 musb->is_active = is_otg_enabled(musb)
596 && musb->xceiv->gadget->b_hnp_enable;
597 if (musb->is_active) {
598 #ifdef CONFIG_USB_MUSB_OTG
599 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
600 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
601 mod_timer(&musb->otg_timer, jiffies
603 OTG_TIME_B_ASE0_BRST));
607 case OTG_STATE_A_WAIT_BCON:
608 if (musb->a_wait_bcon != 0)
609 musb_platform_try_idle(musb, jiffies
610 + msecs_to_jiffies(musb->a_wait_bcon));
612 case OTG_STATE_A_HOST:
613 musb->xceiv->state = OTG_STATE_A_SUSPEND;
614 musb->is_active = is_otg_enabled(musb)
615 && musb->xceiv->host->b_hnp_enable;
617 case OTG_STATE_B_HOST:
618 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
619 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
622 /* "should not happen" */
628 if (int_usb & MUSB_INTR_CONNECT) {
629 struct usb_hcd *hcd = musb_to_hcd(musb);
630 void __iomem *mbase = musb->mregs;
632 handled = IRQ_HANDLED;
634 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
636 musb->ep0_stage = MUSB_EP0_START;
638 #ifdef CONFIG_USB_MUSB_OTG
639 /* flush endpoints when transitioning from Device Mode */
640 if (is_peripheral_active(musb)) {
641 /* REVISIT HNP; just force disconnect */
643 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
644 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
645 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
647 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
648 |USB_PORT_STAT_HIGH_SPEED
649 |USB_PORT_STAT_ENABLE
651 musb->port1_status |= USB_PORT_STAT_CONNECTION
652 |(USB_PORT_STAT_C_CONNECTION << 16);
654 /* high vs full speed is just a guess until after reset */
655 if (devctl & MUSB_DEVCTL_LSDEV)
656 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
658 /* indicate new connection to OTG machine */
659 switch (musb->xceiv->state) {
660 case OTG_STATE_B_PERIPHERAL:
661 if (int_usb & MUSB_INTR_SUSPEND) {
662 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
663 int_usb &= ~MUSB_INTR_SUSPEND;
666 DBG(1, "CONNECT as b_peripheral???\n");
668 case OTG_STATE_B_WAIT_ACON:
669 DBG(1, "HNP: CONNECT, now b_host\n");
671 musb->xceiv->state = OTG_STATE_B_HOST;
672 hcd->self.is_b_host = 1;
673 musb->ignore_disconnect = 0;
674 del_timer(&musb->otg_timer);
677 if ((devctl & MUSB_DEVCTL_VBUS)
678 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
679 musb->xceiv->state = OTG_STATE_A_HOST;
680 hcd->self.is_b_host = 0;
685 /* poke the root hub */
688 usb_hcd_poll_rh_status(hcd);
690 usb_hcd_resume_root_hub(hcd);
692 DBG(1, "CONNECT (%s) devctl %02x\n",
693 otg_state_string(musb), devctl);
695 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
697 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
698 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
699 otg_state_string(musb),
700 MUSB_MODE(musb), devctl);
701 handled = IRQ_HANDLED;
703 switch (musb->xceiv->state) {
704 #ifdef CONFIG_USB_MUSB_HDRC_HCD
705 case OTG_STATE_A_HOST:
706 case OTG_STATE_A_SUSPEND:
707 usb_hcd_resume_root_hub(musb_to_hcd(musb));
708 musb_root_disconnect(musb);
709 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
710 musb_platform_try_idle(musb, jiffies
711 + msecs_to_jiffies(musb->a_wait_bcon));
714 #ifdef CONFIG_USB_MUSB_OTG
715 case OTG_STATE_B_HOST:
716 /* REVISIT this behaves for "real disconnect"
717 * cases; make sure the other transitions from
718 * from B_HOST act right too. The B_HOST code
719 * in hnp_stop() is currently not used...
721 musb_root_disconnect(musb);
722 musb_to_hcd(musb)->self.is_b_host = 0;
723 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
725 musb_g_disconnect(musb);
727 case OTG_STATE_A_PERIPHERAL:
729 musb_root_disconnect(musb);
731 case OTG_STATE_B_WAIT_ACON:
734 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
735 case OTG_STATE_B_PERIPHERAL:
736 case OTG_STATE_B_IDLE:
737 musb_g_disconnect(musb);
741 WARNING("unhandled DISCONNECT transition (%s)\n",
742 otg_state_string(musb));
747 /* mentor saves a bit: bus reset and babble share the same irq.
748 * only host sees babble; only peripheral sees bus reset.
750 if (int_usb & MUSB_INTR_RESET) {
751 handled = IRQ_HANDLED;
752 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
754 * Looks like non-HS BABBLE can be ignored, but
755 * HS BABBLE is an error condition. For HS the solution
756 * is to avoid babble in the first place and fix what
757 * caused BABBLE. When HS BABBLE happens we can only
760 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
761 DBG(1, "BABBLE devctl: %02x\n", devctl);
763 ERR("Stopping host session -- babble\n");
764 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
766 } else if (is_peripheral_capable()) {
767 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
768 switch (musb->xceiv->state) {
769 #ifdef CONFIG_USB_OTG
770 case OTG_STATE_A_SUSPEND:
771 /* We need to ignore disconnect on suspend
772 * otherwise tusb 2.0 won't reconnect after a
773 * power cycle, which breaks otg compliance.
775 musb->ignore_disconnect = 1;
778 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
779 /* never use invalid T(a_wait_bcon) */
780 DBG(1, "HNP: in %s, %d msec timeout\n",
781 otg_state_string(musb),
783 mod_timer(&musb->otg_timer, jiffies
784 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
786 case OTG_STATE_A_PERIPHERAL:
787 musb->ignore_disconnect = 0;
788 del_timer(&musb->otg_timer);
791 case OTG_STATE_B_WAIT_ACON:
792 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
793 otg_state_string(musb));
794 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
798 case OTG_STATE_B_IDLE:
799 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
801 case OTG_STATE_B_PERIPHERAL:
805 DBG(1, "Unhandled BUS RESET as %s\n",
806 otg_state_string(musb));
812 /* REVISIT ... this would be for multiplexing periodic endpoints, or
813 * supporting transfer phasing to prevent exceeding ISO bandwidth
814 * limits of a given frame or microframe.
816 * It's not needed for peripheral side, which dedicates endpoints;
817 * though it _might_ use SOF irqs for other purposes.
819 * And it's not currently needed for host side, which also dedicates
820 * endpoints, relies on TX/RX interval registers, and isn't claimed
821 * to support ISO transfers yet.
823 if (int_usb & MUSB_INTR_SOF) {
824 void __iomem *mbase = musb->mregs;
825 struct musb_hw_ep *ep;
829 DBG(6, "START_OF_FRAME\n");
830 handled = IRQ_HANDLED;
832 /* start any periodic Tx transfers waiting for current frame */
833 frame = musb_readw(mbase, MUSB_FRAME);
834 ep = musb->endpoints;
835 for (epnum = 1; (epnum < musb->nr_endpoints)
836 && (musb->epmask >= (1 << epnum));
839 * FIXME handle framecounter wraps (12 bits)
840 * eliminate duplicated StartUrb logic
842 if (ep->dwWaitFrame >= frame) {
844 pr_debug("SOF --> periodic TX%s on %d\n",
845 ep->tx_channel ? " DMA" : "",
848 musb_h_tx_start(musb, epnum);
850 cppi_hostdma_start(musb, epnum);
852 } /* end of for loop */
856 schedule_work(&musb->irq_work);
861 /*-------------------------------------------------------------------------*/
864 * Program the HDRC to start (enable interrupts, dma, etc.).
866 void musb_start(struct musb *musb)
868 void __iomem *regs = musb->mregs;
869 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
871 DBG(2, "<== devctl %02x\n", devctl);
873 /* Set INT enable registers, enable interrupts */
874 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
875 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
876 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
878 musb_writeb(regs, MUSB_TESTMODE, 0);
880 /* put into basic highspeed mode and start session */
881 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
882 | MUSB_POWER_SOFTCONN
884 /* ENSUSPEND wedges tusb */
885 /* | MUSB_POWER_ENSUSPEND */
889 devctl = musb_readb(regs, MUSB_DEVCTL);
890 devctl &= ~MUSB_DEVCTL_SESSION;
892 if (is_otg_enabled(musb)) {
893 /* session started after:
894 * (a) ID-grounded irq, host mode;
895 * (b) vbus present/connect IRQ, peripheral mode;
896 * (c) peripheral initiates, using SRP
898 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
901 devctl |= MUSB_DEVCTL_SESSION;
903 } else if (is_host_enabled(musb)) {
904 /* assume ID pin is hard-wired to ground */
905 devctl |= MUSB_DEVCTL_SESSION;
907 } else /* peripheral is enabled */ {
908 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
911 musb_platform_enable(musb);
912 musb_writeb(regs, MUSB_DEVCTL, devctl);
916 static void musb_generic_disable(struct musb *musb)
918 void __iomem *mbase = musb->mregs;
921 /* disable interrupts */
922 musb_writeb(mbase, MUSB_INTRUSBE, 0);
923 musb_writew(mbase, MUSB_INTRTXE, 0);
924 musb_writew(mbase, MUSB_INTRRXE, 0);
927 musb_writeb(mbase, MUSB_DEVCTL, 0);
929 /* flush pending interrupts */
930 temp = musb_readb(mbase, MUSB_INTRUSB);
931 temp = musb_readw(mbase, MUSB_INTRTX);
932 temp = musb_readw(mbase, MUSB_INTRRX);
937 * Make the HDRC stop (disable interrupts, etc.);
938 * reversible by musb_start
939 * called on gadget driver unregister
940 * with controller locked, irqs blocked
941 * acts as a NOP unless some role activated the hardware
943 void musb_stop(struct musb *musb)
945 /* stop IRQs, timers, ... */
946 musb_platform_disable(musb);
947 musb_generic_disable(musb);
948 DBG(3, "HDRC disabled\n");
951 * - mark host and/or peripheral drivers unusable/inactive
952 * - disable DMA (and enable it in HdrcStart)
953 * - make sure we can musb_start() after musb_stop(); with
954 * OTG mode, gadget driver module rmmod/modprobe cycles that
957 musb_platform_try_idle(musb, 0);
960 static void musb_shutdown(struct platform_device *pdev)
962 struct musb *musb = dev_to_musb(&pdev->dev);
965 spin_lock_irqsave(&musb->lock, flags);
966 musb_platform_disable(musb);
967 musb_generic_disable(musb);
969 clk_put(musb->clock);
970 spin_unlock_irqrestore(&musb->lock, flags);
972 /* FIXME power down */
976 /*-------------------------------------------------------------------------*/
979 * The silicon either has hard-wired endpoint configurations, or else
980 * "dynamic fifo" sizing. The driver has support for both, though at this
981 * writing only the dynamic sizing is very well tested. Since we switched
982 * away from compile-time hardware parameters, we can no longer rely on
983 * dead code elimination to leave only the relevant one in the object file.
985 * We don't currently use dynamic fifo setup capability to do anything
986 * more than selecting one of a bunch of predefined configurations.
988 #if defined(CONFIG_USB_TUSB6010) || \
989 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
990 static ushort __initdata fifo_mode = 4;
992 static ushort __initdata fifo_mode = 2;
995 /* "modprobe ... fifo_mode=1" etc */
996 module_param(fifo_mode, ushort, 0);
997 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1000 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1001 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1005 enum fifo_style style;
1011 * tables defining fifo_mode values. define more if you like.
1012 * for host side, make sure both halves of ep1 are set up.
1015 /* mode 0 - fits in 2KB */
1016 static struct fifo_cfg __initdata mode_0_cfg[] = {
1017 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1018 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1019 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1020 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1021 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1024 /* mode 1 - fits in 4KB */
1025 static struct fifo_cfg __initdata mode_1_cfg[] = {
1026 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1027 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1028 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1029 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1030 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1033 /* mode 2 - fits in 4KB */
1034 static struct fifo_cfg __initdata mode_2_cfg[] = {
1035 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1036 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1037 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1038 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1039 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1040 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1043 /* mode 3 - fits in 4KB */
1044 static struct fifo_cfg __initdata mode_3_cfg[] = {
1045 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1046 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1047 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1048 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1049 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1050 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1053 /* mode 4 - fits in 16KB */
1054 static struct fifo_cfg __initdata mode_4_cfg[] = {
1055 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1056 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1057 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1058 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1059 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1064 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1065 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1066 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1067 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1068 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1069 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1070 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1071 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1072 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1073 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1074 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1075 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1076 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1077 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1078 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1079 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1080 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1081 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1084 /* mode 5 - fits in 8KB */
1085 static struct fifo_cfg __initdata mode_5_cfg[] = {
1086 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1087 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1088 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1095 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1096 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1097 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1098 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1099 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1100 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1101 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1102 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1103 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1104 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1105 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1106 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1107 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1108 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1109 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1110 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1111 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1112 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1116 * configure a fifo; for non-shared endpoints, this may be called
1117 * once for a tx fifo and once for an rx fifo.
1119 * returns negative errno or offset for next fifo.
1122 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1123 const struct fifo_cfg *cfg, u16 offset)
1125 void __iomem *mbase = musb->mregs;
1127 u16 maxpacket = cfg->maxpacket;
1128 u16 c_off = offset >> 3;
1131 /* expect hw_ep has already been zero-initialized */
1133 size = ffs(max(maxpacket, (u16) 8)) - 1;
1134 maxpacket = 1 << size;
1137 if (cfg->mode == BUF_DOUBLE) {
1138 if ((offset + (maxpacket << 1)) >
1139 (1 << (musb->config->ram_bits + 2)))
1141 c_size |= MUSB_FIFOSZ_DPB;
1143 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1147 /* configure the FIFO */
1148 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1150 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1151 /* EP0 reserved endpoint for control, bidirectional;
1152 * EP1 reserved for bulk, two unidirection halves.
1154 if (hw_ep->epnum == 1)
1155 musb->bulk_ep = hw_ep;
1156 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1158 switch (cfg->style) {
1160 musb_write_txfifosz(mbase, c_size);
1161 musb_write_txfifoadd(mbase, c_off);
1162 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1163 hw_ep->max_packet_sz_tx = maxpacket;
1166 musb_write_rxfifosz(mbase, c_size);
1167 musb_write_rxfifoadd(mbase, c_off);
1168 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1169 hw_ep->max_packet_sz_rx = maxpacket;
1172 musb_write_txfifosz(mbase, c_size);
1173 musb_write_txfifoadd(mbase, c_off);
1174 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1175 hw_ep->max_packet_sz_rx = maxpacket;
1177 musb_write_rxfifosz(mbase, c_size);
1178 musb_write_rxfifoadd(mbase, c_off);
1179 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1180 hw_ep->max_packet_sz_tx = maxpacket;
1182 hw_ep->is_shared_fifo = true;
1186 /* NOTE rx and tx endpoint irqs aren't managed separately,
1187 * which happens to be ok
1189 musb->epmask |= (1 << hw_ep->epnum);
1191 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1194 static struct fifo_cfg __initdata ep0_cfg = {
1195 .style = FIFO_RXTX, .maxpacket = 64,
1198 static int __init ep_config_from_table(struct musb *musb)
1200 const struct fifo_cfg *cfg;
1203 struct musb_hw_ep *hw_ep = musb->endpoints;
1205 switch (fifo_mode) {
1211 n = ARRAY_SIZE(mode_0_cfg);
1215 n = ARRAY_SIZE(mode_1_cfg);
1219 n = ARRAY_SIZE(mode_2_cfg);
1223 n = ARRAY_SIZE(mode_3_cfg);
1227 n = ARRAY_SIZE(mode_4_cfg);
1231 n = ARRAY_SIZE(mode_5_cfg);
1235 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1236 musb_driver_name, fifo_mode);
1239 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1240 /* assert(offset > 0) */
1242 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1243 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1246 for (i = 0; i < n; i++) {
1247 u8 epn = cfg->hw_ep_num;
1249 if (epn >= musb->config->num_eps) {
1250 pr_debug("%s: invalid ep %d\n",
1251 musb_driver_name, epn);
1254 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1256 pr_debug("%s: mem overrun, ep %d\n",
1257 musb_driver_name, epn);
1261 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1264 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1266 n + 1, musb->config->num_eps * 2 - 1,
1267 offset, (1 << (musb->config->ram_bits + 2)));
1269 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1270 if (!musb->bulk_ep) {
1271 pr_debug("%s: missing bulk\n", musb_driver_name);
1281 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1282 * @param musb the controller
1284 static int __init ep_config_from_hw(struct musb *musb)
1287 struct musb_hw_ep *hw_ep;
1288 void *mbase = musb->mregs;
1291 DBG(2, "<== static silicon ep config\n");
1293 /* FIXME pick up ep0 maxpacket size */
1295 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1296 musb_ep_select(mbase, epnum);
1297 hw_ep = musb->endpoints + epnum;
1299 ret = musb_read_fifosize(musb, hw_ep, epnum);
1303 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1305 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1306 /* pick an RX/TX endpoint for bulk */
1307 if (hw_ep->max_packet_sz_tx < 512
1308 || hw_ep->max_packet_sz_rx < 512)
1311 /* REVISIT: this algorithm is lazy, we should at least
1312 * try to pick a double buffered endpoint.
1316 musb->bulk_ep = hw_ep;
1320 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1321 if (!musb->bulk_ep) {
1322 pr_debug("%s: missing bulk\n", musb_driver_name);
1330 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1332 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1333 * configure endpoints, or take their config from silicon
1335 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1339 char aInfo[90], aRevision[32], aDate[12];
1340 void __iomem *mbase = musb->mregs;
1344 /* log core options (read using indexed model) */
1345 reg = musb_read_configdata(mbase);
1347 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1348 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1349 strcat(aInfo, ", dyn FIFOs");
1350 musb->dyn_fifo = true;
1352 if (reg & MUSB_CONFIGDATA_MPRXE) {
1353 strcat(aInfo, ", bulk combine");
1354 musb->bulk_combine = true;
1356 if (reg & MUSB_CONFIGDATA_MPTXE) {
1357 strcat(aInfo, ", bulk split");
1358 musb->bulk_split = true;
1360 if (reg & MUSB_CONFIGDATA_HBRXE) {
1361 strcat(aInfo, ", HB-ISO Rx");
1362 musb->hb_iso_rx = true;
1364 if (reg & MUSB_CONFIGDATA_HBTXE) {
1365 strcat(aInfo, ", HB-ISO Tx");
1366 musb->hb_iso_tx = true;
1368 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1369 strcat(aInfo, ", SoftConn");
1371 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1372 musb_driver_name, reg, aInfo);
1375 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1376 musb->is_multipoint = 1;
1379 musb->is_multipoint = 0;
1381 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1382 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1384 "%s: kernel must blacklist external hubs\n",
1390 /* log release info */
1391 musb->hwvers = musb_read_hwvers(mbase);
1392 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1393 MUSB_HWVERS_MINOR(musb->hwvers),
1394 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1395 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1396 musb_driver_name, type, aRevision, aDate);
1399 musb_configure_ep0(musb);
1401 /* discover endpoint configuration */
1402 musb->nr_endpoints = 1;
1406 status = ep_config_from_table(musb);
1408 status = ep_config_from_hw(musb);
1413 /* finish init, and print endpoint config */
1414 for (i = 0; i < musb->nr_endpoints; i++) {
1415 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1417 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1418 #ifdef CONFIG_USB_TUSB6010
1419 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1420 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1421 hw_ep->fifo_sync_va =
1422 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1425 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1427 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1430 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1431 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1432 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1433 hw_ep->rx_reinit = 1;
1434 hw_ep->tx_reinit = 1;
1437 if (hw_ep->max_packet_sz_tx) {
1439 "%s: hw_ep %d%s, %smax %d\n",
1440 musb_driver_name, i,
1441 hw_ep->is_shared_fifo ? "shared" : "tx",
1442 hw_ep->tx_double_buffered
1443 ? "doublebuffer, " : "",
1444 hw_ep->max_packet_sz_tx);
1446 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1448 "%s: hw_ep %d%s, %smax %d\n",
1449 musb_driver_name, i,
1451 hw_ep->rx_double_buffered
1452 ? "doublebuffer, " : "",
1453 hw_ep->max_packet_sz_rx);
1455 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1456 DBG(1, "hw_ep %d not configured\n", i);
1462 /*-------------------------------------------------------------------------*/
1464 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1466 static irqreturn_t generic_interrupt(int irq, void *__hci)
1468 unsigned long flags;
1469 irqreturn_t retval = IRQ_NONE;
1470 struct musb *musb = __hci;
1472 spin_lock_irqsave(&musb->lock, flags);
1474 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1475 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1476 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1478 if (musb->int_usb || musb->int_tx || musb->int_rx)
1479 retval = musb_interrupt(musb);
1481 spin_unlock_irqrestore(&musb->lock, flags);
1487 #define generic_interrupt NULL
1491 * handle all the irqs defined by the HDRC core. for now we expect: other
1492 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1493 * will be assigned, and the irq will already have been acked.
1495 * called in irq context with spinlock held, irqs blocked
1497 irqreturn_t musb_interrupt(struct musb *musb)
1499 irqreturn_t retval = IRQ_NONE;
1504 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1505 power = musb_readb(musb->mregs, MUSB_POWER);
1507 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1508 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1509 musb->int_usb, musb->int_tx, musb->int_rx);
1511 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1512 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1513 if (!musb->gadget_driver) {
1514 DBG(5, "No gadget driver loaded\n");
1519 /* the core can interrupt us for multiple reasons; docs have
1520 * a generic interrupt flowchart to follow
1522 if (musb->int_usb & STAGE0_MASK)
1523 retval |= musb_stage0_irq(musb, musb->int_usb,
1526 /* "stage 1" is handling endpoint irqs */
1528 /* handle endpoint 0 first */
1529 if (musb->int_tx & 1) {
1530 if (devctl & MUSB_DEVCTL_HM)
1531 retval |= musb_h_ep0_irq(musb);
1533 retval |= musb_g_ep0_irq(musb);
1536 /* RX on endpoints 1-15 */
1537 reg = musb->int_rx >> 1;
1541 /* musb_ep_select(musb->mregs, ep_num); */
1542 /* REVISIT just retval = ep->rx_irq(...) */
1543 retval = IRQ_HANDLED;
1544 if (devctl & MUSB_DEVCTL_HM) {
1545 if (is_host_capable())
1546 musb_host_rx(musb, ep_num);
1548 if (is_peripheral_capable())
1549 musb_g_rx(musb, ep_num);
1557 /* TX on endpoints 1-15 */
1558 reg = musb->int_tx >> 1;
1562 /* musb_ep_select(musb->mregs, ep_num); */
1563 /* REVISIT just retval |= ep->tx_irq(...) */
1564 retval = IRQ_HANDLED;
1565 if (devctl & MUSB_DEVCTL_HM) {
1566 if (is_host_capable())
1567 musb_host_tx(musb, ep_num);
1569 if (is_peripheral_capable())
1570 musb_g_tx(musb, ep_num);
1581 #ifndef CONFIG_MUSB_PIO_ONLY
1582 static int __initdata use_dma = 1;
1584 /* "modprobe ... use_dma=0" etc */
1585 module_param(use_dma, bool, 0);
1586 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1588 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1590 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1592 /* called with controller lock already held */
1595 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1596 if (!is_cppi_enabled()) {
1598 if (devctl & MUSB_DEVCTL_HM)
1599 musb_h_ep0_irq(musb);
1601 musb_g_ep0_irq(musb);
1605 /* endpoints 1..15 */
1607 if (devctl & MUSB_DEVCTL_HM) {
1608 if (is_host_capable())
1609 musb_host_tx(musb, epnum);
1611 if (is_peripheral_capable())
1612 musb_g_tx(musb, epnum);
1616 if (devctl & MUSB_DEVCTL_HM) {
1617 if (is_host_capable())
1618 musb_host_rx(musb, epnum);
1620 if (is_peripheral_capable())
1621 musb_g_rx(musb, epnum);
1631 /*-------------------------------------------------------------------------*/
1636 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1638 struct musb *musb = dev_to_musb(dev);
1639 unsigned long flags;
1642 spin_lock_irqsave(&musb->lock, flags);
1643 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1644 spin_unlock_irqrestore(&musb->lock, flags);
1650 musb_mode_store(struct device *dev, struct device_attribute *attr,
1651 const char *buf, size_t n)
1653 struct musb *musb = dev_to_musb(dev);
1654 unsigned long flags;
1657 spin_lock_irqsave(&musb->lock, flags);
1658 if (sysfs_streq(buf, "host"))
1659 status = musb_platform_set_mode(musb, MUSB_HOST);
1660 else if (sysfs_streq(buf, "peripheral"))
1661 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1662 else if (sysfs_streq(buf, "otg"))
1663 status = musb_platform_set_mode(musb, MUSB_OTG);
1666 spin_unlock_irqrestore(&musb->lock, flags);
1668 return (status == 0) ? n : status;
1670 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1673 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1674 const char *buf, size_t n)
1676 struct musb *musb = dev_to_musb(dev);
1677 unsigned long flags;
1680 if (sscanf(buf, "%lu", &val) < 1) {
1681 dev_err(dev, "Invalid VBUS timeout ms value\n");
1685 spin_lock_irqsave(&musb->lock, flags);
1686 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1687 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1688 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1689 musb->is_active = 0;
1690 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1691 spin_unlock_irqrestore(&musb->lock, flags);
1697 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1699 struct musb *musb = dev_to_musb(dev);
1700 unsigned long flags;
1704 spin_lock_irqsave(&musb->lock, flags);
1705 val = musb->a_wait_bcon;
1706 /* FIXME get_vbus_status() is normally #defined as false...
1707 * and is effectively TUSB-specific.
1709 vbus = musb_platform_get_vbus_status(musb);
1710 spin_unlock_irqrestore(&musb->lock, flags);
1712 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1713 vbus ? "on" : "off", val);
1715 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1717 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1719 /* Gadget drivers can't know that a host is connected so they might want
1720 * to start SRP, but users can. This allows userspace to trigger SRP.
1723 musb_srp_store(struct device *dev, struct device_attribute *attr,
1724 const char *buf, size_t n)
1726 struct musb *musb = dev_to_musb(dev);
1729 if (sscanf(buf, "%hu", &srp) != 1
1731 dev_err(dev, "SRP: Value must be 1\n");
1736 musb_g_wakeup(musb);
1740 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1742 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1744 static struct attribute *musb_attributes[] = {
1745 &dev_attr_mode.attr,
1746 &dev_attr_vbus.attr,
1747 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1753 static const struct attribute_group musb_attr_group = {
1754 .attrs = musb_attributes,
1759 /* Only used to provide driver mode change events */
1760 static void musb_irq_work(struct work_struct *data)
1762 struct musb *musb = container_of(data, struct musb, irq_work);
1763 static int old_state;
1765 if (musb->xceiv->state != old_state) {
1766 old_state = musb->xceiv->state;
1767 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1771 /* --------------------------------------------------------------------------
1775 static struct musb *__init
1776 allocate_instance(struct device *dev,
1777 struct musb_hdrc_config *config, void __iomem *mbase)
1780 struct musb_hw_ep *ep;
1782 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1783 struct usb_hcd *hcd;
1785 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1788 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1790 musb = hcd_to_musb(hcd);
1791 INIT_LIST_HEAD(&musb->control);
1792 INIT_LIST_HEAD(&musb->in_bulk);
1793 INIT_LIST_HEAD(&musb->out_bulk);
1795 hcd->uses_new_polling = 1;
1797 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1798 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1800 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1803 dev_set_drvdata(dev, musb);
1807 musb->mregs = mbase;
1808 musb->ctrl_base = mbase;
1809 musb->nIrq = -ENODEV;
1810 musb->config = config;
1811 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1812 for (epnum = 0, ep = musb->endpoints;
1813 epnum < musb->config->num_eps;
1819 musb->controller = dev;
1823 static void musb_free(struct musb *musb)
1825 /* this has multiple entry modes. it handles fault cleanup after
1826 * probe(), where things may be partially set up, as well as rmmod
1827 * cleanup after everything's been de-activated.
1831 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1834 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1835 musb_gadget_cleanup(musb);
1838 if (musb->nIrq >= 0) {
1840 disable_irq_wake(musb->nIrq);
1841 free_irq(musb->nIrq, musb);
1843 if (is_dma_capable() && musb->dma_controller) {
1844 struct dma_controller *c = musb->dma_controller;
1847 dma_controller_destroy(c);
1850 #ifdef CONFIG_USB_MUSB_OTG
1851 put_device(musb->xceiv->dev);
1854 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1855 usb_put_hcd(musb_to_hcd(musb));
1862 * Perform generic per-controller initialization.
1864 * @pDevice: the controller (already clocked, etc)
1866 * @mregs: virtual address of controller registers,
1867 * not yet corrected for platform-specific offsets
1870 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1874 struct musb_hdrc_platform_data *plat = dev->platform_data;
1876 /* The driver might handle more features than the board; OK.
1877 * Fail when the board needs a feature that's not enabled.
1880 dev_dbg(dev, "no platform_data?\n");
1885 switch (plat->mode) {
1887 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1892 case MUSB_PERIPHERAL:
1893 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1899 #ifdef CONFIG_USB_MUSB_OTG
1905 dev_err(dev, "incompatible Kconfig role setting\n");
1911 musb = allocate_instance(dev, plat->config, ctrl);
1917 spin_lock_init(&musb->lock);
1918 musb->board_mode = plat->mode;
1919 musb->board_set_power = plat->set_power;
1920 musb->set_clock = plat->set_clock;
1921 musb->min_power = plat->min_power;
1923 /* Clock usage is chip-specific ... functional clock (DaVinci,
1924 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1925 * code does is make sure a clock handle is available; platform
1926 * code manages it during start/stop and suspend/resume.
1929 musb->clock = clk_get(dev, plat->clock);
1930 if (IS_ERR(musb->clock)) {
1931 status = PTR_ERR(musb->clock);
1937 /* The musb_platform_init() call:
1938 * - adjusts musb->mregs and musb->isr if needed,
1939 * - may initialize an integrated tranceiver
1940 * - initializes musb->xceiv, usually by otg_get_transceiver()
1941 * - activates clocks.
1942 * - stops powering VBUS
1943 * - assigns musb->board_set_vbus if host mode is enabled
1945 * There are various transciever configurations. Blackfin,
1946 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1947 * external/discrete ones in various flavors (twl4030 family,
1948 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1950 musb->isr = generic_interrupt;
1951 status = musb_platform_init(musb);
1960 #ifndef CONFIG_MUSB_PIO_ONLY
1961 if (use_dma && dev->dma_mask) {
1962 struct dma_controller *c;
1964 c = dma_controller_create(musb, musb->mregs);
1965 musb->dma_controller = c;
1970 /* ideally this would be abstracted in platform setup */
1971 if (!is_dma_capable() || !musb->dma_controller)
1972 dev->dma_mask = NULL;
1974 /* be sure interrupts are disabled before connecting ISR */
1975 musb_platform_disable(musb);
1976 musb_generic_disable(musb);
1978 /* setup musb parts of the core (especially endpoints) */
1979 status = musb_core_init(plat->config->multipoint
1980 ? MUSB_CONTROLLER_MHDRC
1981 : MUSB_CONTROLLER_HDRC, musb);
1985 #ifdef CONFIG_USB_MUSB_OTG
1986 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1989 /* Init IRQ workqueue before request_irq */
1990 INIT_WORK(&musb->irq_work, musb_irq_work);
1992 /* attach to the IRQ */
1993 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1994 dev_err(dev, "request_irq %d failed!\n", nIrq);
1999 /* FIXME this handles wakeup irqs wrong */
2000 if (enable_irq_wake(nIrq) == 0) {
2002 device_init_wakeup(dev, 1);
2007 /* host side needs more setup */
2008 if (is_host_enabled(musb)) {
2009 struct usb_hcd *hcd = musb_to_hcd(musb);
2011 otg_set_host(musb->xceiv, &hcd->self);
2013 if (is_otg_enabled(musb))
2014 hcd->self.otg_port = 1;
2015 musb->xceiv->host = &hcd->self;
2016 hcd->power_budget = 2 * (plat->power ? : 250);
2018 /* program PHY to use external vBus if required */
2019 if (plat->extvbus) {
2020 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2021 busctl |= MUSB_ULPI_USE_EXTVBUS;
2022 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2026 /* For the host-only role, we can activate right away.
2027 * (We expect the ID pin to be forcibly grounded!!)
2028 * Otherwise, wait till the gadget driver hooks up.
2030 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2031 MUSB_HST_MODE(musb);
2032 musb->xceiv->default_a = 1;
2033 musb->xceiv->state = OTG_STATE_A_IDLE;
2035 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2037 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2039 musb_readb(musb->mregs, MUSB_DEVCTL),
2040 (musb_readb(musb->mregs, MUSB_DEVCTL)
2041 & MUSB_DEVCTL_BDEVICE
2044 } else /* peripheral is enabled */ {
2045 MUSB_DEV_MODE(musb);
2046 musb->xceiv->default_a = 0;
2047 musb->xceiv->state = OTG_STATE_B_IDLE;
2049 status = musb_gadget_setup(musb);
2051 DBG(1, "%s mode, status %d, dev%02x\n",
2052 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2054 musb_readb(musb->mregs, MUSB_DEVCTL));
2061 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2066 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2068 switch (musb->board_mode) {
2069 case MUSB_HOST: s = "Host"; break;
2070 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2071 default: s = "OTG"; break;
2074 (is_dma_capable() && musb->dma_controller)
2081 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2082 usb_remove_hcd(musb_to_hcd(musb));
2084 musb_gadget_cleanup(musb);
2088 device_init_wakeup(dev, 0);
2089 musb_platform_exit(musb);
2093 clk_put(musb->clock);
2096 dev_err(musb->controller,
2097 "musb_init_controller failed with status %d\n", status);
2107 /*-------------------------------------------------------------------------*/
2109 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2110 * bridge to a platform device; this driver then suffices.
2113 #ifndef CONFIG_MUSB_PIO_ONLY
2114 static u64 *orig_dma_mask;
2117 static int __init musb_probe(struct platform_device *pdev)
2119 struct device *dev = &pdev->dev;
2120 int irq = platform_get_irq(pdev, 0);
2122 struct resource *iomem;
2125 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2126 if (!iomem || irq == 0)
2129 base = ioremap(iomem->start, resource_size(iomem));
2131 dev_err(dev, "ioremap failed\n");
2135 #ifndef CONFIG_MUSB_PIO_ONLY
2136 /* clobbered by use_dma=n */
2137 orig_dma_mask = dev->dma_mask;
2139 status = musb_init_controller(dev, irq, base);
2146 static int __exit musb_remove(struct platform_device *pdev)
2148 struct musb *musb = dev_to_musb(&pdev->dev);
2149 void __iomem *ctrl_base = musb->ctrl_base;
2151 /* this gets called on rmmod.
2152 * - Host mode: host may still be active
2153 * - Peripheral mode: peripheral is deactivated (or never-activated)
2154 * - OTG mode: both roles are deactivated (or never-activated)
2156 musb_shutdown(pdev);
2157 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2158 if (musb->board_mode == MUSB_HOST)
2159 usb_remove_hcd(musb_to_hcd(musb));
2161 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2162 musb_platform_exit(musb);
2163 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2167 device_init_wakeup(&pdev->dev, 0);
2168 #ifndef CONFIG_MUSB_PIO_ONLY
2169 pdev->dev.dma_mask = orig_dma_mask;
2176 static struct musb_context_registers musb_context;
2178 void musb_save_context(struct musb *musb)
2181 void __iomem *musb_base = musb->mregs;
2183 if (is_host_enabled(musb)) {
2184 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2185 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2186 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2188 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2189 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2190 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2191 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2192 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2193 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2195 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2196 musb_writeb(musb_base, MUSB_INDEX, i);
2197 musb_context.index_regs[i].txmaxp =
2198 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2199 musb_context.index_regs[i].txcsr =
2200 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2201 musb_context.index_regs[i].rxmaxp =
2202 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2203 musb_context.index_regs[i].rxcsr =
2204 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2206 if (musb->dyn_fifo) {
2207 musb_context.index_regs[i].txfifoadd =
2208 musb_read_txfifoadd(musb_base);
2209 musb_context.index_regs[i].rxfifoadd =
2210 musb_read_rxfifoadd(musb_base);
2211 musb_context.index_regs[i].txfifosz =
2212 musb_read_txfifosz(musb_base);
2213 musb_context.index_regs[i].rxfifosz =
2214 musb_read_rxfifosz(musb_base);
2216 if (is_host_enabled(musb)) {
2217 musb_context.index_regs[i].txtype =
2218 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2219 musb_context.index_regs[i].txinterval =
2220 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2221 musb_context.index_regs[i].rxtype =
2222 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2223 musb_context.index_regs[i].rxinterval =
2224 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2226 musb_context.index_regs[i].txfunaddr =
2227 musb_read_txfunaddr(musb_base, i);
2228 musb_context.index_regs[i].txhubaddr =
2229 musb_read_txhubaddr(musb_base, i);
2230 musb_context.index_regs[i].txhubport =
2231 musb_read_txhubport(musb_base, i);
2233 musb_context.index_regs[i].rxfunaddr =
2234 musb_read_rxfunaddr(musb_base, i);
2235 musb_context.index_regs[i].rxhubaddr =
2236 musb_read_rxhubaddr(musb_base, i);
2237 musb_context.index_regs[i].rxhubport =
2238 musb_read_rxhubport(musb_base, i);
2242 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2244 musb_platform_save_context(musb, &musb_context);
2247 void musb_restore_context(struct musb *musb)
2250 void __iomem *musb_base = musb->mregs;
2251 void __iomem *ep_target_regs;
2253 musb_platform_restore_context(musb, &musb_context);
2255 if (is_host_enabled(musb)) {
2256 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2257 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2258 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2260 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2261 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2262 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2263 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2264 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2266 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2267 musb_writeb(musb_base, MUSB_INDEX, i);
2268 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2269 musb_context.index_regs[i].txmaxp);
2270 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2271 musb_context.index_regs[i].txcsr);
2272 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2273 musb_context.index_regs[i].rxmaxp);
2274 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2275 musb_context.index_regs[i].rxcsr);
2277 if (musb->dyn_fifo) {
2278 musb_write_txfifosz(musb_base,
2279 musb_context.index_regs[i].txfifosz);
2280 musb_write_rxfifosz(musb_base,
2281 musb_context.index_regs[i].rxfifosz);
2282 musb_write_txfifoadd(musb_base,
2283 musb_context.index_regs[i].txfifoadd);
2284 musb_write_rxfifoadd(musb_base,
2285 musb_context.index_regs[i].rxfifoadd);
2288 if (is_host_enabled(musb)) {
2289 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2290 musb_context.index_regs[i].txtype);
2291 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2292 musb_context.index_regs[i].txinterval);
2293 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2294 musb_context.index_regs[i].rxtype);
2295 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2297 musb_context.index_regs[i].rxinterval);
2298 musb_write_txfunaddr(musb_base, i,
2299 musb_context.index_regs[i].txfunaddr);
2300 musb_write_txhubaddr(musb_base, i,
2301 musb_context.index_regs[i].txhubaddr);
2302 musb_write_txhubport(musb_base, i,
2303 musb_context.index_regs[i].txhubport);
2306 musb_read_target_reg_base(i, musb_base);
2308 musb_write_rxfunaddr(ep_target_regs,
2309 musb_context.index_regs[i].rxfunaddr);
2310 musb_write_rxhubaddr(ep_target_regs,
2311 musb_context.index_regs[i].rxhubaddr);
2312 musb_write_rxhubport(ep_target_regs,
2313 musb_context.index_regs[i].rxhubport);
2317 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2320 static int musb_suspend(struct device *dev)
2322 struct platform_device *pdev = to_platform_device(dev);
2323 unsigned long flags;
2324 struct musb *musb = dev_to_musb(&pdev->dev);
2329 spin_lock_irqsave(&musb->lock, flags);
2331 if (is_peripheral_active(musb)) {
2332 /* FIXME force disconnect unless we know USB will wake
2333 * the system up quickly enough to respond ...
2335 } else if (is_host_active(musb)) {
2336 /* we know all the children are suspended; sometimes
2337 * they will even be wakeup-enabled.
2341 musb_save_context(musb);
2343 if (musb->set_clock)
2344 musb->set_clock(musb->clock, 0);
2346 clk_disable(musb->clock);
2347 spin_unlock_irqrestore(&musb->lock, flags);
2351 static int musb_resume_noirq(struct device *dev)
2353 struct platform_device *pdev = to_platform_device(dev);
2354 struct musb *musb = dev_to_musb(&pdev->dev);
2359 if (musb->set_clock)
2360 musb->set_clock(musb->clock, 1);
2362 clk_enable(musb->clock);
2364 musb_restore_context(musb);
2366 /* for static cmos like DaVinci, register values were preserved
2367 * unless for some reason the whole soc powered down or the USB
2368 * module got reset through the PSC (vs just being disabled).
2373 static const struct dev_pm_ops musb_dev_pm_ops = {
2374 .suspend = musb_suspend,
2375 .resume_noirq = musb_resume_noirq,
2378 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2380 #define MUSB_DEV_PM_OPS NULL
2383 static struct platform_driver musb_driver = {
2385 .name = (char *)musb_driver_name,
2386 .bus = &platform_bus_type,
2387 .owner = THIS_MODULE,
2388 .pm = MUSB_DEV_PM_OPS,
2390 .remove = __exit_p(musb_remove),
2391 .shutdown = musb_shutdown,
2394 /*-------------------------------------------------------------------------*/
2396 static int __init musb_init(void)
2398 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2403 pr_info("%s: version " MUSB_VERSION ", "
2404 #ifdef CONFIG_MUSB_PIO_ONLY
2406 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2408 #elif defined(CONFIG_USB_INVENTRA_DMA)
2410 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2416 #ifdef CONFIG_USB_MUSB_OTG
2417 "otg (peripheral+host)"
2418 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2420 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2424 musb_driver_name, musb_debug);
2425 return platform_driver_probe(&musb_driver, musb_probe);
2428 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2429 * and before usb gadget and host-side drivers start to register
2431 fs_initcall(musb_init);
2433 static void __exit musb_cleanup(void)
2435 platform_driver_unregister(&musb_driver);
2437 module_exit(musb_cleanup);