2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
33 #define DRIVER_AUTHOR "Sarah Sharp"
34 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
36 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
38 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
39 static int link_quirk;
40 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
41 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
43 /* TODO: copied from ehci-hcd.c - can this be refactored? */
45 * handshake - spin reading hc until handshake completes or fails
46 * @ptr: address of hc register to be read
47 * @mask: bits to look at in result of read
48 * @done: value of those bits when handshake succeeds
49 * @usec: timeout in microseconds
51 * Returns negative errno, or zero on success
53 * Success happens when the "mask" bits have the specified value (hardware
54 * handshake done). There are two failure modes: "usec" have passed (major
55 * hardware flakeout), or the register reads as all-ones (hardware removed).
57 int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
58 u32 mask, u32 done, int usec)
63 result = xhci_readl(xhci, ptr);
64 if (result == ~(u32)0) /* card removed */
76 * Disable interrupts and begin the xHCI halting process.
78 void xhci_quiesce(struct xhci_hcd *xhci)
85 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
89 cmd = xhci_readl(xhci, &xhci->op_regs->command);
91 xhci_writel(xhci, cmd, &xhci->op_regs->command);
95 * Force HC into halt state.
97 * Disable any IRQs and clear the run/stop bit.
98 * HC will complete any current and actively pipelined transactions, and
99 * should halt within 16 ms of the run/stop bit being cleared.
100 * Read HC Halted bit in the status register to see when the HC is finished.
102 int xhci_halt(struct xhci_hcd *xhci)
105 xhci_dbg(xhci, "// Halt the HC\n");
108 ret = handshake(xhci, &xhci->op_regs->status,
109 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
111 xhci->xhc_state |= XHCI_STATE_HALTED;
112 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
114 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
120 * Set the run bit and wait for the host to be running.
122 static int xhci_start(struct xhci_hcd *xhci)
127 temp = xhci_readl(xhci, &xhci->op_regs->command);
129 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
131 xhci_writel(xhci, temp, &xhci->op_regs->command);
134 * Wait for the HCHalted Status bit to be 0 to indicate the host is
137 ret = handshake(xhci, &xhci->op_regs->status,
138 STS_HALT, 0, XHCI_MAX_HALT_USEC);
139 if (ret == -ETIMEDOUT)
140 xhci_err(xhci, "Host took too long to start, "
141 "waited %u microseconds.\n",
144 xhci->xhc_state &= ~(XHCI_STATE_HALTED | XHCI_STATE_DYING);
152 * This resets pipelines, timers, counters, state machines, etc.
153 * Transactions will be terminated immediately, and operational registers
154 * will be set to their defaults.
156 int xhci_reset(struct xhci_hcd *xhci)
162 state = xhci_readl(xhci, &xhci->op_regs->status);
163 if ((state & STS_HALT) == 0) {
164 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
168 xhci_dbg(xhci, "// Reset the HC\n");
169 command = xhci_readl(xhci, &xhci->op_regs->command);
170 command |= CMD_RESET;
171 xhci_writel(xhci, command, &xhci->op_regs->command);
173 /* Existing Intel xHCI controllers require a delay of 1 mS,
174 * after setting the CMD_RESET bit, and before accessing any
175 * HC registers. This allows the HC to complete the
176 * reset operation and be ready for HC register access.
177 * Without this delay, the subsequent HC register access,
178 * may result in a system hang very rarely.
180 if (xhci->quirks & XHCI_INTEL_HOST)
183 ret = handshake(xhci, &xhci->op_regs->command,
184 CMD_RESET, 0, 10 * 1000 * 1000);
188 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
190 * xHCI cannot write to any doorbells or operational registers other
191 * than status until the "Controller Not Ready" flag is cleared.
193 return handshake(xhci, &xhci->op_regs->status,
194 STS_CNR, 0, 10 * 1000 * 1000);
198 static int xhci_free_msi(struct xhci_hcd *xhci)
202 if (!xhci->msix_entries)
205 for (i = 0; i < xhci->msix_count; i++)
206 if (xhci->msix_entries[i].vector)
207 free_irq(xhci->msix_entries[i].vector,
215 static int xhci_setup_msi(struct xhci_hcd *xhci)
218 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
220 ret = pci_enable_msi(pdev);
222 xhci_dbg(xhci, "failed to allocate MSI entry\n");
226 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
227 0, "xhci_hcd", xhci_to_hcd(xhci));
229 xhci_dbg(xhci, "disable MSI interrupt\n");
230 pci_disable_msi(pdev);
238 * free all IRQs request
240 static void xhci_free_irq(struct xhci_hcd *xhci)
242 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
245 /* return if using legacy interrupt */
246 if (xhci_to_hcd(xhci)->irq >= 0)
249 ret = xhci_free_msi(xhci);
253 free_irq(pdev->irq, xhci_to_hcd(xhci));
261 static int xhci_setup_msix(struct xhci_hcd *xhci)
264 struct usb_hcd *hcd = xhci_to_hcd(xhci);
265 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
268 * calculate number of msi-x vectors supported.
269 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
270 * with max number of interrupters based on the xhci HCSPARAMS1.
271 * - num_online_cpus: maximum msi-x vectors per CPUs core.
272 * Add additional 1 vector to ensure always available interrupt.
274 xhci->msix_count = min(num_online_cpus() + 1,
275 HCS_MAX_INTRS(xhci->hcs_params1));
278 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
280 if (!xhci->msix_entries) {
281 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
285 for (i = 0; i < xhci->msix_count; i++) {
286 xhci->msix_entries[i].entry = i;
287 xhci->msix_entries[i].vector = 0;
290 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
292 xhci_dbg(xhci, "Failed to enable MSI-X\n");
296 for (i = 0; i < xhci->msix_count; i++) {
297 ret = request_irq(xhci->msix_entries[i].vector,
298 (irq_handler_t)xhci_msi_irq,
299 0, "xhci_hcd", xhci_to_hcd(xhci));
304 hcd->msix_enabled = 1;
308 xhci_dbg(xhci, "disable MSI-X interrupt\n");
310 pci_disable_msix(pdev);
312 kfree(xhci->msix_entries);
313 xhci->msix_entries = NULL;
317 /* Free any IRQs and disable MSI-X */
318 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
320 struct usb_hcd *hcd = xhci_to_hcd(xhci);
321 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
325 if (xhci->msix_entries) {
326 pci_disable_msix(pdev);
327 kfree(xhci->msix_entries);
328 xhci->msix_entries = NULL;
330 pci_disable_msi(pdev);
333 hcd->msix_enabled = 0;
337 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
341 if (xhci->msix_entries) {
342 for (i = 0; i < xhci->msix_count; i++)
343 synchronize_irq(xhci->msix_entries[i].vector);
347 static int xhci_try_enable_msi(struct usb_hcd *hcd)
349 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
350 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
354 * Some Fresco Logic host controllers advertise MSI, but fail to
355 * generate interrupts. Don't even try to enable MSI.
357 if (xhci->quirks & XHCI_BROKEN_MSI)
360 /* unregister the legacy interrupt */
362 free_irq(hcd->irq, hcd);
365 ret = xhci_setup_msix(xhci);
367 /* fall back to msi*/
368 ret = xhci_setup_msi(xhci);
371 /* hcd->irq is -1, we have MSI */
375 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
380 /* fall back to legacy interrupt*/
381 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
382 hcd->irq_descr, hcd);
384 xhci_err(xhci, "request interrupt %d failed\n",
388 hcd->irq = pdev->irq;
394 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
399 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
403 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
409 static void compliance_mode_recovery(unsigned long arg)
411 struct xhci_hcd *xhci;
416 xhci = (struct xhci_hcd *)arg;
418 for (i = 0; i < xhci->num_usb3_ports; i++) {
419 temp = xhci_readl(xhci, xhci->usb3_ports[i]);
420 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
422 * Compliance Mode Detected. Letting USB Core
423 * handle the Warm Reset
425 xhci_dbg(xhci, "Compliance Mode Detected->Port %d!\n",
427 xhci_dbg(xhci, "Attempting Recovery routine!\n");
428 hcd = xhci->shared_hcd;
430 if (hcd->state == HC_STATE_SUSPENDED)
431 usb_hcd_resume_root_hub(hcd);
433 usb_hcd_poll_rh_status(hcd);
437 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
438 mod_timer(&xhci->comp_mode_recovery_timer,
439 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
443 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
444 * that causes ports behind that hardware to enter compliance mode sometimes.
445 * The quirk creates a timer that polls every 2 seconds the link state of
446 * each host controller's port and recovers it by issuing a Warm reset
447 * if Compliance mode is detected, otherwise the port will become "dead" (no
448 * device connections or disconnections will be detected anymore). Becasue no
449 * status event is generated when entering compliance mode (per xhci spec),
450 * this quirk is needed on systems that have the failing hardware installed.
452 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
454 xhci->port_status_u0 = 0;
455 init_timer(&xhci->comp_mode_recovery_timer);
457 xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
458 xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
459 xhci->comp_mode_recovery_timer.expires = jiffies +
460 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
462 set_timer_slack(&xhci->comp_mode_recovery_timer,
463 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
464 add_timer(&xhci->comp_mode_recovery_timer);
465 xhci_dbg(xhci, "Compliance Mode Recovery Timer Initialized.\n");
469 * This function identifies the systems that have installed the SN65LVPE502CP
470 * USB3.0 re-driver and that need the Compliance Mode Quirk.
472 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
474 static bool compliance_mode_recovery_timer_quirk_check(void)
476 const char *dmi_product_name, *dmi_sys_vendor;
478 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
479 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
480 if (!dmi_product_name || !dmi_sys_vendor)
483 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
486 if (strstr(dmi_product_name, "Z420") ||
487 strstr(dmi_product_name, "Z620") ||
488 strstr(dmi_product_name, "Z820") ||
489 strstr(dmi_product_name, "Z1 Workstation"))
495 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
497 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
502 * Initialize memory for HCD and xHC (one-time init).
504 * Program the PAGESIZE register, initialize the device context array, create
505 * device contexts (?), set up a command ring segment (or two?), create event
506 * ring (one for now).
508 int xhci_init(struct usb_hcd *hcd)
510 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
513 xhci_dbg(xhci, "xhci_init\n");
514 spin_lock_init(&xhci->lock);
515 if (xhci->hci_version == 0x95 && link_quirk) {
516 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
517 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
519 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
521 retval = xhci_mem_init(xhci, GFP_KERNEL);
522 xhci_dbg(xhci, "Finished xhci_init\n");
524 /* Initializing Compliance Mode Recovery Data If Needed */
525 if (compliance_mode_recovery_timer_quirk_check()) {
526 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
527 compliance_mode_recovery_timer_init(xhci);
533 /*-------------------------------------------------------------------------*/
536 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
537 static void xhci_event_ring_work(unsigned long arg)
542 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
545 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
547 spin_lock_irqsave(&xhci->lock, flags);
548 temp = xhci_readl(xhci, &xhci->op_regs->status);
549 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
550 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
551 (xhci->xhc_state & XHCI_STATE_HALTED)) {
552 xhci_dbg(xhci, "HW died, polling stopped.\n");
553 spin_unlock_irqrestore(&xhci->lock, flags);
557 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
558 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
559 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
560 xhci->error_bitmask = 0;
561 xhci_dbg(xhci, "Event ring:\n");
562 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
563 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
564 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
565 temp_64 &= ~ERST_PTR_MASK;
566 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
567 xhci_dbg(xhci, "Command ring:\n");
568 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
569 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
570 xhci_dbg_cmd_ptrs(xhci);
571 for (i = 0; i < MAX_HC_SLOTS; ++i) {
574 for (j = 0; j < 31; ++j) {
575 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
578 spin_unlock_irqrestore(&xhci->lock, flags);
581 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
583 xhci_dbg(xhci, "Quit polling the event ring.\n");
587 static int xhci_run_finished(struct xhci_hcd *xhci)
589 if (xhci_start(xhci)) {
593 xhci->shared_hcd->state = HC_STATE_RUNNING;
594 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
596 if (xhci->quirks & XHCI_NEC_HOST)
597 xhci_ring_cmd_db(xhci);
599 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
604 * Start the HC after it was halted.
606 * This function is called by the USB core when the HC driver is added.
607 * Its opposite is xhci_stop().
609 * xhci_init() must be called once before this function can be called.
610 * Reset the HC, enable device slot contexts, program DCBAAP, and
611 * set command ring pointer and event ring pointer.
613 * Setup MSI-X vectors and enable interrupts.
615 int xhci_run(struct usb_hcd *hcd)
620 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
622 /* Start the xHCI host controller running only after the USB 2.0 roothub
626 hcd->uses_new_polling = 1;
627 if (!usb_hcd_is_primary_hcd(hcd))
628 return xhci_run_finished(xhci);
630 xhci_dbg(xhci, "xhci_run\n");
632 ret = xhci_try_enable_msi(hcd);
636 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
637 init_timer(&xhci->event_ring_timer);
638 xhci->event_ring_timer.data = (unsigned long) xhci;
639 xhci->event_ring_timer.function = xhci_event_ring_work;
640 /* Poll the event ring */
641 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
643 xhci_dbg(xhci, "Setting event ring polling timer\n");
644 add_timer(&xhci->event_ring_timer);
647 xhci_dbg(xhci, "Command ring memory map follows:\n");
648 xhci_debug_ring(xhci, xhci->cmd_ring);
649 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
650 xhci_dbg_cmd_ptrs(xhci);
652 xhci_dbg(xhci, "ERST memory map follows:\n");
653 xhci_dbg_erst(xhci, &xhci->erst);
654 xhci_dbg(xhci, "Event ring:\n");
655 xhci_debug_ring(xhci, xhci->event_ring);
656 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
657 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
658 temp_64 &= ~ERST_PTR_MASK;
659 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
661 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
662 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
665 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
667 /* Set the HCD state before we enable the irqs */
668 temp = xhci_readl(xhci, &xhci->op_regs->command);
670 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
672 xhci_writel(xhci, temp, &xhci->op_regs->command);
674 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
675 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
676 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
677 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
678 &xhci->ir_set->irq_pending);
679 xhci_print_ir_set(xhci, 0);
681 if (xhci->quirks & XHCI_NEC_HOST)
682 xhci_queue_vendor_command(xhci, 0, 0, 0,
683 TRB_TYPE(TRB_NEC_GET_FW));
685 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
689 static void xhci_only_stop_hcd(struct usb_hcd *hcd)
691 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
693 spin_lock_irq(&xhci->lock);
696 /* The shared_hcd is going to be deallocated shortly (the USB core only
697 * calls this function when allocation fails in usb_add_hcd(), or
698 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
700 xhci->shared_hcd = NULL;
701 spin_unlock_irq(&xhci->lock);
707 * This function is called by the USB core when the HC driver is removed.
708 * Its opposite is xhci_run().
710 * Disable device contexts, disable IRQs, and quiesce the HC.
711 * Reset the HC, finish any completed transactions, and cleanup memory.
713 void xhci_stop(struct usb_hcd *hcd)
716 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
718 if (!usb_hcd_is_primary_hcd(hcd)) {
719 xhci_only_stop_hcd(xhci->shared_hcd);
723 spin_lock_irq(&xhci->lock);
724 /* Make sure the xHC is halted for a USB3 roothub
725 * (xhci_stop() could be called as part of failed init).
729 spin_unlock_irq(&xhci->lock);
731 xhci_cleanup_msix(xhci);
733 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
734 /* Tell the event ring poll function not to reschedule */
736 del_timer_sync(&xhci->event_ring_timer);
739 /* Deleting Compliance Mode Recovery Timer */
740 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
741 (!(xhci_all_ports_seen_u0(xhci))))
742 del_timer_sync(&xhci->comp_mode_recovery_timer);
744 if (xhci->quirks & XHCI_AMD_PLL_FIX)
747 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
748 temp = xhci_readl(xhci, &xhci->op_regs->status);
749 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
750 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
751 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
752 &xhci->ir_set->irq_pending);
753 xhci_print_ir_set(xhci, 0);
755 xhci_dbg(xhci, "cleaning up memory\n");
756 xhci_mem_cleanup(xhci);
757 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
758 xhci_readl(xhci, &xhci->op_regs->status));
762 * Shutdown HC (not bus-specific)
764 * This is called when the machine is rebooting or halting. We assume that the
765 * machine will be powered off, and the HC's internal state will be reset.
766 * Don't bother to free memory.
768 * This will only ever be called with the main usb_hcd (the USB3 roothub).
770 void xhci_shutdown(struct usb_hcd *hcd)
772 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
774 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
775 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
777 spin_lock_irq(&xhci->lock);
779 /* Workaround for spurious wakeups at shutdown with HSW */
780 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
782 spin_unlock_irq(&xhci->lock);
784 xhci_cleanup_msix(xhci);
786 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
787 xhci_readl(xhci, &xhci->op_regs->status));
789 /* Yet another workaround for spurious wakeups at shutdown with HSW */
790 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
791 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
795 static void xhci_save_registers(struct xhci_hcd *xhci)
797 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
798 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
799 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
800 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
801 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
802 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
803 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
804 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
805 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
808 static void xhci_restore_registers(struct xhci_hcd *xhci)
810 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
811 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
812 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
813 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
814 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
815 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
816 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
817 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
818 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
821 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
825 /* step 2: initialize command ring buffer */
826 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
827 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
828 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
829 xhci->cmd_ring->dequeue) &
830 (u64) ~CMD_RING_RSVD_BITS) |
831 xhci->cmd_ring->cycle_state;
832 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
833 (long unsigned long) val_64);
834 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
838 * The whole command ring must be cleared to zero when we suspend the host.
840 * The host doesn't save the command ring pointer in the suspend well, so we
841 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
842 * aligned, because of the reserved bits in the command ring dequeue pointer
843 * register. Therefore, we can't just set the dequeue pointer back in the
844 * middle of the ring (TRBs are 16-byte aligned).
846 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
848 struct xhci_ring *ring;
849 struct xhci_segment *seg;
851 ring = xhci->cmd_ring;
855 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
856 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
857 cpu_to_le32(~TRB_CYCLE);
859 } while (seg != ring->deq_seg);
861 /* Reset the software enqueue and dequeue pointers */
862 ring->deq_seg = ring->first_seg;
863 ring->dequeue = ring->first_seg->trbs;
864 ring->enq_seg = ring->deq_seg;
865 ring->enqueue = ring->dequeue;
868 * Ring is now zeroed, so the HW should look for change of ownership
869 * when the cycle bit is set to 1.
871 ring->cycle_state = 1;
874 * Reset the hardware dequeue pointer.
875 * Yes, this will need to be re-written after resume, but we're paranoid
876 * and want to make sure the hardware doesn't access bogus memory
877 * because, say, the BIOS or an SMI started the host without changing
878 * the command ring pointers.
880 xhci_set_cmd_ring_deq(xhci);
883 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
886 __le32 __iomem **port_array;
890 spin_lock_irqsave(&xhci->lock, flags);
892 /* disble usb3 ports Wake bits*/
893 port_index = xhci->num_usb3_ports;
894 port_array = xhci->usb3_ports;
895 while (port_index--) {
896 t1 = readl(port_array[port_index]);
897 t1 = xhci_port_state_to_neutral(t1);
898 t2 = t1 & ~PORT_WAKE_BITS;
900 writel(t2, port_array[port_index]);
903 /* disble usb2 ports Wake bits*/
904 port_index = xhci->num_usb2_ports;
905 port_array = xhci->usb2_ports;
906 while (port_index--) {
907 t1 = readl(port_array[port_index]);
908 t1 = xhci_port_state_to_neutral(t1);
909 t2 = t1 & ~PORT_WAKE_BITS;
911 writel(t2, port_array[port_index]);
914 spin_unlock_irqrestore(&xhci->lock, flags);
918 * Stop HC (not bus-specific)
920 * This is called when the machine transition into S3/S4 mode.
923 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
926 unsigned int delay = XHCI_MAX_HALT_USEC;
927 struct usb_hcd *hcd = xhci_to_hcd(xhci);
930 /* Clear root port wake on bits if wakeup not allowed. */
932 xhci_disable_port_wake_on_bits(xhci);
934 /* Don't poll the roothubs on bus suspend. */
935 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
936 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
937 del_timer_sync(&hcd->rh_timer);
939 if (xhci->quirks & XHCI_SUSPEND_DELAY)
940 usleep_range(1000, 1500);
942 spin_lock_irq(&xhci->lock);
943 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
944 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
945 /* step 1: stop endpoint */
946 /* skipped assuming that port suspend has done */
948 /* step 2: clear Run/Stop bit */
949 command = xhci_readl(xhci, &xhci->op_regs->command);
951 xhci_writel(xhci, command, &xhci->op_regs->command);
953 /* Some chips from Fresco Logic need an extraordinary delay */
954 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
956 if (handshake(xhci, &xhci->op_regs->status,
957 STS_HALT, STS_HALT, delay)) {
958 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
959 spin_unlock_irq(&xhci->lock);
962 xhci_clear_command_ring(xhci);
964 /* step 3: save registers */
965 xhci_save_registers(xhci);
967 /* step 4: set CSS flag */
968 command = xhci_readl(xhci, &xhci->op_regs->command);
970 xhci_writel(xhci, command, &xhci->op_regs->command);
971 if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10 * 1000)) {
972 xhci_warn(xhci, "WARN: xHC save state timeout\n");
973 spin_unlock_irq(&xhci->lock);
976 spin_unlock_irq(&xhci->lock);
979 * Deleting Compliance Mode Recovery Timer because the xHCI Host
980 * is about to be suspended.
982 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
983 (!(xhci_all_ports_seen_u0(xhci)))) {
984 del_timer_sync(&xhci->comp_mode_recovery_timer);
985 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted!\n");
988 /* step 5: remove core well power */
989 /* synchronize irq when using MSI-X */
990 xhci_msix_sync_irqs(xhci);
996 * start xHC (not bus-specific)
998 * This is called when the machine transition from S3/S4 mode.
1001 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1003 u32 command, temp = 0, status;
1004 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1005 struct usb_hcd *secondary_hcd;
1007 bool comp_timer_running = false;
1009 /* Wait a bit if either of the roothubs need to settle from the
1010 * transition into bus suspend.
1012 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1013 time_before(jiffies,
1014 xhci->bus_state[1].next_statechange))
1017 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1018 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1020 spin_lock_irq(&xhci->lock);
1021 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1025 /* step 1: restore register */
1026 xhci_restore_registers(xhci);
1027 /* step 2: initialize command ring buffer */
1028 xhci_set_cmd_ring_deq(xhci);
1029 /* step 3: restore state and start state*/
1030 /* step 3: set CRS flag */
1031 command = xhci_readl(xhci, &xhci->op_regs->command);
1033 xhci_writel(xhci, command, &xhci->op_regs->command);
1034 if (handshake(xhci, &xhci->op_regs->status,
1035 STS_RESTORE, 0, 10 * 1000)) {
1036 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1037 spin_unlock_irq(&xhci->lock);
1040 temp = xhci_readl(xhci, &xhci->op_regs->status);
1043 /* If restore operation fails, re-initialize the HC during resume */
1044 if ((temp & STS_SRE) || hibernated) {
1046 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1047 !(xhci_all_ports_seen_u0(xhci))) {
1048 del_timer_sync(&xhci->comp_mode_recovery_timer);
1049 xhci_dbg(xhci, "Compliance Mode Recovery Timer deleted!\n");
1052 /* Let the USB core know _both_ roothubs lost power. */
1053 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1054 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1056 xhci_dbg(xhci, "Stop HCD\n");
1059 spin_unlock_irq(&xhci->lock);
1060 xhci_cleanup_msix(xhci);
1062 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1063 /* Tell the event ring poll function not to reschedule */
1065 del_timer_sync(&xhci->event_ring_timer);
1068 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1069 temp = xhci_readl(xhci, &xhci->op_regs->status);
1070 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
1071 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
1072 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
1073 &xhci->ir_set->irq_pending);
1074 xhci_print_ir_set(xhci, 0);
1076 xhci_dbg(xhci, "cleaning up memory\n");
1077 xhci_mem_cleanup(xhci);
1078 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1079 xhci_readl(xhci, &xhci->op_regs->status));
1081 /* USB core calls the PCI reinit and start functions twice:
1082 * first with the primary HCD, and then with the secondary HCD.
1083 * If we don't do the same, the host will never be started.
1085 if (!usb_hcd_is_primary_hcd(hcd))
1086 secondary_hcd = hcd;
1088 secondary_hcd = xhci->shared_hcd;
1090 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1091 retval = xhci_init(hcd->primary_hcd);
1094 comp_timer_running = true;
1096 xhci_dbg(xhci, "Start the primary HCD\n");
1097 retval = xhci_run(hcd->primary_hcd);
1099 xhci_dbg(xhci, "Start the secondary HCD\n");
1100 retval = xhci_run(secondary_hcd);
1102 hcd->state = HC_STATE_SUSPENDED;
1103 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1107 /* step 4: set Run/Stop bit */
1108 command = xhci_readl(xhci, &xhci->op_regs->command);
1110 xhci_writel(xhci, command, &xhci->op_regs->command);
1111 handshake(xhci, &xhci->op_regs->status, STS_HALT,
1114 /* step 5: walk topology and initialize portsc,
1115 * portpmsc and portli
1117 /* this is done in bus_resume */
1119 /* step 6: restart each of the previously
1120 * Running endpoints by ringing their doorbells
1123 spin_unlock_irq(&xhci->lock);
1127 /* Resume root hubs only when have pending events. */
1128 status = readl(&xhci->op_regs->status);
1129 if (status & STS_EINT) {
1130 usb_hcd_resume_root_hub(hcd);
1131 usb_hcd_resume_root_hub(xhci->shared_hcd);
1136 * If system is subject to the Quirk, Compliance Mode Timer needs to
1137 * be re-initialized Always after a system resume. Ports are subject
1138 * to suffer the Compliance Mode issue again. It doesn't matter if
1139 * ports have entered previously to U0 before system's suspension.
1141 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1142 compliance_mode_recovery_timer_init(xhci);
1144 /* Re-enable port polling. */
1145 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1146 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1147 usb_hcd_poll_rh_status(hcd);
1151 #endif /* CONFIG_PM */
1153 /*-------------------------------------------------------------------------*/
1156 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1157 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1158 * value to right shift 1 for the bitmask.
1160 * Index = (epnum * 2) + direction - 1,
1161 * where direction = 0 for OUT, 1 for IN.
1162 * For control endpoints, the IN index is used (OUT index is unused), so
1163 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1165 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1168 if (usb_endpoint_xfer_control(desc))
1169 index = (unsigned int) (usb_endpoint_num(desc)*2);
1171 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1172 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1176 /* Find the flag for this endpoint (for use in the control context). Use the
1177 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1180 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1182 return 1 << (xhci_get_endpoint_index(desc) + 1);
1185 /* Find the flag for this endpoint (for use in the control context). Use the
1186 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1189 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1191 return 1 << (ep_index + 1);
1194 /* Compute the last valid endpoint context index. Basically, this is the
1195 * endpoint index plus one. For slot contexts with more than valid endpoint,
1196 * we find the most significant bit set in the added contexts flags.
1197 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1198 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1200 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1202 return fls(added_ctxs) - 1;
1205 /* Returns 1 if the arguments are OK;
1206 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1208 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1209 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1211 struct xhci_hcd *xhci;
1212 struct xhci_virt_device *virt_dev;
1214 if (!hcd || (check_ep && !ep) || !udev) {
1215 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
1219 if (!udev->parent) {
1220 printk(KERN_DEBUG "xHCI %s called for root hub\n",
1225 xhci = hcd_to_xhci(hcd);
1226 if (check_virt_dev) {
1227 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1228 printk(KERN_DEBUG "xHCI %s called with unaddressed "
1233 virt_dev = xhci->devs[udev->slot_id];
1234 if (virt_dev->udev != udev) {
1235 printk(KERN_DEBUG "xHCI %s called with udev and "
1236 "virt_dev does not match\n", func);
1241 if (xhci->xhc_state & XHCI_STATE_HALTED)
1247 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1248 struct usb_device *udev, struct xhci_command *command,
1249 bool ctx_change, bool must_succeed);
1252 * Full speed devices may have a max packet size greater than 8 bytes, but the
1253 * USB core doesn't know that until it reads the first 8 bytes of the
1254 * descriptor. If the usb_device's max packet size changes after that point,
1255 * we need to issue an evaluate context command and wait on it.
1257 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1258 unsigned int ep_index, struct urb *urb)
1260 struct xhci_container_ctx *in_ctx;
1261 struct xhci_container_ctx *out_ctx;
1262 struct xhci_input_control_ctx *ctrl_ctx;
1263 struct xhci_ep_ctx *ep_ctx;
1264 int max_packet_size;
1265 int hw_max_packet_size;
1268 out_ctx = xhci->devs[slot_id]->out_ctx;
1269 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1270 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1271 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1272 if (hw_max_packet_size != max_packet_size) {
1273 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
1274 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
1276 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
1277 hw_max_packet_size);
1278 xhci_dbg(xhci, "Issuing evaluate context command.\n");
1280 /* Set up the modified control endpoint 0 */
1281 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1282 xhci->devs[slot_id]->out_ctx, ep_index);
1283 in_ctx = xhci->devs[slot_id]->in_ctx;
1284 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1285 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1286 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1288 /* Set up the input context flags for the command */
1289 /* FIXME: This won't work if a non-default control endpoint
1290 * changes max packet sizes.
1292 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1293 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1294 ctrl_ctx->drop_flags = 0;
1296 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1297 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1298 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1299 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1301 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1304 /* Clean up the input context for later use by bandwidth
1307 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1313 * non-error returns are a promise to giveback() the urb later
1314 * we drop ownership so next owner (or urb unlink) can get it
1316 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1318 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1319 struct xhci_td *buffer;
1320 unsigned long flags;
1322 unsigned int slot_id, ep_index;
1323 struct urb_priv *urb_priv;
1326 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1327 true, true, __func__) <= 0)
1330 slot_id = urb->dev->slot_id;
1331 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1333 if (!HCD_HW_ACCESSIBLE(hcd)) {
1334 if (!in_interrupt())
1335 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1340 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1341 size = urb->number_of_packets;
1345 urb_priv = kzalloc(sizeof(struct urb_priv) +
1346 size * sizeof(struct xhci_td *), mem_flags);
1350 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1356 for (i = 0; i < size; i++) {
1357 urb_priv->td[i] = buffer;
1361 urb_priv->length = size;
1362 urb_priv->td_cnt = 0;
1363 urb->hcpriv = urb_priv;
1365 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1366 /* Check to see if the max packet size for the default control
1367 * endpoint changed during FS device enumeration
1369 if (urb->dev->speed == USB_SPEED_FULL) {
1370 ret = xhci_check_maxpacket(xhci, slot_id,
1373 xhci_urb_free_priv(xhci, urb_priv);
1379 /* We have a spinlock and interrupts disabled, so we must pass
1380 * atomic context to this function, which may allocate memory.
1382 spin_lock_irqsave(&xhci->lock, flags);
1383 if (xhci->xhc_state & XHCI_STATE_DYING)
1385 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1389 spin_unlock_irqrestore(&xhci->lock, flags);
1390 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1391 spin_lock_irqsave(&xhci->lock, flags);
1392 if (xhci->xhc_state & XHCI_STATE_DYING)
1394 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1395 EP_GETTING_STREAMS) {
1396 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1397 "is transitioning to using streams.\n");
1399 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1400 EP_GETTING_NO_STREAMS) {
1401 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1402 "is transitioning to "
1403 "not having streams.\n");
1406 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1411 spin_unlock_irqrestore(&xhci->lock, flags);
1412 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1413 spin_lock_irqsave(&xhci->lock, flags);
1414 if (xhci->xhc_state & XHCI_STATE_DYING)
1416 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1420 spin_unlock_irqrestore(&xhci->lock, flags);
1422 spin_lock_irqsave(&xhci->lock, flags);
1423 if (xhci->xhc_state & XHCI_STATE_DYING)
1425 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1429 spin_unlock_irqrestore(&xhci->lock, flags);
1434 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1435 "non-responsive xHCI host.\n",
1436 urb->ep->desc.bEndpointAddress, urb);
1439 xhci_urb_free_priv(xhci, urb_priv);
1441 spin_unlock_irqrestore(&xhci->lock, flags);
1445 /* Get the right ring for the given URB.
1446 * If the endpoint supports streams, boundary check the URB's stream ID.
1447 * If the endpoint doesn't support streams, return the singular endpoint ring.
1449 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1452 unsigned int slot_id;
1453 unsigned int ep_index;
1454 unsigned int stream_id;
1455 struct xhci_virt_ep *ep;
1457 slot_id = urb->dev->slot_id;
1458 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1459 stream_id = urb->stream_id;
1460 ep = &xhci->devs[slot_id]->eps[ep_index];
1461 /* Common case: no streams */
1462 if (!(ep->ep_state & EP_HAS_STREAMS))
1465 if (stream_id == 0) {
1467 "WARN: Slot ID %u, ep index %u has streams, "
1468 "but URB has no stream ID.\n",
1473 if (stream_id < ep->stream_info->num_streams)
1474 return ep->stream_info->stream_rings[stream_id];
1477 "WARN: Slot ID %u, ep index %u has "
1478 "stream IDs 1 to %u allocated, "
1479 "but stream ID %u is requested.\n",
1481 ep->stream_info->num_streams - 1,
1487 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1488 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1489 * should pick up where it left off in the TD, unless a Set Transfer Ring
1490 * Dequeue Pointer is issued.
1492 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1493 * the ring. Since the ring is a contiguous structure, they can't be physically
1494 * removed. Instead, there are two options:
1496 * 1) If the HC is in the middle of processing the URB to be canceled, we
1497 * simply move the ring's dequeue pointer past those TRBs using the Set
1498 * Transfer Ring Dequeue Pointer command. This will be the common case,
1499 * when drivers timeout on the last submitted URB and attempt to cancel.
1501 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1502 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1503 * HC will need to invalidate the any TRBs it has cached after the stop
1504 * endpoint command, as noted in the xHCI 0.95 errata.
1506 * 3) The TD may have completed by the time the Stop Endpoint Command
1507 * completes, so software needs to handle that case too.
1509 * This function should protect against the TD enqueueing code ringing the
1510 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1511 * It also needs to account for multiple cancellations on happening at the same
1512 * time for the same endpoint.
1514 * Note that this function can be called in any context, or so says
1515 * usb_hcd_unlink_urb()
1517 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1519 unsigned long flags;
1522 struct xhci_hcd *xhci;
1523 struct urb_priv *urb_priv;
1525 unsigned int ep_index;
1526 struct xhci_ring *ep_ring;
1527 struct xhci_virt_ep *ep;
1528 struct xhci_virt_device *vdev;
1530 xhci = hcd_to_xhci(hcd);
1531 spin_lock_irqsave(&xhci->lock, flags);
1532 /* Make sure the URB hasn't completed or been unlinked already */
1533 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1537 /* give back URB now if we can't queue it for cancel */
1538 vdev = xhci->devs[urb->dev->slot_id];
1539 urb_priv = urb->hcpriv;
1540 if (!vdev || !urb_priv)
1543 xhci_dbg(xhci, "Cancel URB %p\n", urb);
1544 xhci_dbg(xhci, "Event ring:\n");
1545 xhci_debug_ring(xhci, xhci->event_ring);
1546 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1547 ep = &vdev->eps[ep_index];
1548 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1549 if (!ep || !ep_ring)
1552 xhci_dbg(xhci, "Endpoint ring:\n");
1553 xhci_debug_ring(xhci, ep_ring);
1555 temp = xhci_readl(xhci, &xhci->op_regs->status);
1556 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1557 xhci_dbg(xhci, "HW died, freeing TD.\n");
1558 for (i = urb_priv->td_cnt;
1559 i < urb_priv->length;
1561 td = urb_priv->td[i];
1562 if (!list_empty(&td->td_list))
1563 list_del_init(&td->td_list);
1564 if (!list_empty(&td->cancelled_td_list))
1565 list_del_init(&td->cancelled_td_list);
1570 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1571 td = urb_priv->td[i];
1572 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1575 /* Queue a stop endpoint command, but only if this is
1576 * the first cancellation to be handled.
1578 if (!(ep->ep_state & EP_HALT_PENDING)) {
1579 ep->ep_state |= EP_HALT_PENDING;
1580 ep->stop_cmds_pending++;
1581 ep->stop_cmd_timer.expires = jiffies +
1582 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1583 add_timer(&ep->stop_cmd_timer);
1584 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1585 xhci_ring_cmd_db(xhci);
1588 spin_unlock_irqrestore(&xhci->lock, flags);
1593 xhci_urb_free_priv(xhci, urb_priv);
1594 usb_hcd_unlink_urb_from_ep(hcd, urb);
1595 spin_unlock_irqrestore(&xhci->lock, flags);
1596 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1600 /* Drop an endpoint from a new bandwidth configuration for this device.
1601 * Only one call to this function is allowed per endpoint before
1602 * check_bandwidth() or reset_bandwidth() must be called.
1603 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1604 * add the endpoint to the schedule with possibly new parameters denoted by a
1605 * different endpoint descriptor in usb_host_endpoint.
1606 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1609 * The USB core will not allow URBs to be queued to an endpoint that is being
1610 * disabled, so there's no need for mutual exclusion to protect
1611 * the xhci->devs[slot_id] structure.
1613 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1614 struct usb_host_endpoint *ep)
1616 struct xhci_hcd *xhci;
1617 struct xhci_container_ctx *in_ctx, *out_ctx;
1618 struct xhci_input_control_ctx *ctrl_ctx;
1619 struct xhci_slot_ctx *slot_ctx;
1620 unsigned int last_ctx;
1621 unsigned int ep_index;
1622 struct xhci_ep_ctx *ep_ctx;
1624 u32 new_add_flags, new_drop_flags, new_slot_info;
1627 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1630 xhci = hcd_to_xhci(hcd);
1631 if (xhci->xhc_state & XHCI_STATE_DYING)
1634 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1635 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1636 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1637 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1638 __func__, drop_flag);
1642 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1643 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1644 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1645 ep_index = xhci_get_endpoint_index(&ep->desc);
1646 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1647 /* If the HC already knows the endpoint is disabled,
1648 * or the HCD has noted it is disabled, ignore this request
1650 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1651 cpu_to_le32(EP_STATE_DISABLED)) ||
1652 le32_to_cpu(ctrl_ctx->drop_flags) &
1653 xhci_get_endpoint_flag(&ep->desc)) {
1654 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1659 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1660 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1662 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1663 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1665 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1666 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1667 /* Update the last valid endpoint context, if we deleted the last one */
1668 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1669 LAST_CTX(last_ctx)) {
1670 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1671 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1673 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1675 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1677 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1678 (unsigned int) ep->desc.bEndpointAddress,
1680 (unsigned int) new_drop_flags,
1681 (unsigned int) new_add_flags,
1682 (unsigned int) new_slot_info);
1686 /* Add an endpoint to a new possible bandwidth configuration for this device.
1687 * Only one call to this function is allowed per endpoint before
1688 * check_bandwidth() or reset_bandwidth() must be called.
1689 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1690 * add the endpoint to the schedule with possibly new parameters denoted by a
1691 * different endpoint descriptor in usb_host_endpoint.
1692 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1695 * The USB core will not allow URBs to be queued to an endpoint until the
1696 * configuration or alt setting is installed in the device, so there's no need
1697 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1699 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1700 struct usb_host_endpoint *ep)
1702 struct xhci_hcd *xhci;
1703 struct xhci_container_ctx *in_ctx, *out_ctx;
1704 unsigned int ep_index;
1705 struct xhci_ep_ctx *ep_ctx;
1706 struct xhci_slot_ctx *slot_ctx;
1707 struct xhci_input_control_ctx *ctrl_ctx;
1709 unsigned int last_ctx;
1710 u32 new_add_flags, new_drop_flags, new_slot_info;
1711 struct xhci_virt_device *virt_dev;
1714 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1716 /* So we won't queue a reset ep command for a root hub */
1720 xhci = hcd_to_xhci(hcd);
1721 if (xhci->xhc_state & XHCI_STATE_DYING)
1724 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1725 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1726 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1727 /* FIXME when we have to issue an evaluate endpoint command to
1728 * deal with ep0 max packet size changing once we get the
1731 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1732 __func__, added_ctxs);
1736 virt_dev = xhci->devs[udev->slot_id];
1737 in_ctx = virt_dev->in_ctx;
1738 out_ctx = virt_dev->out_ctx;
1739 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1740 ep_index = xhci_get_endpoint_index(&ep->desc);
1741 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1743 /* If this endpoint is already in use, and the upper layers are trying
1744 * to add it again without dropping it, reject the addition.
1746 if (virt_dev->eps[ep_index].ring &&
1747 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1748 xhci_get_endpoint_flag(&ep->desc))) {
1749 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1750 "without dropping it.\n",
1751 (unsigned int) ep->desc.bEndpointAddress);
1755 /* If the HCD has already noted the endpoint is enabled,
1756 * ignore this request.
1758 if (le32_to_cpu(ctrl_ctx->add_flags) &
1759 xhci_get_endpoint_flag(&ep->desc)) {
1760 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1766 * Configuration and alternate setting changes must be done in
1767 * process context, not interrupt context (or so documenation
1768 * for usb_set_interface() and usb_set_configuration() claim).
1770 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1771 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1772 __func__, ep->desc.bEndpointAddress);
1776 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1777 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1779 /* If xhci_endpoint_disable() was called for this endpoint, but the
1780 * xHC hasn't been notified yet through the check_bandwidth() call,
1781 * this re-adds a new state for the endpoint from the new endpoint
1782 * descriptors. We must drop and re-add this endpoint, so we leave the
1785 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1787 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1788 /* Update the last valid endpoint context, if we just added one past */
1789 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1790 LAST_CTX(last_ctx)) {
1791 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1792 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1794 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1796 /* Store the usb_device pointer for later use */
1799 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1800 (unsigned int) ep->desc.bEndpointAddress,
1802 (unsigned int) new_drop_flags,
1803 (unsigned int) new_add_flags,
1804 (unsigned int) new_slot_info);
1808 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1810 struct xhci_input_control_ctx *ctrl_ctx;
1811 struct xhci_ep_ctx *ep_ctx;
1812 struct xhci_slot_ctx *slot_ctx;
1815 /* When a device's add flag and drop flag are zero, any subsequent
1816 * configure endpoint command will leave that endpoint's state
1817 * untouched. Make sure we don't leave any old state in the input
1818 * endpoint contexts.
1820 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1821 ctrl_ctx->drop_flags = 0;
1822 ctrl_ctx->add_flags = 0;
1823 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1824 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1825 /* Endpoint 0 is always valid */
1826 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1827 for (i = 1; i < 31; ++i) {
1828 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1829 ep_ctx->ep_info = 0;
1830 ep_ctx->ep_info2 = 0;
1832 ep_ctx->tx_info = 0;
1836 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1837 struct usb_device *udev, u32 *cmd_status)
1841 switch (*cmd_status) {
1843 dev_warn(&udev->dev, "Not enough host controller resources "
1844 "for new device state.\n");
1846 /* FIXME: can we allocate more resources for the HC? */
1849 case COMP_2ND_BW_ERR:
1850 dev_warn(&udev->dev, "Not enough bandwidth "
1851 "for new device state.\n");
1853 /* FIXME: can we go back to the old state? */
1856 /* the HCD set up something wrong */
1857 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1859 "and endpoint is not disabled.\n");
1863 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1864 "configure command.\n");
1868 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1872 xhci_err(xhci, "ERROR: unexpected command completion "
1873 "code 0x%x.\n", *cmd_status);
1880 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1881 struct usb_device *udev, u32 *cmd_status)
1884 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1886 switch (*cmd_status) {
1888 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1889 "context command.\n");
1893 dev_warn(&udev->dev, "WARN: slot not enabled for"
1894 "evaluate context command.\n");
1895 case COMP_CTX_STATE:
1896 dev_warn(&udev->dev, "WARN: invalid context state for "
1897 "evaluate context command.\n");
1898 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1902 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1903 "context command.\n");
1907 /* Max Exit Latency too large error */
1908 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1912 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1916 xhci_err(xhci, "ERROR: unexpected command completion "
1917 "code 0x%x.\n", *cmd_status);
1924 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1925 struct xhci_container_ctx *in_ctx)
1927 struct xhci_input_control_ctx *ctrl_ctx;
1928 u32 valid_add_flags;
1929 u32 valid_drop_flags;
1931 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1932 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1933 * (bit 1). The default control endpoint is added during the Address
1934 * Device command and is never removed until the slot is disabled.
1936 valid_add_flags = ctrl_ctx->add_flags >> 2;
1937 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1939 /* Use hweight32 to count the number of ones in the add flags, or
1940 * number of endpoints added. Don't count endpoints that are changed
1941 * (both added and dropped).
1943 return hweight32(valid_add_flags) -
1944 hweight32(valid_add_flags & valid_drop_flags);
1947 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1948 struct xhci_container_ctx *in_ctx)
1950 struct xhci_input_control_ctx *ctrl_ctx;
1951 u32 valid_add_flags;
1952 u32 valid_drop_flags;
1954 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1955 valid_add_flags = ctrl_ctx->add_flags >> 2;
1956 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1958 return hweight32(valid_drop_flags) -
1959 hweight32(valid_add_flags & valid_drop_flags);
1963 * We need to reserve the new number of endpoints before the configure endpoint
1964 * command completes. We can't subtract the dropped endpoints from the number
1965 * of active endpoints until the command completes because we can oversubscribe
1966 * the host in this case:
1968 * - the first configure endpoint command drops more endpoints than it adds
1969 * - a second configure endpoint command that adds more endpoints is queued
1970 * - the first configure endpoint command fails, so the config is unchanged
1971 * - the second command may succeed, even though there isn't enough resources
1973 * Must be called with xhci->lock held.
1975 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1976 struct xhci_container_ctx *in_ctx)
1980 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1981 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1982 xhci_dbg(xhci, "Not enough ep ctxs: "
1983 "%u active, need to add %u, limit is %u.\n",
1984 xhci->num_active_eps, added_eps,
1985 xhci->limit_active_eps);
1988 xhci->num_active_eps += added_eps;
1989 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1990 xhci->num_active_eps);
1995 * The configure endpoint was failed by the xHC for some other reason, so we
1996 * need to revert the resources that failed configuration would have used.
1998 * Must be called with xhci->lock held.
2000 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2001 struct xhci_container_ctx *in_ctx)
2005 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
2006 xhci->num_active_eps -= num_failed_eps;
2007 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
2009 xhci->num_active_eps);
2013 * Now that the command has completed, clean up the active endpoint count by
2014 * subtracting out the endpoints that were dropped (but not changed).
2016 * Must be called with xhci->lock held.
2018 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2019 struct xhci_container_ctx *in_ctx)
2021 u32 num_dropped_eps;
2023 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
2024 xhci->num_active_eps -= num_dropped_eps;
2025 if (num_dropped_eps)
2026 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
2028 xhci->num_active_eps);
2031 unsigned int xhci_get_block_size(struct usb_device *udev)
2033 switch (udev->speed) {
2035 case USB_SPEED_FULL:
2037 case USB_SPEED_HIGH:
2039 case USB_SPEED_SUPER:
2041 case USB_SPEED_UNKNOWN:
2042 case USB_SPEED_WIRELESS:
2044 /* Should never happen */
2049 unsigned int xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2051 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2053 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2058 /* If we are changing a LS/FS device under a HS hub,
2059 * make sure (if we are activating a new TT) that the HS bus has enough
2060 * bandwidth for this new TT.
2062 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2063 struct xhci_virt_device *virt_dev,
2066 struct xhci_interval_bw_table *bw_table;
2067 struct xhci_tt_bw_info *tt_info;
2069 /* Find the bandwidth table for the root port this TT is attached to. */
2070 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2071 tt_info = virt_dev->tt_info;
2072 /* If this TT already had active endpoints, the bandwidth for this TT
2073 * has already been added. Removing all periodic endpoints (and thus
2074 * making the TT enactive) will only decrease the bandwidth used.
2078 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2079 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2083 /* Not sure why we would have no new active endpoints...
2085 * Maybe because of an Evaluate Context change for a hub update or a
2086 * control endpoint 0 max packet size change?
2087 * FIXME: skip the bandwidth calculation in that case.
2092 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2093 struct xhci_virt_device *virt_dev)
2095 unsigned int bw_reserved;
2097 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2098 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2101 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2102 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2109 * This algorithm is a very conservative estimate of the worst-case scheduling
2110 * scenario for any one interval. The hardware dynamically schedules the
2111 * packets, so we can't tell which microframe could be the limiting factor in
2112 * the bandwidth scheduling. This only takes into account periodic endpoints.
2114 * Obviously, we can't solve an NP complete problem to find the minimum worst
2115 * case scenario. Instead, we come up with an estimate that is no less than
2116 * the worst case bandwidth used for any one microframe, but may be an
2119 * We walk the requirements for each endpoint by interval, starting with the
2120 * smallest interval, and place packets in the schedule where there is only one
2121 * possible way to schedule packets for that interval. In order to simplify
2122 * this algorithm, we record the largest max packet size for each interval, and
2123 * assume all packets will be that size.
2125 * For interval 0, we obviously must schedule all packets for each interval.
2126 * The bandwidth for interval 0 is just the amount of data to be transmitted
2127 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2128 * the number of packets).
2130 * For interval 1, we have two possible microframes to schedule those packets
2131 * in. For this algorithm, if we can schedule the same number of packets for
2132 * each possible scheduling opportunity (each microframe), we will do so. The
2133 * remaining number of packets will be saved to be transmitted in the gaps in
2134 * the next interval's scheduling sequence.
2136 * As we move those remaining packets to be scheduled with interval 2 packets,
2137 * we have to double the number of remaining packets to transmit. This is
2138 * because the intervals are actually powers of 2, and we would be transmitting
2139 * the previous interval's packets twice in this interval. We also have to be
2140 * sure that when we look at the largest max packet size for this interval, we
2141 * also look at the largest max packet size for the remaining packets and take
2142 * the greater of the two.
2144 * The algorithm continues to evenly distribute packets in each scheduling
2145 * opportunity, and push the remaining packets out, until we get to the last
2146 * interval. Then those packets and their associated overhead are just added
2147 * to the bandwidth used.
2149 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2150 struct xhci_virt_device *virt_dev,
2153 unsigned int bw_reserved;
2154 unsigned int max_bandwidth;
2155 unsigned int bw_used;
2156 unsigned int block_size;
2157 struct xhci_interval_bw_table *bw_table;
2158 unsigned int packet_size = 0;
2159 unsigned int overhead = 0;
2160 unsigned int packets_transmitted = 0;
2161 unsigned int packets_remaining = 0;
2164 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2165 return xhci_check_ss_bw(xhci, virt_dev);
2167 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2168 max_bandwidth = HS_BW_LIMIT;
2169 /* Convert percent of bus BW reserved to blocks reserved */
2170 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2172 max_bandwidth = FS_BW_LIMIT;
2173 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2176 bw_table = virt_dev->bw_table;
2177 /* We need to translate the max packet size and max ESIT payloads into
2178 * the units the hardware uses.
2180 block_size = xhci_get_block_size(virt_dev->udev);
2182 /* If we are manipulating a LS/FS device under a HS hub, double check
2183 * that the HS bus has enough bandwidth if we are activing a new TT.
2185 if (virt_dev->tt_info) {
2186 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2187 virt_dev->real_port);
2188 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2189 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2190 "newly activated TT.\n");
2193 xhci_dbg(xhci, "Recalculating BW for TT slot %u port %u\n",
2194 virt_dev->tt_info->slot_id,
2195 virt_dev->tt_info->ttport);
2197 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2198 virt_dev->real_port);
2201 /* Add in how much bandwidth will be used for interval zero, or the
2202 * rounded max ESIT payload + number of packets * largest overhead.
2204 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2205 bw_table->interval_bw[0].num_packets *
2206 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2208 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2209 unsigned int bw_added;
2210 unsigned int largest_mps;
2211 unsigned int interval_overhead;
2214 * How many packets could we transmit in this interval?
2215 * If packets didn't fit in the previous interval, we will need
2216 * to transmit that many packets twice within this interval.
2218 packets_remaining = 2 * packets_remaining +
2219 bw_table->interval_bw[i].num_packets;
2221 /* Find the largest max packet size of this or the previous
2224 if (list_empty(&bw_table->interval_bw[i].endpoints))
2227 struct xhci_virt_ep *virt_ep;
2228 struct list_head *ep_entry;
2230 ep_entry = bw_table->interval_bw[i].endpoints.next;
2231 virt_ep = list_entry(ep_entry,
2232 struct xhci_virt_ep, bw_endpoint_list);
2233 /* Convert to blocks, rounding up */
2234 largest_mps = DIV_ROUND_UP(
2235 virt_ep->bw_info.max_packet_size,
2238 if (largest_mps > packet_size)
2239 packet_size = largest_mps;
2241 /* Use the larger overhead of this or the previous interval. */
2242 interval_overhead = xhci_get_largest_overhead(
2243 &bw_table->interval_bw[i]);
2244 if (interval_overhead > overhead)
2245 overhead = interval_overhead;
2247 /* How many packets can we evenly distribute across
2248 * (1 << (i + 1)) possible scheduling opportunities?
2250 packets_transmitted = packets_remaining >> (i + 1);
2252 /* Add in the bandwidth used for those scheduled packets */
2253 bw_added = packets_transmitted * (overhead + packet_size);
2255 /* How many packets do we have remaining to transmit? */
2256 packets_remaining = packets_remaining % (1 << (i + 1));
2258 /* What largest max packet size should those packets have? */
2259 /* If we've transmitted all packets, don't carry over the
2260 * largest packet size.
2262 if (packets_remaining == 0) {
2265 } else if (packets_transmitted > 0) {
2266 /* Otherwise if we do have remaining packets, and we've
2267 * scheduled some packets in this interval, take the
2268 * largest max packet size from endpoints with this
2271 packet_size = largest_mps;
2272 overhead = interval_overhead;
2274 /* Otherwise carry over packet_size and overhead from the last
2275 * time we had a remainder.
2277 bw_used += bw_added;
2278 if (bw_used > max_bandwidth) {
2279 xhci_warn(xhci, "Not enough bandwidth. "
2280 "Proposed: %u, Max: %u\n",
2281 bw_used, max_bandwidth);
2286 * Ok, we know we have some packets left over after even-handedly
2287 * scheduling interval 15. We don't know which microframes they will
2288 * fit into, so we over-schedule and say they will be scheduled every
2291 if (packets_remaining > 0)
2292 bw_used += overhead + packet_size;
2294 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2295 unsigned int port_index = virt_dev->real_port - 1;
2297 /* OK, we're manipulating a HS device attached to a
2298 * root port bandwidth domain. Include the number of active TTs
2299 * in the bandwidth used.
2301 bw_used += TT_HS_OVERHEAD *
2302 xhci->rh_bw[port_index].num_active_tts;
2305 xhci_dbg(xhci, "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2306 "Available: %u " "percent\n",
2307 bw_used, max_bandwidth, bw_reserved,
2308 (max_bandwidth - bw_used - bw_reserved) * 100 /
2311 bw_used += bw_reserved;
2312 if (bw_used > max_bandwidth) {
2313 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2314 bw_used, max_bandwidth);
2318 bw_table->bw_used = bw_used;
2322 static bool xhci_is_async_ep(unsigned int ep_type)
2324 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2325 ep_type != ISOC_IN_EP &&
2326 ep_type != INT_IN_EP);
2329 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2331 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2334 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2336 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2338 if (ep_bw->ep_interval == 0)
2339 return SS_OVERHEAD_BURST +
2340 (ep_bw->mult * ep_bw->num_packets *
2341 (SS_OVERHEAD + mps));
2342 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2343 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2344 1 << ep_bw->ep_interval);
2348 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2349 struct xhci_bw_info *ep_bw,
2350 struct xhci_interval_bw_table *bw_table,
2351 struct usb_device *udev,
2352 struct xhci_virt_ep *virt_ep,
2353 struct xhci_tt_bw_info *tt_info)
2355 struct xhci_interval_bw *interval_bw;
2356 int normalized_interval;
2358 if (xhci_is_async_ep(ep_bw->type))
2361 if (udev->speed == USB_SPEED_SUPER) {
2362 if (xhci_is_sync_in_ep(ep_bw->type))
2363 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2364 xhci_get_ss_bw_consumed(ep_bw);
2366 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2367 xhci_get_ss_bw_consumed(ep_bw);
2371 /* SuperSpeed endpoints never get added to intervals in the table, so
2372 * this check is only valid for HS/FS/LS devices.
2374 if (list_empty(&virt_ep->bw_endpoint_list))
2376 /* For LS/FS devices, we need to translate the interval expressed in
2377 * microframes to frames.
2379 if (udev->speed == USB_SPEED_HIGH)
2380 normalized_interval = ep_bw->ep_interval;
2382 normalized_interval = ep_bw->ep_interval - 3;
2384 if (normalized_interval == 0)
2385 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2386 interval_bw = &bw_table->interval_bw[normalized_interval];
2387 interval_bw->num_packets -= ep_bw->num_packets;
2388 switch (udev->speed) {
2390 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2392 case USB_SPEED_FULL:
2393 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2395 case USB_SPEED_HIGH:
2396 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2398 case USB_SPEED_SUPER:
2399 case USB_SPEED_UNKNOWN:
2400 case USB_SPEED_WIRELESS:
2401 /* Should never happen because only LS/FS/HS endpoints will get
2402 * added to the endpoint list.
2407 tt_info->active_eps -= 1;
2408 list_del_init(&virt_ep->bw_endpoint_list);
2411 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2412 struct xhci_bw_info *ep_bw,
2413 struct xhci_interval_bw_table *bw_table,
2414 struct usb_device *udev,
2415 struct xhci_virt_ep *virt_ep,
2416 struct xhci_tt_bw_info *tt_info)
2418 struct xhci_interval_bw *interval_bw;
2419 struct xhci_virt_ep *smaller_ep;
2420 int normalized_interval;
2422 if (xhci_is_async_ep(ep_bw->type))
2425 if (udev->speed == USB_SPEED_SUPER) {
2426 if (xhci_is_sync_in_ep(ep_bw->type))
2427 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2428 xhci_get_ss_bw_consumed(ep_bw);
2430 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2431 xhci_get_ss_bw_consumed(ep_bw);
2435 /* For LS/FS devices, we need to translate the interval expressed in
2436 * microframes to frames.
2438 if (udev->speed == USB_SPEED_HIGH)
2439 normalized_interval = ep_bw->ep_interval;
2441 normalized_interval = ep_bw->ep_interval - 3;
2443 if (normalized_interval == 0)
2444 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2445 interval_bw = &bw_table->interval_bw[normalized_interval];
2446 interval_bw->num_packets += ep_bw->num_packets;
2447 switch (udev->speed) {
2449 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2451 case USB_SPEED_FULL:
2452 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2454 case USB_SPEED_HIGH:
2455 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2457 case USB_SPEED_SUPER:
2458 case USB_SPEED_UNKNOWN:
2459 case USB_SPEED_WIRELESS:
2460 /* Should never happen because only LS/FS/HS endpoints will get
2461 * added to the endpoint list.
2467 tt_info->active_eps += 1;
2468 /* Insert the endpoint into the list, largest max packet size first. */
2469 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2471 if (ep_bw->max_packet_size >=
2472 smaller_ep->bw_info.max_packet_size) {
2473 /* Add the new ep before the smaller endpoint */
2474 list_add_tail(&virt_ep->bw_endpoint_list,
2475 &smaller_ep->bw_endpoint_list);
2479 /* Add the new endpoint at the end of the list. */
2480 list_add_tail(&virt_ep->bw_endpoint_list,
2481 &interval_bw->endpoints);
2484 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2485 struct xhci_virt_device *virt_dev,
2488 struct xhci_root_port_bw_info *rh_bw_info;
2489 if (!virt_dev->tt_info)
2492 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2493 if (old_active_eps == 0 &&
2494 virt_dev->tt_info->active_eps != 0) {
2495 rh_bw_info->num_active_tts += 1;
2496 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2497 } else if (old_active_eps != 0 &&
2498 virt_dev->tt_info->active_eps == 0) {
2499 rh_bw_info->num_active_tts -= 1;
2500 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2504 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2505 struct xhci_virt_device *virt_dev,
2506 struct xhci_container_ctx *in_ctx)
2508 struct xhci_bw_info ep_bw_info[31];
2510 struct xhci_input_control_ctx *ctrl_ctx;
2511 int old_active_eps = 0;
2513 if (virt_dev->tt_info)
2514 old_active_eps = virt_dev->tt_info->active_eps;
2516 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2518 for (i = 0; i < 31; i++) {
2519 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2522 /* Make a copy of the BW info in case we need to revert this */
2523 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2524 sizeof(ep_bw_info[i]));
2525 /* Drop the endpoint from the interval table if the endpoint is
2526 * being dropped or changed.
2528 if (EP_IS_DROPPED(ctrl_ctx, i))
2529 xhci_drop_ep_from_interval_table(xhci,
2530 &virt_dev->eps[i].bw_info,
2536 /* Overwrite the information stored in the endpoints' bw_info */
2537 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2538 for (i = 0; i < 31; i++) {
2539 /* Add any changed or added endpoints to the interval table */
2540 if (EP_IS_ADDED(ctrl_ctx, i))
2541 xhci_add_ep_to_interval_table(xhci,
2542 &virt_dev->eps[i].bw_info,
2549 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2550 /* Ok, this fits in the bandwidth we have.
2551 * Update the number of active TTs.
2553 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2557 /* We don't have enough bandwidth for this, revert the stored info. */
2558 for (i = 0; i < 31; i++) {
2559 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2562 /* Drop the new copies of any added or changed endpoints from
2563 * the interval table.
2565 if (EP_IS_ADDED(ctrl_ctx, i)) {
2566 xhci_drop_ep_from_interval_table(xhci,
2567 &virt_dev->eps[i].bw_info,
2573 /* Revert the endpoint back to its old information */
2574 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2575 sizeof(ep_bw_info[i]));
2576 /* Add any changed or dropped endpoints back into the table */
2577 if (EP_IS_DROPPED(ctrl_ctx, i))
2578 xhci_add_ep_to_interval_table(xhci,
2579 &virt_dev->eps[i].bw_info,
2589 /* Issue a configure endpoint command or evaluate context command
2590 * and wait for it to finish.
2592 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2593 struct usb_device *udev,
2594 struct xhci_command *command,
2595 bool ctx_change, bool must_succeed)
2599 unsigned long flags;
2600 struct xhci_container_ctx *in_ctx;
2601 struct completion *cmd_completion;
2603 struct xhci_virt_device *virt_dev;
2604 union xhci_trb *cmd_trb;
2606 spin_lock_irqsave(&xhci->lock, flags);
2607 virt_dev = xhci->devs[udev->slot_id];
2610 in_ctx = command->in_ctx;
2612 in_ctx = virt_dev->in_ctx;
2614 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2615 xhci_reserve_host_resources(xhci, in_ctx)) {
2616 spin_unlock_irqrestore(&xhci->lock, flags);
2617 xhci_warn(xhci, "Not enough host resources, "
2618 "active endpoint contexts = %u\n",
2619 xhci->num_active_eps);
2622 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2623 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2624 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2625 xhci_free_host_resources(xhci, in_ctx);
2626 spin_unlock_irqrestore(&xhci->lock, flags);
2627 xhci_warn(xhci, "Not enough bandwidth\n");
2632 cmd_completion = command->completion;
2633 cmd_status = &command->status;
2634 command->command_trb = xhci->cmd_ring->enqueue;
2636 /* Enqueue pointer can be left pointing to the link TRB,
2637 * we must handle that
2639 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
2640 command->command_trb =
2641 xhci->cmd_ring->enq_seg->next->trbs;
2643 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2645 cmd_completion = &virt_dev->cmd_completion;
2646 cmd_status = &virt_dev->cmd_status;
2648 init_completion(cmd_completion);
2650 cmd_trb = xhci->cmd_ring->dequeue;
2652 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2653 udev->slot_id, must_succeed);
2655 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
2659 list_del(&command->cmd_list);
2660 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2661 xhci_free_host_resources(xhci, in_ctx);
2662 spin_unlock_irqrestore(&xhci->lock, flags);
2663 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
2666 xhci_ring_cmd_db(xhci);
2667 spin_unlock_irqrestore(&xhci->lock, flags);
2669 /* Wait for the configure endpoint command to complete */
2670 timeleft = wait_for_completion_interruptible_timeout(
2672 XHCI_CMD_DEFAULT_TIMEOUT);
2673 if (timeleft <= 0) {
2674 xhci_warn(xhci, "%s while waiting for %s command\n",
2675 timeleft == 0 ? "Timeout" : "Signal",
2677 "configure endpoint" :
2678 "evaluate context");
2679 /* cancel the configure endpoint command */
2680 ret = xhci_cancel_cmd(xhci, command, cmd_trb);
2687 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2689 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2691 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2692 spin_lock_irqsave(&xhci->lock, flags);
2693 /* If the command failed, remove the reserved resources.
2694 * Otherwise, clean up the estimate to include dropped eps.
2697 xhci_free_host_resources(xhci, in_ctx);
2699 xhci_finish_resource_reservation(xhci, in_ctx);
2700 spin_unlock_irqrestore(&xhci->lock, flags);
2705 /* Called after one or more calls to xhci_add_endpoint() or
2706 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2707 * to call xhci_reset_bandwidth().
2709 * Since we are in the middle of changing either configuration or
2710 * installing a new alt setting, the USB core won't allow URBs to be
2711 * enqueued for any endpoint on the old config or interface. Nothing
2712 * else should be touching the xhci->devs[slot_id] structure, so we
2713 * don't need to take the xhci->lock for manipulating that.
2715 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2719 struct xhci_hcd *xhci;
2720 struct xhci_virt_device *virt_dev;
2721 struct xhci_input_control_ctx *ctrl_ctx;
2722 struct xhci_slot_ctx *slot_ctx;
2724 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2727 xhci = hcd_to_xhci(hcd);
2728 if (xhci->xhc_state & XHCI_STATE_DYING)
2731 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2732 virt_dev = xhci->devs[udev->slot_id];
2734 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2735 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2736 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2737 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2738 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2740 /* Don't issue the command if there's no endpoints to update. */
2741 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2742 ctrl_ctx->drop_flags == 0)
2745 xhci_dbg(xhci, "New Input Control Context:\n");
2746 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2747 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2748 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2750 ret = xhci_configure_endpoint(xhci, udev, NULL,
2753 /* Callee should call reset_bandwidth() */
2757 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2758 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2759 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2761 /* Free any rings that were dropped, but not changed. */
2762 for (i = 1; i < 31; ++i) {
2763 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2764 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
2765 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2767 xhci_zero_in_ctx(xhci, virt_dev);
2769 * Install any rings for completely new endpoints or changed endpoints,
2770 * and free or cache any old rings from changed endpoints.
2772 for (i = 1; i < 31; ++i) {
2773 if (!virt_dev->eps[i].new_ring)
2775 /* Only cache or free the old ring if it exists.
2776 * It may not if this is the first add of an endpoint.
2778 if (virt_dev->eps[i].ring) {
2779 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2781 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2782 virt_dev->eps[i].new_ring = NULL;
2788 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2790 struct xhci_hcd *xhci;
2791 struct xhci_virt_device *virt_dev;
2794 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2797 xhci = hcd_to_xhci(hcd);
2799 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2800 virt_dev = xhci->devs[udev->slot_id];
2801 /* Free any rings allocated for added endpoints */
2802 for (i = 0; i < 31; ++i) {
2803 if (virt_dev->eps[i].new_ring) {
2804 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2805 virt_dev->eps[i].new_ring = NULL;
2808 xhci_zero_in_ctx(xhci, virt_dev);
2811 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2812 struct xhci_container_ctx *in_ctx,
2813 struct xhci_container_ctx *out_ctx,
2814 u32 add_flags, u32 drop_flags)
2816 struct xhci_input_control_ctx *ctrl_ctx;
2817 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2818 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2819 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2820 xhci_slot_copy(xhci, in_ctx, out_ctx);
2821 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2823 xhci_dbg(xhci, "Input Context:\n");
2824 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2827 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2828 unsigned int slot_id, unsigned int ep_index,
2829 struct xhci_dequeue_state *deq_state)
2831 struct xhci_container_ctx *in_ctx;
2832 struct xhci_ep_ctx *ep_ctx;
2836 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2837 xhci->devs[slot_id]->out_ctx, ep_index);
2838 in_ctx = xhci->devs[slot_id]->in_ctx;
2839 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2840 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2841 deq_state->new_deq_ptr);
2843 xhci_warn(xhci, "WARN Cannot submit config ep after "
2844 "reset ep command\n");
2845 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2846 deq_state->new_deq_seg,
2847 deq_state->new_deq_ptr);
2850 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2852 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2853 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2854 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
2857 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2858 struct usb_device *udev, unsigned int ep_index)
2860 struct xhci_dequeue_state deq_state;
2861 struct xhci_virt_ep *ep;
2863 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
2864 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2865 /* We need to move the HW's dequeue pointer past this TD,
2866 * or it will attempt to resend it on the next doorbell ring.
2868 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2869 ep_index, ep->stopped_stream, ep->stopped_td,
2872 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2875 /* HW with the reset endpoint quirk will use the saved dequeue state to
2876 * issue a configure endpoint command later.
2878 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2879 xhci_dbg(xhci, "Queueing new dequeue state\n");
2880 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2881 ep_index, ep->stopped_stream, &deq_state);
2883 /* Better hope no one uses the input context between now and the
2884 * reset endpoint completion!
2885 * XXX: No idea how this hardware will react when stream rings
2888 xhci_dbg(xhci, "Setting up input context for "
2889 "configure endpoint command\n");
2890 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2891 ep_index, &deq_state);
2895 /* Called when clearing halted device. The core should have sent the control
2896 * message to clear the device halt condition. The host side of the halt should
2897 * already be cleared with a reset endpoint command issued when the STALL tx
2898 * event was received.
2900 * Context: in_interrupt
2903 void xhci_endpoint_reset(struct usb_hcd *hcd,
2904 struct usb_host_endpoint *ep)
2906 struct xhci_hcd *xhci;
2908 xhci = hcd_to_xhci(hcd);
2911 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2912 * The Reset Endpoint Command may only be issued to endpoints in the
2913 * Halted state. If software wishes reset the Data Toggle or Sequence
2914 * Number of an endpoint that isn't in the Halted state, then software
2915 * may issue a Configure Endpoint Command with the Drop and Add bits set
2916 * for the target endpoint. that is in the Stopped state.
2919 /* For now just print debug to follow the situation */
2920 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2921 ep->desc.bEndpointAddress);
2924 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2925 struct usb_device *udev, struct usb_host_endpoint *ep,
2926 unsigned int slot_id)
2929 unsigned int ep_index;
2930 unsigned int ep_state;
2934 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2937 if (ep->ss_ep_comp.bmAttributes == 0) {
2938 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2939 " descriptor for ep 0x%x does not support streams\n",
2940 ep->desc.bEndpointAddress);
2944 ep_index = xhci_get_endpoint_index(&ep->desc);
2945 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2946 if (ep_state & EP_HAS_STREAMS ||
2947 ep_state & EP_GETTING_STREAMS) {
2948 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2949 "already has streams set up.\n",
2950 ep->desc.bEndpointAddress);
2951 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2952 "dynamic stream context array reallocation.\n");
2955 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2956 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2957 "endpoint 0x%x; URBs are pending.\n",
2958 ep->desc.bEndpointAddress);
2964 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2965 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2967 unsigned int max_streams;
2969 /* The stream context array size must be a power of two */
2970 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2972 * Find out how many primary stream array entries the host controller
2973 * supports. Later we may use secondary stream arrays (similar to 2nd
2974 * level page entries), but that's an optional feature for xHCI host
2975 * controllers. xHCs must support at least 4 stream IDs.
2977 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2978 if (*num_stream_ctxs > max_streams) {
2979 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2981 *num_stream_ctxs = max_streams;
2982 *num_streams = max_streams;
2986 /* Returns an error code if one of the endpoint already has streams.
2987 * This does not change any data structures, it only checks and gathers
2990 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2991 struct usb_device *udev,
2992 struct usb_host_endpoint **eps, unsigned int num_eps,
2993 unsigned int *num_streams, u32 *changed_ep_bitmask)
2995 unsigned int max_streams;
2996 unsigned int endpoint_flag;
3000 for (i = 0; i < num_eps; i++) {
3001 ret = xhci_check_streams_endpoint(xhci, udev,
3002 eps[i], udev->slot_id);
3006 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3007 if (max_streams < (*num_streams - 1)) {
3008 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3009 eps[i]->desc.bEndpointAddress,
3011 *num_streams = max_streams+1;
3014 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3015 if (*changed_ep_bitmask & endpoint_flag)
3017 *changed_ep_bitmask |= endpoint_flag;
3022 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3023 struct usb_device *udev,
3024 struct usb_host_endpoint **eps, unsigned int num_eps)
3026 u32 changed_ep_bitmask = 0;
3027 unsigned int slot_id;
3028 unsigned int ep_index;
3029 unsigned int ep_state;
3032 slot_id = udev->slot_id;
3033 if (!xhci->devs[slot_id])
3036 for (i = 0; i < num_eps; i++) {
3037 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3038 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3039 /* Are streams already being freed for the endpoint? */
3040 if (ep_state & EP_GETTING_NO_STREAMS) {
3041 xhci_warn(xhci, "WARN Can't disable streams for "
3043 "streams are being disabled already.",
3044 eps[i]->desc.bEndpointAddress);
3047 /* Are there actually any streams to free? */
3048 if (!(ep_state & EP_HAS_STREAMS) &&
3049 !(ep_state & EP_GETTING_STREAMS)) {
3050 xhci_warn(xhci, "WARN Can't disable streams for "
3052 "streams are already disabled!",
3053 eps[i]->desc.bEndpointAddress);
3054 xhci_warn(xhci, "WARN xhci_free_streams() called "
3055 "with non-streams endpoint\n");
3058 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3060 return changed_ep_bitmask;
3064 * The USB device drivers use this function (though the HCD interface in USB
3065 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3066 * coordinate mass storage command queueing across multiple endpoints (basically
3067 * a stream ID == a task ID).
3069 * Setting up streams involves allocating the same size stream context array
3070 * for each endpoint and issuing a configure endpoint command for all endpoints.
3072 * Don't allow the call to succeed if one endpoint only supports one stream
3073 * (which means it doesn't support streams at all).
3075 * Drivers may get less stream IDs than they asked for, if the host controller
3076 * hardware or endpoints claim they can't support the number of requested
3079 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3080 struct usb_host_endpoint **eps, unsigned int num_eps,
3081 unsigned int num_streams, gfp_t mem_flags)
3084 struct xhci_hcd *xhci;
3085 struct xhci_virt_device *vdev;
3086 struct xhci_command *config_cmd;
3087 unsigned int ep_index;
3088 unsigned int num_stream_ctxs;
3089 unsigned long flags;
3090 u32 changed_ep_bitmask = 0;
3095 /* Add one to the number of streams requested to account for
3096 * stream 0 that is reserved for xHCI usage.
3099 xhci = hcd_to_xhci(hcd);
3100 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3103 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3105 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3109 /* Check to make sure all endpoints are not already configured for
3110 * streams. While we're at it, find the maximum number of streams that
3111 * all the endpoints will support and check for duplicate endpoints.
3113 spin_lock_irqsave(&xhci->lock, flags);
3114 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3115 num_eps, &num_streams, &changed_ep_bitmask);
3117 xhci_free_command(xhci, config_cmd);
3118 spin_unlock_irqrestore(&xhci->lock, flags);
3121 if (num_streams <= 1) {
3122 xhci_warn(xhci, "WARN: endpoints can't handle "
3123 "more than one stream.\n");
3124 xhci_free_command(xhci, config_cmd);
3125 spin_unlock_irqrestore(&xhci->lock, flags);
3128 vdev = xhci->devs[udev->slot_id];
3129 /* Mark each endpoint as being in transition, so
3130 * xhci_urb_enqueue() will reject all URBs.
3132 for (i = 0; i < num_eps; i++) {
3133 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3134 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3136 spin_unlock_irqrestore(&xhci->lock, flags);
3138 /* Setup internal data structures and allocate HW data structures for
3139 * streams (but don't install the HW structures in the input context
3140 * until we're sure all memory allocation succeeded).
3142 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3143 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3144 num_stream_ctxs, num_streams);
3146 for (i = 0; i < num_eps; i++) {
3147 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3148 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3150 num_streams, mem_flags);
3151 if (!vdev->eps[ep_index].stream_info)
3153 /* Set maxPstreams in endpoint context and update deq ptr to
3154 * point to stream context array. FIXME
3158 /* Set up the input context for a configure endpoint command. */
3159 for (i = 0; i < num_eps; i++) {
3160 struct xhci_ep_ctx *ep_ctx;
3162 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3163 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3165 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3166 vdev->out_ctx, ep_index);
3167 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3168 vdev->eps[ep_index].stream_info);
3170 /* Tell the HW to drop its old copy of the endpoint context info
3171 * and add the updated copy from the input context.
3173 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3174 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3176 /* Issue and wait for the configure endpoint command */
3177 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3180 /* xHC rejected the configure endpoint command for some reason, so we
3181 * leave the old ring intact and free our internal streams data
3187 spin_lock_irqsave(&xhci->lock, flags);
3188 for (i = 0; i < num_eps; i++) {
3189 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3190 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3191 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3192 udev->slot_id, ep_index);
3193 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3195 xhci_free_command(xhci, config_cmd);
3196 spin_unlock_irqrestore(&xhci->lock, flags);
3198 /* Subtract 1 for stream 0, which drivers can't use */
3199 return num_streams - 1;
3202 /* If it didn't work, free the streams! */
3203 for (i = 0; i < num_eps; i++) {
3204 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3205 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3206 vdev->eps[ep_index].stream_info = NULL;
3207 /* FIXME Unset maxPstreams in endpoint context and
3208 * update deq ptr to point to normal string ring.
3210 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3211 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3212 xhci_endpoint_zero(xhci, vdev, eps[i]);
3214 xhci_free_command(xhci, config_cmd);
3218 /* Transition the endpoint from using streams to being a "normal" endpoint
3221 * Modify the endpoint context state, submit a configure endpoint command,
3222 * and free all endpoint rings for streams if that completes successfully.
3224 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3225 struct usb_host_endpoint **eps, unsigned int num_eps,
3229 struct xhci_hcd *xhci;
3230 struct xhci_virt_device *vdev;
3231 struct xhci_command *command;
3232 unsigned int ep_index;
3233 unsigned long flags;
3234 u32 changed_ep_bitmask;
3236 xhci = hcd_to_xhci(hcd);
3237 vdev = xhci->devs[udev->slot_id];
3239 /* Set up a configure endpoint command to remove the streams rings */
3240 spin_lock_irqsave(&xhci->lock, flags);
3241 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3242 udev, eps, num_eps);
3243 if (changed_ep_bitmask == 0) {
3244 spin_unlock_irqrestore(&xhci->lock, flags);
3248 /* Use the xhci_command structure from the first endpoint. We may have
3249 * allocated too many, but the driver may call xhci_free_streams() for
3250 * each endpoint it grouped into one call to xhci_alloc_streams().
3252 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3253 command = vdev->eps[ep_index].stream_info->free_streams_command;
3254 for (i = 0; i < num_eps; i++) {
3255 struct xhci_ep_ctx *ep_ctx;
3257 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3258 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3259 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3260 EP_GETTING_NO_STREAMS;
3262 xhci_endpoint_copy(xhci, command->in_ctx,
3263 vdev->out_ctx, ep_index);
3264 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3265 &vdev->eps[ep_index]);
3267 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3268 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3269 spin_unlock_irqrestore(&xhci->lock, flags);
3271 /* Issue and wait for the configure endpoint command,
3272 * which must succeed.
3274 ret = xhci_configure_endpoint(xhci, udev, command,
3277 /* xHC rejected the configure endpoint command for some reason, so we
3278 * leave the streams rings intact.
3283 spin_lock_irqsave(&xhci->lock, flags);
3284 for (i = 0; i < num_eps; i++) {
3285 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3286 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3287 vdev->eps[ep_index].stream_info = NULL;
3288 /* FIXME Unset maxPstreams in endpoint context and
3289 * update deq ptr to point to normal string ring.
3291 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3292 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3294 spin_unlock_irqrestore(&xhci->lock, flags);
3300 * Deletes endpoint resources for endpoints that were active before a Reset
3301 * Device command, or a Disable Slot command. The Reset Device command leaves
3302 * the control endpoint intact, whereas the Disable Slot command deletes it.
3304 * Must be called with xhci->lock held.
3306 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3307 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3310 unsigned int num_dropped_eps = 0;
3311 unsigned int drop_flags = 0;
3313 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3314 if (virt_dev->eps[i].ring) {
3315 drop_flags |= 1 << i;
3319 xhci->num_active_eps -= num_dropped_eps;
3320 if (num_dropped_eps)
3321 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
3323 num_dropped_eps, drop_flags,
3324 xhci->num_active_eps);
3328 * This submits a Reset Device Command, which will set the device state to 0,
3329 * set the device address to 0, and disable all the endpoints except the default
3330 * control endpoint. The USB core should come back and call
3331 * xhci_address_device(), and then re-set up the configuration. If this is
3332 * called because of a usb_reset_and_verify_device(), then the old alternate
3333 * settings will be re-installed through the normal bandwidth allocation
3336 * Wait for the Reset Device command to finish. Remove all structures
3337 * associated with the endpoints that were disabled. Clear the input device
3338 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3340 * If the virt_dev to be reset does not exist or does not match the udev,
3341 * it means the device is lost, possibly due to the xHC restore error and
3342 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3343 * re-allocate the device.
3345 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3348 unsigned long flags;
3349 struct xhci_hcd *xhci;
3350 unsigned int slot_id;
3351 struct xhci_virt_device *virt_dev;
3352 struct xhci_command *reset_device_cmd;
3354 int last_freed_endpoint;
3355 struct xhci_slot_ctx *slot_ctx;
3356 int old_active_eps = 0;
3358 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3361 xhci = hcd_to_xhci(hcd);
3362 slot_id = udev->slot_id;
3363 virt_dev = xhci->devs[slot_id];
3365 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3366 "not exist. Re-allocate the device\n", slot_id);
3367 ret = xhci_alloc_dev(hcd, udev);
3374 if (virt_dev->tt_info)
3375 old_active_eps = virt_dev->tt_info->active_eps;
3377 if (virt_dev->udev != udev) {
3378 /* If the virt_dev and the udev does not match, this virt_dev
3379 * may belong to another udev.
3380 * Re-allocate the device.
3382 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3383 "not match the udev. Re-allocate the device\n",
3385 ret = xhci_alloc_dev(hcd, udev);
3392 /* If device is not setup, there is no point in resetting it */
3393 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3394 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3395 SLOT_STATE_DISABLED)
3398 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3399 /* Allocate the command structure that holds the struct completion.
3400 * Assume we're in process context, since the normal device reset
3401 * process has to wait for the device anyway. Storage devices are
3402 * reset as part of error handling, so use GFP_NOIO instead of
3405 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3406 if (!reset_device_cmd) {
3407 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3411 /* Attempt to submit the Reset Device command to the command ring */
3412 spin_lock_irqsave(&xhci->lock, flags);
3413 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
3415 /* Enqueue pointer can be left pointing to the link TRB,
3416 * we must handle that
3418 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
3419 reset_device_cmd->command_trb =
3420 xhci->cmd_ring->enq_seg->next->trbs;
3422 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3423 ret = xhci_queue_reset_device(xhci, slot_id);
3425 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3426 list_del(&reset_device_cmd->cmd_list);
3427 spin_unlock_irqrestore(&xhci->lock, flags);
3428 goto command_cleanup;
3430 xhci_ring_cmd_db(xhci);
3431 spin_unlock_irqrestore(&xhci->lock, flags);
3433 /* Wait for the Reset Device command to finish */
3434 timeleft = wait_for_completion_interruptible_timeout(
3435 reset_device_cmd->completion,
3436 USB_CTRL_SET_TIMEOUT);
3437 if (timeleft <= 0) {
3438 xhci_warn(xhci, "%s while waiting for reset device command\n",
3439 timeleft == 0 ? "Timeout" : "Signal");
3440 spin_lock_irqsave(&xhci->lock, flags);
3441 /* The timeout might have raced with the event ring handler, so
3442 * only delete from the list if the item isn't poisoned.
3444 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3445 list_del(&reset_device_cmd->cmd_list);
3446 spin_unlock_irqrestore(&xhci->lock, flags);
3448 goto command_cleanup;
3451 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3452 * unless we tried to reset a slot ID that wasn't enabled,
3453 * or the device wasn't in the addressed or configured state.
3455 ret = reset_device_cmd->status;
3457 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3458 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3459 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
3461 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3462 xhci_info(xhci, "Not freeing device rings.\n");
3463 /* Don't treat this as an error. May change my mind later. */
3465 goto command_cleanup;
3467 xhci_dbg(xhci, "Successful reset device command.\n");
3470 if (xhci_is_vendor_info_code(xhci, ret))
3472 xhci_warn(xhci, "Unknown completion code %u for "
3473 "reset device command.\n", ret);
3475 goto command_cleanup;
3478 /* Free up host controller endpoint resources */
3479 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3480 spin_lock_irqsave(&xhci->lock, flags);
3481 /* Don't delete the default control endpoint resources */
3482 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3483 spin_unlock_irqrestore(&xhci->lock, flags);
3486 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3487 last_freed_endpoint = 1;
3488 for (i = 1; i < 31; ++i) {
3489 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3491 if (ep->ep_state & EP_HAS_STREAMS) {
3492 xhci_free_stream_info(xhci, ep->stream_info);
3493 ep->stream_info = NULL;
3494 ep->ep_state &= ~EP_HAS_STREAMS;
3498 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3499 last_freed_endpoint = i;
3501 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3502 xhci_drop_ep_from_interval_table(xhci,
3503 &virt_dev->eps[i].bw_info,
3508 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3510 /* If necessary, update the number of active TTs on this root port */
3511 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3513 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3514 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3518 xhci_free_command(xhci, reset_device_cmd);
3523 * At this point, the struct usb_device is about to go away, the device has
3524 * disconnected, and all traffic has been stopped and the endpoints have been
3525 * disabled. Free any HC data structures associated with that device.
3527 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3529 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3530 struct xhci_virt_device *virt_dev;
3531 struct device *dev = hcd->self.controller;
3532 unsigned long flags;
3536 #ifndef CONFIG_USB_DEFAULT_PERSIST
3538 * We called pm_runtime_get_noresume when the device was attached.
3539 * Decrement the counter here to allow controller to runtime suspend
3540 * if no devices remain.
3542 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3543 pm_runtime_put_noidle(dev);
3546 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3547 /* If the host is halted due to driver unload, we still need to free the
3550 if (ret <= 0 && ret != -ENODEV)
3553 virt_dev = xhci->devs[udev->slot_id];
3555 /* Stop any wayward timer functions (which may grab the lock) */
3556 for (i = 0; i < 31; ++i) {
3557 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3558 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3561 if (udev->usb2_hw_lpm_enabled) {
3562 xhci_set_usb2_hardware_lpm(hcd, udev, 0);
3563 udev->usb2_hw_lpm_enabled = 0;
3566 spin_lock_irqsave(&xhci->lock, flags);
3567 /* Don't disable the slot if the host controller is dead. */
3568 state = xhci_readl(xhci, &xhci->op_regs->status);
3569 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3570 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3571 xhci_free_virt_device(xhci, udev->slot_id);
3572 spin_unlock_irqrestore(&xhci->lock, flags);
3576 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3577 spin_unlock_irqrestore(&xhci->lock, flags);
3578 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3581 xhci_ring_cmd_db(xhci);
3582 spin_unlock_irqrestore(&xhci->lock, flags);
3584 * Event command completion handler will free any data structures
3585 * associated with the slot. XXX Can free sleep?
3590 * Checks if we have enough host controller resources for the default control
3593 * Must be called with xhci->lock held.
3595 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3597 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3598 xhci_dbg(xhci, "Not enough ep ctxs: "
3599 "%u active, need to add 1, limit is %u.\n",
3600 xhci->num_active_eps, xhci->limit_active_eps);
3603 xhci->num_active_eps += 1;
3604 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
3605 xhci->num_active_eps);
3611 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3612 * timed out, or allocating memory failed. Returns 1 on success.
3614 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3616 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3617 struct device *dev = hcd->self.controller;
3618 unsigned long flags;
3621 union xhci_trb *cmd_trb;
3623 spin_lock_irqsave(&xhci->lock, flags);
3624 cmd_trb = xhci->cmd_ring->dequeue;
3625 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3627 spin_unlock_irqrestore(&xhci->lock, flags);
3628 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3631 xhci_ring_cmd_db(xhci);
3632 spin_unlock_irqrestore(&xhci->lock, flags);
3634 /* XXX: how much time for xHC slot assignment? */
3635 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3636 XHCI_CMD_DEFAULT_TIMEOUT);
3637 if (timeleft <= 0) {
3638 xhci_warn(xhci, "%s while waiting for a slot\n",
3639 timeleft == 0 ? "Timeout" : "Signal");
3640 /* cancel the enable slot request */
3641 return xhci_cancel_cmd(xhci, NULL, cmd_trb);
3644 if (!xhci->slot_id) {
3645 xhci_err(xhci, "Error while assigning device slot ID\n");
3649 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3650 spin_lock_irqsave(&xhci->lock, flags);
3651 ret = xhci_reserve_host_control_ep_resources(xhci);
3653 spin_unlock_irqrestore(&xhci->lock, flags);
3654 xhci_warn(xhci, "Not enough host resources, "
3655 "active endpoint contexts = %u\n",
3656 xhci->num_active_eps);
3659 spin_unlock_irqrestore(&xhci->lock, flags);
3661 /* Use GFP_NOIO, since this function can be called from
3662 * xhci_discover_or_reset_device(), which may be called as part of
3663 * mass storage driver error handling.
3665 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3666 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3669 udev->slot_id = xhci->slot_id;
3671 #ifndef CONFIG_USB_DEFAULT_PERSIST
3673 * If resetting upon resume, we can't put the controller into runtime
3674 * suspend if there is a device attached.
3676 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3677 pm_runtime_get_noresume(dev);
3680 /* Is this a LS or FS device under a HS hub? */
3681 /* Hub or peripherial? */
3685 /* Disable slot, if we can do it without mem alloc */
3686 spin_lock_irqsave(&xhci->lock, flags);
3687 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3688 xhci_ring_cmd_db(xhci);
3689 spin_unlock_irqrestore(&xhci->lock, flags);
3694 * Issue an Address Device command (which will issue a SetAddress request to
3696 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3697 * we should only issue and wait on one address command at the same time.
3699 * We add one to the device address issued by the hardware because the USB core
3700 * uses address 1 for the root hubs (even though they're not really devices).
3702 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3704 unsigned long flags;
3706 struct xhci_virt_device *virt_dev;
3708 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3709 struct xhci_slot_ctx *slot_ctx;
3710 struct xhci_input_control_ctx *ctrl_ctx;
3712 union xhci_trb *cmd_trb;
3714 if (!udev->slot_id) {
3715 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
3719 virt_dev = xhci->devs[udev->slot_id];
3721 if (WARN_ON(!virt_dev)) {
3723 * In plug/unplug torture test with an NEC controller,
3724 * a zero-dereference was observed once due to virt_dev = 0.
3725 * Print useful debug rather than crash if it is observed again!
3727 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3732 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3734 * If this is the first Set Address since device plug-in or
3735 * virt_device realloaction after a resume with an xHCI power loss,
3736 * then set up the slot context.
3738 if (!slot_ctx->dev_info)
3739 xhci_setup_addressable_virt_dev(xhci, udev);
3740 /* Otherwise, update the control endpoint ring enqueue pointer. */
3742 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3743 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3744 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3745 ctrl_ctx->drop_flags = 0;
3747 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3748 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3750 spin_lock_irqsave(&xhci->lock, flags);
3751 cmd_trb = xhci->cmd_ring->dequeue;
3752 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3755 spin_unlock_irqrestore(&xhci->lock, flags);
3756 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3759 xhci_ring_cmd_db(xhci);
3760 spin_unlock_irqrestore(&xhci->lock, flags);
3762 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3763 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3764 XHCI_CMD_DEFAULT_TIMEOUT);
3765 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3766 * the SetAddress() "recovery interval" required by USB and aborting the
3767 * command on a timeout.
3769 if (timeleft <= 0) {
3770 xhci_warn(xhci, "%s while waiting for address device command\n",
3771 timeleft == 0 ? "Timeout" : "Signal");
3772 /* cancel the address device command */
3773 ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
3779 switch (virt_dev->cmd_status) {
3780 case COMP_CTX_STATE:
3782 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
3787 dev_warn(&udev->dev, "Device not responding to set address.\n");
3791 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
3792 "device command.\n");
3796 xhci_dbg(xhci, "Successful Address Device command\n");
3799 xhci_err(xhci, "ERROR: unexpected command completion "
3800 "code 0x%x.\n", virt_dev->cmd_status);
3801 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3802 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3809 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3810 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
3811 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
3813 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3814 (unsigned long long)
3815 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3816 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
3817 (unsigned long long)virt_dev->out_ctx->dma);
3818 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3819 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3820 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3821 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3823 * USB core uses address 1 for the roothubs, so we add one to the
3824 * address given back to us by the HC.
3826 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3827 /* Use kernel assigned address for devices; store xHC assigned
3828 * address locally. */
3829 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
3831 /* Zero the input context control for later use */
3832 ctrl_ctx->add_flags = 0;
3833 ctrl_ctx->drop_flags = 0;
3835 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
3840 #ifdef CONFIG_USB_SUSPEND
3842 /* BESL to HIRD Encoding array for USB2 LPM */
3843 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3844 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3846 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
3847 static int xhci_calculate_hird_besl(int u2del, bool use_besl)
3852 for (hird = 0; hird < 16; hird++) {
3853 if (xhci_besl_encoding[hird] >= u2del)
3860 hird = (u2del - 51) / 75 + 1;
3869 static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
3870 struct usb_device *udev)
3872 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3873 struct dev_info *dev_info;
3874 __le32 __iomem **port_array;
3875 __le32 __iomem *addr, *pm_addr;
3877 unsigned int port_num;
3878 unsigned long flags;
3882 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
3886 /* we only support lpm for non-hub device connected to root hub yet */
3887 if (!udev->parent || udev->parent->parent ||
3888 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
3891 spin_lock_irqsave(&xhci->lock, flags);
3893 /* Look for devices in lpm_failed_devs list */
3894 dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
3895 le16_to_cpu(udev->descriptor.idProduct);
3896 list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
3897 if (dev_info->dev_id == dev_id) {
3903 port_array = xhci->usb2_ports;
3904 port_num = udev->portnum - 1;
3906 if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
3907 xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
3913 * Test USB 2.0 software LPM.
3914 * FIXME: some xHCI 1.0 hosts may implement a new register to set up
3915 * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
3916 * in the June 2011 errata release.
3918 xhci_dbg(xhci, "test port %d software LPM\n", port_num);
3920 * Set L1 Device Slot and HIRD/BESL.
3921 * Check device's USB 2.0 extension descriptor to determine whether
3922 * HIRD or BESL shoule be used. See USB2.0 LPM errata.
3924 pm_addr = port_array[port_num] + 1;
3925 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3926 if (le32_to_cpu(udev->bos->ext_cap->bmAttributes) & (1 << 2))
3927 hird = xhci_calculate_hird_besl(u2del, 1);
3929 hird = xhci_calculate_hird_besl(u2del, 0);
3931 temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
3932 xhci_writel(xhci, temp, pm_addr);
3934 /* Set port link state to U2(L1) */
3935 addr = port_array[port_num];
3936 xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
3939 spin_unlock_irqrestore(&xhci->lock, flags);
3941 spin_lock_irqsave(&xhci->lock, flags);
3943 /* Check L1 Status */
3944 ret = handshake(xhci, pm_addr, PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
3945 if (ret != -ETIMEDOUT) {
3946 /* enter L1 successfully */
3947 temp = xhci_readl(xhci, addr);
3948 xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
3952 temp = xhci_readl(xhci, pm_addr);
3953 xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
3954 port_num, temp & PORT_L1S_MASK);
3958 /* Resume the port */
3959 xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
3961 spin_unlock_irqrestore(&xhci->lock, flags);
3963 spin_lock_irqsave(&xhci->lock, flags);
3966 xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
3968 /* Check PORTSC to make sure the device is in the right state */
3970 temp = xhci_readl(xhci, addr);
3971 xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
3972 if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
3973 (temp & PORT_PLS_MASK) != XDEV_U0) {
3974 xhci_dbg(xhci, "port L1 resume fail\n");
3980 /* Insert dev to lpm_failed_devs list */
3981 xhci_warn(xhci, "device LPM test failed, may disconnect and "
3983 dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
3988 dev_info->dev_id = dev_id;
3989 INIT_LIST_HEAD(&dev_info->list);
3990 list_add(&dev_info->list, &xhci->lpm_failed_devs);
3992 xhci_ring_device(xhci, udev->slot_id);
3996 spin_unlock_irqrestore(&xhci->lock, flags);
4000 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4001 struct usb_device *udev, int enable)
4003 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4004 __le32 __iomem **port_array;
4005 __le32 __iomem *pm_addr;
4007 unsigned int port_num;
4008 unsigned long flags;
4011 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
4015 if (!udev->parent || udev->parent->parent ||
4016 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4019 if (udev->usb2_hw_lpm_capable != 1)
4022 spin_lock_irqsave(&xhci->lock, flags);
4024 port_array = xhci->usb2_ports;
4025 port_num = udev->portnum - 1;
4026 pm_addr = port_array[port_num] + 1;
4027 temp = xhci_readl(xhci, pm_addr);
4029 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4030 enable ? "enable" : "disable", port_num);
4032 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4033 if (le32_to_cpu(udev->bos->ext_cap->bmAttributes) & (1 << 2))
4034 hird = xhci_calculate_hird_besl(u2del, 1);
4036 hird = xhci_calculate_hird_besl(u2del, 0);
4039 temp &= ~PORT_HIRD_MASK;
4040 temp |= PORT_HIRD(hird) | PORT_RWE;
4041 xhci_writel(xhci, temp, pm_addr);
4042 temp = xhci_readl(xhci, pm_addr);
4044 xhci_writel(xhci, temp, pm_addr);
4046 temp &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
4047 xhci_writel(xhci, temp, pm_addr);
4050 spin_unlock_irqrestore(&xhci->lock, flags);
4054 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4056 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4059 ret = xhci_usb2_software_lpm_test(hcd, udev);
4061 xhci_dbg(xhci, "software LPM test succeed\n");
4062 if (xhci->hw_lpm_support == 1) {
4063 udev->usb2_hw_lpm_capable = 1;
4064 ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
4066 udev->usb2_hw_lpm_enabled = 1;
4075 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4076 struct usb_device *udev, int enable)
4081 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4086 #endif /* CONFIG_USB_SUSPEND */
4088 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4089 * internal data structures for the device.
4091 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4092 struct usb_tt *tt, gfp_t mem_flags)
4094 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4095 struct xhci_virt_device *vdev;
4096 struct xhci_command *config_cmd;
4097 struct xhci_input_control_ctx *ctrl_ctx;
4098 struct xhci_slot_ctx *slot_ctx;
4099 unsigned long flags;
4100 unsigned think_time;
4103 /* Ignore root hubs */
4107 vdev = xhci->devs[hdev->slot_id];
4109 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4112 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4114 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4118 spin_lock_irqsave(&xhci->lock, flags);
4119 if (hdev->speed == USB_SPEED_HIGH &&
4120 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4121 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4122 xhci_free_command(xhci, config_cmd);
4123 spin_unlock_irqrestore(&xhci->lock, flags);
4127 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4128 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
4129 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4130 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4131 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4133 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4134 * but it may be already set to 1 when setup an xHCI virtual
4135 * device, so clear it anyway.
4138 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4139 else if (hdev->speed == USB_SPEED_FULL)
4140 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4142 if (xhci->hci_version > 0x95) {
4143 xhci_dbg(xhci, "xHCI version %x needs hub "
4144 "TT think time and number of ports\n",
4145 (unsigned int) xhci->hci_version);
4146 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4147 /* Set TT think time - convert from ns to FS bit times.
4148 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4149 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4151 * xHCI 1.0: this field shall be 0 if the device is not a
4154 think_time = tt->think_time;
4155 if (think_time != 0)
4156 think_time = (think_time / 666) - 1;
4157 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4158 slot_ctx->tt_info |=
4159 cpu_to_le32(TT_THINK_TIME(think_time));
4161 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4162 "TT think time or number of ports\n",
4163 (unsigned int) xhci->hci_version);
4165 slot_ctx->dev_state = 0;
4166 spin_unlock_irqrestore(&xhci->lock, flags);
4168 xhci_dbg(xhci, "Set up %s for hub device.\n",
4169 (xhci->hci_version > 0x95) ?
4170 "configure endpoint" : "evaluate context");
4171 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4172 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4174 /* Issue and wait for the configure endpoint or
4175 * evaluate context command.
4177 if (xhci->hci_version > 0x95)
4178 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4181 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4184 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4185 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4187 xhci_free_command(xhci, config_cmd);
4191 int xhci_get_frame(struct usb_hcd *hcd)
4193 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4194 /* EHCI mods by the periodic size. Why? */
4195 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
4198 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4200 struct xhci_hcd *xhci;
4201 struct device *dev = hcd->self.controller;
4205 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
4207 if (usb_hcd_is_primary_hcd(hcd)) {
4208 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
4211 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
4212 xhci->main_hcd = hcd;
4213 /* Mark the first roothub as being USB 2.0.
4214 * The xHCI driver will register the USB 3.0 roothub.
4216 hcd->speed = HCD_USB2;
4217 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4219 * USB 2.0 roothub under xHCI has an integrated TT,
4220 * (rate matching hub) as opposed to having an OHCI/UHCI
4221 * companion controller.
4225 /* xHCI private pointer was set in xhci_pci_probe for the second
4226 * registered roothub.
4228 xhci = hcd_to_xhci(hcd);
4229 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4230 if (HCC_64BIT_ADDR(temp)) {
4231 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4232 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4234 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4239 xhci->cap_regs = hcd->regs;
4240 xhci->op_regs = hcd->regs +
4241 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
4242 xhci->run_regs = hcd->regs +
4243 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4244 /* Cache read-only capability registers */
4245 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
4246 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
4247 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
4248 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
4249 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4250 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4251 xhci_print_registers(xhci);
4253 get_quirks(dev, xhci);
4255 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4256 * success event after a short transfer. This quirk will ignore such
4259 if (xhci->hci_version > 0x96)
4260 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4262 /* Make sure the HC is halted. */
4263 retval = xhci_halt(xhci);
4267 xhci_dbg(xhci, "Resetting HCD\n");
4268 /* Reset the internal HC memory state and registers. */
4269 retval = xhci_reset(xhci);
4272 xhci_dbg(xhci, "Reset complete\n");
4274 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4275 if (HCC_64BIT_ADDR(temp)) {
4276 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4277 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4279 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4282 xhci_dbg(xhci, "Calling HCD init\n");
4283 /* Initialize HCD and host controller data structures. */
4284 retval = xhci_init(hcd);
4287 xhci_dbg(xhci, "Called HCD init\n");
4294 MODULE_DESCRIPTION(DRIVER_DESC);
4295 MODULE_AUTHOR(DRIVER_AUTHOR);
4296 MODULE_LICENSE("GPL");
4298 static int __init xhci_hcd_init(void)
4305 retval = xhci_register_pci();
4307 printk(KERN_DEBUG "Problem registering PCI driver.");
4311 * Check the compiler generated sizes of structures that must be laid
4312 * out in specific ways for hardware access.
4314 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4315 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4316 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4317 /* xhci_device_control has eight fields, and also
4318 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4320 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4321 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4322 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4323 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4324 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4325 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4326 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
4327 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4330 module_init(xhci_hcd_init);
4332 static void __exit xhci_hcd_cleanup(void)
4334 xhci_unregister_pci();
4336 module_exit(xhci_hcd_cleanup);