drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 xhci_err(xhci, "Stopped the command ring failed, "
 354                                 "maybe the host is dead\n");
 355                 xhci->xhc_state |= XHCI_STATE_DYING;
 356                 xhci_quiesce(xhci);
 357                 xhci_halt(xhci);
 358                 return -ESHUTDOWN;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int xhci_queue_cd(struct xhci_hcd *xhci,
 365                 struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         struct xhci_cd *cd;
 369         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 370         if (!cd)
 371                 return -ENOMEM;
 372         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 373
 374         cd->command = command;
 375         cd->cmd_trb = cmd_trb;
 376         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * Cancel the command which has issue.
 383  *
 384  * Some commands may hang due to waiting for acknowledgement from
 385  * usb device. It is outside of the xHC's ability to control and
 386  * will cause the command ring is blocked. When it occurs software
 387  * should intervene to recover the command ring.
 388  * See Section 4.6.1.1 and 4.6.1.2
 389  */
 390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 391                 union xhci_trb *cmd_trb)
 392 {
 393         int retval = 0;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&xhci->lock, flags);
 397
 398         if (xhci->xhc_state & XHCI_STATE_DYING) {
 399                 xhci_warn(xhci, "Abort the command ring,"
 400                                 " but the xHCI is dead.\n");
 401                 retval = -ESHUTDOWN;
 402                 goto fail;
 403         }
 404
 405         /* queue the cmd desriptor to cancel_cmd_list */
 406         retval = xhci_queue_cd(xhci, command, cmd_trb);
 407         if (retval) {
 408                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 409                 goto fail;
 410         }
 411
 412         /* abort command ring */
 413         retval = xhci_abort_cmd_ring(xhci);
 414         if (retval) {
 415                 xhci_err(xhci, "Abort command ring failed\n");
 416                 if (unlikely(retval == -ESHUTDOWN)) {
 417                         spin_unlock_irqrestore(&xhci->lock, flags);
 418                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 419                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 420                         return retval;
 421                 }
 422         }
 423
 424 fail:
 425         spin_unlock_irqrestore(&xhci->lock, flags);
 426         return retval;
 427 }
 428
 429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 430                 unsigned int slot_id,
 431                 unsigned int ep_index,
 432                 unsigned int stream_id)
 433 {
 434         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 435         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 436         unsigned int ep_state = ep->ep_state;
 437
 438         /* Don't ring the doorbell for this endpoint if there are pending
 439          * cancellations because we don't want to interrupt processing.
 440          * We don't want to restart any stream rings if there's a set dequeue
 441          * pointer command pending because the device can choose to start any
 442          * stream once the endpoint is on the HW schedule.
 443          * FIXME - check all the stream rings for pending cancellations.
 444          */
 445         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 446             (ep_state & EP_HALTED))
 447                 return;
 448         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 449         /* The CPU has better things to do at this point than wait for a
 450          * write-posting flush.  It'll get there soon enough.
 451          */
 452 }
 453
 454 /* Ring the doorbell for any rings with pending URBs */
 455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 456                 unsigned int slot_id,
 457                 unsigned int ep_index)
 458 {
 459         unsigned int stream_id;
 460         struct xhci_virt_ep *ep;
 461
 462         ep = &xhci->devs[slot_id]->eps[ep_index];
 463
 464         /* A ring has pending URBs if its TD list is not empty */
 465         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 466                 if (!(list_empty(&ep->ring->td_list)))
 467                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 468                 return;
 469         }
 470
 471         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 472                         stream_id++) {
 473                 struct xhci_stream_info *stream_info = ep->stream_info;
 474                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 475                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 476                                                 stream_id);
 477         }
 478 }
 479
 480 /*
 481  * Find the segment that trb is in.  Start searching in start_seg.
 482  * If we must move past a segment that has a link TRB with a toggle cycle state
 483  * bit set, then we will toggle the value pointed at by cycle_state.
 484  */
 485 static struct xhci_segment *find_trb_seg(
 486                 struct xhci_segment *start_seg,
 487                 union xhci_trb  *trb, int *cycle_state)
 488 {
 489         struct xhci_segment *cur_seg = start_seg;
 490         struct xhci_generic_trb *generic_trb;
 491
 492         while (cur_seg->trbs > trb ||
 493                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 494                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 495                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 496                         *cycle_state ^= 0x1;
 497                 cur_seg = cur_seg->next;
 498                 if (cur_seg == start_seg)
 499                         /* Looped over the entire list.  Oops! */
 500                         return NULL;
 501         }
 502         return cur_seg;
 503 }
 504
 505
 506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 507                 unsigned int slot_id, unsigned int ep_index,
 508                 unsigned int stream_id)
 509 {
 510         struct xhci_virt_ep *ep;
 511
 512         ep = &xhci->devs[slot_id]->eps[ep_index];
 513         /* Common case: no streams */
 514         if (!(ep->ep_state & EP_HAS_STREAMS))
 515                 return ep->ring;
 516
 517         if (stream_id == 0) {
 518                 xhci_warn(xhci,
 519                                 "WARN: Slot ID %u, ep index %u has streams, "
 520                                 "but URB has no stream ID.\n",
 521                                 slot_id, ep_index);
 522                 return NULL;
 523         }
 524
 525         if (stream_id < ep->stream_info->num_streams)
 526                 return ep->stream_info->stream_rings[stream_id];
 527
 528         xhci_warn(xhci,
 529                         "WARN: Slot ID %u, ep index %u has "
 530                         "stream IDs 1 to %u allocated, "
 531                         "but stream ID %u is requested.\n",
 532                         slot_id, ep_index,
 533                         ep->stream_info->num_streams - 1,
 534                         stream_id);
 535         return NULL;
 536 }
 537
 538 /* Get the right ring for the given URB.
 539  * If the endpoint supports streams, boundary check the URB's stream ID.
 540  * If the endpoint doesn't support streams, return the singular endpoint ring.
 541  */
 542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 543                 struct urb *urb)
 544 {
 545         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 546                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 547 }
 548
 549 /*
 550  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 551  * Record the new state of the xHC's endpoint ring dequeue segment,
 552  * dequeue pointer, and new consumer cycle state in state.
 553  * Update our internal representation of the ring's dequeue pointer.
 554  *
 555  * We do this in three jumps:
 556  *  - First we update our new ring state to be the same as when the xHC stopped.
 557  *  - Then we traverse the ring to find the segment that contains
 558  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 559  *    any link TRBs with the toggle cycle bit set.
 560  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 561  *    if we've moved it past a link TRB with the toggle cycle bit set.
 562  *
 563  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 564  * with correct __le32 accesses they should work fine.  Only users of this are
 565  * in here.
 566  */
 567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 568                 unsigned int slot_id, unsigned int ep_index,
 569                 unsigned int stream_id, struct xhci_td *cur_td,
 570                 struct xhci_dequeue_state *state)
 571 {
 572         struct xhci_virt_device *dev = xhci->devs[slot_id];
 573         struct xhci_ring *ep_ring;
 574         struct xhci_generic_trb *trb;
 575         struct xhci_ep_ctx *ep_ctx;
 576         dma_addr_t addr;
 577
 578         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 579                         ep_index, stream_id);
 580         if (!ep_ring) {
 581                 xhci_warn(xhci, "WARN can't find new dequeue state "
 582                                 "for invalid stream ID %u.\n",
 583                                 stream_id);
 584                 return;
 585         }
 586         state->new_cycle_state = 0;
 587         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 588         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 589                         dev->eps[ep_index].stopped_trb,
 590                         &state->new_cycle_state);
 591         if (!state->new_deq_seg) {
 592                 WARN_ON(1);
 593                 return;
 594         }
 595
 596         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 597         xhci_dbg(xhci, "Finding endpoint context\n");
 598         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 599         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 600
 601         state->new_deq_ptr = cur_td->last_trb;
 602         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 603         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 604                         state->new_deq_ptr,
 605                         &state->new_cycle_state);
 606         if (!state->new_deq_seg) {
 607                 WARN_ON(1);
 608                 return;
 609         }
 610
 611         trb = &state->new_deq_ptr->generic;
 612         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 613             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 614                 state->new_cycle_state ^= 0x1;
 615         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 616
 617         /*
 618          * If there is only one segment in a ring, find_trb_seg()'s while loop
 619          * will not run, and it will return before it has a chance to see if it
 620          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 621          * ended just before the link TRB on a one-segment ring, or if the TD
 622          * wrapped around the top of the ring, because it doesn't have the TD in
 623          * question.  Look for the one-segment case where stalled TRB's address
 624          * is greater than the new dequeue pointer address.
 625          */
 626         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 627                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 628                 state->new_cycle_state ^= 0x1;
 629         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 630
 631         /* Don't update the ring cycle state for the producer (us). */
 632         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 633                         state->new_deq_seg);
 634         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 635         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 636                         (unsigned long long) addr);
 637 }
 638
 639 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 640  * (The last TRB actually points to the ring enqueue pointer, which is not part
 641  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 642  */
 643 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 644                 struct xhci_td *cur_td, bool flip_cycle)
 645 {
 646         struct xhci_segment *cur_seg;
 647         union xhci_trb *cur_trb;
 648
 649         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 650                         true;
 651                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 652                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 653                         /* Unchain any chained Link TRBs, but
 654                          * leave the pointers intact.
 655                          */
 656                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 657                         /* Flip the cycle bit (link TRBs can't be the first
 658                          * or last TRB).
 659                          */
 660                         if (flip_cycle)
 661                                 cur_trb->generic.field[3] ^=
 662                                         cpu_to_le32(TRB_CYCLE);
 663                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 664                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 665                                         "in seg %p (0x%llx dma)\n",
 666                                         cur_trb,
 667                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 668                                         cur_seg,
 669                                         (unsigned long long)cur_seg->dma);
 670                 } else {
 671                         cur_trb->generic.field[0] = 0;
 672                         cur_trb->generic.field[1] = 0;
 673                         cur_trb->generic.field[2] = 0;
 674                         /* Preserve only the cycle bit of this TRB */
 675                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 676                         /* Flip the cycle bit except on the first or last TRB */
 677                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 678                                         cur_trb != cur_td->last_trb)
 679                                 cur_trb->generic.field[3] ^=
 680                                         cpu_to_le32(TRB_CYCLE);
 681                         cur_trb->generic.field[3] |= cpu_to_le32(
 682                                 TRB_TYPE(TRB_TR_NOOP));
 683                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 684                                         "in seg %p (0x%llx dma)\n",
 685                                         cur_trb,
 686                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 687                                         cur_seg,
 688                                         (unsigned long long)cur_seg->dma);
 689                 }
 690                 if (cur_trb == cur_td->last_trb)
 691                         break;
 692         }
 693 }
 694
 695 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 696                 unsigned int ep_index, unsigned int stream_id,
 697                 struct xhci_segment *deq_seg,
 698                 union xhci_trb *deq_ptr, u32 cycle_state);
 699
 700 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 701                 unsigned int slot_id, unsigned int ep_index,
 702                 unsigned int stream_id,
 703                 struct xhci_dequeue_state *deq_state)
 704 {
 705         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 706
 707         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 708                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 709                         deq_state->new_deq_seg,
 710                         (unsigned long long)deq_state->new_deq_seg->dma,
 711                         deq_state->new_deq_ptr,
 712                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 713                         deq_state->new_cycle_state);
 714         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 715                         deq_state->new_deq_seg,
 716                         deq_state->new_deq_ptr,
 717                         (u32) deq_state->new_cycle_state);
 718         /* Stop the TD queueing code from ringing the doorbell until
 719          * this command completes.  The HC won't set the dequeue pointer
 720          * if the ring is running, and ringing the doorbell starts the
 721          * ring running.
 722          */
 723         ep->ep_state |= SET_DEQ_PENDING;
 724 }
 725
 726 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 727                 struct xhci_virt_ep *ep)
 728 {
 729         ep->ep_state &= ~EP_HALT_PENDING;
 730         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 731          * timer is running on another CPU, we don't decrement stop_cmds_pending
 732          * (since we didn't successfully stop the watchdog timer).
 733          */
 734         if (del_timer(&ep->stop_cmd_timer))
 735                 ep->stop_cmds_pending--;
 736 }
 737
 738 /* Must be called with xhci->lock held in interrupt context */
 739 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 740                 struct xhci_td *cur_td, int status, char *adjective)
 741 {
 742         struct usb_hcd *hcd;
 743         struct urb      *urb;
 744         struct urb_priv *urb_priv;
 745
 746         urb = cur_td->urb;
 747         urb_priv = urb->hcpriv;
 748         urb_priv->td_cnt++;
 749         hcd = bus_to_hcd(urb->dev->bus);
 750
 751         /* Only giveback urb when this is the last td in urb */
 752         if (urb_priv->td_cnt == urb_priv->length) {
 753                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 754                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 755                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 756                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 757                                         usb_amd_quirk_pll_enable();
 758                         }
 759                 }
 760                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 761
 762                 spin_unlock(&xhci->lock);
 763                 usb_hcd_giveback_urb(hcd, urb, status);
 764                 xhci_urb_free_priv(xhci, urb_priv);
 765                 spin_lock(&xhci->lock);
 766         }
 767 }
 768
 769 /*
 770  * When we get a command completion for a Stop Endpoint Command, we need to
 771  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 772  *
 773  *  1. If the HW was in the middle of processing the TD that needs to be
 774  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 775  *     in the TD with a Set Dequeue Pointer Command.
 776  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 777  *     bit cleared) so that the HW will skip over them.
 778  */
 779 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 780                 union xhci_trb *trb, struct xhci_event_cmd *event)
 781 {
 782         unsigned int slot_id;
 783         unsigned int ep_index;
 784         struct xhci_virt_device *virt_dev;
 785         struct xhci_ring *ep_ring;
 786         struct xhci_virt_ep *ep;
 787         struct list_head *entry;
 788         struct xhci_td *cur_td = NULL;
 789         struct xhci_td *last_unlinked_td;
 790
 791         struct xhci_dequeue_state deq_state;
 792
 793         if (unlikely(TRB_TO_SUSPEND_PORT(
 794                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 795                 slot_id = TRB_TO_SLOT_ID(
 796                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 797                 virt_dev = xhci->devs[slot_id];
 798                 if (virt_dev)
 799                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 800                                 event);
 801                 else
 802                         xhci_warn(xhci, "Stop endpoint command "
 803                                 "completion for disabled slot %u\n",
 804                                 slot_id);
 805                 return;
 806         }
 807
 808         memset(&deq_state, 0, sizeof(deq_state));
 809         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 810         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 811         ep = &xhci->devs[slot_id]->eps[ep_index];
 812
 813         if (list_empty(&ep->cancelled_td_list)) {
 814                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 815                 ep->stopped_td = NULL;
 816                 ep->stopped_trb = NULL;
 817                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 818                 return;
 819         }
 820
 821         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 822          * We have the xHCI lock, so nothing can modify this list until we drop
 823          * it.  We're also in the event handler, so we can't get re-interrupted
 824          * if another Stop Endpoint command completes
 825          */
 826         list_for_each(entry, &ep->cancelled_td_list) {
 827                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 828                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 829                                 cur_td->first_trb,
 830                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 831                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 832                 if (!ep_ring) {
 833                         /* This shouldn't happen unless a driver is mucking
 834                          * with the stream ID after submission.  This will
 835                          * leave the TD on the hardware ring, and the hardware
 836                          * will try to execute it, and may access a buffer
 837                          * that has already been freed.  In the best case, the
 838                          * hardware will execute it, and the event handler will
 839                          * ignore the completion event for that TD, since it was
 840                          * removed from the td_list for that endpoint.  In
 841                          * short, don't muck with the stream ID after
 842                          * submission.
 843                          */
 844                         xhci_warn(xhci, "WARN Cancelled URB %p "
 845                                         "has invalid stream ID %u.\n",
 846                                         cur_td->urb,
 847                                         cur_td->urb->stream_id);
 848                         goto remove_finished_td;
 849                 }
 850                 /*
 851                  * If we stopped on the TD we need to cancel, then we have to
 852                  * move the xHC endpoint ring dequeue pointer past this TD.
 853                  */
 854                 if (cur_td == ep->stopped_td)
 855                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 856                                         cur_td->urb->stream_id,
 857                                         cur_td, &deq_state);
 858                 else
 859                         td_to_noop(xhci, ep_ring, cur_td, false);
 860 remove_finished_td:
 861                 /*
 862                  * The event handler won't see a completion for this TD anymore,
 863                  * so remove it from the endpoint ring's TD list.  Keep it in
 864                  * the cancelled TD list for URB completion later.
 865                  */
 866                 list_del_init(&cur_td->td_list);
 867         }
 868         last_unlinked_td = cur_td;
 869         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 870
 871         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 872         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 873                 xhci_queue_new_dequeue_state(xhci,
 874                                 slot_id, ep_index,
 875                                 ep->stopped_td->urb->stream_id,
 876                                 &deq_state);
 877                 xhci_ring_cmd_db(xhci);
 878         } else {
 879                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 880                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 881         }
 882         ep->stopped_td = NULL;
 883         ep->stopped_trb = NULL;
 884
 885         /*
 886          * Drop the lock and complete the URBs in the cancelled TD list.
 887          * New TDs to be cancelled might be added to the end of the list before
 888          * we can complete all the URBs for the TDs we already unlinked.
 889          * So stop when we've completed the URB for the last TD we unlinked.
 890          */
 891         do {
 892                 cur_td = list_entry(ep->cancelled_td_list.next,
 893                                 struct xhci_td, cancelled_td_list);
 894                 list_del_init(&cur_td->cancelled_td_list);
 895
 896                 /* Clean up the cancelled URB */
 897                 /* Doesn't matter what we pass for status, since the core will
 898                  * just overwrite it (because the URB has been unlinked).
 899                  */
 900                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 901
 902                 /* Stop processing the cancelled list if the watchdog timer is
 903                  * running.
 904                  */
 905                 if (xhci->xhc_state & XHCI_STATE_DYING)
 906                         return;
 907         } while (cur_td != last_unlinked_td);
 908
 909         /* Return to the event handler with xhci->lock re-acquired */
 910 }
 911
 912 /* Watchdog timer function for when a stop endpoint command fails to complete.
 913  * In this case, we assume the host controller is broken or dying or dead.  The
 914  * host may still be completing some other events, so we have to be careful to
 915  * let the event ring handler and the URB dequeueing/enqueueing functions know
 916  * through xhci->state.
 917  *
 918  * The timer may also fire if the host takes a very long time to respond to the
 919  * command, and the stop endpoint command completion handler cannot delete the
 920  * timer before the timer function is called.  Another endpoint cancellation may
 921  * sneak in before the timer function can grab the lock, and that may queue
 922  * another stop endpoint command and add the timer back.  So we cannot use a
 923  * simple flag to say whether there is a pending stop endpoint command for a
 924  * particular endpoint.
 925  *
 926  * Instead we use a combination of that flag and a counter for the number of
 927  * pending stop endpoint commands.  If the timer is the tail end of the last
 928  * stop endpoint command, and the endpoint's command is still pending, we assume
 929  * the host is dying.
 930  */
 931 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 932 {
 933         struct xhci_hcd *xhci;
 934         struct xhci_virt_ep *ep;
 935         struct xhci_virt_ep *temp_ep;
 936         struct xhci_ring *ring;
 937         struct xhci_td *cur_td;
 938         int ret, i, j;
 939         unsigned long flags;
 940
 941         ep = (struct xhci_virt_ep *) arg;
 942         xhci = ep->xhci;
 943
 944         spin_lock_irqsave(&xhci->lock, flags);
 945
 946         ep->stop_cmds_pending--;
 947         if (xhci->xhc_state & XHCI_STATE_DYING) {
 948                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 949                                 "xHCI as DYING, exiting.\n");
 950                 spin_unlock_irqrestore(&xhci->lock, flags);
 951                 return;
 952         }
 953         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 954                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 955                                 "exiting.\n");
 956                 spin_unlock_irqrestore(&xhci->lock, flags);
 957                 return;
 958         }
 959
 960         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 961         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 962         /* Oops, HC is dead or dying or at least not responding to the stop
 963          * endpoint command.
 964          */
 965         xhci->xhc_state |= XHCI_STATE_DYING;
 966         /* Disable interrupts from the host controller and start halting it */
 967         xhci_quiesce(xhci);
 968         spin_unlock_irqrestore(&xhci->lock, flags);
 969
 970         ret = xhci_halt(xhci);
 971
 972         spin_lock_irqsave(&xhci->lock, flags);
 973         if (ret < 0) {
 974                 /* This is bad; the host is not responding to commands and it's
 975                  * not allowing itself to be halted.  At least interrupts are
 976                  * disabled. If we call usb_hc_died(), it will attempt to
 977                  * disconnect all device drivers under this host.  Those
 978                  * disconnect() methods will wait for all URBs to be unlinked,
 979                  * so we must complete them.
 980                  */
 981                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 982                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 983                 /* We could turn all TDs on the rings to no-ops.  This won't
 984                  * help if the host has cached part of the ring, and is slow if
 985                  * we want to preserve the cycle bit.  Skip it and hope the host
 986                  * doesn't touch the memory.
 987                  */
 988         }
 989         for (i = 0; i < MAX_HC_SLOTS; i++) {
 990                 if (!xhci->devs[i])
 991                         continue;
 992                 for (j = 0; j < 31; j++) {
 993                         temp_ep = &xhci->devs[i]->eps[j];
 994                         ring = temp_ep->ring;
 995                         if (!ring)
 996                                 continue;
 997                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 998                                         "ep index %u\n", i, j);
 999                         while (!list_empty(&ring->td_list)) {
1000                                 cur_td = list_first_entry(&ring->td_list,
1001                                                 struct xhci_td,
1002                                                 td_list);
1003                                 list_del_init(&cur_td->td_list);
1004                                 if (!list_empty(&cur_td->cancelled_td_list))
1005                                         list_del_init(&cur_td->cancelled_td_list);
1006                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1007                                                 -ESHUTDOWN, "killed");
1008                         }
1009                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1010                                 cur_td = list_first_entry(
1011                                                 &temp_ep->cancelled_td_list,
1012                                                 struct xhci_td,
1013                                                 cancelled_td_list);
1014                                 list_del_init(&cur_td->cancelled_td_list);
1015                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1016                                                 -ESHUTDOWN, "killed");
1017                         }
1018                 }
1019         }
1020         spin_unlock_irqrestore(&xhci->lock, flags);
1021         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1022         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1023         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1024 }
1025
1026 /*
1027  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1028  * we need to clear the set deq pending flag in the endpoint ring state, so that
1029  * the TD queueing code can ring the doorbell again.  We also need to ring the
1030  * endpoint doorbell to restart the ring, but only if there aren't more
1031  * cancellations pending.
1032  */
1033 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1034                 struct xhci_event_cmd *event,
1035                 union xhci_trb *trb)
1036 {
1037         unsigned int slot_id;
1038         unsigned int ep_index;
1039         unsigned int stream_id;
1040         struct xhci_ring *ep_ring;
1041         struct xhci_virt_device *dev;
1042         struct xhci_ep_ctx *ep_ctx;
1043         struct xhci_slot_ctx *slot_ctx;
1044
1045         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1046         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1047         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1048         dev = xhci->devs[slot_id];
1049
1050         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1051         if (!ep_ring) {
1052                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1053                                 "freed stream ID %u\n",
1054                                 stream_id);
1055                 /* XXX: Harmless??? */
1056                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1057                 return;
1058         }
1059
1060         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1061         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1062
1063         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1064                 unsigned int ep_state;
1065                 unsigned int slot_state;
1066
1067                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1068                 case COMP_TRB_ERR:
1069                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1070                                         "of stream ID configuration\n");
1071                         break;
1072                 case COMP_CTX_STATE:
1073                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1074                                         "to incorrect slot or ep state.\n");
1075                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1076                         ep_state &= EP_STATE_MASK;
1077                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1078                         slot_state = GET_SLOT_STATE(slot_state);
1079                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1080                                         slot_state, ep_state);
1081                         break;
1082                 case COMP_EBADSLT:
1083                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1084                                         "slot %u was not enabled.\n", slot_id);
1085                         break;
1086                 default:
1087                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1088                                         "completion code of %u.\n",
1089                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1090                         break;
1091                 }
1092                 /* OK what do we do now?  The endpoint state is hosed, and we
1093                  * should never get to this point if the synchronization between
1094                  * queueing, and endpoint state are correct.  This might happen
1095                  * if the device gets disconnected after we've finished
1096                  * cancelling URBs, which might not be an error...
1097                  */
1098         } else {
1099                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1100                          le64_to_cpu(ep_ctx->deq));
1101                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1102                                          dev->eps[ep_index].queued_deq_ptr) ==
1103                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1104                         /* Update the ring's dequeue segment and dequeue pointer
1105                          * to reflect the new position.
1106                          */
1107                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1108                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1109                 } else {
1110                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1111                                         "Ptr command & xHCI internal state.\n");
1112                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1113                                         dev->eps[ep_index].queued_deq_seg,
1114                                         dev->eps[ep_index].queued_deq_ptr);
1115                 }
1116         }
1117
1118         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1119         dev->eps[ep_index].queued_deq_seg = NULL;
1120         dev->eps[ep_index].queued_deq_ptr = NULL;
1121         /* Restart any rings with pending URBs */
1122         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1123 }
1124
1125 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1126                 struct xhci_event_cmd *event,
1127                 union xhci_trb *trb)
1128 {
1129         int slot_id;
1130         unsigned int ep_index;
1131
1132         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1133         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1134         /* This command will only fail if the endpoint wasn't halted,
1135          * but we don't care.
1136          */
1137         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1138                  GET_COMP_CODE(le32_to_cpu(event->status)));
1139
1140         /* HW with the reset endpoint quirk needs to have a configure endpoint
1141          * command complete before the endpoint can be used.  Queue that here
1142          * because the HW can't handle two commands being queued in a row.
1143          */
1144         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1145                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1146                 xhci_queue_configure_endpoint(xhci,
1147                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1148                                 false);
1149                 xhci_ring_cmd_db(xhci);
1150         } else {
1151                 /* Clear our internal halted state and restart the ring(s) */
1152                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1153                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1154         }
1155 }
1156
1157 /* Check to see if a command in the device's command queue matches this one.
1158  * Signal the completion or free the command, and return 1.  Return 0 if the
1159  * completed command isn't at the head of the command list.
1160  */
1161 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1162                 struct xhci_virt_device *virt_dev,
1163                 struct xhci_event_cmd *event)
1164 {
1165         struct xhci_command *command;
1166
1167         if (list_empty(&virt_dev->cmd_list))
1168                 return 0;
1169
1170         command = list_entry(virt_dev->cmd_list.next,
1171                         struct xhci_command, cmd_list);
1172         if (xhci->cmd_ring->dequeue != command->command_trb)
1173                 return 0;
1174
1175         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1176         list_del(&command->cmd_list);
1177         if (command->completion)
1178                 complete(command->completion);
1179         else
1180                 xhci_free_command(xhci, command);
1181         return 1;
1182 }
1183
1184 static void handle_cmd_completion(struct xhci_hcd *xhci,
1185                 struct xhci_event_cmd *event)
1186 {
1187         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1188         u64 cmd_dma;
1189         dma_addr_t cmd_dequeue_dma;
1190         struct xhci_input_control_ctx *ctrl_ctx;
1191         struct xhci_virt_device *virt_dev;
1192         unsigned int ep_index;
1193         struct xhci_ring *ep_ring;
1194         unsigned int ep_state;
1195
1196         cmd_dma = le64_to_cpu(event->cmd_trb);
1197         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1198                         xhci->cmd_ring->dequeue);
1199         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1200         if (cmd_dequeue_dma == 0) {
1201                 xhci->error_bitmask |= 1 << 4;
1202                 return;
1203         }
1204         /* Does the DMA address match our internal dequeue pointer address? */
1205         if (cmd_dma != (u64) cmd_dequeue_dma) {
1206                 xhci->error_bitmask |= 1 << 5;
1207                 return;
1208         }
1209         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1210                 & TRB_TYPE_BITMASK) {
1211         case TRB_TYPE(TRB_ENABLE_SLOT):
1212                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1213                         xhci->slot_id = slot_id;
1214                 else
1215                         xhci->slot_id = 0;
1216                 complete(&xhci->addr_dev);
1217                 break;
1218         case TRB_TYPE(TRB_DISABLE_SLOT):
1219                 if (xhci->devs[slot_id]) {
1220                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1221                                 /* Delete default control endpoint resources */
1222                                 xhci_free_device_endpoint_resources(xhci,
1223                                                 xhci->devs[slot_id], true);
1224                         xhci_free_virt_device(xhci, slot_id);
1225                 }
1226                 break;
1227         case TRB_TYPE(TRB_CONFIG_EP):
1228                 virt_dev = xhci->devs[slot_id];
1229                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1230                         break;
1231                 /*
1232                  * Configure endpoint commands can come from the USB core
1233                  * configuration or alt setting changes, or because the HW
1234                  * needed an extra configure endpoint command after a reset
1235                  * endpoint command or streams were being configured.
1236                  * If the command was for a halted endpoint, the xHCI driver
1237                  * is not waiting on the configure endpoint command.
1238                  */
1239                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1240                                 virt_dev->in_ctx);
1241                 /* Input ctx add_flags are the endpoint index plus one */
1242                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1243                 /* A usb_set_interface() call directly after clearing a halted
1244                  * condition may race on this quirky hardware.  Not worth
1245                  * worrying about, since this is prototype hardware.  Not sure
1246                  * if this will work for streams, but streams support was
1247                  * untested on this prototype.
1248                  */
1249                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1250                                 ep_index != (unsigned int) -1 &&
1251                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1252                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1253                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1254                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1255                         if (!(ep_state & EP_HALTED))
1256                                 goto bandwidth_change;
1257                         xhci_dbg(xhci, "Completed config ep cmd - "
1258                                         "last ep index = %d, state = %d\n",
1259                                         ep_index, ep_state);
1260                         /* Clear internal halted state and restart ring(s) */
1261                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1262                                 ~EP_HALTED;
1263                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1264                         break;
1265                 }
1266 bandwidth_change:
1267                 xhci_dbg(xhci, "Completed config ep cmd\n");
1268                 xhci->devs[slot_id]->cmd_status =
1269                         GET_COMP_CODE(le32_to_cpu(event->status));
1270                 complete(&xhci->devs[slot_id]->cmd_completion);
1271                 break;
1272         case TRB_TYPE(TRB_EVAL_CONTEXT):
1273                 virt_dev = xhci->devs[slot_id];
1274                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1275                         break;
1276                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1277                 complete(&xhci->devs[slot_id]->cmd_completion);
1278                 break;
1279         case TRB_TYPE(TRB_ADDR_DEV):
1280                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1281                 complete(&xhci->addr_dev);
1282                 break;
1283         case TRB_TYPE(TRB_STOP_RING):
1284                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1285                 break;
1286         case TRB_TYPE(TRB_SET_DEQ):
1287                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1288                 break;
1289         case TRB_TYPE(TRB_CMD_NOOP):
1290                 break;
1291         case TRB_TYPE(TRB_RESET_EP):
1292                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1293                 break;
1294         case TRB_TYPE(TRB_RESET_DEV):
1295                 xhci_dbg(xhci, "Completed reset device command.\n");
1296                 slot_id = TRB_TO_SLOT_ID(
1297                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1298                 virt_dev = xhci->devs[slot_id];
1299                 if (virt_dev)
1300                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1301                 else
1302                         xhci_warn(xhci, "Reset device command completion "
1303                                         "for disabled slot %u\n", slot_id);
1304                 break;
1305         case TRB_TYPE(TRB_NEC_GET_FW):
1306                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1307                         xhci->error_bitmask |= 1 << 6;
1308                         break;
1309                 }
1310                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1311                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1312                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1313                 break;
1314         default:
1315                 /* Skip over unknown commands on the event ring */
1316                 xhci->error_bitmask |= 1 << 6;
1317                 break;
1318         }
1319         inc_deq(xhci, xhci->cmd_ring, false);
1320 }
1321
1322 static void handle_vendor_event(struct xhci_hcd *xhci,
1323                 union xhci_trb *event)
1324 {
1325         u32 trb_type;
1326
1327         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1328         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1329         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1330                 handle_cmd_completion(xhci, &event->event_cmd);
1331 }
1332
1333 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1334  * port registers -- USB 3.0 and USB 2.0).
1335  *
1336  * Returns a zero-based port number, which is suitable for indexing into each of
1337  * the split roothubs' port arrays and bus state arrays.
1338  * Add one to it in order to call xhci_find_slot_id_by_port.
1339  */
1340 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1341                 struct xhci_hcd *xhci, u32 port_id)
1342 {
1343         unsigned int i;
1344         unsigned int num_similar_speed_ports = 0;
1345
1346         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1347          * and usb2_ports are 0-based indexes.  Count the number of similar
1348          * speed ports, up to 1 port before this port.
1349          */
1350         for (i = 0; i < (port_id - 1); i++) {
1351                 u8 port_speed = xhci->port_array[i];
1352
1353                 /*
1354                  * Skip ports that don't have known speeds, or have duplicate
1355                  * Extended Capabilities port speed entries.
1356                  */
1357                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1358                         continue;
1359
1360                 /*
1361                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1362                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1363                  * matches the device speed, it's a similar speed port.
1364                  */
1365                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1366                         num_similar_speed_ports++;
1367         }
1368         return num_similar_speed_ports;
1369 }
1370
1371 static void handle_port_status(struct xhci_hcd *xhci,
1372                 union xhci_trb *event)
1373 {
1374         struct usb_hcd *hcd;
1375         u32 port_id;
1376         u32 temp, temp1;
1377         int max_ports;
1378         int slot_id;
1379         unsigned int faked_port_index;
1380         u8 major_revision;
1381         struct xhci_bus_state *bus_state;
1382         __le32 __iomem **port_array;
1383         bool bogus_port_status = false;
1384
1385         /* Port status change events always have a successful completion code */
1386         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1387                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1388                 xhci->error_bitmask |= 1 << 8;
1389         }
1390         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1391         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1392
1393         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1394         if ((port_id <= 0) || (port_id > max_ports)) {
1395                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1396                 bogus_port_status = true;
1397                 goto cleanup;
1398         }
1399
1400         /* Figure out which usb_hcd this port is attached to:
1401          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1402          */
1403         major_revision = xhci->port_array[port_id - 1];
1404         if (major_revision == 0) {
1405                 xhci_warn(xhci, "Event for port %u not in "
1406                                 "Extended Capabilities, ignoring.\n",
1407                                 port_id);
1408                 bogus_port_status = true;
1409                 goto cleanup;
1410         }
1411         if (major_revision == DUPLICATE_ENTRY) {
1412                 xhci_warn(xhci, "Event for port %u duplicated in"
1413                                 "Extended Capabilities, ignoring.\n",
1414                                 port_id);
1415                 bogus_port_status = true;
1416                 goto cleanup;
1417         }
1418
1419         /*
1420          * Hardware port IDs reported by a Port Status Change Event include USB
1421          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1422          * resume event, but we first need to translate the hardware port ID
1423          * into the index into the ports on the correct split roothub, and the
1424          * correct bus_state structure.
1425          */
1426         /* Find the right roothub. */
1427         hcd = xhci_to_hcd(xhci);
1428         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1429                 hcd = xhci->shared_hcd;
1430         bus_state = &xhci->bus_state[hcd_index(hcd)];
1431         if (hcd->speed == HCD_USB3)
1432                 port_array = xhci->usb3_ports;
1433         else
1434                 port_array = xhci->usb2_ports;
1435         /* Find the faked port hub number */
1436         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1437                         port_id);
1438
1439         temp = xhci_readl(xhci, port_array[faked_port_index]);
1440         if (hcd->state == HC_STATE_SUSPENDED) {
1441                 xhci_dbg(xhci, "resume root hub\n");
1442                 usb_hcd_resume_root_hub(hcd);
1443         }
1444
1445         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1446                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1447
1448                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1449                 if (!(temp1 & CMD_RUN)) {
1450                         xhci_warn(xhci, "xHC is not running.\n");
1451                         goto cleanup;
1452                 }
1453
1454                 if (DEV_SUPERSPEED(temp)) {
1455                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1456                         xhci_set_link_state(xhci, port_array, faked_port_index,
1457                                                 XDEV_U0);
1458                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1459                                         faked_port_index + 1);
1460                         if (!slot_id) {
1461                                 xhci_dbg(xhci, "slot_id is zero\n");
1462                                 goto cleanup;
1463                         }
1464                         xhci_ring_device(xhci, slot_id);
1465                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1466                         /* Clear PORT_PLC */
1467                         xhci_test_and_clear_bit(xhci, port_array,
1468                                                 faked_port_index, PORT_PLC);
1469                 } else {
1470                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1471                         bus_state->resume_done[faked_port_index] = jiffies +
1472                                 msecs_to_jiffies(20);
1473                         mod_timer(&hcd->rh_timer,
1474                                   bus_state->resume_done[faked_port_index]);
1475                         /* Do the rest in GetPortStatus */
1476                 }
1477         }
1478
1479         if (hcd->speed != HCD_USB3)
1480                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1481                                         PORT_PLC);
1482
1483 cleanup:
1484         /* Update event ring dequeue pointer before dropping the lock */
1485         inc_deq(xhci, xhci->event_ring, true);
1486
1487         /* Don't make the USB core poll the roothub if we got a bad port status
1488          * change event.  Besides, at that point we can't tell which roothub
1489          * (USB 2.0 or USB 3.0) to kick.
1490          */
1491         if (bogus_port_status)
1492                 return;
1493
1494         spin_unlock(&xhci->lock);
1495         /* Pass this up to the core */
1496         usb_hcd_poll_rh_status(hcd);
1497         spin_lock(&xhci->lock);
1498 }
1499
1500 /*
1501  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1502  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1503  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1504  * returns 0.
1505  */
1506 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1507                 union xhci_trb  *start_trb,
1508                 union xhci_trb  *end_trb,
1509                 dma_addr_t      suspect_dma)
1510 {
1511         dma_addr_t start_dma;
1512         dma_addr_t end_seg_dma;
1513         dma_addr_t end_trb_dma;
1514         struct xhci_segment *cur_seg;
1515
1516         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1517         cur_seg = start_seg;
1518
1519         do {
1520                 if (start_dma == 0)
1521                         return NULL;
1522                 /* We may get an event for a Link TRB in the middle of a TD */
1523                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1524                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1525                 /* If the end TRB isn't in this segment, this is set to 0 */
1526                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1527
1528                 if (end_trb_dma > 0) {
1529                         /* The end TRB is in this segment, so suspect should be here */
1530                         if (start_dma <= end_trb_dma) {
1531                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1532                                         return cur_seg;
1533                         } else {
1534                                 /* Case for one segment with
1535                                  * a TD wrapped around to the top
1536                                  */
1537                                 if ((suspect_dma >= start_dma &&
1538                                                         suspect_dma <= end_seg_dma) ||
1539                                                 (suspect_dma >= cur_seg->dma &&
1540                                                  suspect_dma <= end_trb_dma))
1541                                         return cur_seg;
1542                         }
1543                         return NULL;
1544                 } else {
1545                         /* Might still be somewhere in this segment */
1546                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1547                                 return cur_seg;
1548                 }
1549                 cur_seg = cur_seg->next;
1550                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1551         } while (cur_seg != start_seg);
1552
1553         return NULL;
1554 }
1555
1556 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1557                 unsigned int slot_id, unsigned int ep_index,
1558                 unsigned int stream_id,
1559                 struct xhci_td *td, union xhci_trb *event_trb)
1560 {
1561         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1562         ep->ep_state |= EP_HALTED;
1563         ep->stopped_td = td;
1564         ep->stopped_trb = event_trb;
1565         ep->stopped_stream = stream_id;
1566
1567         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1568         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1569
1570         ep->stopped_td = NULL;
1571         ep->stopped_trb = NULL;
1572         ep->stopped_stream = 0;
1573
1574         xhci_ring_cmd_db(xhci);
1575 }
1576
1577 /* Check if an error has halted the endpoint ring.  The class driver will
1578  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1579  * However, a babble and other errors also halt the endpoint ring, and the class
1580  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1581  * Ring Dequeue Pointer command manually.
1582  */
1583 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1584                 struct xhci_ep_ctx *ep_ctx,
1585                 unsigned int trb_comp_code)
1586 {
1587         /* TRB completion codes that may require a manual halt cleanup */
1588         if (trb_comp_code == COMP_TX_ERR ||
1589                         trb_comp_code == COMP_BABBLE ||
1590                         trb_comp_code == COMP_SPLIT_ERR)
1591                 /* The 0.96 spec says a babbling control endpoint
1592                  * is not halted. The 0.96 spec says it is.  Some HW
1593                  * claims to be 0.95 compliant, but it halts the control
1594                  * endpoint anyway.  Check if a babble halted the
1595                  * endpoint.
1596                  */
1597                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1598                     cpu_to_le32(EP_STATE_HALTED))
1599                         return 1;
1600
1601         return 0;
1602 }
1603
1604 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1605 {
1606         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1607                 /* Vendor defined "informational" completion code,
1608                  * treat as not-an-error.
1609                  */
1610                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1611                                 trb_comp_code);
1612                 xhci_dbg(xhci, "Treating code as success.\n");
1613                 return 1;
1614         }
1615         return 0;
1616 }
1617
1618 /*
1619  * Finish the td processing, remove the td from td list;
1620  * Return 1 if the urb can be given back.
1621  */
1622 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1623         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1624         struct xhci_virt_ep *ep, int *status, bool skip)
1625 {
1626         struct xhci_virt_device *xdev;
1627         struct xhci_ring *ep_ring;
1628         unsigned int slot_id;
1629         int ep_index;
1630         struct urb *urb = NULL;
1631         struct xhci_ep_ctx *ep_ctx;
1632         int ret = 0;
1633         struct urb_priv *urb_priv;
1634         u32 trb_comp_code;
1635
1636         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1637         xdev = xhci->devs[slot_id];
1638         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1639         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1640         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1641         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1642
1643         if (skip)
1644                 goto td_cleanup;
1645
1646         if (trb_comp_code == COMP_STOP_INVAL ||
1647                         trb_comp_code == COMP_STOP) {
1648                 /* The Endpoint Stop Command completion will take care of any
1649                  * stopped TDs.  A stopped TD may be restarted, so don't update
1650                  * the ring dequeue pointer or take this TD off any lists yet.
1651                  */
1652                 ep->stopped_td = td;
1653                 ep->stopped_trb = event_trb;
1654                 return 0;
1655         } else {
1656                 if (trb_comp_code == COMP_STALL) {
1657                         /* The transfer is completed from the driver's
1658                          * perspective, but we need to issue a set dequeue
1659                          * command for this stalled endpoint to move the dequeue
1660                          * pointer past the TD.  We can't do that here because
1661                          * the halt condition must be cleared first.  Let the
1662                          * USB class driver clear the stall later.
1663                          */
1664                         ep->stopped_td = td;
1665                         ep->stopped_trb = event_trb;
1666                         ep->stopped_stream = ep_ring->stream_id;
1667                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1668                                         ep_ctx, trb_comp_code)) {
1669                         /* Other types of errors halt the endpoint, but the
1670                          * class driver doesn't call usb_reset_endpoint() unless
1671                          * the error is -EPIPE.  Clear the halted status in the
1672                          * xHCI hardware manually.
1673                          */
1674                         xhci_cleanup_halted_endpoint(xhci,
1675                                         slot_id, ep_index, ep_ring->stream_id,
1676                                         td, event_trb);
1677                 } else {
1678                         /* Update ring dequeue pointer */
1679                         while (ep_ring->dequeue != td->last_trb)
1680                                 inc_deq(xhci, ep_ring, false);
1681                         inc_deq(xhci, ep_ring, false);
1682                 }
1683
1684 td_cleanup:
1685                 /* Clean up the endpoint's TD list */
1686                 urb = td->urb;
1687                 urb_priv = urb->hcpriv;
1688
1689                 /* Do one last check of the actual transfer length.
1690                  * If the host controller said we transferred more data than
1691                  * the buffer length, urb->actual_length will be a very big
1692                  * number (since it's unsigned).  Play it safe and say we didn't
1693                  * transfer anything.
1694                  */
1695                 if (urb->actual_length > urb->transfer_buffer_length) {
1696                         xhci_warn(xhci, "URB transfer length is wrong, "
1697                                         "xHC issue? req. len = %u, "
1698                                         "act. len = %u\n",
1699                                         urb->transfer_buffer_length,
1700                                         urb->actual_length);
1701                         urb->actual_length = 0;
1702                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1703                                 *status = -EREMOTEIO;
1704                         else
1705                                 *status = 0;
1706                 }
1707                 list_del_init(&td->td_list);
1708                 /* Was this TD slated to be cancelled but completed anyway? */
1709                 if (!list_empty(&td->cancelled_td_list))
1710                         list_del_init(&td->cancelled_td_list);
1711
1712                 urb_priv->td_cnt++;
1713                 /* Giveback the urb when all the tds are completed */
1714                 if (urb_priv->td_cnt == urb_priv->length) {
1715                         ret = 1;
1716                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1717                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1718                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1719                                         == 0) {
1720                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1721                                                 usb_amd_quirk_pll_enable();
1722                                 }
1723                         }
1724                 }
1725         }
1726
1727         return ret;
1728 }
1729
1730 /*
1731  * Process control tds, update urb status and actual_length.
1732  */
1733 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1734         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1735         struct xhci_virt_ep *ep, int *status)
1736 {
1737         struct xhci_virt_device *xdev;
1738         struct xhci_ring *ep_ring;
1739         unsigned int slot_id;
1740         int ep_index;
1741         struct xhci_ep_ctx *ep_ctx;
1742         u32 trb_comp_code;
1743
1744         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1745         xdev = xhci->devs[slot_id];
1746         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1747         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1748         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1749         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1750
1751         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1752         switch (trb_comp_code) {
1753         case COMP_SUCCESS:
1754                 if (event_trb == ep_ring->dequeue) {
1755                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1756                                         "without IOC set??\n");
1757                         *status = -ESHUTDOWN;
1758                 } else if (event_trb != td->last_trb) {
1759                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1760                                         "without IOC set??\n");
1761                         *status = -ESHUTDOWN;
1762                 } else {
1763                         *status = 0;
1764                 }
1765                 break;
1766         case COMP_SHORT_TX:
1767                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1768                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1769                         *status = -EREMOTEIO;
1770                 else
1771                         *status = 0;
1772                 break;
1773         case COMP_STOP_INVAL:
1774         case COMP_STOP:
1775                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1776         default:
1777                 if (!xhci_requires_manual_halt_cleanup(xhci,
1778                                         ep_ctx, trb_comp_code))
1779                         break;
1780                 xhci_dbg(xhci, "TRB error code %u, "
1781                                 "halted endpoint index = %u\n",
1782                                 trb_comp_code, ep_index);
1783                 /* else fall through */
1784         case COMP_STALL:
1785                 /* Did we transfer part of the data (middle) phase? */
1786                 if (event_trb != ep_ring->dequeue &&
1787                                 event_trb != td->last_trb)
1788                         td->urb->actual_length =
1789                                 td->urb->transfer_buffer_length
1790                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1791                 else
1792                         td->urb->actual_length = 0;
1793
1794                 xhci_cleanup_halted_endpoint(xhci,
1795                         slot_id, ep_index, 0, td, event_trb);
1796                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1797         }
1798         /*
1799          * Did we transfer any data, despite the errors that might have
1800          * happened?  I.e. did we get past the setup stage?
1801          */
1802         if (event_trb != ep_ring->dequeue) {
1803                 /* The event was for the status stage */
1804                 if (event_trb == td->last_trb) {
1805                         if (td->urb->actual_length != 0) {
1806                                 /* Don't overwrite a previously set error code
1807                                  */
1808                                 if ((*status == -EINPROGRESS || *status == 0) &&
1809                                                 (td->urb->transfer_flags
1810                                                  & URB_SHORT_NOT_OK))
1811                                         /* Did we already see a short data
1812                                          * stage? */
1813                                         *status = -EREMOTEIO;
1814                         } else {
1815                                 td->urb->actual_length =
1816                                         td->urb->transfer_buffer_length;
1817                         }
1818                 } else {
1819                 /* Maybe the event was for the data stage? */
1820                         td->urb->actual_length =
1821                                 td->urb->transfer_buffer_length -
1822                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1823                         xhci_dbg(xhci, "Waiting for status "
1824                                         "stage event\n");
1825                         return 0;
1826                 }
1827         }
1828
1829         return finish_td(xhci, td, event_trb, event, ep, status, false);
1830 }
1831
1832 /*
1833  * Process isochronous tds, update urb packet status and actual_length.
1834  */
1835 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1836         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1837         struct xhci_virt_ep *ep, int *status)
1838 {
1839         struct xhci_ring *ep_ring;
1840         struct urb_priv *urb_priv;
1841         int idx;
1842         int len = 0;
1843         union xhci_trb *cur_trb;
1844         struct xhci_segment *cur_seg;
1845         struct usb_iso_packet_descriptor *frame;
1846         u32 trb_comp_code;
1847         bool skip_td = false;
1848
1849         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1850         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1851         urb_priv = td->urb->hcpriv;
1852         idx = urb_priv->td_cnt;
1853         frame = &td->urb->iso_frame_desc[idx];
1854
1855         /* handle completion code */
1856         switch (trb_comp_code) {
1857         case COMP_SUCCESS:
1858                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
1859                         frame->status = 0;
1860                         break;
1861                 }
1862                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1863                         trb_comp_code = COMP_SHORT_TX;
1864         case COMP_SHORT_TX:
1865                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1866                                 -EREMOTEIO : 0;
1867                 break;
1868         case COMP_BW_OVER:
1869                 frame->status = -ECOMM;
1870                 skip_td = true;
1871                 break;
1872         case COMP_BUFF_OVER:
1873         case COMP_BABBLE:
1874                 frame->status = -EOVERFLOW;
1875                 skip_td = true;
1876                 break;
1877         case COMP_DEV_ERR:
1878         case COMP_STALL:
1879         case COMP_TX_ERR:
1880                 frame->status = -EPROTO;
1881                 skip_td = true;
1882                 break;
1883         case COMP_STOP:
1884         case COMP_STOP_INVAL:
1885                 break;
1886         default:
1887                 frame->status = -1;
1888                 break;
1889         }
1890
1891         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1892                 frame->actual_length = frame->length;
1893                 td->urb->actual_length += frame->length;
1894         } else {
1895                 for (cur_trb = ep_ring->dequeue,
1896                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1897                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1898                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1899                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1900                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1901                 }
1902                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1903                         TRB_LEN(le32_to_cpu(event->transfer_len));
1904
1905                 if (trb_comp_code != COMP_STOP_INVAL) {
1906                         frame->actual_length = len;
1907                         td->urb->actual_length += len;
1908                 }
1909         }
1910
1911         return finish_td(xhci, td, event_trb, event, ep, status, false);
1912 }
1913
1914 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1915                         struct xhci_transfer_event *event,
1916                         struct xhci_virt_ep *ep, int *status)
1917 {
1918         struct xhci_ring *ep_ring;
1919         struct urb_priv *urb_priv;
1920         struct usb_iso_packet_descriptor *frame;
1921         int idx;
1922
1923         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1924         urb_priv = td->urb->hcpriv;
1925         idx = urb_priv->td_cnt;
1926         frame = &td->urb->iso_frame_desc[idx];
1927
1928         /* The transfer is partly done. */
1929         frame->status = -EXDEV;
1930
1931         /* calc actual length */
1932         frame->actual_length = 0;
1933
1934         /* Update ring dequeue pointer */
1935         while (ep_ring->dequeue != td->last_trb)
1936                 inc_deq(xhci, ep_ring, false);
1937         inc_deq(xhci, ep_ring, false);
1938
1939         return finish_td(xhci, td, NULL, event, ep, status, true);
1940 }
1941
1942 /*
1943  * Process bulk and interrupt tds, update urb status and actual_length.
1944  */
1945 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1946         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1947         struct xhci_virt_ep *ep, int *status)
1948 {
1949         struct xhci_ring *ep_ring;
1950         union xhci_trb *cur_trb;
1951         struct xhci_segment *cur_seg;
1952         u32 trb_comp_code;
1953
1954         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1955         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1956
1957         switch (trb_comp_code) {
1958         case COMP_SUCCESS:
1959                 /* Double check that the HW transferred everything. */
1960                 if (event_trb != td->last_trb ||
1961                                 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1962                         xhci_warn(xhci, "WARN Successful completion "
1963                                         "on short TX\n");
1964                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1965                                 *status = -EREMOTEIO;
1966                         else
1967                                 *status = 0;
1968                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1969                                 trb_comp_code = COMP_SHORT_TX;
1970                 } else {
1971                         *status = 0;
1972                 }
1973                 break;
1974         case COMP_SHORT_TX:
1975                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1976                         *status = -EREMOTEIO;
1977                 else
1978                         *status = 0;
1979                 break;
1980         default:
1981                 /* Others already handled above */
1982                 break;
1983         }
1984         if (trb_comp_code == COMP_SHORT_TX)
1985                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1986                                 "%d bytes untransferred\n",
1987                                 td->urb->ep->desc.bEndpointAddress,
1988                                 td->urb->transfer_buffer_length,
1989                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1990         /* Fast path - was this the last TRB in the TD for this URB? */
1991         if (event_trb == td->last_trb) {
1992                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1993                         td->urb->actual_length =
1994                                 td->urb->transfer_buffer_length -
1995                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1996                         if (td->urb->transfer_buffer_length <
1997                                         td->urb->actual_length) {
1998                                 xhci_warn(xhci, "HC gave bad length "
1999                                                 "of %d bytes left\n",
2000                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
2001                                 td->urb->actual_length = 0;
2002                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2003                                         *status = -EREMOTEIO;
2004                                 else
2005                                         *status = 0;
2006                         }
2007                         /* Don't overwrite a previously set error code */
2008                         if (*status == -EINPROGRESS) {
2009                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2010                                         *status = -EREMOTEIO;
2011                                 else
2012                                         *status = 0;
2013                         }
2014                 } else {
2015                         td->urb->actual_length =
2016                                 td->urb->transfer_buffer_length;
2017                         /* Ignore a short packet completion if the
2018                          * untransferred length was zero.
2019                          */
2020                         if (*status == -EREMOTEIO)
2021                                 *status = 0;
2022                 }
2023         } else {
2024                 /* Slow path - walk the list, starting from the dequeue
2025                  * pointer, to get the actual length transferred.
2026                  */
2027                 td->urb->actual_length = 0;
2028                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2029                                 cur_trb != event_trb;
2030                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2031                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2032                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2033                                 td->urb->actual_length +=
2034                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2035                 }
2036                 /* If the ring didn't stop on a Link or No-op TRB, add
2037                  * in the actual bytes transferred from the Normal TRB
2038                  */
2039                 if (trb_comp_code != COMP_STOP_INVAL)
2040                         td->urb->actual_length +=
2041                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2042                                 TRB_LEN(le32_to_cpu(event->transfer_len));
2043         }
2044
2045         return finish_td(xhci, td, event_trb, event, ep, status, false);
2046 }
2047
2048 /*
2049  * If this function returns an error condition, it means it got a Transfer
2050  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2051  * At this point, the host controller is probably hosed and should be reset.
2052  */
2053 static int handle_tx_event(struct xhci_hcd *xhci,
2054                 struct xhci_transfer_event *event)
2055 {
2056         struct xhci_virt_device *xdev;
2057         struct xhci_virt_ep *ep;
2058         struct xhci_ring *ep_ring;
2059         unsigned int slot_id;
2060         int ep_index;
2061         struct xhci_td *td = NULL;
2062         dma_addr_t event_dma;
2063         struct xhci_segment *event_seg;
2064         union xhci_trb *event_trb;
2065         struct urb *urb = NULL;
2066         int status = -EINPROGRESS;
2067         struct urb_priv *urb_priv;
2068         struct xhci_ep_ctx *ep_ctx;
2069         struct list_head *tmp;
2070         u32 trb_comp_code;
2071         int ret = 0;
2072         int td_num = 0;
2073
2074         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2075         xdev = xhci->devs[slot_id];
2076         if (!xdev) {
2077                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2078                 return -ENODEV;
2079         }
2080
2081         /* Endpoint ID is 1 based, our index is zero based */
2082         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2083         ep = &xdev->eps[ep_index];
2084         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2085         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2086         if (!ep_ring ||
2087             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2088             EP_STATE_DISABLED) {
2089                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2090                                 "or incorrect stream ring\n");
2091                 return -ENODEV;
2092         }
2093
2094         /* Count current td numbers if ep->skip is set */
2095         if (ep->skip) {
2096                 list_for_each(tmp, &ep_ring->td_list)
2097                         td_num++;
2098         }
2099
2100         event_dma = le64_to_cpu(event->buffer);
2101         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2102         /* Look for common error cases */
2103         switch (trb_comp_code) {
2104         /* Skip codes that require special handling depending on
2105          * transfer type
2106          */
2107         case COMP_SUCCESS:
2108                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2109                         break;
2110                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2111                         trb_comp_code = COMP_SHORT_TX;
2112                 else
2113                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2114                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2115         case COMP_SHORT_TX:
2116                 break;
2117         case COMP_STOP:
2118                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2119                 break;
2120         case COMP_STOP_INVAL:
2121                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2122                 break;
2123         case COMP_STALL:
2124                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
2125                 ep->ep_state |= EP_HALTED;
2126                 status = -EPIPE;
2127                 break;
2128         case COMP_TRB_ERR:
2129                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2130                 status = -EILSEQ;
2131                 break;
2132         case COMP_SPLIT_ERR:
2133         case COMP_TX_ERR:
2134                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
2135                 status = -EPROTO;
2136                 break;
2137         case COMP_BABBLE:
2138                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2139                 status = -EOVERFLOW;
2140                 break;
2141         case COMP_DB_ERR:
2142                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2143                 status = -ENOSR;
2144                 break;
2145         case COMP_BW_OVER:
2146                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2147                 break;
2148         case COMP_BUFF_OVER:
2149                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2150                 break;
2151         case COMP_UNDERRUN:
2152                 /*
2153                  * When the Isoch ring is empty, the xHC will generate
2154                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2155                  * Underrun Event for OUT Isoch endpoint.
2156                  */
2157                 xhci_dbg(xhci, "underrun event on endpoint\n");
2158                 if (!list_empty(&ep_ring->td_list))
2159                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2160                                         "still with TDs queued?\n",
2161                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2162                                  ep_index);
2163                 goto cleanup;
2164         case COMP_OVERRUN:
2165                 xhci_dbg(xhci, "overrun event on endpoint\n");
2166                 if (!list_empty(&ep_ring->td_list))
2167                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2168                                         "still with TDs queued?\n",
2169                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2170                                  ep_index);
2171                 goto cleanup;
2172         case COMP_DEV_ERR:
2173                 xhci_warn(xhci, "WARN: detect an incompatible device");
2174                 status = -EPROTO;
2175                 break;
2176         case COMP_MISSED_INT:
2177                 /*
2178                  * When encounter missed service error, one or more isoc tds
2179                  * may be missed by xHC.
2180                  * Set skip flag of the ep_ring; Complete the missed tds as
2181                  * short transfer when process the ep_ring next time.
2182                  */
2183                 ep->skip = true;
2184                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2185                 goto cleanup;
2186         default:
2187                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2188                         status = 0;
2189                         break;
2190                 }
2191                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2192                                 "busted\n");
2193                 goto cleanup;
2194         }
2195
2196         do {
2197                 /* This TRB should be in the TD at the head of this ring's
2198                  * TD list.
2199                  */
2200                 if (list_empty(&ep_ring->td_list)) {
2201                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2202                                         "with no TDs queued?\n",
2203                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2204                                   ep_index);
2205                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2206                                  (le32_to_cpu(event->flags) &
2207                                   TRB_TYPE_BITMASK)>>10);
2208                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2209                         if (ep->skip) {
2210                                 ep->skip = false;
2211                                 xhci_dbg(xhci, "td_list is empty while skip "
2212                                                 "flag set. Clear skip flag.\n");
2213                         }
2214                         ret = 0;
2215                         goto cleanup;
2216                 }
2217
2218                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2219                 if (ep->skip && td_num == 0) {
2220                         ep->skip = false;
2221                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2222                                                 "Clear skip flag.\n");
2223                         ret = 0;
2224                         goto cleanup;
2225                 }
2226
2227                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2228                 if (ep->skip)
2229                         td_num--;
2230
2231                 /* Is this a TRB in the currently executing TD? */
2232                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2233                                 td->last_trb, event_dma);
2234
2235                 /*
2236                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2237                  * is not in the current TD pointed by ep_ring->dequeue because
2238                  * that the hardware dequeue pointer still at the previous TRB
2239                  * of the current TD. The previous TRB maybe a Link TD or the
2240                  * last TRB of the previous TD. The command completion handle
2241                  * will take care the rest.
2242                  */
2243                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2244                         ret = 0;
2245                         goto cleanup;
2246                 }
2247
2248                 if (!event_seg) {
2249                         if (!ep->skip ||
2250                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2251                                 /* Some host controllers give a spurious
2252                                  * successful event after a short transfer.
2253                                  * Ignore it.
2254                                  */
2255                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2256                                                 ep_ring->last_td_was_short) {
2257                                         ep_ring->last_td_was_short = false;
2258                                         ret = 0;
2259                                         goto cleanup;
2260                                 }
2261                                 /* HC is busted, give up! */
2262                                 xhci_err(xhci,
2263                                         "ERROR Transfer event TRB DMA ptr not "
2264                                         "part of current TD\n");
2265                                 return -ESHUTDOWN;
2266                         }
2267
2268                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2269                         goto cleanup;
2270                 }
2271                 if (trb_comp_code == COMP_SHORT_TX)
2272                         ep_ring->last_td_was_short = true;
2273                 else
2274                         ep_ring->last_td_was_short = false;
2275
2276                 if (ep->skip) {
2277                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2278                         ep->skip = false;
2279                 }
2280
2281                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2282                                                 sizeof(*event_trb)];
2283                 /*
2284                  * No-op TRB should not trigger interrupts.
2285                  * If event_trb is a no-op TRB, it means the
2286                  * corresponding TD has been cancelled. Just ignore
2287                  * the TD.
2288                  */
2289                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2290                         xhci_dbg(xhci,
2291                                  "event_trb is a no-op TRB. Skip it\n");
2292                         goto cleanup;
2293                 }
2294
2295                 /* Now update the urb's actual_length and give back to
2296                  * the core
2297                  */
2298                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2299                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2300                                                  &status);
2301                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2302                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2303                                                  &status);
2304                 else
2305                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2306                                                  ep, &status);
2307
2308 cleanup:
2309                 /*
2310                  * Do not update event ring dequeue pointer if ep->skip is set.
2311                  * Will roll back to continue process missed tds.
2312                  */
2313                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2314                         inc_deq(xhci, xhci->event_ring, true);
2315                 }
2316
2317                 if (ret) {
2318                         urb = td->urb;
2319                         urb_priv = urb->hcpriv;
2320                         /* Leave the TD around for the reset endpoint function
2321                          * to use(but only if it's not a control endpoint,
2322                          * since we already queued the Set TR dequeue pointer
2323                          * command for stalled control endpoints).
2324                          */
2325                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2326                                 (trb_comp_code != COMP_STALL &&
2327                                         trb_comp_code != COMP_BABBLE))
2328                                 xhci_urb_free_priv(xhci, urb_priv);
2329
2330                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2331                         if ((urb->actual_length != urb->transfer_buffer_length &&
2332                                                 (urb->transfer_flags &
2333                                                  URB_SHORT_NOT_OK)) ||
2334                                         (status != 0 &&
2335                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2336                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2337                                                 "expected = %x, status = %d\n",
2338                                                 urb, urb->actual_length,
2339                                                 urb->transfer_buffer_length,
2340                                                 status);
2341                         spin_unlock(&xhci->lock);
2342                         /* EHCI, UHCI, and OHCI always unconditionally set the
2343                          * urb->status of an isochronous endpoint to 0.
2344                          */
2345                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2346                                 status = 0;
2347                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2348                         spin_lock(&xhci->lock);
2349                 }
2350
2351         /*
2352          * If ep->skip is set, it means there are missed tds on the
2353          * endpoint ring need to take care of.
2354          * Process them as short transfer until reach the td pointed by
2355          * the event.
2356          */
2357         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2358
2359         return 0;
2360 }
2361
2362 /*
2363  * This function handles all OS-owned events on the event ring.  It may drop
2364  * xhci->lock between event processing (e.g. to pass up port status changes).
2365  * Returns >0 for "possibly more events to process" (caller should call again),
2366  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2367  */
2368 static int xhci_handle_event(struct xhci_hcd *xhci)
2369 {
2370         union xhci_trb *event;
2371         int update_ptrs = 1;
2372         int ret;
2373
2374         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2375                 xhci->error_bitmask |= 1 << 1;
2376                 return 0;
2377         }
2378
2379         event = xhci->event_ring->dequeue;
2380         /* Does the HC or OS own the TRB? */
2381         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2382             xhci->event_ring->cycle_state) {
2383                 xhci->error_bitmask |= 1 << 2;
2384                 return 0;
2385         }
2386
2387         /*
2388          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2389          * speculative reads of the event's flags/data below.
2390          */
2391         rmb();
2392         /* FIXME: Handle more event types. */
2393         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2394         case TRB_TYPE(TRB_COMPLETION):
2395                 handle_cmd_completion(xhci, &event->event_cmd);
2396                 break;
2397         case TRB_TYPE(TRB_PORT_STATUS):
2398                 handle_port_status(xhci, event);
2399                 update_ptrs = 0;
2400                 break;
2401         case TRB_TYPE(TRB_TRANSFER):
2402                 ret = handle_tx_event(xhci, &event->trans_event);
2403                 if (ret < 0)
2404                         xhci->error_bitmask |= 1 << 9;
2405                 else
2406                         update_ptrs = 0;
2407                 break;
2408         default:
2409                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2410                     TRB_TYPE(48))
2411                         handle_vendor_event(xhci, event);
2412                 else
2413                         xhci->error_bitmask |= 1 << 3;
2414         }
2415         /* Any of the above functions may drop and re-acquire the lock, so check
2416          * to make sure a watchdog timer didn't mark the host as non-responsive.
2417          */
2418         if (xhci->xhc_state & XHCI_STATE_DYING) {
2419                 xhci_dbg(xhci, "xHCI host dying, returning from "
2420                                 "event handler.\n");
2421                 return 0;
2422         }
2423
2424         if (update_ptrs)
2425                 /* Update SW event ring dequeue pointer */
2426                 inc_deq(xhci, xhci->event_ring, true);
2427
2428         /* Are there more items on the event ring?  Caller will call us again to
2429          * check.
2430          */
2431         return 1;
2432 }
2433
2434 /*
2435  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2436  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2437  * indicators of an event TRB error, but we check the status *first* to be safe.
2438  */
2439 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2440 {
2441         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2442         u32 status;
2443         union xhci_trb *trb;
2444         u64 temp_64;
2445         union xhci_trb *event_ring_deq;
2446         dma_addr_t deq;
2447
2448         spin_lock(&xhci->lock);
2449         trb = xhci->event_ring->dequeue;
2450         /* Check if the xHC generated the interrupt, or the irq is shared */
2451         status = xhci_readl(xhci, &xhci->op_regs->status);
2452         if (status == 0xffffffff)
2453                 goto hw_died;
2454
2455         if (!(status & STS_EINT)) {
2456                 spin_unlock(&xhci->lock);
2457                 return IRQ_NONE;
2458         }
2459         if (status & STS_FATAL) {
2460                 xhci_warn(xhci, "WARNING: Host System Error\n");
2461                 xhci_halt(xhci);
2462 hw_died:
2463                 spin_unlock(&xhci->lock);
2464                 return -ESHUTDOWN;
2465         }
2466
2467         /*
2468          * Clear the op reg interrupt status first,
2469          * so we can receive interrupts from other MSI-X interrupters.
2470          * Write 1 to clear the interrupt status.
2471          */
2472         status |= STS_EINT;
2473         xhci_writel(xhci, status, &xhci->op_regs->status);
2474         /* FIXME when MSI-X is supported and there are multiple vectors */
2475         /* Clear the MSI-X event interrupt status */
2476
2477         if (hcd->irq != -1) {
2478                 u32 irq_pending;
2479                 /* Acknowledge the PCI interrupt */
2480                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2481                 irq_pending |= IMAN_IP;
2482                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2483         }
2484
2485         if (xhci->xhc_state & XHCI_STATE_DYING) {
2486                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2487                                 "Shouldn't IRQs be disabled?\n");
2488                 /* Clear the event handler busy flag (RW1C);
2489                  * the event ring should be empty.
2490                  */
2491                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2492                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2493                                 &xhci->ir_set->erst_dequeue);
2494                 spin_unlock(&xhci->lock);
2495
2496                 return IRQ_HANDLED;
2497         }
2498
2499         event_ring_deq = xhci->event_ring->dequeue;
2500         /* FIXME this should be a delayed service routine
2501          * that clears the EHB.
2502          */
2503         while (xhci_handle_event(xhci) > 0) {}
2504
2505         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2506         /* If necessary, update the HW's version of the event ring deq ptr. */
2507         if (event_ring_deq != xhci->event_ring->dequeue) {
2508                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2509                                 xhci->event_ring->dequeue);
2510                 if (deq == 0)
2511                         xhci_warn(xhci, "WARN something wrong with SW event "
2512                                         "ring dequeue ptr.\n");
2513                 /* Update HC event ring dequeue pointer */
2514                 temp_64 &= ERST_PTR_MASK;
2515                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2516         }
2517
2518         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2519         temp_64 |= ERST_EHB;
2520         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2521
2522         spin_unlock(&xhci->lock);
2523
2524         return IRQ_HANDLED;
2525 }
2526
2527 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2528 {
2529         irqreturn_t ret;
2530         struct xhci_hcd *xhci;
2531
2532         xhci = hcd_to_xhci(hcd);
2533         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2534         if (xhci->shared_hcd)
2535                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2536
2537         ret = xhci_irq(hcd);
2538
2539         return ret;
2540 }
2541
2542 /****           Endpoint Ring Operations        ****/
2543
2544 /*
2545  * Generic function for queueing a TRB on a ring.
2546  * The caller must have checked to make sure there's room on the ring.
2547  *
2548  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2549  *                      prepare_transfer()?
2550  */
2551 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2552                 bool consumer, bool more_trbs_coming, bool isoc,
2553                 u32 field1, u32 field2, u32 field3, u32 field4)
2554 {
2555         struct xhci_generic_trb *trb;
2556
2557         trb = &ring->enqueue->generic;
2558         trb->field[0] = cpu_to_le32(field1);
2559         trb->field[1] = cpu_to_le32(field2);
2560         trb->field[2] = cpu_to_le32(field3);
2561         trb->field[3] = cpu_to_le32(field4);
2562         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2563 }
2564
2565 /*
2566  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2567  * FIXME allocate segments if the ring is full.
2568  */
2569 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2570                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2571 {
2572         /* Make sure the endpoint has been added to xHC schedule */
2573         switch (ep_state) {
2574         case EP_STATE_DISABLED:
2575                 /*
2576                  * USB core changed config/interfaces without notifying us,
2577                  * or hardware is reporting the wrong state.
2578                  */
2579                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2580                 return -ENOENT;
2581         case EP_STATE_ERROR:
2582                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2583                 /* FIXME event handling code for error needs to clear it */
2584                 /* XXX not sure if this should be -ENOENT or not */
2585                 return -EINVAL;
2586         case EP_STATE_HALTED:
2587                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2588         case EP_STATE_STOPPED:
2589         case EP_STATE_RUNNING:
2590                 break;
2591         default:
2592                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2593                 /*
2594                  * FIXME issue Configure Endpoint command to try to get the HC
2595                  * back into a known state.
2596                  */
2597                 return -EINVAL;
2598         }
2599         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2600                 /* FIXME allocate more room */
2601                 xhci_err(xhci, "ERROR no room on ep ring\n");
2602                 return -ENOMEM;
2603         }
2604
2605         if (enqueue_is_link_trb(ep_ring)) {
2606                 struct xhci_ring *ring = ep_ring;
2607                 union xhci_trb *next;
2608
2609                 next = ring->enqueue;
2610
2611                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2612                         /* If we're not dealing with 0.95 hardware or isoc rings
2613                          * on AMD 0.96 host, clear the chain bit.
2614                          */
2615                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2616                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2617                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2618                         else
2619                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2620
2621                         wmb();
2622                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2623
2624                         /* Toggle the cycle bit after the last ring segment. */
2625                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2626                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2627                                 if (!in_interrupt()) {
2628                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2629                                                 "state for ring %p = %i\n",
2630                                                 ring, (unsigned int)ring->cycle_state);
2631                                 }
2632                         }
2633                         ring->enq_seg = ring->enq_seg->next;
2634                         ring->enqueue = ring->enq_seg->trbs;
2635                         next = ring->enqueue;
2636                 }
2637         }
2638
2639         return 0;
2640 }
2641
2642 static int prepare_transfer(struct xhci_hcd *xhci,
2643                 struct xhci_virt_device *xdev,
2644                 unsigned int ep_index,
2645                 unsigned int stream_id,
2646                 unsigned int num_trbs,
2647                 struct urb *urb,
2648                 unsigned int td_index,
2649                 bool isoc,
2650                 gfp_t mem_flags)
2651 {
2652         int ret;
2653         struct urb_priv *urb_priv;
2654         struct xhci_td  *td;
2655         struct xhci_ring *ep_ring;
2656         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2657
2658         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2659         if (!ep_ring) {
2660                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2661                                 stream_id);
2662                 return -EINVAL;
2663         }
2664
2665         ret = prepare_ring(xhci, ep_ring,
2666                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2667                            num_trbs, isoc, mem_flags);
2668         if (ret)
2669                 return ret;
2670
2671         urb_priv = urb->hcpriv;
2672         td = urb_priv->td[td_index];
2673
2674         INIT_LIST_HEAD(&td->td_list);
2675         INIT_LIST_HEAD(&td->cancelled_td_list);
2676
2677         if (td_index == 0) {
2678                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2679                 if (unlikely(ret))
2680                         return ret;
2681         }
2682
2683         td->urb = urb;
2684         /* Add this TD to the tail of the endpoint ring's TD list */
2685         list_add_tail(&td->td_list, &ep_ring->td_list);
2686         td->start_seg = ep_ring->enq_seg;
2687         td->first_trb = ep_ring->enqueue;
2688
2689         urb_priv->td[td_index] = td;
2690
2691         return 0;
2692 }
2693
2694 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2695 {
2696         int num_sgs, num_trbs, running_total, temp, i;
2697         struct scatterlist *sg;
2698
2699         sg = NULL;
2700         num_sgs = urb->num_mapped_sgs;
2701         temp = urb->transfer_buffer_length;
2702
2703         xhci_dbg(xhci, "count sg list trbs: \n");
2704         num_trbs = 0;
2705         for_each_sg(urb->sg, sg, num_sgs, i) {
2706                 unsigned int previous_total_trbs = num_trbs;
2707                 unsigned int len = sg_dma_len(sg);
2708
2709                 /* Scatter gather list entries may cross 64KB boundaries */
2710                 running_total = TRB_MAX_BUFF_SIZE -
2711                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2712                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2713                 if (running_total != 0)
2714                         num_trbs++;
2715
2716                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2717                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2718                         num_trbs++;
2719                         running_total += TRB_MAX_BUFF_SIZE;
2720                 }
2721                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2722                                 i, (unsigned long long)sg_dma_address(sg),
2723                                 len, len, num_trbs - previous_total_trbs);
2724
2725                 len = min_t(int, len, temp);
2726                 temp -= len;
2727                 if (temp == 0)
2728                         break;
2729         }
2730         xhci_dbg(xhci, "\n");
2731         if (!in_interrupt())
2732                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2733                                 "num_trbs = %d\n",
2734                                 urb->ep->desc.bEndpointAddress,
2735                                 urb->transfer_buffer_length,
2736                                 num_trbs);
2737         return num_trbs;
2738 }
2739
2740 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2741 {
2742         if (num_trbs != 0)
2743                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2744                                 "TRBs, %d left\n", __func__,
2745                                 urb->ep->desc.bEndpointAddress, num_trbs);
2746         if (running_total != urb->transfer_buffer_length)
2747                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2748                                 "queued %#x (%d), asked for %#x (%d)\n",
2749                                 __func__,
2750                                 urb->ep->desc.bEndpointAddress,
2751                                 running_total, running_total,
2752                                 urb->transfer_buffer_length,
2753                                 urb->transfer_buffer_length);
2754 }
2755
2756 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2757                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2758                 struct xhci_generic_trb *start_trb)
2759 {
2760         /*
2761          * Pass all the TRBs to the hardware at once and make sure this write
2762          * isn't reordered.
2763          */
2764         wmb();
2765         if (start_cycle)
2766                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2767         else
2768                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2769         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2770 }
2771
2772 /*
2773  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2774  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2775  * (comprised of sg list entries) can take several service intervals to
2776  * transmit.
2777  */
2778 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2779                 struct urb *urb, int slot_id, unsigned int ep_index)
2780 {
2781         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2782                         xhci->devs[slot_id]->out_ctx, ep_index);
2783         int xhci_interval;
2784         int ep_interval;
2785
2786         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2787         ep_interval = urb->interval;
2788         /* Convert to microframes */
2789         if (urb->dev->speed == USB_SPEED_LOW ||
2790                         urb->dev->speed == USB_SPEED_FULL)
2791                 ep_interval *= 8;
2792         /* FIXME change this to a warning and a suggestion to use the new API
2793          * to set the polling interval (once the API is added).
2794          */
2795         if (xhci_interval != ep_interval) {
2796                 if (printk_ratelimit())
2797                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2798                                         " (%d microframe%s) than xHCI "
2799                                         "(%d microframe%s)\n",
2800                                         ep_interval,
2801                                         ep_interval == 1 ? "" : "s",
2802                                         xhci_interval,
2803                                         xhci_interval == 1 ? "" : "s");
2804                 urb->interval = xhci_interval;
2805                 /* Convert back to frames for LS/FS devices */
2806                 if (urb->dev->speed == USB_SPEED_LOW ||
2807                                 urb->dev->speed == USB_SPEED_FULL)
2808                         urb->interval /= 8;
2809         }
2810         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2811 }
2812
2813 /*
2814  * The TD size is the number of bytes remaining in the TD (including this TRB),
2815  * right shifted by 10.
2816  * It must fit in bits 21:17, so it can't be bigger than 31.
2817  */
2818 static u32 xhci_td_remainder(unsigned int remainder)
2819 {
2820         u32 max = (1 << (21 - 17 + 1)) - 1;
2821
2822         if ((remainder >> 10) >= max)
2823                 return max << 17;
2824         else
2825                 return (remainder >> 10) << 17;
2826 }
2827
2828 /*
2829  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2830  * the TD (*not* including this TRB).
2831  *
2832  * Total TD packet count = total_packet_count =
2833  *     roundup(TD size in bytes / wMaxPacketSize)
2834  *
2835  * Packets transferred up to and including this TRB = packets_transferred =
2836  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2837  *
2838  * TD size = total_packet_count - packets_transferred
2839  *
2840  * It must fit in bits 21:17, so it can't be bigger than 31.
2841  */
2842
2843 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2844                 unsigned int total_packet_count, struct urb *urb)
2845 {
2846         int packets_transferred;
2847
2848         /* One TRB with a zero-length data packet. */
2849         if (running_total == 0 && trb_buff_len == 0)
2850                 return 0;
2851
2852         /* All the TRB queueing functions don't count the current TRB in
2853          * running_total.
2854          */
2855         packets_transferred = (running_total + trb_buff_len) /
2856                 usb_endpoint_maxp(&urb->ep->desc);
2857
2858         return xhci_td_remainder(total_packet_count - packets_transferred);
2859 }
2860
2861 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2862                 struct urb *urb, int slot_id, unsigned int ep_index)
2863 {
2864         struct xhci_ring *ep_ring;
2865         unsigned int num_trbs;
2866         struct urb_priv *urb_priv;
2867         struct xhci_td *td;
2868         struct scatterlist *sg;
2869         int num_sgs;
2870         int trb_buff_len, this_sg_len, running_total;
2871         unsigned int total_packet_count;
2872         bool first_trb;
2873         u64 addr;
2874         bool more_trbs_coming;
2875
2876         struct xhci_generic_trb *start_trb;
2877         int start_cycle;
2878
2879         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2880         if (!ep_ring)
2881                 return -EINVAL;
2882
2883         num_trbs = count_sg_trbs_needed(xhci, urb);
2884         num_sgs = urb->num_mapped_sgs;
2885         total_packet_count = roundup(urb->transfer_buffer_length,
2886                         usb_endpoint_maxp(&urb->ep->desc));
2887
2888         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2889                         ep_index, urb->stream_id,
2890                         num_trbs, urb, 0, false, mem_flags);
2891         if (trb_buff_len < 0)
2892                 return trb_buff_len;
2893
2894         urb_priv = urb->hcpriv;
2895         td = urb_priv->td[0];
2896
2897         /*
2898          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2899          * until we've finished creating all the other TRBs.  The ring's cycle
2900          * state may change as we enqueue the other TRBs, so save it too.
2901          */
2902         start_trb = &ep_ring->enqueue->generic;
2903         start_cycle = ep_ring->cycle_state;
2904
2905         running_total = 0;
2906         /*
2907          * How much data is in the first TRB?
2908          *
2909          * There are three forces at work for TRB buffer pointers and lengths:
2910          * 1. We don't want to walk off the end of this sg-list entry buffer.
2911          * 2. The transfer length that the driver requested may be smaller than
2912          *    the amount of memory allocated for this scatter-gather list.
2913          * 3. TRBs buffers can't cross 64KB boundaries.
2914          */
2915         sg = urb->sg;
2916         addr = (u64) sg_dma_address(sg);
2917         this_sg_len = sg_dma_len(sg);
2918         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2919         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2920         if (trb_buff_len > urb->transfer_buffer_length)
2921                 trb_buff_len = urb->transfer_buffer_length;
2922         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2923                         trb_buff_len);
2924
2925         first_trb = true;
2926         /* Queue the first TRB, even if it's zero-length */
2927         do {
2928                 u32 field = 0;
2929                 u32 length_field = 0;
2930                 u32 remainder = 0;
2931
2932                 /* Don't change the cycle bit of the first TRB until later */
2933                 if (first_trb) {
2934                         first_trb = false;
2935                         if (start_cycle == 0)
2936                                 field |= 0x1;
2937                 } else
2938                         field |= ep_ring->cycle_state;
2939
2940                 /* Chain all the TRBs together; clear the chain bit in the last
2941                  * TRB to indicate it's the last TRB in the chain.
2942                  */
2943                 if (num_trbs > 1) {
2944                         field |= TRB_CHAIN;
2945                 } else {
2946                         /* FIXME - add check for ZERO_PACKET flag before this */
2947                         td->last_trb = ep_ring->enqueue;
2948                         field |= TRB_IOC;
2949                 }
2950
2951                 /* Only set interrupt on short packet for IN endpoints */
2952                 if (usb_urb_dir_in(urb))
2953                         field |= TRB_ISP;
2954
2955                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2956                                 "64KB boundary at %#x, end dma = %#x\n",
2957                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2958                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2959                                 (unsigned int) addr + trb_buff_len);
2960                 if (TRB_MAX_BUFF_SIZE -
2961                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2962                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2963                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2964                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2965                                         (unsigned int) addr + trb_buff_len);
2966                 }
2967
2968                 /* Set the TRB length, TD size, and interrupter fields. */
2969                 if (xhci->hci_version < 0x100) {
2970                         remainder = xhci_td_remainder(
2971                                         urb->transfer_buffer_length -
2972                                         running_total);
2973                 } else {
2974                         remainder = xhci_v1_0_td_remainder(running_total,
2975                                         trb_buff_len, total_packet_count, urb);
2976                 }
2977                 length_field = TRB_LEN(trb_buff_len) |
2978                         remainder |
2979                         TRB_INTR_TARGET(0);
2980
2981                 if (num_trbs > 1)
2982                         more_trbs_coming = true;
2983                 else
2984                         more_trbs_coming = false;
2985                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2986                                 lower_32_bits(addr),
2987                                 upper_32_bits(addr),
2988                                 length_field,
2989                                 field | TRB_TYPE(TRB_NORMAL));
2990                 --num_trbs;
2991                 running_total += trb_buff_len;
2992
2993                 /* Calculate length for next transfer --
2994                  * Are we done queueing all the TRBs for this sg entry?
2995                  */
2996                 this_sg_len -= trb_buff_len;
2997                 if (this_sg_len == 0) {
2998                         --num_sgs;
2999                         if (num_sgs == 0)
3000                                 break;
3001                         sg = sg_next(sg);
3002                         addr = (u64) sg_dma_address(sg);
3003                         this_sg_len = sg_dma_len(sg);
3004                 } else {
3005                         addr += trb_buff_len;
3006                 }
3007
3008                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3009                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3010                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3011                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3012                         trb_buff_len =
3013                                 urb->transfer_buffer_length - running_total;
3014         } while (running_total < urb->transfer_buffer_length);
3015
3016         check_trb_math(urb, num_trbs, running_total);
3017         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3018                         start_cycle, start_trb);
3019         return 0;
3020 }
3021
3022 /* This is very similar to what ehci-q.c qtd_fill() does */
3023 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3024                 struct urb *urb, int slot_id, unsigned int ep_index)
3025 {
3026         struct xhci_ring *ep_ring;
3027         struct urb_priv *urb_priv;
3028         struct xhci_td *td;
3029         int num_trbs;
3030         struct xhci_generic_trb *start_trb;
3031         bool first_trb;
3032         bool more_trbs_coming;
3033         int start_cycle;
3034         u32 field, length_field;
3035
3036         int running_total, trb_buff_len, ret;
3037         unsigned int total_packet_count;
3038         u64 addr;
3039
3040         if (urb->num_sgs)
3041                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3042
3043         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3044         if (!ep_ring)
3045                 return -EINVAL;
3046
3047         num_trbs = 0;
3048         /* How much data is (potentially) left before the 64KB boundary? */
3049         running_total = TRB_MAX_BUFF_SIZE -
3050                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3051         running_total &= TRB_MAX_BUFF_SIZE - 1;
3052
3053         /* If there's some data on this 64KB chunk, or we have to send a
3054          * zero-length transfer, we need at least one TRB
3055          */
3056         if (running_total != 0 || urb->transfer_buffer_length == 0)
3057                 num_trbs++;
3058         /* How many more 64KB chunks to transfer, how many more TRBs? */
3059         while (running_total < urb->transfer_buffer_length) {
3060                 num_trbs++;
3061                 running_total += TRB_MAX_BUFF_SIZE;
3062         }
3063         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3064
3065         if (!in_interrupt())
3066                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3067                                 "addr = %#llx, num_trbs = %d\n",
3068                                 urb->ep->desc.bEndpointAddress,
3069                                 urb->transfer_buffer_length,
3070                                 urb->transfer_buffer_length,
3071                                 (unsigned long long)urb->transfer_dma,
3072                                 num_trbs);
3073
3074         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3075                         ep_index, urb->stream_id,
3076                         num_trbs, urb, 0, false, mem_flags);
3077         if (ret < 0)
3078                 return ret;
3079
3080         urb_priv = urb->hcpriv;
3081         td = urb_priv->td[0];
3082
3083         /*
3084          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3085          * until we've finished creating all the other TRBs.  The ring's cycle
3086          * state may change as we enqueue the other TRBs, so save it too.
3087          */
3088         start_trb = &ep_ring->enqueue->generic;
3089         start_cycle = ep_ring->cycle_state;
3090
3091         running_total = 0;
3092         total_packet_count = roundup(urb->transfer_buffer_length,
3093                         usb_endpoint_maxp(&urb->ep->desc));
3094         /* How much data is in the first TRB? */
3095         addr = (u64) urb->transfer_dma;
3096         trb_buff_len = TRB_MAX_BUFF_SIZE -
3097                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3098         if (trb_buff_len > urb->transfer_buffer_length)
3099                 trb_buff_len = urb->transfer_buffer_length;
3100
3101         first_trb = true;
3102
3103         /* Queue the first TRB, even if it's zero-length */
3104         do {
3105                 u32 remainder = 0;
3106                 field = 0;
3107
3108                 /* Don't change the cycle bit of the first TRB until later */
3109                 if (first_trb) {
3110                         first_trb = false;
3111                         if (start_cycle == 0)
3112                                 field |= 0x1;
3113                 } else
3114                         field |= ep_ring->cycle_state;
3115
3116                 /* Chain all the TRBs together; clear the chain bit in the last
3117                  * TRB to indicate it's the last TRB in the chain.
3118                  */
3119                 if (num_trbs > 1) {
3120                         field |= TRB_CHAIN;
3121                 } else {
3122                         /* FIXME - add check for ZERO_PACKET flag before this */
3123                         td->last_trb = ep_ring->enqueue;
3124                         field |= TRB_IOC;
3125                 }
3126
3127                 /* Only set interrupt on short packet for IN endpoints */
3128                 if (usb_urb_dir_in(urb))
3129                         field |= TRB_ISP;
3130
3131                 /* Set the TRB length, TD size, and interrupter fields. */
3132                 if (xhci->hci_version < 0x100) {
3133                         remainder = xhci_td_remainder(
3134                                         urb->transfer_buffer_length -
3135                                         running_total);
3136                 } else {
3137                         remainder = xhci_v1_0_td_remainder(running_total,
3138                                         trb_buff_len, total_packet_count, urb);
3139                 }
3140                 length_field = TRB_LEN(trb_buff_len) |
3141                         remainder |
3142                         TRB_INTR_TARGET(0);
3143
3144                 if (num_trbs > 1)
3145                         more_trbs_coming = true;
3146                 else
3147                         more_trbs_coming = false;
3148                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3149                                 lower_32_bits(addr),
3150                                 upper_32_bits(addr),
3151                                 length_field,
3152                                 field | TRB_TYPE(TRB_NORMAL));
3153                 --num_trbs;
3154                 running_total += trb_buff_len;
3155
3156                 /* Calculate length for next transfer */
3157                 addr += trb_buff_len;
3158                 trb_buff_len = urb->transfer_buffer_length - running_total;
3159                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3160                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3161         } while (running_total < urb->transfer_buffer_length);
3162
3163         check_trb_math(urb, num_trbs, running_total);
3164         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3165                         start_cycle, start_trb);
3166         return 0;
3167 }
3168
3169 /* Caller must have locked xhci->lock */
3170 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3171                 struct urb *urb, int slot_id, unsigned int ep_index)
3172 {
3173         struct xhci_ring *ep_ring;
3174         int num_trbs;
3175         int ret;
3176         struct usb_ctrlrequest *setup;
3177         struct xhci_generic_trb *start_trb;
3178         int start_cycle;
3179         u32 field, length_field;
3180         struct urb_priv *urb_priv;
3181         struct xhci_td *td;
3182
3183         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3184         if (!ep_ring)
3185                 return -EINVAL;
3186
3187         /*
3188          * Need to copy setup packet into setup TRB, so we can't use the setup
3189          * DMA address.
3190          */
3191         if (!urb->setup_packet)
3192                 return -EINVAL;
3193
3194         if (!in_interrupt())
3195                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3196                                 slot_id, ep_index);
3197         /* 1 TRB for setup, 1 for status */
3198         num_trbs = 2;
3199         /*
3200          * Don't need to check if we need additional event data and normal TRBs,
3201          * since data in control transfers will never get bigger than 16MB
3202          * XXX: can we get a buffer that crosses 64KB boundaries?
3203          */
3204         if (urb->transfer_buffer_length > 0)
3205                 num_trbs++;
3206         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3207                         ep_index, urb->stream_id,
3208                         num_trbs, urb, 0, false, mem_flags);
3209         if (ret < 0)
3210                 return ret;
3211
3212         urb_priv = urb->hcpriv;
3213         td = urb_priv->td[0];
3214
3215         /*
3216          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3217          * until we've finished creating all the other TRBs.  The ring's cycle
3218          * state may change as we enqueue the other TRBs, so save it too.
3219          */
3220         start_trb = &ep_ring->enqueue->generic;
3221         start_cycle = ep_ring->cycle_state;
3222
3223         /* Queue setup TRB - see section 6.4.1.2.1 */
3224         /* FIXME better way to translate setup_packet into two u32 fields? */
3225         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3226         field = 0;
3227         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3228         if (start_cycle == 0)
3229                 field |= 0x1;
3230
3231         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3232         if (xhci->hci_version == 0x100) {
3233                 if (urb->transfer_buffer_length > 0) {
3234                         if (setup->bRequestType & USB_DIR_IN)
3235                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3236                         else
3237                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3238                 }
3239         }
3240
3241         queue_trb(xhci, ep_ring, false, true, false,
3242                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3243                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3244                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3245                   /* Immediate data in pointer */
3246                   field);
3247
3248         /* If there's data, queue data TRBs */
3249         /* Only set interrupt on short packet for IN endpoints */
3250         if (usb_urb_dir_in(urb))
3251                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3252         else
3253                 field = TRB_TYPE(TRB_DATA);
3254
3255         length_field = TRB_LEN(urb->transfer_buffer_length) |
3256                 xhci_td_remainder(urb->transfer_buffer_length) |
3257                 TRB_INTR_TARGET(0);
3258         if (urb->transfer_buffer_length > 0) {
3259                 if (setup->bRequestType & USB_DIR_IN)
3260                         field |= TRB_DIR_IN;
3261                 queue_trb(xhci, ep_ring, false, true, false,
3262                                 lower_32_bits(urb->transfer_dma),
3263                                 upper_32_bits(urb->transfer_dma),
3264                                 length_field,
3265                                 field | ep_ring->cycle_state);
3266         }
3267
3268         /* Save the DMA address of the last TRB in the TD */
3269         td->last_trb = ep_ring->enqueue;
3270
3271         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3272         /* If the device sent data, the status stage is an OUT transfer */
3273         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3274                 field = 0;
3275         else
3276                 field = TRB_DIR_IN;
3277         queue_trb(xhci, ep_ring, false, false, false,
3278                         0,
3279                         0,
3280                         TRB_INTR_TARGET(0),
3281                         /* Event on completion */
3282                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3283
3284         giveback_first_trb(xhci, slot_id, ep_index, 0,
3285                         start_cycle, start_trb);
3286         return 0;
3287 }
3288
3289 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3290                 struct urb *urb, int i)
3291 {
3292         int num_trbs = 0;
3293         u64 addr, td_len;
3294
3295         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3296         td_len = urb->iso_frame_desc[i].length;
3297
3298         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3299                         TRB_MAX_BUFF_SIZE);
3300         if (num_trbs == 0)
3301                 num_trbs++;
3302
3303         return num_trbs;
3304 }
3305
3306 /*
3307  * The transfer burst count field of the isochronous TRB defines the number of
3308  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3309  * devices can burst up to bMaxBurst number of packets per service interval.
3310  * This field is zero based, meaning a value of zero in the field means one
3311  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3312  * zero.  Only xHCI 1.0 host controllers support this field.
3313  */
3314 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3315                 struct usb_device *udev,
3316                 struct urb *urb, unsigned int total_packet_count)
3317 {
3318         unsigned int max_burst;
3319
3320         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3321                 return 0;
3322
3323         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3324         return roundup(total_packet_count, max_burst + 1) - 1;
3325 }
3326
3327 /*
3328  * Returns the number of packets in the last "burst" of packets.  This field is
3329  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3330  * the last burst packet count is equal to the total number of packets in the
3331  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3332  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3333  * contain 1 to (bMaxBurst + 1) packets.
3334  */
3335 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3336                 struct usb_device *udev,
3337                 struct urb *urb, unsigned int total_packet_count)
3338 {
3339         unsigned int max_burst;
3340         unsigned int residue;
3341
3342         if (xhci->hci_version < 0x100)
3343                 return 0;
3344
3345         switch (udev->speed) {
3346         case USB_SPEED_SUPER:
3347                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3348                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3349                 residue = total_packet_count % (max_burst + 1);
3350                 /* If residue is zero, the last burst contains (max_burst + 1)
3351                  * number of packets, but the TLBPC field is zero-based.
3352                  */
3353                 if (residue == 0)
3354                         return max_burst;
3355                 return residue - 1;
3356         default:
3357                 if (total_packet_count == 0)
3358                         return 0;
3359                 return total_packet_count - 1;
3360         }
3361 }
3362
3363 /* This is for isoc transfer */
3364 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3365                 struct urb *urb, int slot_id, unsigned int ep_index)
3366 {
3367         struct xhci_ring *ep_ring;
3368         struct urb_priv *urb_priv;
3369         struct xhci_td *td;
3370         int num_tds, trbs_per_td;
3371         struct xhci_generic_trb *start_trb;
3372         bool first_trb;
3373         int start_cycle;
3374         u32 field, length_field;
3375         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3376         u64 start_addr, addr;
3377         int i, j;
3378         bool more_trbs_coming;
3379
3380         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3381
3382         num_tds = urb->number_of_packets;
3383         if (num_tds < 1) {
3384                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3385                 return -EINVAL;
3386         }
3387
3388         if (!in_interrupt())
3389                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3390                                 " addr = %#llx, num_tds = %d\n",
3391                                 urb->ep->desc.bEndpointAddress,
3392                                 urb->transfer_buffer_length,
3393                                 urb->transfer_buffer_length,
3394                                 (unsigned long long)urb->transfer_dma,
3395                                 num_tds);
3396
3397         start_addr = (u64) urb->transfer_dma;
3398         start_trb = &ep_ring->enqueue->generic;
3399         start_cycle = ep_ring->cycle_state;
3400
3401         urb_priv = urb->hcpriv;
3402         /* Queue the first TRB, even if it's zero-length */
3403         for (i = 0; i < num_tds; i++) {
3404                 unsigned int total_packet_count;
3405                 unsigned int burst_count;
3406                 unsigned int residue;
3407
3408                 first_trb = true;
3409                 running_total = 0;
3410                 addr = start_addr + urb->iso_frame_desc[i].offset;
3411                 td_len = urb->iso_frame_desc[i].length;
3412                 td_remain_len = td_len;
3413                 total_packet_count = roundup(td_len,
3414                                 usb_endpoint_maxp(&urb->ep->desc));
3415                 /* A zero-length transfer still involves at least one packet. */
3416                 if (total_packet_count == 0)
3417                         total_packet_count++;
3418                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3419                                 total_packet_count);
3420                 residue = xhci_get_last_burst_packet_count(xhci,
3421                                 urb->dev, urb, total_packet_count);
3422
3423                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3424
3425                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3426                                 urb->stream_id, trbs_per_td, urb, i, true,
3427                                 mem_flags);
3428                 if (ret < 0) {
3429                         if (i == 0)
3430                                 return ret;
3431                         goto cleanup;
3432                 }
3433
3434                 td = urb_priv->td[i];
3435                 for (j = 0; j < trbs_per_td; j++) {
3436                         u32 remainder = 0;
3437                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3438
3439                         if (first_trb) {
3440                                 /* Queue the isoc TRB */
3441                                 field |= TRB_TYPE(TRB_ISOC);
3442                                 /* Assume URB_ISO_ASAP is set */
3443                                 field |= TRB_SIA;
3444                                 if (i == 0) {
3445                                         if (start_cycle == 0)
3446                                                 field |= 0x1;
3447                                 } else
3448                                         field |= ep_ring->cycle_state;
3449                                 first_trb = false;
3450                         } else {
3451                                 /* Queue other normal TRBs */
3452                                 field |= TRB_TYPE(TRB_NORMAL);
3453                                 field |= ep_ring->cycle_state;
3454                         }
3455
3456                         /* Only set interrupt on short packet for IN EPs */
3457                         if (usb_urb_dir_in(urb))
3458                                 field |= TRB_ISP;
3459
3460                         /* Chain all the TRBs together; clear the chain bit in
3461                          * the last TRB to indicate it's the last TRB in the
3462                          * chain.
3463                          */
3464                         if (j < trbs_per_td - 1) {
3465                                 field |= TRB_CHAIN;
3466                                 more_trbs_coming = true;
3467                         } else {
3468                                 td->last_trb = ep_ring->enqueue;
3469                                 field |= TRB_IOC;
3470                                 if (xhci->hci_version == 0x100) {
3471                                         /* Set BEI bit except for the last td */
3472                                         if (i < num_tds - 1)
3473                                                 field |= TRB_BEI;
3474                                 }
3475                                 more_trbs_coming = false;
3476                         }
3477
3478                         /* Calculate TRB length */
3479                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3480                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3481                         if (trb_buff_len > td_remain_len)
3482                                 trb_buff_len = td_remain_len;
3483
3484                         /* Set the TRB length, TD size, & interrupter fields. */
3485                         if (xhci->hci_version < 0x100) {
3486                                 remainder = xhci_td_remainder(
3487                                                 td_len - running_total);
3488                         } else {
3489                                 remainder = xhci_v1_0_td_remainder(
3490                                                 running_total, trb_buff_len,
3491                                                 total_packet_count, urb);
3492                         }
3493                         length_field = TRB_LEN(trb_buff_len) |
3494                                 remainder |
3495                                 TRB_INTR_TARGET(0);
3496
3497                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3498                                 lower_32_bits(addr),
3499                                 upper_32_bits(addr),
3500                                 length_field,
3501                                 field);
3502                         running_total += trb_buff_len;
3503
3504                         addr += trb_buff_len;
3505                         td_remain_len -= trb_buff_len;
3506                 }
3507
3508                 /* Check TD length */
3509                 if (running_total != td_len) {
3510                         xhci_err(xhci, "ISOC TD length unmatch\n");
3511                         ret = -EINVAL;
3512                         goto cleanup;
3513                 }
3514         }
3515
3516         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3517                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3518                         usb_amd_quirk_pll_disable();
3519         }
3520         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3521
3522         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3523                         start_cycle, start_trb);
3524         return 0;
3525 cleanup:
3526         /* Clean up a partially enqueued isoc transfer. */
3527
3528         for (i--; i >= 0; i--)
3529                 list_del_init(&urb_priv->td[i]->td_list);
3530
3531         /* Use the first TD as a temporary variable to turn the TDs we've queued
3532          * into No-ops with a software-owned cycle bit. That way the hardware
3533          * won't accidentally start executing bogus TDs when we partially
3534          * overwrite them.  td->first_trb and td->start_seg are already set.
3535          */
3536         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3537         /* Every TRB except the first & last will have its cycle bit flipped. */
3538         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3539
3540         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3541         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3542         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3543         ep_ring->cycle_state = start_cycle;
3544         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3545         return ret;
3546 }
3547
3548 /*
3549  * Check transfer ring to guarantee there is enough room for the urb.
3550  * Update ISO URB start_frame and interval.
3551  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3552  * update the urb->start_frame by now.
3553  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3554  */
3555 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3556                 struct urb *urb, int slot_id, unsigned int ep_index)
3557 {
3558         struct xhci_virt_device *xdev;
3559         struct xhci_ring *ep_ring;
3560         struct xhci_ep_ctx *ep_ctx;
3561         int start_frame;
3562         int xhci_interval;
3563         int ep_interval;
3564         int num_tds, num_trbs, i;
3565         int ret;
3566
3567         xdev = xhci->devs[slot_id];
3568         ep_ring = xdev->eps[ep_index].ring;
3569         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3570
3571         num_trbs = 0;
3572         num_tds = urb->number_of_packets;
3573         for (i = 0; i < num_tds; i++)
3574                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3575
3576         /* Check the ring to guarantee there is enough room for the whole urb.
3577          * Do not insert any td of the urb to the ring if the check failed.
3578          */
3579         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3580                            num_trbs, true, mem_flags);
3581         if (ret)
3582                 return ret;
3583
3584         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3585         start_frame &= 0x3fff;
3586
3587         urb->start_frame = start_frame;
3588         if (urb->dev->speed == USB_SPEED_LOW ||
3589                         urb->dev->speed == USB_SPEED_FULL)
3590                 urb->start_frame >>= 3;
3591
3592         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3593         ep_interval = urb->interval;
3594         /* Convert to microframes */
3595         if (urb->dev->speed == USB_SPEED_LOW ||
3596                         urb->dev->speed == USB_SPEED_FULL)
3597                 ep_interval *= 8;
3598         /* FIXME change this to a warning and a suggestion to use the new API
3599          * to set the polling interval (once the API is added).
3600          */
3601         if (xhci_interval != ep_interval) {
3602                 if (printk_ratelimit())
3603                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3604                                         " (%d microframe%s) than xHCI "
3605                                         "(%d microframe%s)\n",
3606                                         ep_interval,
3607                                         ep_interval == 1 ? "" : "s",
3608                                         xhci_interval,
3609                                         xhci_interval == 1 ? "" : "s");
3610                 urb->interval = xhci_interval;
3611                 /* Convert back to frames for LS/FS devices */
3612                 if (urb->dev->speed == USB_SPEED_LOW ||
3613                                 urb->dev->speed == USB_SPEED_FULL)
3614                         urb->interval /= 8;
3615         }
3616         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3617 }
3618
3619 /****           Command Ring Operations         ****/
3620
3621 /* Generic function for queueing a command TRB on the command ring.
3622  * Check to make sure there's room on the command ring for one command TRB.
3623  * Also check that there's room reserved for commands that must not fail.
3624  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3625  * then only check for the number of reserved spots.
3626  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3627  * because the command event handler may want to resubmit a failed command.
3628  */
3629 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3630                 u32 field3, u32 field4, bool command_must_succeed)
3631 {
3632         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3633         int ret;
3634
3635         if (!command_must_succeed)
3636                 reserved_trbs++;
3637
3638         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3639                         reserved_trbs, false, GFP_ATOMIC);
3640         if (ret < 0) {
3641                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3642                 if (command_must_succeed)
3643                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3644                                         "unfailable commands failed.\n");
3645                 return ret;
3646         }
3647         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3648                         field3, field4 | xhci->cmd_ring->cycle_state);
3649         return 0;
3650 }
3651
3652 /* Queue a slot enable or disable request on the command ring */
3653 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3654 {
3655         return queue_command(xhci, 0, 0, 0,
3656                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3657 }
3658
3659 /* Queue an address device command TRB */
3660 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3661                 u32 slot_id)
3662 {
3663         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3664                         upper_32_bits(in_ctx_ptr), 0,
3665                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3666                         false);
3667 }
3668
3669 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3670                 u32 field1, u32 field2, u32 field3, u32 field4)
3671 {
3672         return queue_command(xhci, field1, field2, field3, field4, false);
3673 }
3674
3675 /* Queue a reset device command TRB */
3676 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3677 {
3678         return queue_command(xhci, 0, 0, 0,
3679                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3680                         false);
3681 }
3682
3683 /* Queue a configure endpoint command TRB */
3684 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3685                 u32 slot_id, bool command_must_succeed)
3686 {
3687         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3688                         upper_32_bits(in_ctx_ptr), 0,
3689                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3690                         command_must_succeed);
3691 }
3692
3693 /* Queue an evaluate context command TRB */
3694 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3695                 u32 slot_id)
3696 {
3697         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3698                         upper_32_bits(in_ctx_ptr), 0,
3699                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3700                         false);
3701 }
3702
3703 /*
3704  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3705  * activity on an endpoint that is about to be suspended.
3706  */
3707 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3708                 unsigned int ep_index, int suspend)
3709 {
3710         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3711         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3712         u32 type = TRB_TYPE(TRB_STOP_RING);
3713         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3714
3715         return queue_command(xhci, 0, 0, 0,
3716                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3717 }
3718
3719 /* Set Transfer Ring Dequeue Pointer command.
3720  * This should not be used for endpoints that have streams enabled.
3721  */
3722 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3723                 unsigned int ep_index, unsigned int stream_id,
3724                 struct xhci_segment *deq_seg,
3725                 union xhci_trb *deq_ptr, u32 cycle_state)
3726 {
3727         dma_addr_t addr;
3728         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3729         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3730         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3731         u32 type = TRB_TYPE(TRB_SET_DEQ);
3732         struct xhci_virt_ep *ep;
3733
3734         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3735         if (addr == 0) {
3736                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3737                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3738                                 deq_seg, deq_ptr);
3739                 return 0;
3740         }
3741         ep = &xhci->devs[slot_id]->eps[ep_index];
3742         if ((ep->ep_state & SET_DEQ_PENDING)) {
3743                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3744                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3745                 return 0;
3746         }
3747         ep->queued_deq_seg = deq_seg;
3748         ep->queued_deq_ptr = deq_ptr;
3749         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3750                         upper_32_bits(addr), trb_stream_id,
3751                         trb_slot_id | trb_ep_index | type, false);
3752 }
3753
3754 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3755                 unsigned int ep_index)
3756 {
3757         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3758         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3759         u32 type = TRB_TYPE(TRB_RESET_EP);
3760
3761         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3762                         false);
3763 }