drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 xhci_err(xhci, "Stopped the command ring failed, "
 354                                 "maybe the host is dead\n");
 355                 xhci->xhc_state |= XHCI_STATE_DYING;
 356                 xhci_quiesce(xhci);
 357                 xhci_halt(xhci);
 358                 return -ESHUTDOWN;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int xhci_queue_cd(struct xhci_hcd *xhci,
 365                 struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         struct xhci_cd *cd;
 369         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 370         if (!cd)
 371                 return -ENOMEM;
 372         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 373
 374         cd->command = command;
 375         cd->cmd_trb = cmd_trb;
 376         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * Cancel the command which has issue.
 383  *
 384  * Some commands may hang due to waiting for acknowledgement from
 385  * usb device. It is outside of the xHC's ability to control and
 386  * will cause the command ring is blocked. When it occurs software
 387  * should intervene to recover the command ring.
 388  * See Section 4.6.1.1 and 4.6.1.2
 389  */
 390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 391                 union xhci_trb *cmd_trb)
 392 {
 393         int retval = 0;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&xhci->lock, flags);
 397
 398         if (xhci->xhc_state & XHCI_STATE_DYING) {
 399                 xhci_warn(xhci, "Abort the command ring,"
 400                                 " but the xHCI is dead.\n");
 401                 retval = -ESHUTDOWN;
 402                 goto fail;
 403         }
 404
 405         /* queue the cmd desriptor to cancel_cmd_list */
 406         retval = xhci_queue_cd(xhci, command, cmd_trb);
 407         if (retval) {
 408                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 409                 goto fail;
 410         }
 411
 412         /* abort command ring */
 413         retval = xhci_abort_cmd_ring(xhci);
 414         if (retval) {
 415                 xhci_err(xhci, "Abort command ring failed\n");
 416                 if (unlikely(retval == -ESHUTDOWN)) {
 417                         spin_unlock_irqrestore(&xhci->lock, flags);
 418                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 419                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 420                         return retval;
 421                 }
 422         }
 423
 424 fail:
 425         spin_unlock_irqrestore(&xhci->lock, flags);
 426         return retval;
 427 }
 428
 429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 430                 unsigned int slot_id,
 431                 unsigned int ep_index,
 432                 unsigned int stream_id)
 433 {
 434         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 435         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 436         unsigned int ep_state = ep->ep_state;
 437
 438         /* Don't ring the doorbell for this endpoint if there are pending
 439          * cancellations because we don't want to interrupt processing.
 440          * We don't want to restart any stream rings if there's a set dequeue
 441          * pointer command pending because the device can choose to start any
 442          * stream once the endpoint is on the HW schedule.
 443          * FIXME - check all the stream rings for pending cancellations.
 444          */
 445         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 446             (ep_state & EP_HALTED))
 447                 return;
 448         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 449         /* The CPU has better things to do at this point than wait for a
 450          * write-posting flush.  It'll get there soon enough.
 451          */
 452 }
 453
 454 /* Ring the doorbell for any rings with pending URBs */
 455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 456                 unsigned int slot_id,
 457                 unsigned int ep_index)
 458 {
 459         unsigned int stream_id;
 460         struct xhci_virt_ep *ep;
 461
 462         ep = &xhci->devs[slot_id]->eps[ep_index];
 463
 464         /* A ring has pending URBs if its TD list is not empty */
 465         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 466                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 467                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 468                 return;
 469         }
 470
 471         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 472                         stream_id++) {
 473                 struct xhci_stream_info *stream_info = ep->stream_info;
 474                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 475                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 476                                                 stream_id);
 477         }
 478 }
 479
 480 /*
 481  * Find the segment that trb is in.  Start searching in start_seg.
 482  * If we must move past a segment that has a link TRB with a toggle cycle state
 483  * bit set, then we will toggle the value pointed at by cycle_state.
 484  */
 485 static struct xhci_segment *find_trb_seg(
 486                 struct xhci_segment *start_seg,
 487                 union xhci_trb  *trb, int *cycle_state)
 488 {
 489         struct xhci_segment *cur_seg = start_seg;
 490         struct xhci_generic_trb *generic_trb;
 491
 492         while (cur_seg->trbs > trb ||
 493                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 494                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 495                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 496                         *cycle_state ^= 0x1;
 497                 cur_seg = cur_seg->next;
 498                 if (cur_seg == start_seg)
 499                         /* Looped over the entire list.  Oops! */
 500                         return NULL;
 501         }
 502         return cur_seg;
 503 }
 504
 505
 506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 507                 unsigned int slot_id, unsigned int ep_index,
 508                 unsigned int stream_id)
 509 {
 510         struct xhci_virt_ep *ep;
 511
 512         ep = &xhci->devs[slot_id]->eps[ep_index];
 513         /* Common case: no streams */
 514         if (!(ep->ep_state & EP_HAS_STREAMS))
 515                 return ep->ring;
 516
 517         if (stream_id == 0) {
 518                 xhci_warn(xhci,
 519                                 "WARN: Slot ID %u, ep index %u has streams, "
 520                                 "but URB has no stream ID.\n",
 521                                 slot_id, ep_index);
 522                 return NULL;
 523         }
 524
 525         if (stream_id < ep->stream_info->num_streams)
 526                 return ep->stream_info->stream_rings[stream_id];
 527
 528         xhci_warn(xhci,
 529                         "WARN: Slot ID %u, ep index %u has "
 530                         "stream IDs 1 to %u allocated, "
 531                         "but stream ID %u is requested.\n",
 532                         slot_id, ep_index,
 533                         ep->stream_info->num_streams - 1,
 534                         stream_id);
 535         return NULL;
 536 }
 537
 538 /* Get the right ring for the given URB.
 539  * If the endpoint supports streams, boundary check the URB's stream ID.
 540  * If the endpoint doesn't support streams, return the singular endpoint ring.
 541  */
 542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 543                 struct urb *urb)
 544 {
 545         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 546                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 547 }
 548
 549 /*
 550  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 551  * Record the new state of the xHC's endpoint ring dequeue segment,
 552  * dequeue pointer, and new consumer cycle state in state.
 553  * Update our internal representation of the ring's dequeue pointer.
 554  *
 555  * We do this in three jumps:
 556  *  - First we update our new ring state to be the same as when the xHC stopped.
 557  *  - Then we traverse the ring to find the segment that contains
 558  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 559  *    any link TRBs with the toggle cycle bit set.
 560  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 561  *    if we've moved it past a link TRB with the toggle cycle bit set.
 562  *
 563  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 564  * with correct __le32 accesses they should work fine.  Only users of this are
 565  * in here.
 566  */
 567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 568                 unsigned int slot_id, unsigned int ep_index,
 569                 unsigned int stream_id, struct xhci_td *cur_td,
 570                 struct xhci_dequeue_state *state)
 571 {
 572         struct xhci_virt_device *dev = xhci->devs[slot_id];
 573         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 574         struct xhci_ring *ep_ring;
 575         struct xhci_generic_trb *trb;
 576         dma_addr_t addr;
 577
 578         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 579                         ep_index, stream_id);
 580         if (!ep_ring) {
 581                 xhci_warn(xhci, "WARN can't find new dequeue state "
 582                                 "for invalid stream ID %u.\n",
 583                                 stream_id);
 584                 return;
 585         }
 586         state->new_cycle_state = 0;
 587         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 588         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 589                         dev->eps[ep_index].stopped_trb,
 590                         &state->new_cycle_state);
 591         if (!state->new_deq_seg) {
 592                 WARN_ON(1);
 593                 return;
 594         }
 595
 596         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 597         xhci_dbg(xhci, "Finding endpoint context\n");
 598         /* 4.6.9 the css flag is written to the stream context for streams */
 599         if (ep->ep_state & EP_HAS_STREAMS) {
 600                 struct xhci_stream_ctx *ctx =
 601                         &ep->stream_info->stream_ctx_array[stream_id];
 602                 state->new_cycle_state = 0x1 & le64_to_cpu(ctx->stream_ring);
 603         } else {
 604                 struct xhci_ep_ctx *ep_ctx
 605                         = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 606                 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 607         }
 608
 609         state->new_deq_ptr = cur_td->last_trb;
 610         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 611         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 612                         state->new_deq_ptr,
 613                         &state->new_cycle_state);
 614         if (!state->new_deq_seg) {
 615                 WARN_ON(1);
 616                 return;
 617         }
 618
 619         trb = &state->new_deq_ptr->generic;
 620         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 621             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 622                 state->new_cycle_state ^= 0x1;
 623         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 624
 625         /*
 626          * If there is only one segment in a ring, find_trb_seg()'s while loop
 627          * will not run, and it will return before it has a chance to see if it
 628          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 629          * ended just before the link TRB on a one-segment ring, or if the TD
 630          * wrapped around the top of the ring, because it doesn't have the TD in
 631          * question.  Look for the one-segment case where stalled TRB's address
 632          * is greater than the new dequeue pointer address.
 633          */
 634         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 635                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 636                 state->new_cycle_state ^= 0x1;
 637         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 638
 639         /* Don't update the ring cycle state for the producer (us). */
 640         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 641                         state->new_deq_seg);
 642         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 643         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 644                         (unsigned long long) addr);
 645 }
 646
 647 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 648  * (The last TRB actually points to the ring enqueue pointer, which is not part
 649  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 650  */
 651 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 652                 struct xhci_td *cur_td, bool flip_cycle)
 653 {
 654         struct xhci_segment *cur_seg;
 655         union xhci_trb *cur_trb;
 656
 657         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 658                         true;
 659                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 660                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 661                         /* Unchain any chained Link TRBs, but
 662                          * leave the pointers intact.
 663                          */
 664                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 665                         /* Flip the cycle bit (link TRBs can't be the first
 666                          * or last TRB).
 667                          */
 668                         if (flip_cycle)
 669                                 cur_trb->generic.field[3] ^=
 670                                         cpu_to_le32(TRB_CYCLE);
 671                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 672                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 673                                         "in seg %p (0x%llx dma)\n",
 674                                         cur_trb,
 675                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 676                                         cur_seg,
 677                                         (unsigned long long)cur_seg->dma);
 678                 } else {
 679                         cur_trb->generic.field[0] = 0;
 680                         cur_trb->generic.field[1] = 0;
 681                         cur_trb->generic.field[2] = 0;
 682                         /* Preserve only the cycle bit of this TRB */
 683                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 684                         /* Flip the cycle bit except on the first or last TRB */
 685                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 686                                         cur_trb != cur_td->last_trb)
 687                                 cur_trb->generic.field[3] ^=
 688                                         cpu_to_le32(TRB_CYCLE);
 689                         cur_trb->generic.field[3] |= cpu_to_le32(
 690                                 TRB_TYPE(TRB_TR_NOOP));
 691                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 692                                         "in seg %p (0x%llx dma)\n",
 693                                         cur_trb,
 694                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 695                                         cur_seg,
 696                                         (unsigned long long)cur_seg->dma);
 697                 }
 698                 if (cur_trb == cur_td->last_trb)
 699                         break;
 700         }
 701 }
 702
 703 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 704                 unsigned int ep_index, unsigned int stream_id,
 705                 struct xhci_segment *deq_seg,
 706                 union xhci_trb *deq_ptr, u32 cycle_state);
 707
 708 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 709                 unsigned int slot_id, unsigned int ep_index,
 710                 unsigned int stream_id,
 711                 struct xhci_dequeue_state *deq_state)
 712 {
 713         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 714
 715         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 716                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 717                         deq_state->new_deq_seg,
 718                         (unsigned long long)deq_state->new_deq_seg->dma,
 719                         deq_state->new_deq_ptr,
 720                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 721                         deq_state->new_cycle_state);
 722         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 723                         deq_state->new_deq_seg,
 724                         deq_state->new_deq_ptr,
 725                         (u32) deq_state->new_cycle_state);
 726         /* Stop the TD queueing code from ringing the doorbell until
 727          * this command completes.  The HC won't set the dequeue pointer
 728          * if the ring is running, and ringing the doorbell starts the
 729          * ring running.
 730          */
 731         ep->ep_state |= SET_DEQ_PENDING;
 732 }
 733
 734 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 735                 struct xhci_virt_ep *ep)
 736 {
 737         ep->ep_state &= ~EP_HALT_PENDING;
 738         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 739          * timer is running on another CPU, we don't decrement stop_cmds_pending
 740          * (since we didn't successfully stop the watchdog timer).
 741          */
 742         if (del_timer(&ep->stop_cmd_timer))
 743                 ep->stop_cmds_pending--;
 744 }
 745
 746 /* Must be called with xhci->lock held in interrupt context */
 747 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 748                 struct xhci_td *cur_td, int status, char *adjective)
 749 {
 750         struct usb_hcd *hcd;
 751         struct urb      *urb;
 752         struct urb_priv *urb_priv;
 753
 754         urb = cur_td->urb;
 755         urb_priv = urb->hcpriv;
 756         urb_priv->td_cnt++;
 757         hcd = bus_to_hcd(urb->dev->bus);
 758
 759         /* Only giveback urb when this is the last td in urb */
 760         if (urb_priv->td_cnt == urb_priv->length) {
 761                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 762                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 763                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 764                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 765                                         usb_amd_quirk_pll_enable();
 766                         }
 767                 }
 768                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 769
 770                 spin_unlock(&xhci->lock);
 771                 usb_hcd_giveback_urb(hcd, urb, status);
 772                 xhci_urb_free_priv(xhci, urb_priv);
 773                 spin_lock(&xhci->lock);
 774         }
 775 }
 776
 777 /*
 778  * When we get a command completion for a Stop Endpoint Command, we need to
 779  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 780  *
 781  *  1. If the HW was in the middle of processing the TD that needs to be
 782  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 783  *     in the TD with a Set Dequeue Pointer Command.
 784  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 785  *     bit cleared) so that the HW will skip over them.
 786  */
 787 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 788                 union xhci_trb *trb, struct xhci_event_cmd *event)
 789 {
 790         unsigned int slot_id;
 791         unsigned int ep_index;
 792         struct xhci_virt_device *virt_dev;
 793         struct xhci_ring *ep_ring;
 794         struct xhci_virt_ep *ep;
 795         struct list_head *entry;
 796         struct xhci_td *cur_td = NULL;
 797         struct xhci_td *last_unlinked_td;
 798
 799         struct xhci_dequeue_state deq_state;
 800
 801         if (unlikely(TRB_TO_SUSPEND_PORT(
 802                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 803                 slot_id = TRB_TO_SLOT_ID(
 804                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 805                 virt_dev = xhci->devs[slot_id];
 806                 if (virt_dev)
 807                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 808                                 event);
 809                 else
 810                         xhci_warn(xhci, "Stop endpoint command "
 811                                 "completion for disabled slot %u\n",
 812                                 slot_id);
 813                 return;
 814         }
 815
 816         memset(&deq_state, 0, sizeof(deq_state));
 817         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 818         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 819         ep = &xhci->devs[slot_id]->eps[ep_index];
 820
 821         if (list_empty(&ep->cancelled_td_list)) {
 822                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 823                 ep->stopped_td = NULL;
 824                 ep->stopped_trb = NULL;
 825                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 826                 return;
 827         }
 828
 829         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 830          * We have the xHCI lock, so nothing can modify this list until we drop
 831          * it.  We're also in the event handler, so we can't get re-interrupted
 832          * if another Stop Endpoint command completes
 833          */
 834         list_for_each(entry, &ep->cancelled_td_list) {
 835                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 836                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 837                                 cur_td->first_trb,
 838                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 839                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 840                 if (!ep_ring) {
 841                         /* This shouldn't happen unless a driver is mucking
 842                          * with the stream ID after submission.  This will
 843                          * leave the TD on the hardware ring, and the hardware
 844                          * will try to execute it, and may access a buffer
 845                          * that has already been freed.  In the best case, the
 846                          * hardware will execute it, and the event handler will
 847                          * ignore the completion event for that TD, since it was
 848                          * removed from the td_list for that endpoint.  In
 849                          * short, don't muck with the stream ID after
 850                          * submission.
 851                          */
 852                         xhci_warn(xhci, "WARN Cancelled URB %p "
 853                                         "has invalid stream ID %u.\n",
 854                                         cur_td->urb,
 855                                         cur_td->urb->stream_id);
 856                         goto remove_finished_td;
 857                 }
 858                 /*
 859                  * If we stopped on the TD we need to cancel, then we have to
 860                  * move the xHC endpoint ring dequeue pointer past this TD.
 861                  */
 862                 if (cur_td == ep->stopped_td)
 863                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 864                                         cur_td->urb->stream_id,
 865                                         cur_td, &deq_state);
 866                 else
 867                         td_to_noop(xhci, ep_ring, cur_td, false);
 868 remove_finished_td:
 869                 /*
 870                  * The event handler won't see a completion for this TD anymore,
 871                  * so remove it from the endpoint ring's TD list.  Keep it in
 872                  * the cancelled TD list for URB completion later.
 873                  */
 874                 list_del_init(&cur_td->td_list);
 875         }
 876         last_unlinked_td = cur_td;
 877         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 878
 879         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 880         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 881                 xhci_queue_new_dequeue_state(xhci,
 882                                 slot_id, ep_index,
 883                                 ep->stopped_td->urb->stream_id,
 884                                 &deq_state);
 885                 xhci_ring_cmd_db(xhci);
 886         } else {
 887                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 888                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 889         }
 890
 891         /* Clear stopped_td and stopped_trb if endpoint is not halted */
 892         if (!(ep->ep_state & EP_HALTED)) {
 893                 ep->stopped_td = NULL;
 894                 ep->stopped_trb = NULL;
 895         }
 896
 897         /*
 898          * Drop the lock and complete the URBs in the cancelled TD list.
 899          * New TDs to be cancelled might be added to the end of the list before
 900          * we can complete all the URBs for the TDs we already unlinked.
 901          * So stop when we've completed the URB for the last TD we unlinked.
 902          */
 903         do {
 904                 cur_td = list_entry(ep->cancelled_td_list.next,
 905                                 struct xhci_td, cancelled_td_list);
 906                 list_del_init(&cur_td->cancelled_td_list);
 907
 908                 /* Clean up the cancelled URB */
 909                 /* Doesn't matter what we pass for status, since the core will
 910                  * just overwrite it (because the URB has been unlinked).
 911                  */
 912                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 913
 914                 /* Stop processing the cancelled list if the watchdog timer is
 915                  * running.
 916                  */
 917                 if (xhci->xhc_state & XHCI_STATE_DYING)
 918                         return;
 919         } while (cur_td != last_unlinked_td);
 920
 921         /* Return to the event handler with xhci->lock re-acquired */
 922 }
 923
 924 /* Watchdog timer function for when a stop endpoint command fails to complete.
 925  * In this case, we assume the host controller is broken or dying or dead.  The
 926  * host may still be completing some other events, so we have to be careful to
 927  * let the event ring handler and the URB dequeueing/enqueueing functions know
 928  * through xhci->state.
 929  *
 930  * The timer may also fire if the host takes a very long time to respond to the
 931  * command, and the stop endpoint command completion handler cannot delete the
 932  * timer before the timer function is called.  Another endpoint cancellation may
 933  * sneak in before the timer function can grab the lock, and that may queue
 934  * another stop endpoint command and add the timer back.  So we cannot use a
 935  * simple flag to say whether there is a pending stop endpoint command for a
 936  * particular endpoint.
 937  *
 938  * Instead we use a combination of that flag and a counter for the number of
 939  * pending stop endpoint commands.  If the timer is the tail end of the last
 940  * stop endpoint command, and the endpoint's command is still pending, we assume
 941  * the host is dying.
 942  */
 943 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 944 {
 945         struct xhci_hcd *xhci;
 946         struct xhci_virt_ep *ep;
 947         struct xhci_virt_ep *temp_ep;
 948         struct xhci_ring *ring;
 949         struct xhci_td *cur_td;
 950         int ret, i, j;
 951         unsigned long flags;
 952
 953         ep = (struct xhci_virt_ep *) arg;
 954         xhci = ep->xhci;
 955
 956         spin_lock_irqsave(&xhci->lock, flags);
 957
 958         ep->stop_cmds_pending--;
 959         if (xhci->xhc_state & XHCI_STATE_DYING) {
 960                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 961                                 "xHCI as DYING, exiting.\n");
 962                 spin_unlock_irqrestore(&xhci->lock, flags);
 963                 return;
 964         }
 965         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 966                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 967                                 "exiting.\n");
 968                 spin_unlock_irqrestore(&xhci->lock, flags);
 969                 return;
 970         }
 971
 972         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 973         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 974         /* Oops, HC is dead or dying or at least not responding to the stop
 975          * endpoint command.
 976          */
 977         xhci->xhc_state |= XHCI_STATE_DYING;
 978         /* Disable interrupts from the host controller and start halting it */
 979         xhci_quiesce(xhci);
 980         spin_unlock_irqrestore(&xhci->lock, flags);
 981
 982         ret = xhci_halt(xhci);
 983
 984         spin_lock_irqsave(&xhci->lock, flags);
 985         if (ret < 0) {
 986                 /* This is bad; the host is not responding to commands and it's
 987                  * not allowing itself to be halted.  At least interrupts are
 988                  * disabled. If we call usb_hc_died(), it will attempt to
 989                  * disconnect all device drivers under this host.  Those
 990                  * disconnect() methods will wait for all URBs to be unlinked,
 991                  * so we must complete them.
 992                  */
 993                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 994                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 995                 /* We could turn all TDs on the rings to no-ops.  This won't
 996                  * help if the host has cached part of the ring, and is slow if
 997                  * we want to preserve the cycle bit.  Skip it and hope the host
 998                  * doesn't touch the memory.
 999                  */
1000         }
1001         for (i = 0; i < MAX_HC_SLOTS; i++) {
1002                 if (!xhci->devs[i])
1003                         continue;
1004                 for (j = 0; j < 31; j++) {
1005                         temp_ep = &xhci->devs[i]->eps[j];
1006                         ring = temp_ep->ring;
1007                         if (!ring)
1008                                 continue;
1009                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1010                                         "ep index %u\n", i, j);
1011                         while (!list_empty(&ring->td_list)) {
1012                                 cur_td = list_first_entry(&ring->td_list,
1013                                                 struct xhci_td,
1014                                                 td_list);
1015                                 list_del_init(&cur_td->td_list);
1016                                 if (!list_empty(&cur_td->cancelled_td_list))
1017                                         list_del_init(&cur_td->cancelled_td_list);
1018                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1019                                                 -ESHUTDOWN, "killed");
1020                         }
1021                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1022                                 cur_td = list_first_entry(
1023                                                 &temp_ep->cancelled_td_list,
1024                                                 struct xhci_td,
1025                                                 cancelled_td_list);
1026                                 list_del_init(&cur_td->cancelled_td_list);
1027                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1028                                                 -ESHUTDOWN, "killed");
1029                         }
1030                 }
1031         }
1032         spin_unlock_irqrestore(&xhci->lock, flags);
1033         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1034         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1035         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1036 }
1037
1038 /*
1039  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1040  * we need to clear the set deq pending flag in the endpoint ring state, so that
1041  * the TD queueing code can ring the doorbell again.  We also need to ring the
1042  * endpoint doorbell to restart the ring, but only if there aren't more
1043  * cancellations pending.
1044  */
1045 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1046                 struct xhci_event_cmd *event,
1047                 union xhci_trb *trb)
1048 {
1049         unsigned int slot_id;
1050         unsigned int ep_index;
1051         unsigned int stream_id;
1052         struct xhci_ring *ep_ring;
1053         struct xhci_virt_device *dev;
1054         struct xhci_ep_ctx *ep_ctx;
1055         struct xhci_slot_ctx *slot_ctx;
1056
1057         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1058         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1059         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1060         dev = xhci->devs[slot_id];
1061
1062         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1063         if (!ep_ring) {
1064                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1065                                 "freed stream ID %u\n",
1066                                 stream_id);
1067                 /* XXX: Harmless??? */
1068                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1069                 return;
1070         }
1071
1072         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1073         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1074
1075         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1076                 unsigned int ep_state;
1077                 unsigned int slot_state;
1078
1079                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1080                 case COMP_TRB_ERR:
1081                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1082                                         "of stream ID configuration\n");
1083                         break;
1084                 case COMP_CTX_STATE:
1085                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1086                                         "to incorrect slot or ep state.\n");
1087                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1088                         ep_state &= EP_STATE_MASK;
1089                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1090                         slot_state = GET_SLOT_STATE(slot_state);
1091                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1092                                         slot_state, ep_state);
1093                         break;
1094                 case COMP_EBADSLT:
1095                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1096                                         "slot %u was not enabled.\n", slot_id);
1097                         break;
1098                 default:
1099                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1100                                         "completion code of %u.\n",
1101                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1102                         break;
1103                 }
1104                 /* OK what do we do now?  The endpoint state is hosed, and we
1105                  * should never get to this point if the synchronization between
1106                  * queueing, and endpoint state are correct.  This might happen
1107                  * if the device gets disconnected after we've finished
1108                  * cancelling URBs, which might not be an error...
1109                  */
1110         } else {
1111                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1112                          le64_to_cpu(ep_ctx->deq));
1113                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1114                                          dev->eps[ep_index].queued_deq_ptr) ==
1115                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1116                         /* Update the ring's dequeue segment and dequeue pointer
1117                          * to reflect the new position.
1118                          */
1119                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1120                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1121                 } else {
1122                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1123                                         "Ptr command & xHCI internal state.\n");
1124                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1125                                         dev->eps[ep_index].queued_deq_seg,
1126                                         dev->eps[ep_index].queued_deq_ptr);
1127                 }
1128         }
1129
1130         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1131         dev->eps[ep_index].queued_deq_seg = NULL;
1132         dev->eps[ep_index].queued_deq_ptr = NULL;
1133         /* Restart any rings with pending URBs */
1134         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1135 }
1136
1137 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1138                 struct xhci_event_cmd *event,
1139                 union xhci_trb *trb)
1140 {
1141         int slot_id;
1142         unsigned int ep_index;
1143
1144         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1145         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1146         /* This command will only fail if the endpoint wasn't halted,
1147          * but we don't care.
1148          */
1149         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1150                  GET_COMP_CODE(le32_to_cpu(event->status)));
1151
1152         /* HW with the reset endpoint quirk needs to have a configure endpoint
1153          * command complete before the endpoint can be used.  Queue that here
1154          * because the HW can't handle two commands being queued in a row.
1155          */
1156         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1157                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1158                 xhci_queue_configure_endpoint(xhci,
1159                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1160                                 false);
1161                 xhci_ring_cmd_db(xhci);
1162         } else {
1163                 /* Clear our internal halted state and restart the ring(s) */
1164                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1165                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1166         }
1167 }
1168
1169 /* Complete the command and detele it from the devcie's command queue.
1170  */
1171 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1172                 struct xhci_command *command, u32 status)
1173 {
1174         command->status = status;
1175         list_del(&command->cmd_list);
1176         if (command->completion)
1177                 complete(command->completion);
1178         else
1179                 xhci_free_command(xhci, command);
1180 }
1181
1182
1183 /* Check to see if a command in the device's command queue matches this one.
1184  * Signal the completion or free the command, and return 1.  Return 0 if the
1185  * completed command isn't at the head of the command list.
1186  */
1187 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1188                 struct xhci_virt_device *virt_dev,
1189                 struct xhci_event_cmd *event)
1190 {
1191         struct xhci_command *command;
1192
1193         if (list_empty(&virt_dev->cmd_list))
1194                 return 0;
1195
1196         command = list_entry(virt_dev->cmd_list.next,
1197                         struct xhci_command, cmd_list);
1198         if (xhci->cmd_ring->dequeue != command->command_trb)
1199                 return 0;
1200
1201         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1202                         GET_COMP_CODE(le32_to_cpu(event->status)));
1203         return 1;
1204 }
1205
1206 /*
1207  * Finding the command trb need to be cancelled and modifying it to
1208  * NO OP command. And if the command is in device's command wait
1209  * list, finishing and freeing it.
1210  *
1211  * If we can't find the command trb, we think it had already been
1212  * executed.
1213  */
1214 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1215 {
1216         struct xhci_segment *cur_seg;
1217         union xhci_trb *cmd_trb;
1218         u32 cycle_state;
1219
1220         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1221                 return;
1222
1223         /* find the current segment of command ring */
1224         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1225                         xhci->cmd_ring->dequeue, &cycle_state);
1226
1227         if (!cur_seg) {
1228                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1229                                 xhci->cmd_ring->dequeue,
1230                                 (unsigned long long)
1231                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1232                                         xhci->cmd_ring->dequeue));
1233                 xhci_debug_ring(xhci, xhci->cmd_ring);
1234                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1235                 return;
1236         }
1237
1238         /* find the command trb matched by cd from command ring */
1239         for (cmd_trb = xhci->cmd_ring->dequeue;
1240                         cmd_trb != xhci->cmd_ring->enqueue;
1241                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1242                 /* If the trb is link trb, continue */
1243                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1244                         continue;
1245
1246                 if (cur_cd->cmd_trb == cmd_trb) {
1247
1248                         /* If the command in device's command list, we should
1249                          * finish it and free the command structure.
1250                          */
1251                         if (cur_cd->command)
1252                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1253                                         cur_cd->command, COMP_CMD_STOP);
1254
1255                         /* get cycle state from the origin command trb */
1256                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1257                                 & TRB_CYCLE;
1258
1259                         /* modify the command trb to NO OP command */
1260                         cmd_trb->generic.field[0] = 0;
1261                         cmd_trb->generic.field[1] = 0;
1262                         cmd_trb->generic.field[2] = 0;
1263                         cmd_trb->generic.field[3] = cpu_to_le32(
1264                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1265                         break;
1266                 }
1267         }
1268 }
1269
1270 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1271 {
1272         struct xhci_cd *cur_cd, *next_cd;
1273
1274         if (list_empty(&xhci->cancel_cmd_list))
1275                 return;
1276
1277         list_for_each_entry_safe(cur_cd, next_cd,
1278                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1279                 xhci_cmd_to_noop(xhci, cur_cd);
1280                 list_del(&cur_cd->cancel_cmd_list);
1281                 kfree(cur_cd);
1282         }
1283 }
1284
1285 /*
1286  * traversing the cancel_cmd_list. If the command descriptor according
1287  * to cmd_trb is found, the function free it and return 1, otherwise
1288  * return 0.
1289  */
1290 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1291                 union xhci_trb *cmd_trb)
1292 {
1293         struct xhci_cd *cur_cd, *next_cd;
1294
1295         if (list_empty(&xhci->cancel_cmd_list))
1296                 return 0;
1297
1298         list_for_each_entry_safe(cur_cd, next_cd,
1299                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1300                 if (cur_cd->cmd_trb == cmd_trb) {
1301                         if (cur_cd->command)
1302                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1303                                         cur_cd->command, COMP_CMD_STOP);
1304                         list_del(&cur_cd->cancel_cmd_list);
1305                         kfree(cur_cd);
1306                         return 1;
1307                 }
1308         }
1309
1310         return 0;
1311 }
1312
1313 /*
1314  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1315  * trb pointed by the command ring dequeue pointer is the trb we want to
1316  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1317  * traverse the cancel_cmd_list to trun the all of the commands according
1318  * to command descriptor to NO-OP trb.
1319  */
1320 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1321                 int cmd_trb_comp_code)
1322 {
1323         int cur_trb_is_good = 0;
1324
1325         /* Searching the cmd trb pointed by the command ring dequeue
1326          * pointer in command descriptor list. If it is found, free it.
1327          */
1328         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1329                         xhci->cmd_ring->dequeue);
1330
1331         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1332                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1333         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1334                 /* traversing the cancel_cmd_list and canceling
1335                  * the command according to command descriptor
1336                  */
1337                 xhci_cancel_cmd_in_cd_list(xhci);
1338
1339                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1340                 /*
1341                  * ring command ring doorbell again to restart the
1342                  * command ring
1343                  */
1344                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1345                         xhci_ring_cmd_db(xhci);
1346         }
1347         return cur_trb_is_good;
1348 }
1349
1350 static void handle_cmd_completion(struct xhci_hcd *xhci,
1351                 struct xhci_event_cmd *event)
1352 {
1353         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1354         u64 cmd_dma;
1355         dma_addr_t cmd_dequeue_dma;
1356         struct xhci_input_control_ctx *ctrl_ctx;
1357         struct xhci_virt_device *virt_dev;
1358         unsigned int ep_index;
1359         struct xhci_ring *ep_ring;
1360         unsigned int ep_state;
1361
1362         cmd_dma = le64_to_cpu(event->cmd_trb);
1363         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1364                         xhci->cmd_ring->dequeue);
1365         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1366         if (cmd_dequeue_dma == 0) {
1367                 xhci->error_bitmask |= 1 << 4;
1368                 return;
1369         }
1370         /* Does the DMA address match our internal dequeue pointer address? */
1371         if (cmd_dma != (u64) cmd_dequeue_dma) {
1372                 xhci->error_bitmask |= 1 << 5;
1373                 return;
1374         }
1375
1376         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1377                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1378                 /* If the return value is 0, we think the trb pointed by
1379                  * command ring dequeue pointer is a good trb. The good
1380                  * trb means we don't want to cancel the trb, but it have
1381                  * been stopped by host. So we should handle it normally.
1382                  * Otherwise, driver should invoke inc_deq() and return.
1383                  */
1384                 if (handle_stopped_cmd_ring(xhci,
1385                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1386                         inc_deq(xhci, xhci->cmd_ring, false);
1387                         return;
1388                 }
1389         }
1390
1391         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1392                 & TRB_TYPE_BITMASK) {
1393         case TRB_TYPE(TRB_ENABLE_SLOT):
1394                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1395                         xhci->slot_id = slot_id;
1396                 else
1397                         xhci->slot_id = 0;
1398                 complete(&xhci->addr_dev);
1399                 break;
1400         case TRB_TYPE(TRB_DISABLE_SLOT):
1401                 if (xhci->devs[slot_id]) {
1402                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1403                                 /* Delete default control endpoint resources */
1404                                 xhci_free_device_endpoint_resources(xhci,
1405                                                 xhci->devs[slot_id], true);
1406                         xhci_free_virt_device(xhci, slot_id);
1407                 }
1408                 break;
1409         case TRB_TYPE(TRB_CONFIG_EP):
1410                 virt_dev = xhci->devs[slot_id];
1411                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1412                         break;
1413                 /*
1414                  * Configure endpoint commands can come from the USB core
1415                  * configuration or alt setting changes, or because the HW
1416                  * needed an extra configure endpoint command after a reset
1417                  * endpoint command or streams were being configured.
1418                  * If the command was for a halted endpoint, the xHCI driver
1419                  * is not waiting on the configure endpoint command.
1420                  */
1421                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1422                                 virt_dev->in_ctx);
1423                 /* Input ctx add_flags are the endpoint index plus one */
1424                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1425                 /* A usb_set_interface() call directly after clearing a halted
1426                  * condition may race on this quirky hardware.  Not worth
1427                  * worrying about, since this is prototype hardware.  Not sure
1428                  * if this will work for streams, but streams support was
1429                  * untested on this prototype.
1430                  */
1431                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1432                                 ep_index != (unsigned int) -1 &&
1433                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1434                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1435                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1436                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1437                         if (!(ep_state & EP_HALTED))
1438                                 goto bandwidth_change;
1439                         xhci_dbg(xhci, "Completed config ep cmd - "
1440                                         "last ep index = %d, state = %d\n",
1441                                         ep_index, ep_state);
1442                         /* Clear internal halted state and restart ring(s) */
1443                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1444                                 ~EP_HALTED;
1445                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1446                         break;
1447                 }
1448 bandwidth_change:
1449                 xhci_dbg(xhci, "Completed config ep cmd\n");
1450                 xhci->devs[slot_id]->cmd_status =
1451                         GET_COMP_CODE(le32_to_cpu(event->status));
1452                 complete(&xhci->devs[slot_id]->cmd_completion);
1453                 break;
1454         case TRB_TYPE(TRB_EVAL_CONTEXT):
1455                 virt_dev = xhci->devs[slot_id];
1456                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1457                         break;
1458                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1459                 complete(&xhci->devs[slot_id]->cmd_completion);
1460                 break;
1461         case TRB_TYPE(TRB_ADDR_DEV):
1462                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1463                 complete(&xhci->addr_dev);
1464                 break;
1465         case TRB_TYPE(TRB_STOP_RING):
1466                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1467                 break;
1468         case TRB_TYPE(TRB_SET_DEQ):
1469                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1470                 break;
1471         case TRB_TYPE(TRB_CMD_NOOP):
1472                 break;
1473         case TRB_TYPE(TRB_RESET_EP):
1474                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1475                 break;
1476         case TRB_TYPE(TRB_RESET_DEV):
1477                 xhci_dbg(xhci, "Completed reset device command.\n");
1478                 slot_id = TRB_TO_SLOT_ID(
1479                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1480                 virt_dev = xhci->devs[slot_id];
1481                 if (virt_dev)
1482                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1483                 else
1484                         xhci_warn(xhci, "Reset device command completion "
1485                                         "for disabled slot %u\n", slot_id);
1486                 break;
1487         case TRB_TYPE(TRB_NEC_GET_FW):
1488                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1489                         xhci->error_bitmask |= 1 << 6;
1490                         break;
1491                 }
1492                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1493                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1494                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1495                 break;
1496         default:
1497                 /* Skip over unknown commands on the event ring */
1498                 xhci->error_bitmask |= 1 << 6;
1499                 break;
1500         }
1501         inc_deq(xhci, xhci->cmd_ring, false);
1502 }
1503
1504 static void handle_vendor_event(struct xhci_hcd *xhci,
1505                 union xhci_trb *event)
1506 {
1507         u32 trb_type;
1508
1509         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1510         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1511         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1512                 handle_cmd_completion(xhci, &event->event_cmd);
1513 }
1514
1515 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1516  * port registers -- USB 3.0 and USB 2.0).
1517  *
1518  * Returns a zero-based port number, which is suitable for indexing into each of
1519  * the split roothubs' port arrays and bus state arrays.
1520  * Add one to it in order to call xhci_find_slot_id_by_port.
1521  */
1522 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1523                 struct xhci_hcd *xhci, u32 port_id)
1524 {
1525         unsigned int i;
1526         unsigned int num_similar_speed_ports = 0;
1527
1528         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1529          * and usb2_ports are 0-based indexes.  Count the number of similar
1530          * speed ports, up to 1 port before this port.
1531          */
1532         for (i = 0; i < (port_id - 1); i++) {
1533                 u8 port_speed = xhci->port_array[i];
1534
1535                 /*
1536                  * Skip ports that don't have known speeds, or have duplicate
1537                  * Extended Capabilities port speed entries.
1538                  */
1539                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1540                         continue;
1541
1542                 /*
1543                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1544                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1545                  * matches the device speed, it's a similar speed port.
1546                  */
1547                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1548                         num_similar_speed_ports++;
1549         }
1550         return num_similar_speed_ports;
1551 }
1552
1553 static void handle_port_status(struct xhci_hcd *xhci,
1554                 union xhci_trb *event)
1555 {
1556         struct usb_hcd *hcd;
1557         u32 port_id;
1558         u32 temp, temp1;
1559         int max_ports;
1560         int slot_id;
1561         unsigned int faked_port_index;
1562         u8 major_revision;
1563         struct xhci_bus_state *bus_state;
1564         __le32 __iomem **port_array;
1565         bool bogus_port_status = false;
1566
1567         /* Port status change events always have a successful completion code */
1568         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1569                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1570                 xhci->error_bitmask |= 1 << 8;
1571         }
1572         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1573         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1574
1575         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1576         if ((port_id <= 0) || (port_id > max_ports)) {
1577                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1578                 bogus_port_status = true;
1579                 goto cleanup;
1580         }
1581
1582         /* Figure out which usb_hcd this port is attached to:
1583          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1584          */
1585         major_revision = xhci->port_array[port_id - 1];
1586         if (major_revision == 0) {
1587                 xhci_warn(xhci, "Event for port %u not in "
1588                                 "Extended Capabilities, ignoring.\n",
1589                                 port_id);
1590                 bogus_port_status = true;
1591                 goto cleanup;
1592         }
1593         if (major_revision == DUPLICATE_ENTRY) {
1594                 xhci_warn(xhci, "Event for port %u duplicated in"
1595                                 "Extended Capabilities, ignoring.\n",
1596                                 port_id);
1597                 bogus_port_status = true;
1598                 goto cleanup;
1599         }
1600
1601         /*
1602          * Hardware port IDs reported by a Port Status Change Event include USB
1603          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1604          * resume event, but we first need to translate the hardware port ID
1605          * into the index into the ports on the correct split roothub, and the
1606          * correct bus_state structure.
1607          */
1608         /* Find the right roothub. */
1609         hcd = xhci_to_hcd(xhci);
1610         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1611                 hcd = xhci->shared_hcd;
1612         bus_state = &xhci->bus_state[hcd_index(hcd)];
1613         if (hcd->speed == HCD_USB3)
1614                 port_array = xhci->usb3_ports;
1615         else
1616                 port_array = xhci->usb2_ports;
1617         /* Find the faked port hub number */
1618         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1619                         port_id);
1620
1621         temp = xhci_readl(xhci, port_array[faked_port_index]);
1622         if (hcd->state == HC_STATE_SUSPENDED) {
1623                 xhci_dbg(xhci, "resume root hub\n");
1624                 usb_hcd_resume_root_hub(hcd);
1625         }
1626
1627         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1628                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1629
1630                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1631                 if (!(temp1 & CMD_RUN)) {
1632                         xhci_warn(xhci, "xHC is not running.\n");
1633                         goto cleanup;
1634                 }
1635
1636                 if (DEV_SUPERSPEED(temp)) {
1637                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1638                         xhci_set_link_state(xhci, port_array, faked_port_index,
1639                                                 XDEV_U0);
1640                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1641                                         faked_port_index + 1);
1642                         if (!slot_id) {
1643                                 xhci_dbg(xhci, "slot_id is zero\n");
1644                                 goto cleanup;
1645                         }
1646                         xhci_ring_device(xhci, slot_id);
1647                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1648                         /* Clear PORT_PLC */
1649                         xhci_test_and_clear_bit(xhci, port_array,
1650                                                 faked_port_index, PORT_PLC);
1651                 } else {
1652                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1653                         bus_state->resume_done[faked_port_index] = jiffies +
1654                                 msecs_to_jiffies(20);
1655                         mod_timer(&hcd->rh_timer,
1656                                   bus_state->resume_done[faked_port_index]);
1657                         /* Do the rest in GetPortStatus */
1658                 }
1659         }
1660
1661         if (hcd->speed != HCD_USB3)
1662                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1663                                         PORT_PLC);
1664
1665 cleanup:
1666         /* Update event ring dequeue pointer before dropping the lock */
1667         inc_deq(xhci, xhci->event_ring, true);
1668
1669         /* Don't make the USB core poll the roothub if we got a bad port status
1670          * change event.  Besides, at that point we can't tell which roothub
1671          * (USB 2.0 or USB 3.0) to kick.
1672          */
1673         if (bogus_port_status)
1674                 return;
1675
1676         /*
1677          * xHCI port-status-change events occur when the "or" of all the
1678          * status-change bits in the portsc register changes from 0 to 1.
1679          * New status changes won't cause an event if any other change
1680          * bits are still set.  When an event occurs, switch over to
1681          * polling to avoid losing status changes.
1682          */
1683         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1684         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1685         spin_unlock(&xhci->lock);
1686         /* Pass this up to the core */
1687         usb_hcd_poll_rh_status(hcd);
1688         spin_lock(&xhci->lock);
1689 }
1690
1691 /*
1692  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1693  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1694  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1695  * returns 0.
1696  */
1697 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1698                 union xhci_trb  *start_trb,
1699                 union xhci_trb  *end_trb,
1700                 dma_addr_t      suspect_dma)
1701 {
1702         dma_addr_t start_dma;
1703         dma_addr_t end_seg_dma;
1704         dma_addr_t end_trb_dma;
1705         struct xhci_segment *cur_seg;
1706
1707         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1708         cur_seg = start_seg;
1709
1710         do {
1711                 if (start_dma == 0)
1712                         return NULL;
1713                 /* We may get an event for a Link TRB in the middle of a TD */
1714                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1715                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1716                 /* If the end TRB isn't in this segment, this is set to 0 */
1717                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1718
1719                 if (end_trb_dma > 0) {
1720                         /* The end TRB is in this segment, so suspect should be here */
1721                         if (start_dma <= end_trb_dma) {
1722                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1723                                         return cur_seg;
1724                         } else {
1725                                 /* Case for one segment with
1726                                  * a TD wrapped around to the top
1727                                  */
1728                                 if ((suspect_dma >= start_dma &&
1729                                                         suspect_dma <= end_seg_dma) ||
1730                                                 (suspect_dma >= cur_seg->dma &&
1731                                                  suspect_dma <= end_trb_dma))
1732                                         return cur_seg;
1733                         }
1734                         return NULL;
1735                 } else {
1736                         /* Might still be somewhere in this segment */
1737                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1738                                 return cur_seg;
1739                 }
1740                 cur_seg = cur_seg->next;
1741                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1742         } while (cur_seg != start_seg);
1743
1744         return NULL;
1745 }
1746
1747 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1748                 unsigned int slot_id, unsigned int ep_index,
1749                 unsigned int stream_id,
1750                 struct xhci_td *td, union xhci_trb *event_trb)
1751 {
1752         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1753         ep->ep_state |= EP_HALTED;
1754         ep->stopped_td = td;
1755         ep->stopped_trb = event_trb;
1756         ep->stopped_stream = stream_id;
1757
1758         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1759         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1760
1761         ep->stopped_td = NULL;
1762         ep->stopped_trb = NULL;
1763         ep->stopped_stream = 0;
1764
1765         xhci_ring_cmd_db(xhci);
1766 }
1767
1768 /* Check if an error has halted the endpoint ring.  The class driver will
1769  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1770  * However, a babble and other errors also halt the endpoint ring, and the class
1771  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1772  * Ring Dequeue Pointer command manually.
1773  */
1774 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1775                 struct xhci_ep_ctx *ep_ctx,
1776                 unsigned int trb_comp_code)
1777 {
1778         /* TRB completion codes that may require a manual halt cleanup */
1779         if (trb_comp_code == COMP_TX_ERR ||
1780                         trb_comp_code == COMP_BABBLE ||
1781                         trb_comp_code == COMP_SPLIT_ERR)
1782                 /* The 0.96 spec says a babbling control endpoint
1783                  * is not halted. The 0.96 spec says it is.  Some HW
1784                  * claims to be 0.95 compliant, but it halts the control
1785                  * endpoint anyway.  Check if a babble halted the
1786                  * endpoint.
1787                  */
1788                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1789                     cpu_to_le32(EP_STATE_HALTED))
1790                         return 1;
1791
1792         return 0;
1793 }
1794
1795 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1796 {
1797         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1798                 /* Vendor defined "informational" completion code,
1799                  * treat as not-an-error.
1800                  */
1801                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1802                                 trb_comp_code);
1803                 xhci_dbg(xhci, "Treating code as success.\n");
1804                 return 1;
1805         }
1806         return 0;
1807 }
1808
1809 /*
1810  * Finish the td processing, remove the td from td list;
1811  * Return 1 if the urb can be given back.
1812  */
1813 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1814         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1815         struct xhci_virt_ep *ep, int *status, bool skip)
1816 {
1817         struct xhci_virt_device *xdev;
1818         struct xhci_ring *ep_ring;
1819         unsigned int slot_id;
1820         int ep_index;
1821         struct urb *urb = NULL;
1822         struct xhci_ep_ctx *ep_ctx;
1823         int ret = 0;
1824         struct urb_priv *urb_priv;
1825         u32 trb_comp_code;
1826
1827         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1828         xdev = xhci->devs[slot_id];
1829         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1830         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1831         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1832         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1833
1834         if (skip)
1835                 goto td_cleanup;
1836
1837         if (trb_comp_code == COMP_STOP_INVAL ||
1838                         trb_comp_code == COMP_STOP) {
1839                 /* The Endpoint Stop Command completion will take care of any
1840                  * stopped TDs.  A stopped TD may be restarted, so don't update
1841                  * the ring dequeue pointer or take this TD off any lists yet.
1842                  */
1843                 ep->stopped_td = td;
1844                 ep->stopped_trb = event_trb;
1845                 return 0;
1846         } else {
1847                 if (trb_comp_code == COMP_STALL) {
1848                         /* The transfer is completed from the driver's
1849                          * perspective, but we need to issue a set dequeue
1850                          * command for this stalled endpoint to move the dequeue
1851                          * pointer past the TD.  We can't do that here because
1852                          * the halt condition must be cleared first.  Let the
1853                          * USB class driver clear the stall later.
1854                          */
1855                         ep->stopped_td = td;
1856                         ep->stopped_trb = event_trb;
1857                         ep->stopped_stream = ep_ring->stream_id;
1858                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1859                                         ep_ctx, trb_comp_code)) {
1860                         /* Other types of errors halt the endpoint, but the
1861                          * class driver doesn't call usb_reset_endpoint() unless
1862                          * the error is -EPIPE.  Clear the halted status in the
1863                          * xHCI hardware manually.
1864                          */
1865                         xhci_cleanup_halted_endpoint(xhci,
1866                                         slot_id, ep_index, ep_ring->stream_id,
1867                                         td, event_trb);
1868                 } else {
1869                         /* Update ring dequeue pointer */
1870                         while (ep_ring->dequeue != td->last_trb)
1871                                 inc_deq(xhci, ep_ring, false);
1872                         inc_deq(xhci, ep_ring, false);
1873                 }
1874
1875 td_cleanup:
1876                 /* Clean up the endpoint's TD list */
1877                 urb = td->urb;
1878                 urb_priv = urb->hcpriv;
1879
1880                 /* Do one last check of the actual transfer length.
1881                  * If the host controller said we transferred more data than
1882                  * the buffer length, urb->actual_length will be a very big
1883                  * number (since it's unsigned).  Play it safe and say we didn't
1884                  * transfer anything.
1885                  */
1886                 if (urb->actual_length > urb->transfer_buffer_length) {
1887                         xhci_warn(xhci, "URB transfer length is wrong, "
1888                                         "xHC issue? req. len = %u, "
1889                                         "act. len = %u\n",
1890                                         urb->transfer_buffer_length,
1891                                         urb->actual_length);
1892                         urb->actual_length = 0;
1893                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1894                                 *status = -EREMOTEIO;
1895                         else
1896                                 *status = 0;
1897                 }
1898                 list_del_init(&td->td_list);
1899                 /* Was this TD slated to be cancelled but completed anyway? */
1900                 if (!list_empty(&td->cancelled_td_list))
1901                         list_del_init(&td->cancelled_td_list);
1902
1903                 urb_priv->td_cnt++;
1904                 /* Giveback the urb when all the tds are completed */
1905                 if (urb_priv->td_cnt == urb_priv->length) {
1906                         ret = 1;
1907                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1908                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1909                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1910                                         == 0) {
1911                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1912                                                 usb_amd_quirk_pll_enable();
1913                                 }
1914                         }
1915                 }
1916         }
1917
1918         return ret;
1919 }
1920
1921 /*
1922  * Process control tds, update urb status and actual_length.
1923  */
1924 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1925         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1926         struct xhci_virt_ep *ep, int *status)
1927 {
1928         struct xhci_virt_device *xdev;
1929         struct xhci_ring *ep_ring;
1930         unsigned int slot_id;
1931         int ep_index;
1932         struct xhci_ep_ctx *ep_ctx;
1933         u32 trb_comp_code;
1934
1935         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1936         xdev = xhci->devs[slot_id];
1937         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1938         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1939         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1940         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1941
1942         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1943         switch (trb_comp_code) {
1944         case COMP_SUCCESS:
1945                 if (event_trb == ep_ring->dequeue) {
1946                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1947                                         "without IOC set??\n");
1948                         *status = -ESHUTDOWN;
1949                 } else if (event_trb != td->last_trb) {
1950                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1951                                         "without IOC set??\n");
1952                         *status = -ESHUTDOWN;
1953                 } else {
1954                         *status = 0;
1955                 }
1956                 break;
1957         case COMP_SHORT_TX:
1958                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1959                         *status = -EREMOTEIO;
1960                 else
1961                         *status = 0;
1962                 break;
1963         case COMP_STOP_INVAL:
1964         case COMP_STOP:
1965                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1966         default:
1967                 if (!xhci_requires_manual_halt_cleanup(xhci,
1968                                         ep_ctx, trb_comp_code))
1969                         break;
1970                 xhci_dbg(xhci, "TRB error code %u, "
1971                                 "halted endpoint index = %u\n",
1972                                 trb_comp_code, ep_index);
1973                 /* else fall through */
1974         case COMP_STALL:
1975                 /* Did we transfer part of the data (middle) phase? */
1976                 if (event_trb != ep_ring->dequeue &&
1977                                 event_trb != td->last_trb)
1978                         td->urb->actual_length =
1979                                 td->urb->transfer_buffer_length -
1980                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1981                 else
1982                         td->urb->actual_length = 0;
1983
1984                 xhci_cleanup_halted_endpoint(xhci,
1985                         slot_id, ep_index, 0, td, event_trb);
1986                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1987         }
1988         /*
1989          * Did we transfer any data, despite the errors that might have
1990          * happened?  I.e. did we get past the setup stage?
1991          */
1992         if (event_trb != ep_ring->dequeue) {
1993                 /* The event was for the status stage */
1994                 if (event_trb == td->last_trb) {
1995                         if (td->urb->actual_length != 0) {
1996                                 /* Don't overwrite a previously set error code
1997                                  */
1998                                 if ((*status == -EINPROGRESS || *status == 0) &&
1999                                                 (td->urb->transfer_flags
2000                                                  & URB_SHORT_NOT_OK))
2001                                         /* Did we already see a short data
2002                                          * stage? */
2003                                         *status = -EREMOTEIO;
2004                         } else {
2005                                 td->urb->actual_length =
2006                                         td->urb->transfer_buffer_length;
2007                         }
2008                 } else {
2009                 /* Maybe the event was for the data stage? */
2010                         td->urb->actual_length =
2011                                 td->urb->transfer_buffer_length -
2012                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2013                         xhci_dbg(xhci, "Waiting for status "
2014                                         "stage event\n");
2015                         return 0;
2016                 }
2017         }
2018
2019         return finish_td(xhci, td, event_trb, event, ep, status, false);
2020 }
2021
2022 /*
2023  * Process isochronous tds, update urb packet status and actual_length.
2024  */
2025 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2026         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2027         struct xhci_virt_ep *ep, int *status)
2028 {
2029         struct xhci_ring *ep_ring;
2030         struct urb_priv *urb_priv;
2031         int idx;
2032         int len = 0;
2033         union xhci_trb *cur_trb;
2034         struct xhci_segment *cur_seg;
2035         struct usb_iso_packet_descriptor *frame;
2036         u32 trb_comp_code;
2037         bool skip_td = false;
2038
2039         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2040         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2041         urb_priv = td->urb->hcpriv;
2042         idx = urb_priv->td_cnt;
2043         frame = &td->urb->iso_frame_desc[idx];
2044
2045         /* handle completion code */
2046         switch (trb_comp_code) {
2047         case COMP_SUCCESS:
2048                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2049                         frame->status = 0;
2050                         break;
2051                 }
2052                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2053                         trb_comp_code = COMP_SHORT_TX;
2054         case COMP_SHORT_TX:
2055                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2056                                 -EREMOTEIO : 0;
2057                 break;
2058         case COMP_BW_OVER:
2059                 frame->status = -ECOMM;
2060                 skip_td = true;
2061                 break;
2062         case COMP_BUFF_OVER:
2063         case COMP_BABBLE:
2064                 frame->status = -EOVERFLOW;
2065                 skip_td = true;
2066                 break;
2067         case COMP_DEV_ERR:
2068         case COMP_STALL:
2069         case COMP_TX_ERR:
2070                 frame->status = -EPROTO;
2071                 skip_td = true;
2072                 break;
2073         case COMP_STOP:
2074         case COMP_STOP_INVAL:
2075                 break;
2076         default:
2077                 frame->status = -1;
2078                 break;
2079         }
2080
2081         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2082                 frame->actual_length = frame->length;
2083                 td->urb->actual_length += frame->length;
2084         } else {
2085                 for (cur_trb = ep_ring->dequeue,
2086                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2087                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2088                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2089                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2090                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2091                 }
2092                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2093                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2094
2095                 if (trb_comp_code != COMP_STOP_INVAL) {
2096                         frame->actual_length = len;
2097                         td->urb->actual_length += len;
2098                 }
2099         }
2100
2101         return finish_td(xhci, td, event_trb, event, ep, status, false);
2102 }
2103
2104 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2105                         struct xhci_transfer_event *event,
2106                         struct xhci_virt_ep *ep, int *status)
2107 {
2108         struct xhci_ring *ep_ring;
2109         struct urb_priv *urb_priv;
2110         struct usb_iso_packet_descriptor *frame;
2111         int idx;
2112
2113         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2114         urb_priv = td->urb->hcpriv;
2115         idx = urb_priv->td_cnt;
2116         frame = &td->urb->iso_frame_desc[idx];
2117
2118         /* The transfer is partly done. */
2119         frame->status = -EXDEV;
2120
2121         /* calc actual length */
2122         frame->actual_length = 0;
2123
2124         /* Update ring dequeue pointer */
2125         while (ep_ring->dequeue != td->last_trb)
2126                 inc_deq(xhci, ep_ring, false);
2127         inc_deq(xhci, ep_ring, false);
2128
2129         return finish_td(xhci, td, NULL, event, ep, status, true);
2130 }
2131
2132 /*
2133  * Process bulk and interrupt tds, update urb status and actual_length.
2134  */
2135 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2136         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2137         struct xhci_virt_ep *ep, int *status)
2138 {
2139         struct xhci_ring *ep_ring;
2140         union xhci_trb *cur_trb;
2141         struct xhci_segment *cur_seg;
2142         u32 trb_comp_code;
2143
2144         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2145         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2146
2147         switch (trb_comp_code) {
2148         case COMP_SUCCESS:
2149                 /* Double check that the HW transferred everything. */
2150                 if (event_trb != td->last_trb ||
2151                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2152                         xhci_warn(xhci, "WARN Successful completion "
2153                                         "on short TX\n");
2154                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2155                                 *status = -EREMOTEIO;
2156                         else
2157                                 *status = 0;
2158                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2159                                 trb_comp_code = COMP_SHORT_TX;
2160                 } else {
2161                         *status = 0;
2162                 }
2163                 break;
2164         case COMP_SHORT_TX:
2165                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2166                         *status = -EREMOTEIO;
2167                 else
2168                         *status = 0;
2169                 break;
2170         default:
2171                 /* Others already handled above */
2172                 break;
2173         }
2174         if (trb_comp_code == COMP_SHORT_TX)
2175                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2176                                 "%d bytes untransferred\n",
2177                                 td->urb->ep->desc.bEndpointAddress,
2178                                 td->urb->transfer_buffer_length,
2179                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2180         /* Fast path - was this the last TRB in the TD for this URB? */
2181         if (event_trb == td->last_trb) {
2182                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2183                         td->urb->actual_length =
2184                                 td->urb->transfer_buffer_length -
2185                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2186                         if (td->urb->transfer_buffer_length <
2187                                         td->urb->actual_length) {
2188                                 xhci_warn(xhci, "HC gave bad length "
2189                                                 "of %d bytes left\n",
2190                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2191                                 td->urb->actual_length = 0;
2192                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2193                                         *status = -EREMOTEIO;
2194                                 else
2195                                         *status = 0;
2196                         }
2197                         /* Don't overwrite a previously set error code */
2198                         if (*status == -EINPROGRESS) {
2199                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2200                                         *status = -EREMOTEIO;
2201                                 else
2202                                         *status = 0;
2203                         }
2204                 } else {
2205                         td->urb->actual_length =
2206                                 td->urb->transfer_buffer_length;
2207                         /* Ignore a short packet completion if the
2208                          * untransferred length was zero.
2209                          */
2210                         if (*status == -EREMOTEIO)
2211                                 *status = 0;
2212                 }
2213         } else {
2214                 /* Slow path - walk the list, starting from the dequeue
2215                  * pointer, to get the actual length transferred.
2216                  */
2217                 td->urb->actual_length = 0;
2218                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2219                                 cur_trb != event_trb;
2220                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2221                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2222                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2223                                 td->urb->actual_length +=
2224                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2225                 }
2226                 /* If the ring didn't stop on a Link or No-op TRB, add
2227                  * in the actual bytes transferred from the Normal TRB
2228                  */
2229                 if (trb_comp_code != COMP_STOP_INVAL)
2230                         td->urb->actual_length +=
2231                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2232                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2233         }
2234
2235         return finish_td(xhci, td, event_trb, event, ep, status, false);
2236 }
2237
2238 /*
2239  * If this function returns an error condition, it means it got a Transfer
2240  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2241  * At this point, the host controller is probably hosed and should be reset.
2242  */
2243 static int handle_tx_event(struct xhci_hcd *xhci,
2244                 struct xhci_transfer_event *event)
2245 {
2246         struct xhci_virt_device *xdev;
2247         struct xhci_virt_ep *ep;
2248         struct xhci_ring *ep_ring;
2249         unsigned int slot_id;
2250         int ep_index;
2251         struct xhci_td *td = NULL;
2252         dma_addr_t event_dma;
2253         struct xhci_segment *event_seg;
2254         union xhci_trb *event_trb;
2255         struct urb *urb = NULL;
2256         int status = -EINPROGRESS;
2257         struct urb_priv *urb_priv;
2258         struct xhci_ep_ctx *ep_ctx;
2259         struct list_head *tmp;
2260         u32 trb_comp_code;
2261         int ret = 0;
2262         int td_num = 0;
2263
2264         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2265         xdev = xhci->devs[slot_id];
2266         if (!xdev) {
2267                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2268                 return -ENODEV;
2269         }
2270
2271         /* Endpoint ID is 1 based, our index is zero based */
2272         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2273         ep = &xdev->eps[ep_index];
2274         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2275         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2276         if (!ep_ring ||
2277             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2278             EP_STATE_DISABLED) {
2279                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2280                                 "or incorrect stream ring\n");
2281                 return -ENODEV;
2282         }
2283
2284         /* Count current td numbers if ep->skip is set */
2285         if (ep->skip) {
2286                 list_for_each(tmp, &ep_ring->td_list)
2287                         td_num++;
2288         }
2289
2290         event_dma = le64_to_cpu(event->buffer);
2291         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2292         /* Look for common error cases */
2293         switch (trb_comp_code) {
2294         /* Skip codes that require special handling depending on
2295          * transfer type
2296          */
2297         case COMP_SUCCESS:
2298                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2299                         break;
2300                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2301                         trb_comp_code = COMP_SHORT_TX;
2302                 else
2303                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2304                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2305         case COMP_SHORT_TX:
2306                 break;
2307         case COMP_STOP:
2308                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2309                 break;
2310         case COMP_STOP_INVAL:
2311                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2312                 break;
2313         case COMP_STALL:
2314                 xhci_dbg(xhci, "Stalled endpoint\n");
2315                 ep->ep_state |= EP_HALTED;
2316                 status = -EPIPE;
2317                 break;
2318         case COMP_TRB_ERR:
2319                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2320                 status = -EILSEQ;
2321                 break;
2322         case COMP_SPLIT_ERR:
2323         case COMP_TX_ERR:
2324                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2325                 status = -EPROTO;
2326                 break;
2327         case COMP_BABBLE:
2328                 xhci_dbg(xhci, "Babble error on endpoint\n");
2329                 status = -EOVERFLOW;
2330                 break;
2331         case COMP_DB_ERR:
2332                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2333                 status = -ENOSR;
2334                 break;
2335         case COMP_BW_OVER:
2336                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2337                 break;
2338         case COMP_BUFF_OVER:
2339                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2340                 break;
2341         case COMP_UNDERRUN:
2342                 /*
2343                  * When the Isoch ring is empty, the xHC will generate
2344                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2345                  * Underrun Event for OUT Isoch endpoint.
2346                  */
2347                 xhci_dbg(xhci, "underrun event on endpoint\n");
2348                 if (!list_empty(&ep_ring->td_list))
2349                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2350                                         "still with TDs queued?\n",
2351                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2352                                  ep_index);
2353                 goto cleanup;
2354         case COMP_OVERRUN:
2355                 xhci_dbg(xhci, "overrun event on endpoint\n");
2356                 if (!list_empty(&ep_ring->td_list))
2357                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2358                                         "still with TDs queued?\n",
2359                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2360                                  ep_index);
2361                 goto cleanup;
2362         case COMP_DEV_ERR:
2363                 xhci_warn(xhci, "WARN: detect an incompatible device");
2364                 status = -EPROTO;
2365                 break;
2366         case COMP_MISSED_INT:
2367                 /*
2368                  * When encounter missed service error, one or more isoc tds
2369                  * may be missed by xHC.
2370                  * Set skip flag of the ep_ring; Complete the missed tds as
2371                  * short transfer when process the ep_ring next time.
2372                  */
2373                 ep->skip = true;
2374                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2375                 goto cleanup;
2376         default:
2377                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2378                         status = 0;
2379                         break;
2380                 }
2381                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2382                                 "busted\n");
2383                 goto cleanup;
2384         }
2385
2386         do {
2387                 /* This TRB should be in the TD at the head of this ring's
2388                  * TD list.
2389                  */
2390                 if (list_empty(&ep_ring->td_list)) {
2391                         /*
2392                          * A stopped endpoint may generate an extra completion
2393                          * event if the device was suspended.  Don't print
2394                          * warnings.
2395                          */
2396                         if (!(trb_comp_code == COMP_STOP ||
2397                                                 trb_comp_code == COMP_STOP_INVAL)) {
2398                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2399                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2400                                                 ep_index);
2401                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2402                                                 (le32_to_cpu(event->flags) &
2403                                                  TRB_TYPE_BITMASK)>>10);
2404                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2405                         }
2406                         if (ep->skip) {
2407                                 ep->skip = false;
2408                                 xhci_dbg(xhci, "td_list is empty while skip "
2409                                                 "flag set. Clear skip flag.\n");
2410                         }
2411                         ret = 0;
2412                         goto cleanup;
2413                 }
2414
2415                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2416                 if (ep->skip && td_num == 0) {
2417                         ep->skip = false;
2418                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2419                                                 "Clear skip flag.\n");
2420                         ret = 0;
2421                         goto cleanup;
2422                 }
2423
2424                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2425                 if (ep->skip)
2426                         td_num--;
2427
2428                 /* Is this a TRB in the currently executing TD? */
2429                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2430                                 td->last_trb, event_dma);
2431
2432                 /*
2433                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2434                  * is not in the current TD pointed by ep_ring->dequeue because
2435                  * that the hardware dequeue pointer still at the previous TRB
2436                  * of the current TD. The previous TRB maybe a Link TD or the
2437                  * last TRB of the previous TD. The command completion handle
2438                  * will take care the rest.
2439                  */
2440                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2441                         ret = 0;
2442                         goto cleanup;
2443                 }
2444
2445                 if (!event_seg) {
2446                         if (!ep->skip ||
2447                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2448                                 /* Some host controllers give a spurious
2449                                  * successful event after a short transfer.
2450                                  * Ignore it.
2451                                  */
2452                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2453                                                 ep_ring->last_td_was_short) {
2454                                         ep_ring->last_td_was_short = false;
2455                                         ret = 0;
2456                                         goto cleanup;
2457                                 }
2458                                 /* HC is busted, give up! */
2459                                 xhci_err(xhci,
2460                                         "ERROR Transfer event TRB DMA ptr not "
2461                                         "part of current TD\n");
2462                                 return -ESHUTDOWN;
2463                         }
2464
2465                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2466                         goto cleanup;
2467                 }
2468                 if (trb_comp_code == COMP_SHORT_TX)
2469                         ep_ring->last_td_was_short = true;
2470                 else
2471                         ep_ring->last_td_was_short = false;
2472
2473                 if (ep->skip) {
2474                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2475                         ep->skip = false;
2476                 }
2477
2478                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2479                                                 sizeof(*event_trb)];
2480                 /*
2481                  * No-op TRB should not trigger interrupts.
2482                  * If event_trb is a no-op TRB, it means the
2483                  * corresponding TD has been cancelled. Just ignore
2484                  * the TD.
2485                  */
2486                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2487                         xhci_dbg(xhci,
2488                                  "event_trb is a no-op TRB. Skip it\n");
2489                         goto cleanup;
2490                 }
2491
2492                 /* Now update the urb's actual_length and give back to
2493                  * the core
2494                  */
2495                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2496                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2497                                                  &status);
2498                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2499                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2500                                                  &status);
2501                 else
2502                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2503                                                  ep, &status);
2504
2505 cleanup:
2506                 /*
2507                  * Do not update event ring dequeue pointer if ep->skip is set.
2508                  * Will roll back to continue process missed tds.
2509                  */
2510                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2511                         inc_deq(xhci, xhci->event_ring, true);
2512                 }
2513
2514                 if (ret) {
2515                         urb = td->urb;
2516                         urb_priv = urb->hcpriv;
2517                         /* Leave the TD around for the reset endpoint function
2518                          * to use(but only if it's not a control endpoint,
2519                          * since we already queued the Set TR dequeue pointer
2520                          * command for stalled control endpoints).
2521                          */
2522                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2523                                 (trb_comp_code != COMP_STALL &&
2524                                         trb_comp_code != COMP_BABBLE))
2525                                 xhci_urb_free_priv(xhci, urb_priv);
2526                         else
2527                                 kfree(urb_priv);
2528
2529                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2530                         if ((urb->actual_length != urb->transfer_buffer_length &&
2531                                                 (urb->transfer_flags &
2532                                                  URB_SHORT_NOT_OK)) ||
2533                                         (status != 0 &&
2534                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2535                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2536                                                 "expected = %x, status = %d\n",
2537                                                 urb, urb->actual_length,
2538                                                 urb->transfer_buffer_length,
2539                                                 status);
2540                         spin_unlock(&xhci->lock);
2541                         /* EHCI, UHCI, and OHCI always unconditionally set the
2542                          * urb->status of an isochronous endpoint to 0.
2543                          */
2544                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2545                                 status = 0;
2546                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2547                         spin_lock(&xhci->lock);
2548                 }
2549
2550         /*
2551          * If ep->skip is set, it means there are missed tds on the
2552          * endpoint ring need to take care of.
2553          * Process them as short transfer until reach the td pointed by
2554          * the event.
2555          */
2556         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2557
2558         return 0;
2559 }
2560
2561 /*
2562  * This function handles all OS-owned events on the event ring.  It may drop
2563  * xhci->lock between event processing (e.g. to pass up port status changes).
2564  * Returns >0 for "possibly more events to process" (caller should call again),
2565  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2566  */
2567 static int xhci_handle_event(struct xhci_hcd *xhci)
2568 {
2569         union xhci_trb *event;
2570         int update_ptrs = 1;
2571         int ret;
2572
2573         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2574                 xhci->error_bitmask |= 1 << 1;
2575                 return 0;
2576         }
2577
2578         event = xhci->event_ring->dequeue;
2579         /* Does the HC or OS own the TRB? */
2580         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2581             xhci->event_ring->cycle_state) {
2582                 xhci->error_bitmask |= 1 << 2;
2583                 return 0;
2584         }
2585
2586         /*
2587          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2588          * speculative reads of the event's flags/data below.
2589          */
2590         rmb();
2591         /* FIXME: Handle more event types. */
2592         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2593         case TRB_TYPE(TRB_COMPLETION):
2594                 handle_cmd_completion(xhci, &event->event_cmd);
2595                 break;
2596         case TRB_TYPE(TRB_PORT_STATUS):
2597                 handle_port_status(xhci, event);
2598                 update_ptrs = 0;
2599                 break;
2600         case TRB_TYPE(TRB_TRANSFER):
2601                 ret = handle_tx_event(xhci, &event->trans_event);
2602                 if (ret < 0)
2603                         xhci->error_bitmask |= 1 << 9;
2604                 else
2605                         update_ptrs = 0;
2606                 break;
2607         default:
2608                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2609                     TRB_TYPE(48))
2610                         handle_vendor_event(xhci, event);
2611                 else
2612                         xhci->error_bitmask |= 1 << 3;
2613         }
2614         /* Any of the above functions may drop and re-acquire the lock, so check
2615          * to make sure a watchdog timer didn't mark the host as non-responsive.
2616          */
2617         if (xhci->xhc_state & XHCI_STATE_DYING) {
2618                 xhci_dbg(xhci, "xHCI host dying, returning from "
2619                                 "event handler.\n");
2620                 return 0;
2621         }
2622
2623         if (update_ptrs)
2624                 /* Update SW event ring dequeue pointer */
2625                 inc_deq(xhci, xhci->event_ring, true);
2626
2627         /* Are there more items on the event ring?  Caller will call us again to
2628          * check.
2629          */
2630         return 1;
2631 }
2632
2633 /*
2634  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2635  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2636  * indicators of an event TRB error, but we check the status *first* to be safe.
2637  */
2638 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2639 {
2640         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2641         u32 status;
2642         union xhci_trb *trb;
2643         u64 temp_64;
2644         union xhci_trb *event_ring_deq;
2645         dma_addr_t deq;
2646
2647         spin_lock(&xhci->lock);
2648         trb = xhci->event_ring->dequeue;
2649         /* Check if the xHC generated the interrupt, or the irq is shared */
2650         status = xhci_readl(xhci, &xhci->op_regs->status);
2651         if (status == 0xffffffff)
2652                 goto hw_died;
2653
2654         if (!(status & STS_EINT)) {
2655                 spin_unlock(&xhci->lock);
2656                 return IRQ_NONE;
2657         }
2658         if (status & STS_FATAL) {
2659                 xhci_warn(xhci, "WARNING: Host System Error\n");
2660                 xhci_halt(xhci);
2661 hw_died:
2662                 spin_unlock(&xhci->lock);
2663                 return -ESHUTDOWN;
2664         }
2665
2666         /*
2667          * Clear the op reg interrupt status first,
2668          * so we can receive interrupts from other MSI-X interrupters.
2669          * Write 1 to clear the interrupt status.
2670          */
2671         status |= STS_EINT;
2672         xhci_writel(xhci, status, &xhci->op_regs->status);
2673         /* FIXME when MSI-X is supported and there are multiple vectors */
2674         /* Clear the MSI-X event interrupt status */
2675
2676         if (hcd->irq != -1) {
2677                 u32 irq_pending;
2678                 /* Acknowledge the PCI interrupt */
2679                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2680                 irq_pending |= IMAN_IP;
2681                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2682         }
2683
2684         if (xhci->xhc_state & XHCI_STATE_DYING) {
2685                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2686                                 "Shouldn't IRQs be disabled?\n");
2687                 /* Clear the event handler busy flag (RW1C);
2688                  * the event ring should be empty.
2689                  */
2690                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2691                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2692                                 &xhci->ir_set->erst_dequeue);
2693                 spin_unlock(&xhci->lock);
2694
2695                 return IRQ_HANDLED;
2696         }
2697
2698         event_ring_deq = xhci->event_ring->dequeue;
2699         /* FIXME this should be a delayed service routine
2700          * that clears the EHB.
2701          */
2702         while (xhci_handle_event(xhci) > 0) {}
2703
2704         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2705         /* If necessary, update the HW's version of the event ring deq ptr. */
2706         if (event_ring_deq != xhci->event_ring->dequeue) {
2707                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2708                                 xhci->event_ring->dequeue);
2709                 if (deq == 0)
2710                         xhci_warn(xhci, "WARN something wrong with SW event "
2711                                         "ring dequeue ptr.\n");
2712                 /* Update HC event ring dequeue pointer */
2713                 temp_64 &= ERST_PTR_MASK;
2714                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2715         }
2716
2717         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2718         temp_64 |= ERST_EHB;
2719         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2720
2721         spin_unlock(&xhci->lock);
2722
2723         return IRQ_HANDLED;
2724 }
2725
2726 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2727 {
2728         irqreturn_t ret;
2729         struct xhci_hcd *xhci;
2730
2731         xhci = hcd_to_xhci(hcd);
2732         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2733         if (xhci->shared_hcd)
2734                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2735
2736         ret = xhci_irq(hcd);
2737
2738         return ret;
2739 }
2740
2741 /****           Endpoint Ring Operations        ****/
2742
2743 /*
2744  * Generic function for queueing a TRB on a ring.
2745  * The caller must have checked to make sure there's room on the ring.
2746  *
2747  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2748  *                      prepare_transfer()?
2749  */
2750 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2751                 bool consumer, bool more_trbs_coming, bool isoc,
2752                 u32 field1, u32 field2, u32 field3, u32 field4)
2753 {
2754         struct xhci_generic_trb *trb;
2755
2756         trb = &ring->enqueue->generic;
2757         trb->field[0] = cpu_to_le32(field1);
2758         trb->field[1] = cpu_to_le32(field2);
2759         trb->field[2] = cpu_to_le32(field3);
2760         trb->field[3] = cpu_to_le32(field4);
2761         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2762 }
2763
2764 /*
2765  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2766  * FIXME allocate segments if the ring is full.
2767  */
2768 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2769                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2770 {
2771         /* Make sure the endpoint has been added to xHC schedule */
2772         switch (ep_state) {
2773         case EP_STATE_DISABLED:
2774                 /*
2775                  * USB core changed config/interfaces without notifying us,
2776                  * or hardware is reporting the wrong state.
2777                  */
2778                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2779                 return -ENOENT;
2780         case EP_STATE_ERROR:
2781                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2782                 /* FIXME event handling code for error needs to clear it */
2783                 /* XXX not sure if this should be -ENOENT or not */
2784                 return -EINVAL;
2785         case EP_STATE_HALTED:
2786                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2787         case EP_STATE_STOPPED:
2788         case EP_STATE_RUNNING:
2789                 break;
2790         default:
2791                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2792                 /*
2793                  * FIXME issue Configure Endpoint command to try to get the HC
2794                  * back into a known state.
2795                  */
2796                 return -EINVAL;
2797         }
2798         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2799                 /* FIXME allocate more room */
2800                 xhci_err(xhci, "ERROR no room on ep ring\n");
2801                 return -ENOMEM;
2802         }
2803
2804         if (enqueue_is_link_trb(ep_ring)) {
2805                 struct xhci_ring *ring = ep_ring;
2806                 union xhci_trb *next;
2807
2808                 next = ring->enqueue;
2809
2810                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2811                         /* If we're not dealing with 0.95 hardware or isoc rings
2812                          * on AMD 0.96 host, clear the chain bit.
2813                          */
2814                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2815                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2816                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2817                         else
2818                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2819
2820                         wmb();
2821                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2822
2823                         /* Toggle the cycle bit after the last ring segment. */
2824                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2825                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2826                                 if (!in_interrupt()) {
2827                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2828                                                 "state for ring %p = %i\n",
2829                                                 ring, (unsigned int)ring->cycle_state);
2830                                 }
2831                         }
2832                         ring->enq_seg = ring->enq_seg->next;
2833                         ring->enqueue = ring->enq_seg->trbs;
2834                         next = ring->enqueue;
2835                 }
2836         }
2837
2838         return 0;
2839 }
2840
2841 static int prepare_transfer(struct xhci_hcd *xhci,
2842                 struct xhci_virt_device *xdev,
2843                 unsigned int ep_index,
2844                 unsigned int stream_id,
2845                 unsigned int num_trbs,
2846                 struct urb *urb,
2847                 unsigned int td_index,
2848                 bool isoc,
2849                 gfp_t mem_flags)
2850 {
2851         int ret;
2852         struct urb_priv *urb_priv;
2853         struct xhci_td  *td;
2854         struct xhci_ring *ep_ring;
2855         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2856
2857         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2858         if (!ep_ring) {
2859                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2860                                 stream_id);
2861                 return -EINVAL;
2862         }
2863
2864         ret = prepare_ring(xhci, ep_ring,
2865                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2866                            num_trbs, isoc, mem_flags);
2867         if (ret)
2868                 return ret;
2869
2870         urb_priv = urb->hcpriv;
2871         td = urb_priv->td[td_index];
2872
2873         INIT_LIST_HEAD(&td->td_list);
2874         INIT_LIST_HEAD(&td->cancelled_td_list);
2875
2876         if (td_index == 0) {
2877                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2878                 if (unlikely(ret))
2879                         return ret;
2880         }
2881
2882         td->urb = urb;
2883         /* Add this TD to the tail of the endpoint ring's TD list */
2884         list_add_tail(&td->td_list, &ep_ring->td_list);
2885         td->start_seg = ep_ring->enq_seg;
2886         td->first_trb = ep_ring->enqueue;
2887
2888         urb_priv->td[td_index] = td;
2889
2890         return 0;
2891 }
2892
2893 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2894 {
2895         int num_sgs, num_trbs, running_total, temp, i;
2896         struct scatterlist *sg;
2897
2898         sg = NULL;
2899         num_sgs = urb->num_mapped_sgs;
2900         temp = urb->transfer_buffer_length;
2901
2902         xhci_dbg(xhci, "count sg list trbs: \n");
2903         num_trbs = 0;
2904         for_each_sg(urb->sg, sg, num_sgs, i) {
2905                 unsigned int previous_total_trbs = num_trbs;
2906                 unsigned int len = sg_dma_len(sg);
2907
2908                 /* Scatter gather list entries may cross 64KB boundaries */
2909                 running_total = TRB_MAX_BUFF_SIZE -
2910                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2911                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2912                 if (running_total != 0)
2913                         num_trbs++;
2914
2915                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2916                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2917                         num_trbs++;
2918                         running_total += TRB_MAX_BUFF_SIZE;
2919                 }
2920                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2921                                 i, (unsigned long long)sg_dma_address(sg),
2922                                 len, len, num_trbs - previous_total_trbs);
2923
2924                 len = min_t(int, len, temp);
2925                 temp -= len;
2926                 if (temp == 0)
2927                         break;
2928         }
2929         xhci_dbg(xhci, "\n");
2930         if (!in_interrupt())
2931                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2932                                 "num_trbs = %d\n",
2933                                 urb->ep->desc.bEndpointAddress,
2934                                 urb->transfer_buffer_length,
2935                                 num_trbs);
2936         return num_trbs;
2937 }
2938
2939 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2940 {
2941         if (num_trbs != 0)
2942                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2943                                 "TRBs, %d left\n", __func__,
2944                                 urb->ep->desc.bEndpointAddress, num_trbs);
2945         if (running_total != urb->transfer_buffer_length)
2946                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2947                                 "queued %#x (%d), asked for %#x (%d)\n",
2948                                 __func__,
2949                                 urb->ep->desc.bEndpointAddress,
2950                                 running_total, running_total,
2951                                 urb->transfer_buffer_length,
2952                                 urb->transfer_buffer_length);
2953 }
2954
2955 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2956                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2957                 struct xhci_generic_trb *start_trb)
2958 {
2959         /*
2960          * Pass all the TRBs to the hardware at once and make sure this write
2961          * isn't reordered.
2962          */
2963         wmb();
2964         if (start_cycle)
2965                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2966         else
2967                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2968         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2969 }
2970
2971 /*
2972  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2973  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2974  * (comprised of sg list entries) can take several service intervals to
2975  * transmit.
2976  */
2977 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2978                 struct urb *urb, int slot_id, unsigned int ep_index)
2979 {
2980         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2981                         xhci->devs[slot_id]->out_ctx, ep_index);
2982         int xhci_interval;
2983         int ep_interval;
2984
2985         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2986         ep_interval = urb->interval;
2987         /* Convert to microframes */
2988         if (urb->dev->speed == USB_SPEED_LOW ||
2989                         urb->dev->speed == USB_SPEED_FULL)
2990                 ep_interval *= 8;
2991         /* FIXME change this to a warning and a suggestion to use the new API
2992          * to set the polling interval (once the API is added).
2993          */
2994         if (xhci_interval != ep_interval) {
2995                 if (printk_ratelimit())
2996                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2997                                         " (%d microframe%s) than xHCI "
2998                                         "(%d microframe%s)\n",
2999                                         ep_interval,
3000                                         ep_interval == 1 ? "" : "s",
3001                                         xhci_interval,
3002                                         xhci_interval == 1 ? "" : "s");
3003                 urb->interval = xhci_interval;
3004                 /* Convert back to frames for LS/FS devices */
3005                 if (urb->dev->speed == USB_SPEED_LOW ||
3006                                 urb->dev->speed == USB_SPEED_FULL)
3007                         urb->interval /= 8;
3008         }
3009         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3010 }
3011
3012 /*
3013  * The TD size is the number of bytes remaining in the TD (including this TRB),
3014  * right shifted by 10.
3015  * It must fit in bits 21:17, so it can't be bigger than 31.
3016  */
3017 static u32 xhci_td_remainder(unsigned int remainder)
3018 {
3019         u32 max = (1 << (21 - 17 + 1)) - 1;
3020
3021         if ((remainder >> 10) >= max)
3022                 return max << 17;
3023         else
3024                 return (remainder >> 10) << 17;
3025 }
3026
3027 /*
3028  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3029  * packets remaining in the TD (*not* including this TRB).
3030  *
3031  * Total TD packet count = total_packet_count =
3032  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3033  *
3034  * Packets transferred up to and including this TRB = packets_transferred =
3035  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3036  *
3037  * TD size = total_packet_count - packets_transferred
3038  *
3039  * It must fit in bits 21:17, so it can't be bigger than 31.
3040  * The last TRB in a TD must have the TD size set to zero.
3041  */
3042 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3043                 unsigned int total_packet_count, struct urb *urb,
3044                 unsigned int num_trbs_left)
3045 {
3046         int packets_transferred;
3047
3048         /* One TRB with a zero-length data packet. */
3049         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3050                 return 0;
3051
3052         /* All the TRB queueing functions don't count the current TRB in
3053          * running_total.
3054          */
3055         packets_transferred = (running_total + trb_buff_len) /
3056                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3057
3058         if ((total_packet_count - packets_transferred) > 31)
3059                 return 31 << 17;
3060         return (total_packet_count - packets_transferred) << 17;
3061 }
3062
3063 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3064                 struct urb *urb, int slot_id, unsigned int ep_index)
3065 {
3066         struct xhci_ring *ep_ring;
3067         unsigned int num_trbs;
3068         struct urb_priv *urb_priv;
3069         struct xhci_td *td;
3070         struct scatterlist *sg;
3071         int num_sgs;
3072         int trb_buff_len, this_sg_len, running_total;
3073         unsigned int total_packet_count;
3074         bool first_trb;
3075         u64 addr;
3076         bool more_trbs_coming;
3077
3078         struct xhci_generic_trb *start_trb;
3079         int start_cycle;
3080
3081         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3082         if (!ep_ring)
3083                 return -EINVAL;
3084
3085         num_trbs = count_sg_trbs_needed(xhci, urb);
3086         num_sgs = urb->num_mapped_sgs;
3087         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3088                         usb_endpoint_maxp(&urb->ep->desc));
3089
3090         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3091                         ep_index, urb->stream_id,
3092                         num_trbs, urb, 0, false, mem_flags);
3093         if (trb_buff_len < 0)
3094                 return trb_buff_len;
3095
3096         urb_priv = urb->hcpriv;
3097         td = urb_priv->td[0];
3098
3099         /*
3100          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3101          * until we've finished creating all the other TRBs.  The ring's cycle
3102          * state may change as we enqueue the other TRBs, so save it too.
3103          */
3104         start_trb = &ep_ring->enqueue->generic;
3105         start_cycle = ep_ring->cycle_state;
3106
3107         running_total = 0;
3108         /*
3109          * How much data is in the first TRB?
3110          *
3111          * There are three forces at work for TRB buffer pointers and lengths:
3112          * 1. We don't want to walk off the end of this sg-list entry buffer.
3113          * 2. The transfer length that the driver requested may be smaller than
3114          *    the amount of memory allocated for this scatter-gather list.
3115          * 3. TRBs buffers can't cross 64KB boundaries.
3116          */
3117         sg = urb->sg;
3118         addr = (u64) sg_dma_address(sg);
3119         this_sg_len = sg_dma_len(sg);
3120         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3121         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3122         if (trb_buff_len > urb->transfer_buffer_length)
3123                 trb_buff_len = urb->transfer_buffer_length;
3124         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3125                         trb_buff_len);
3126
3127         first_trb = true;
3128         /* Queue the first TRB, even if it's zero-length */
3129         do {
3130                 u32 field = 0;
3131                 u32 length_field = 0;
3132                 u32 remainder = 0;
3133
3134                 /* Don't change the cycle bit of the first TRB until later */
3135                 if (first_trb) {
3136                         first_trb = false;
3137                         if (start_cycle == 0)
3138                                 field |= 0x1;
3139                 } else
3140                         field |= ep_ring->cycle_state;
3141
3142                 /* Chain all the TRBs together; clear the chain bit in the last
3143                  * TRB to indicate it's the last TRB in the chain.
3144                  */
3145                 if (num_trbs > 1) {
3146                         field |= TRB_CHAIN;
3147                 } else {
3148                         /* FIXME - add check for ZERO_PACKET flag before this */
3149                         td->last_trb = ep_ring->enqueue;
3150                         field |= TRB_IOC;
3151                 }
3152
3153                 /* Only set interrupt on short packet for IN endpoints */
3154                 if (usb_urb_dir_in(urb))
3155                         field |= TRB_ISP;
3156
3157                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3158                                 "64KB boundary at %#x, end dma = %#x\n",
3159                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
3160                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3161                                 (unsigned int) addr + trb_buff_len);
3162                 if (TRB_MAX_BUFF_SIZE -
3163                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3164                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3165                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3166                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3167                                         (unsigned int) addr + trb_buff_len);
3168                 }
3169
3170                 /* Set the TRB length, TD size, and interrupter fields. */
3171                 if (xhci->hci_version < 0x100) {
3172                         remainder = xhci_td_remainder(
3173                                         urb->transfer_buffer_length -
3174                                         running_total);
3175                 } else {
3176                         remainder = xhci_v1_0_td_remainder(running_total,
3177                                         trb_buff_len, total_packet_count, urb,
3178                                         num_trbs - 1);
3179                 }
3180                 length_field = TRB_LEN(trb_buff_len) |
3181                         remainder |
3182                         TRB_INTR_TARGET(0);
3183
3184                 if (num_trbs > 1)
3185                         more_trbs_coming = true;
3186                 else
3187                         more_trbs_coming = false;
3188                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3189                                 lower_32_bits(addr),
3190                                 upper_32_bits(addr),
3191                                 length_field,
3192                                 field | TRB_TYPE(TRB_NORMAL));
3193                 --num_trbs;
3194                 running_total += trb_buff_len;
3195
3196                 /* Calculate length for next transfer --
3197                  * Are we done queueing all the TRBs for this sg entry?
3198                  */
3199                 this_sg_len -= trb_buff_len;
3200                 if (this_sg_len == 0) {
3201                         --num_sgs;
3202                         if (num_sgs == 0)
3203                                 break;
3204                         sg = sg_next(sg);
3205                         addr = (u64) sg_dma_address(sg);
3206                         this_sg_len = sg_dma_len(sg);
3207                 } else {
3208                         addr += trb_buff_len;
3209                 }
3210
3211                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3212                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3213                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3214                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3215                         trb_buff_len =
3216                                 urb->transfer_buffer_length - running_total;
3217         } while (running_total < urb->transfer_buffer_length);
3218
3219         check_trb_math(urb, num_trbs, running_total);
3220         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3221                         start_cycle, start_trb);
3222         return 0;
3223 }
3224
3225 /* This is very similar to what ehci-q.c qtd_fill() does */
3226 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3227                 struct urb *urb, int slot_id, unsigned int ep_index)
3228 {
3229         struct xhci_ring *ep_ring;
3230         struct urb_priv *urb_priv;
3231         struct xhci_td *td;
3232         int num_trbs;
3233         struct xhci_generic_trb *start_trb;
3234         bool first_trb;
3235         bool more_trbs_coming;
3236         int start_cycle;
3237         u32 field, length_field;
3238
3239         int running_total, trb_buff_len, ret;
3240         unsigned int total_packet_count;
3241         u64 addr;
3242
3243         if (urb->num_sgs)
3244                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3245
3246         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3247         if (!ep_ring)
3248                 return -EINVAL;
3249
3250         num_trbs = 0;
3251         /* How much data is (potentially) left before the 64KB boundary? */
3252         running_total = TRB_MAX_BUFF_SIZE -
3253                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3254         running_total &= TRB_MAX_BUFF_SIZE - 1;
3255
3256         /* If there's some data on this 64KB chunk, or we have to send a
3257          * zero-length transfer, we need at least one TRB
3258          */
3259         if (running_total != 0 || urb->transfer_buffer_length == 0)
3260                 num_trbs++;
3261         /* How many more 64KB chunks to transfer, how many more TRBs? */
3262         while (running_total < urb->transfer_buffer_length) {
3263                 num_trbs++;
3264                 running_total += TRB_MAX_BUFF_SIZE;
3265         }
3266         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3267
3268         if (!in_interrupt())
3269                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3270                                 "addr = %#llx, num_trbs = %d\n",
3271                                 urb->ep->desc.bEndpointAddress,
3272                                 urb->transfer_buffer_length,
3273                                 urb->transfer_buffer_length,
3274                                 (unsigned long long)urb->transfer_dma,
3275                                 num_trbs);
3276
3277         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3278                         ep_index, urb->stream_id,
3279                         num_trbs, urb, 0, false, mem_flags);
3280         if (ret < 0)
3281                 return ret;
3282
3283         urb_priv = urb->hcpriv;
3284         td = urb_priv->td[0];
3285
3286         /*
3287          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3288          * until we've finished creating all the other TRBs.  The ring's cycle
3289          * state may change as we enqueue the other TRBs, so save it too.
3290          */
3291         start_trb = &ep_ring->enqueue->generic;
3292         start_cycle = ep_ring->cycle_state;
3293
3294         running_total = 0;
3295         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3296                         usb_endpoint_maxp(&urb->ep->desc));
3297         /* How much data is in the first TRB? */
3298         addr = (u64) urb->transfer_dma;
3299         trb_buff_len = TRB_MAX_BUFF_SIZE -
3300                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3301         if (trb_buff_len > urb->transfer_buffer_length)
3302                 trb_buff_len = urb->transfer_buffer_length;
3303
3304         first_trb = true;
3305
3306         /* Queue the first TRB, even if it's zero-length */
3307         do {
3308                 u32 remainder = 0;
3309                 field = 0;
3310
3311                 /* Don't change the cycle bit of the first TRB until later */
3312                 if (first_trb) {
3313                         first_trb = false;
3314                         if (start_cycle == 0)
3315                                 field |= 0x1;
3316                 } else
3317                         field |= ep_ring->cycle_state;
3318
3319                 /* Chain all the TRBs together; clear the chain bit in the last
3320                  * TRB to indicate it's the last TRB in the chain.
3321                  */
3322                 if (num_trbs > 1) {
3323                         field |= TRB_CHAIN;
3324                 } else {
3325                         /* FIXME - add check for ZERO_PACKET flag before this */
3326                         td->last_trb = ep_ring->enqueue;
3327                         field |= TRB_IOC;
3328                 }
3329
3330                 /* Only set interrupt on short packet for IN endpoints */
3331                 if (usb_urb_dir_in(urb))
3332                         field |= TRB_ISP;
3333
3334                 /* Set the TRB length, TD size, and interrupter fields. */
3335                 if (xhci->hci_version < 0x100) {
3336                         remainder = xhci_td_remainder(
3337                                         urb->transfer_buffer_length -
3338                                         running_total);
3339                 } else {
3340                         remainder = xhci_v1_0_td_remainder(running_total,
3341                                         trb_buff_len, total_packet_count, urb,
3342                                         num_trbs - 1);
3343                 }
3344                 length_field = TRB_LEN(trb_buff_len) |
3345                         remainder |
3346                         TRB_INTR_TARGET(0);
3347
3348                 if (num_trbs > 1)
3349                         more_trbs_coming = true;
3350                 else
3351                         more_trbs_coming = false;
3352                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3353                                 lower_32_bits(addr),
3354                                 upper_32_bits(addr),
3355                                 length_field,
3356                                 field | TRB_TYPE(TRB_NORMAL));
3357                 --num_trbs;
3358                 running_total += trb_buff_len;
3359
3360                 /* Calculate length for next transfer */
3361                 addr += trb_buff_len;
3362                 trb_buff_len = urb->transfer_buffer_length - running_total;
3363                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3364                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3365         } while (running_total < urb->transfer_buffer_length);
3366
3367         check_trb_math(urb, num_trbs, running_total);
3368         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3369                         start_cycle, start_trb);
3370         return 0;
3371 }
3372
3373 /* Caller must have locked xhci->lock */
3374 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3375                 struct urb *urb, int slot_id, unsigned int ep_index)
3376 {
3377         struct xhci_ring *ep_ring;
3378         int num_trbs;
3379         int ret;
3380         struct usb_ctrlrequest *setup;
3381         struct xhci_generic_trb *start_trb;
3382         int start_cycle;
3383         u32 field, length_field;
3384         struct urb_priv *urb_priv;
3385         struct xhci_td *td;
3386
3387         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3388         if (!ep_ring)
3389                 return -EINVAL;
3390
3391         /*
3392          * Need to copy setup packet into setup TRB, so we can't use the setup
3393          * DMA address.
3394          */
3395         if (!urb->setup_packet)
3396                 return -EINVAL;
3397
3398         if (!in_interrupt())
3399                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3400                                 slot_id, ep_index);
3401         /* 1 TRB for setup, 1 for status */
3402         num_trbs = 2;
3403         /*
3404          * Don't need to check if we need additional event data and normal TRBs,
3405          * since data in control transfers will never get bigger than 16MB
3406          * XXX: can we get a buffer that crosses 64KB boundaries?
3407          */
3408         if (urb->transfer_buffer_length > 0)
3409                 num_trbs++;
3410         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3411                         ep_index, urb->stream_id,
3412                         num_trbs, urb, 0, false, mem_flags);
3413         if (ret < 0)
3414                 return ret;
3415
3416         urb_priv = urb->hcpriv;
3417         td = urb_priv->td[0];
3418
3419         /*
3420          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3421          * until we've finished creating all the other TRBs.  The ring's cycle
3422          * state may change as we enqueue the other TRBs, so save it too.
3423          */
3424         start_trb = &ep_ring->enqueue->generic;
3425         start_cycle = ep_ring->cycle_state;
3426
3427         /* Queue setup TRB - see section 6.4.1.2.1 */
3428         /* FIXME better way to translate setup_packet into two u32 fields? */
3429         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3430         field = 0;
3431         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3432         if (start_cycle == 0)
3433                 field |= 0x1;
3434
3435         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3436         if (xhci->hci_version == 0x100) {
3437                 if (urb->transfer_buffer_length > 0) {
3438                         if (setup->bRequestType & USB_DIR_IN)
3439                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3440                         else
3441                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3442                 }
3443         }
3444
3445         queue_trb(xhci, ep_ring, false, true, false,
3446                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3447                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3448                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3449                   /* Immediate data in pointer */
3450                   field);
3451
3452         /* If there's data, queue data TRBs */
3453         /* Only set interrupt on short packet for IN endpoints */
3454         if (usb_urb_dir_in(urb))
3455                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3456         else
3457                 field = TRB_TYPE(TRB_DATA);
3458
3459         length_field = TRB_LEN(urb->transfer_buffer_length) |
3460                 xhci_td_remainder(urb->transfer_buffer_length) |
3461                 TRB_INTR_TARGET(0);
3462         if (urb->transfer_buffer_length > 0) {
3463                 if (setup->bRequestType & USB_DIR_IN)
3464                         field |= TRB_DIR_IN;
3465                 queue_trb(xhci, ep_ring, false, true, false,
3466                                 lower_32_bits(urb->transfer_dma),
3467                                 upper_32_bits(urb->transfer_dma),
3468                                 length_field,
3469                                 field | ep_ring->cycle_state);
3470         }
3471
3472         /* Save the DMA address of the last TRB in the TD */
3473         td->last_trb = ep_ring->enqueue;
3474
3475         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3476         /* If the device sent data, the status stage is an OUT transfer */
3477         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3478                 field = 0;
3479         else
3480                 field = TRB_DIR_IN;
3481         queue_trb(xhci, ep_ring, false, false, false,
3482                         0,
3483                         0,
3484                         TRB_INTR_TARGET(0),
3485                         /* Event on completion */
3486                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3487
3488         giveback_first_trb(xhci, slot_id, ep_index, 0,
3489                         start_cycle, start_trb);
3490         return 0;
3491 }
3492
3493 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3494                 struct urb *urb, int i)
3495 {
3496         int num_trbs = 0;
3497         u64 addr, td_len;
3498
3499         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3500         td_len = urb->iso_frame_desc[i].length;
3501
3502         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3503                         TRB_MAX_BUFF_SIZE);
3504         if (num_trbs == 0)
3505                 num_trbs++;
3506
3507         return num_trbs;
3508 }
3509
3510 /*
3511  * The transfer burst count field of the isochronous TRB defines the number of
3512  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3513  * devices can burst up to bMaxBurst number of packets per service interval.
3514  * This field is zero based, meaning a value of zero in the field means one
3515  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3516  * zero.  Only xHCI 1.0 host controllers support this field.
3517  */
3518 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3519                 struct usb_device *udev,
3520                 struct urb *urb, unsigned int total_packet_count)
3521 {
3522         unsigned int max_burst;
3523
3524         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3525                 return 0;
3526
3527         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3528         return roundup(total_packet_count, max_burst + 1) - 1;
3529 }
3530
3531 /*
3532  * Returns the number of packets in the last "burst" of packets.  This field is
3533  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3534  * the last burst packet count is equal to the total number of packets in the
3535  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3536  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3537  * contain 1 to (bMaxBurst + 1) packets.
3538  */
3539 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3540                 struct usb_device *udev,
3541                 struct urb *urb, unsigned int total_packet_count)
3542 {
3543         unsigned int max_burst;
3544         unsigned int residue;
3545
3546         if (xhci->hci_version < 0x100)
3547                 return 0;
3548
3549         switch (udev->speed) {
3550         case USB_SPEED_SUPER:
3551                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3552                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3553                 residue = total_packet_count % (max_burst + 1);
3554                 /* If residue is zero, the last burst contains (max_burst + 1)
3555                  * number of packets, but the TLBPC field is zero-based.
3556                  */
3557                 if (residue == 0)
3558                         return max_burst;
3559                 return residue - 1;
3560         default:
3561                 if (total_packet_count == 0)
3562                         return 0;
3563                 return total_packet_count - 1;
3564         }
3565 }
3566
3567 /* This is for isoc transfer */
3568 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3569                 struct urb *urb, int slot_id, unsigned int ep_index)
3570 {
3571         struct xhci_ring *ep_ring;
3572         struct urb_priv *urb_priv;
3573         struct xhci_td *td;
3574         int num_tds, trbs_per_td;
3575         struct xhci_generic_trb *start_trb;
3576         bool first_trb;
3577         int start_cycle;
3578         u32 field, length_field;
3579         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3580         u64 start_addr, addr;
3581         int i, j;
3582         bool more_trbs_coming;
3583
3584         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3585
3586         num_tds = urb->number_of_packets;
3587         if (num_tds < 1) {
3588                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3589                 return -EINVAL;
3590         }
3591
3592         if (!in_interrupt())
3593                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3594                                 " addr = %#llx, num_tds = %d\n",
3595                                 urb->ep->desc.bEndpointAddress,
3596                                 urb->transfer_buffer_length,
3597                                 urb->transfer_buffer_length,
3598                                 (unsigned long long)urb->transfer_dma,
3599                                 num_tds);
3600
3601         start_addr = (u64) urb->transfer_dma;
3602         start_trb = &ep_ring->enqueue->generic;
3603         start_cycle = ep_ring->cycle_state;
3604
3605         urb_priv = urb->hcpriv;
3606         /* Queue the first TRB, even if it's zero-length */
3607         for (i = 0; i < num_tds; i++) {
3608                 unsigned int total_packet_count;
3609                 unsigned int burst_count;
3610                 unsigned int residue;
3611
3612                 first_trb = true;
3613                 running_total = 0;
3614                 addr = start_addr + urb->iso_frame_desc[i].offset;
3615                 td_len = urb->iso_frame_desc[i].length;
3616                 td_remain_len = td_len;
3617                 total_packet_count = DIV_ROUND_UP(td_len,
3618                                 GET_MAX_PACKET(
3619                                         usb_endpoint_maxp(&urb->ep->desc)));
3620                 /* A zero-length transfer still involves at least one packet. */
3621                 if (total_packet_count == 0)
3622                         total_packet_count++;
3623                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3624                                 total_packet_count);
3625                 residue = xhci_get_last_burst_packet_count(xhci,
3626                                 urb->dev, urb, total_packet_count);
3627
3628                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3629
3630                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3631                                 urb->stream_id, trbs_per_td, urb, i, true,
3632                                 mem_flags);
3633                 if (ret < 0) {
3634                         if (i == 0)
3635                                 return ret;
3636                         goto cleanup;
3637                 }
3638
3639                 td = urb_priv->td[i];
3640                 for (j = 0; j < trbs_per_td; j++) {
3641                         u32 remainder = 0;
3642                         field = 0;
3643
3644                         if (first_trb) {
3645                                 field = TRB_TBC(burst_count) |
3646                                         TRB_TLBPC(residue);
3647                                 /* Queue the isoc TRB */
3648                                 field |= TRB_TYPE(TRB_ISOC);
3649                                 /* Assume URB_ISO_ASAP is set */
3650                                 field |= TRB_SIA;
3651                                 if (i == 0) {
3652                                         if (start_cycle == 0)
3653                                                 field |= 0x1;
3654                                 } else
3655                                         field |= ep_ring->cycle_state;
3656                                 first_trb = false;
3657                         } else {
3658                                 /* Queue other normal TRBs */
3659                                 field |= TRB_TYPE(TRB_NORMAL);
3660                                 field |= ep_ring->cycle_state;
3661                         }
3662
3663                         /* Only set interrupt on short packet for IN EPs */
3664                         if (usb_urb_dir_in(urb))
3665                                 field |= TRB_ISP;
3666
3667                         /* Chain all the TRBs together; clear the chain bit in
3668                          * the last TRB to indicate it's the last TRB in the
3669                          * chain.
3670                          */
3671                         if (j < trbs_per_td - 1) {
3672                                 field |= TRB_CHAIN;
3673                                 more_trbs_coming = true;
3674                         } else {
3675                                 td->last_trb = ep_ring->enqueue;
3676                                 field |= TRB_IOC;
3677                                 if (xhci->hci_version == 0x100 &&
3678                                                 !(xhci->quirks &
3679                                                         XHCI_AVOID_BEI)) {
3680                                         /* Set BEI bit except for the last td */
3681                                         if (i < num_tds - 1)
3682                                                 field |= TRB_BEI;
3683                                 }
3684                                 more_trbs_coming = false;
3685                         }
3686
3687                         /* Calculate TRB length */
3688                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3689                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3690                         if (trb_buff_len > td_remain_len)
3691                                 trb_buff_len = td_remain_len;
3692
3693                         /* Set the TRB length, TD size, & interrupter fields. */
3694                         if (xhci->hci_version < 0x100) {
3695                                 remainder = xhci_td_remainder(
3696                                                 td_len - running_total);
3697                         } else {
3698                                 remainder = xhci_v1_0_td_remainder(
3699                                                 running_total, trb_buff_len,
3700                                                 total_packet_count, urb,
3701                                                 (trbs_per_td - j - 1));
3702                         }
3703                         length_field = TRB_LEN(trb_buff_len) |
3704                                 remainder |
3705                                 TRB_INTR_TARGET(0);
3706
3707                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3708                                 lower_32_bits(addr),
3709                                 upper_32_bits(addr),
3710                                 length_field,
3711                                 field);
3712                         running_total += trb_buff_len;
3713
3714                         addr += trb_buff_len;
3715                         td_remain_len -= trb_buff_len;
3716                 }
3717
3718                 /* Check TD length */
3719                 if (running_total != td_len) {
3720                         xhci_err(xhci, "ISOC TD length unmatch\n");
3721                         ret = -EINVAL;
3722                         goto cleanup;
3723                 }
3724         }
3725
3726         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3727                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3728                         usb_amd_quirk_pll_disable();
3729         }
3730         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3731
3732         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3733                         start_cycle, start_trb);
3734         return 0;
3735 cleanup:
3736         /* Clean up a partially enqueued isoc transfer. */
3737
3738         for (i--; i >= 0; i--)
3739                 list_del_init(&urb_priv->td[i]->td_list);
3740
3741         /* Use the first TD as a temporary variable to turn the TDs we've queued
3742          * into No-ops with a software-owned cycle bit. That way the hardware
3743          * won't accidentally start executing bogus TDs when we partially
3744          * overwrite them.  td->first_trb and td->start_seg are already set.
3745          */
3746         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3747         /* Every TRB except the first & last will have its cycle bit flipped. */
3748         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3749
3750         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3751         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3752         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3753         ep_ring->cycle_state = start_cycle;
3754         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3755         return ret;
3756 }
3757
3758 /*
3759  * Check transfer ring to guarantee there is enough room for the urb.
3760  * Update ISO URB start_frame and interval.
3761  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3762  * update the urb->start_frame by now.
3763  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3764  */
3765 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3766                 struct urb *urb, int slot_id, unsigned int ep_index)
3767 {
3768         struct xhci_virt_device *xdev;
3769         struct xhci_ring *ep_ring;
3770         struct xhci_ep_ctx *ep_ctx;
3771         int start_frame;
3772         int xhci_interval;
3773         int ep_interval;
3774         int num_tds, num_trbs, i;
3775         int ret;
3776
3777         xdev = xhci->devs[slot_id];
3778         ep_ring = xdev->eps[ep_index].ring;
3779         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3780
3781         num_trbs = 0;
3782         num_tds = urb->number_of_packets;
3783         for (i = 0; i < num_tds; i++)
3784                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3785
3786         /* Check the ring to guarantee there is enough room for the whole urb.
3787          * Do not insert any td of the urb to the ring if the check failed.
3788          */
3789         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3790                            num_trbs, true, mem_flags);
3791         if (ret)
3792                 return ret;
3793
3794         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3795         start_frame &= 0x3fff;
3796
3797         urb->start_frame = start_frame;
3798         if (urb->dev->speed == USB_SPEED_LOW ||
3799                         urb->dev->speed == USB_SPEED_FULL)
3800                 urb->start_frame >>= 3;
3801
3802         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3803         ep_interval = urb->interval;
3804         /* Convert to microframes */
3805         if (urb->dev->speed == USB_SPEED_LOW ||
3806                         urb->dev->speed == USB_SPEED_FULL)
3807                 ep_interval *= 8;
3808         /* FIXME change this to a warning and a suggestion to use the new API
3809          * to set the polling interval (once the API is added).
3810          */
3811         if (xhci_interval != ep_interval) {
3812                 if (printk_ratelimit())
3813                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3814                                         " (%d microframe%s) than xHCI "
3815                                         "(%d microframe%s)\n",
3816                                         ep_interval,
3817                                         ep_interval == 1 ? "" : "s",
3818                                         xhci_interval,
3819                                         xhci_interval == 1 ? "" : "s");
3820                 urb->interval = xhci_interval;
3821                 /* Convert back to frames for LS/FS devices */
3822                 if (urb->dev->speed == USB_SPEED_LOW ||
3823                                 urb->dev->speed == USB_SPEED_FULL)
3824                         urb->interval /= 8;
3825         }
3826         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3827 }
3828
3829 /****           Command Ring Operations         ****/
3830
3831 /* Generic function for queueing a command TRB on the command ring.
3832  * Check to make sure there's room on the command ring for one command TRB.
3833  * Also check that there's room reserved for commands that must not fail.
3834  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3835  * then only check for the number of reserved spots.
3836  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3837  * because the command event handler may want to resubmit a failed command.
3838  */
3839 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3840                 u32 field3, u32 field4, bool command_must_succeed)
3841 {
3842         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3843         int ret;
3844
3845         if (!command_must_succeed)
3846                 reserved_trbs++;
3847
3848         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3849                         reserved_trbs, false, GFP_ATOMIC);
3850         if (ret < 0) {
3851                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3852                 if (command_must_succeed)
3853                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3854                                         "unfailable commands failed.\n");
3855                 return ret;
3856         }
3857         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3858                         field3, field4 | xhci->cmd_ring->cycle_state);
3859         return 0;
3860 }
3861
3862 /* Queue a slot enable or disable request on the command ring */
3863 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3864 {
3865         return queue_command(xhci, 0, 0, 0,
3866                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3867 }
3868
3869 /* Queue an address device command TRB */
3870 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3871                 u32 slot_id)
3872 {
3873         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3874                         upper_32_bits(in_ctx_ptr), 0,
3875                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3876                         false);
3877 }
3878
3879 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3880                 u32 field1, u32 field2, u32 field3, u32 field4)
3881 {
3882         return queue_command(xhci, field1, field2, field3, field4, false);
3883 }
3884
3885 /* Queue a reset device command TRB */
3886 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3887 {
3888         return queue_command(xhci, 0, 0, 0,
3889                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3890                         false);
3891 }
3892
3893 /* Queue a configure endpoint command TRB */
3894 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3895                 u32 slot_id, bool command_must_succeed)
3896 {
3897         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3898                         upper_32_bits(in_ctx_ptr), 0,
3899                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3900                         command_must_succeed);
3901 }
3902
3903 /* Queue an evaluate context command TRB */
3904 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3905                 u32 slot_id)
3906 {
3907         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3908                         upper_32_bits(in_ctx_ptr), 0,
3909                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3910                         false);
3911 }
3912
3913 /*
3914  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3915  * activity on an endpoint that is about to be suspended.
3916  */
3917 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3918                 unsigned int ep_index, int suspend)
3919 {
3920         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3921         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3922         u32 type = TRB_TYPE(TRB_STOP_RING);
3923         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3924
3925         return queue_command(xhci, 0, 0, 0,
3926                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3927 }
3928
3929 /* Set Transfer Ring Dequeue Pointer command.
3930  * This should not be used for endpoints that have streams enabled.
3931  */
3932 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3933                 unsigned int ep_index, unsigned int stream_id,
3934                 struct xhci_segment *deq_seg,
3935                 union xhci_trb *deq_ptr, u32 cycle_state)
3936 {
3937         dma_addr_t addr;
3938         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3939         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3940         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3941         u32 type = TRB_TYPE(TRB_SET_DEQ);
3942         struct xhci_virt_ep *ep;
3943
3944         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3945         if (addr == 0) {
3946                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3947                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3948                                 deq_seg, deq_ptr);
3949                 return 0;
3950         }
3951         ep = &xhci->devs[slot_id]->eps[ep_index];
3952         if ((ep->ep_state & SET_DEQ_PENDING)) {
3953                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3954                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3955                 return 0;
3956         }
3957         ep->queued_deq_seg = deq_seg;
3958         ep->queued_deq_ptr = deq_ptr;
3959         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3960                         upper_32_bits(addr), trb_stream_id,
3961                         trb_slot_id | trb_ep_index | type, false);
3962 }
3963
3964 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3965                 unsigned int ep_index)
3966 {
3967         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3968         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3969         u32 type = TRB_TYPE(TRB_RESET_EP);
3970
3971         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3972                         false);
3973 }