drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                         if (!in_interrupt())
 159                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 160                                                 ring,
 161                                                 (unsigned int) ring->cycle_state);
 162                 }
 163                 ring->deq_seg = ring->deq_seg->next;
 164                 ring->dequeue = ring->deq_seg->trbs;
 165                 next = ring->dequeue;
 166         }
 167         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 168 }
 169
 170 /*
 171  * See Cycle bit rules. SW is the consumer for the event ring only.
 172  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 173  *
 174  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 175  * chain bit is set), then set the chain bit in all the following link TRBs.
 176  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 177  * have their chain bit cleared (so that each Link TRB is a separate TD).
 178  *
 179  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 180  * set, but other sections talk about dealing with the chain bit set.  This was
 181  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 182  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 183  *
 184  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 185  *                      prepare_transfer()?
 186  */
 187 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 188                 bool consumer, bool more_trbs_coming, bool isoc)
 189 {
 190         u32 chain;
 191         union xhci_trb *next;
 192         unsigned long long addr;
 193
 194         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 195         next = ++(ring->enqueue);
 196
 197         ring->enq_updates++;
 198         /* Update the dequeue pointer further if that was a link TRB or we're at
 199          * the end of an event ring segment (which doesn't have link TRBS)
 200          */
 201         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 202                 if (!consumer) {
 203                         if (ring != xhci->event_ring) {
 204                                 /*
 205                                  * If the caller doesn't plan on enqueueing more
 206                                  * TDs before ringing the doorbell, then we
 207                                  * don't want to give the link TRB to the
 208                                  * hardware just yet.  We'll give the link TRB
 209                                  * back in prepare_ring() just before we enqueue
 210                                  * the TD at the top of the ring.
 211                                  */
 212                                 if (!chain && !more_trbs_coming)
 213                                         break;
 214
 215                                 /* If we're not dealing with 0.95 hardware or
 216                                  * isoc rings on AMD 0.96 host,
 217                                  * carry over the chain bit of the previous TRB
 218                                  * (which may mean the chain bit is cleared).
 219                                  */
 220                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 221                                                 && !xhci_link_trb_quirk(xhci)) {
 222                                         next->link.control &=
 223                                                 cpu_to_le32(~TRB_CHAIN);
 224                                         next->link.control |=
 225                                                 cpu_to_le32(chain);
 226                                 }
 227                                 /* Give this link TRB to the hardware */
 228                                 wmb();
 229                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 230                         }
 231                         /* Toggle the cycle bit after the last ring segment. */
 232                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 233                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 234                                 if (!in_interrupt())
 235                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 236                                                         ring,
 237                                                         (unsigned int) ring->cycle_state);
 238                         }
 239                 }
 240                 ring->enq_seg = ring->enq_seg->next;
 241                 ring->enqueue = ring->enq_seg->trbs;
 242                 next = ring->enqueue;
 243         }
 244         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 245 }
 246
 247 /*
 248  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 249  * above.
 250  * FIXME: this would be simpler and faster if we just kept track of the number
 251  * of free TRBs in a ring.
 252  */
 253 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 254                 unsigned int num_trbs)
 255 {
 256         int i;
 257         union xhci_trb *enq = ring->enqueue;
 258         struct xhci_segment *enq_seg = ring->enq_seg;
 259         struct xhci_segment *cur_seg;
 260         unsigned int left_on_ring;
 261
 262         /* If we are currently pointing to a link TRB, advance the
 263          * enqueue pointer before checking for space */
 264         while (last_trb(xhci, ring, enq_seg, enq)) {
 265                 enq_seg = enq_seg->next;
 266                 enq = enq_seg->trbs;
 267         }
 268
 269         /* Check if ring is empty */
 270         if (enq == ring->dequeue) {
 271                 /* Can't use link trbs */
 272                 left_on_ring = TRBS_PER_SEGMENT - 1;
 273                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 274                                 cur_seg = cur_seg->next)
 275                         left_on_ring += TRBS_PER_SEGMENT - 1;
 276
 277                 /* Always need one TRB free in the ring. */
 278                 left_on_ring -= 1;
 279                 if (num_trbs > left_on_ring) {
 280                         xhci_warn(xhci, "Not enough room on ring; "
 281                                         "need %u TRBs, %u TRBs left\n",
 282                                         num_trbs, left_on_ring);
 283                         return 0;
 284                 }
 285                 return 1;
 286         }
 287         /* Make sure there's an extra empty TRB available */
 288         for (i = 0; i <= num_trbs; ++i) {
 289                 if (enq == ring->dequeue)
 290                         return 0;
 291                 enq++;
 292                 while (last_trb(xhci, ring, enq_seg, enq)) {
 293                         enq_seg = enq_seg->next;
 294                         enq = enq_seg->trbs;
 295                 }
 296         }
 297         return 1;
 298 }
 299
 300 /* Ring the host controller doorbell after placing a command on the ring */
 301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 302 {
 303         xhci_dbg(xhci, "// Ding dong!\n");
 304         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 305         /* Flush PCI posted writes */
 306         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 307 }
 308
 309 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 310                 unsigned int slot_id,
 311                 unsigned int ep_index,
 312                 unsigned int stream_id)
 313 {
 314         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 315         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 316         unsigned int ep_state = ep->ep_state;
 317
 318         /* Don't ring the doorbell for this endpoint if there are pending
 319          * cancellations because we don't want to interrupt processing.
 320          * We don't want to restart any stream rings if there's a set dequeue
 321          * pointer command pending because the device can choose to start any
 322          * stream once the endpoint is on the HW schedule.
 323          * FIXME - check all the stream rings for pending cancellations.
 324          */
 325         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 326             (ep_state & EP_HALTED))
 327                 return;
 328         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 329         /* The CPU has better things to do at this point than wait for a
 330          * write-posting flush.  It'll get there soon enough.
 331          */
 332 }
 333
 334 /* Ring the doorbell for any rings with pending URBs */
 335 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 336                 unsigned int slot_id,
 337                 unsigned int ep_index)
 338 {
 339         unsigned int stream_id;
 340         struct xhci_virt_ep *ep;
 341
 342         ep = &xhci->devs[slot_id]->eps[ep_index];
 343
 344         /* A ring has pending URBs if its TD list is not empty */
 345         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 346                 if (!(list_empty(&ep->ring->td_list)))
 347                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 348                 return;
 349         }
 350
 351         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 352                         stream_id++) {
 353                 struct xhci_stream_info *stream_info = ep->stream_info;
 354                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 355                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 356                                                 stream_id);
 357         }
 358 }
 359
 360 /*
 361  * Find the segment that trb is in.  Start searching in start_seg.
 362  * If we must move past a segment that has a link TRB with a toggle cycle state
 363  * bit set, then we will toggle the value pointed at by cycle_state.
 364  */
 365 static struct xhci_segment *find_trb_seg(
 366                 struct xhci_segment *start_seg,
 367                 union xhci_trb  *trb, int *cycle_state)
 368 {
 369         struct xhci_segment *cur_seg = start_seg;
 370         struct xhci_generic_trb *generic_trb;
 371
 372         while (cur_seg->trbs > trb ||
 373                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 374                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 375                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 376                         *cycle_state ^= 0x1;
 377                 cur_seg = cur_seg->next;
 378                 if (cur_seg == start_seg)
 379                         /* Looped over the entire list.  Oops! */
 380                         return NULL;
 381         }
 382         return cur_seg;
 383 }
 384
 385
 386 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 387                 unsigned int slot_id, unsigned int ep_index,
 388                 unsigned int stream_id)
 389 {
 390         struct xhci_virt_ep *ep;
 391
 392         ep = &xhci->devs[slot_id]->eps[ep_index];
 393         /* Common case: no streams */
 394         if (!(ep->ep_state & EP_HAS_STREAMS))
 395                 return ep->ring;
 396
 397         if (stream_id == 0) {
 398                 xhci_warn(xhci,
 399                                 "WARN: Slot ID %u, ep index %u has streams, "
 400                                 "but URB has no stream ID.\n",
 401                                 slot_id, ep_index);
 402                 return NULL;
 403         }
 404
 405         if (stream_id < ep->stream_info->num_streams)
 406                 return ep->stream_info->stream_rings[stream_id];
 407
 408         xhci_warn(xhci,
 409                         "WARN: Slot ID %u, ep index %u has "
 410                         "stream IDs 1 to %u allocated, "
 411                         "but stream ID %u is requested.\n",
 412                         slot_id, ep_index,
 413                         ep->stream_info->num_streams - 1,
 414                         stream_id);
 415         return NULL;
 416 }
 417
 418 /* Get the right ring for the given URB.
 419  * If the endpoint supports streams, boundary check the URB's stream ID.
 420  * If the endpoint doesn't support streams, return the singular endpoint ring.
 421  */
 422 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 423                 struct urb *urb)
 424 {
 425         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 426                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 427 }
 428
 429 /*
 430  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 431  * Record the new state of the xHC's endpoint ring dequeue segment,
 432  * dequeue pointer, and new consumer cycle state in state.
 433  * Update our internal representation of the ring's dequeue pointer.
 434  *
 435  * We do this in three jumps:
 436  *  - First we update our new ring state to be the same as when the xHC stopped.
 437  *  - Then we traverse the ring to find the segment that contains
 438  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 439  *    any link TRBs with the toggle cycle bit set.
 440  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 441  *    if we've moved it past a link TRB with the toggle cycle bit set.
 442  *
 443  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 444  * with correct __le32 accesses they should work fine.  Only users of this are
 445  * in here.
 446  */
 447 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 448                 unsigned int slot_id, unsigned int ep_index,
 449                 unsigned int stream_id, struct xhci_td *cur_td,
 450                 struct xhci_dequeue_state *state)
 451 {
 452         struct xhci_virt_device *dev = xhci->devs[slot_id];
 453         struct xhci_ring *ep_ring;
 454         struct xhci_generic_trb *trb;
 455         struct xhci_ep_ctx *ep_ctx;
 456         dma_addr_t addr;
 457
 458         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 459                         ep_index, stream_id);
 460         if (!ep_ring) {
 461                 xhci_warn(xhci, "WARN can't find new dequeue state "
 462                                 "for invalid stream ID %u.\n",
 463                                 stream_id);
 464                 return;
 465         }
 466         state->new_cycle_state = 0;
 467         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 468         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 469                         dev->eps[ep_index].stopped_trb,
 470                         &state->new_cycle_state);
 471         if (!state->new_deq_seg) {
 472                 WARN_ON(1);
 473                 return;
 474         }
 475
 476         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 477         xhci_dbg(xhci, "Finding endpoint context\n");
 478         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 479         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 480
 481         state->new_deq_ptr = cur_td->last_trb;
 482         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 483         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 484                         state->new_deq_ptr,
 485                         &state->new_cycle_state);
 486         if (!state->new_deq_seg) {
 487                 WARN_ON(1);
 488                 return;
 489         }
 490
 491         trb = &state->new_deq_ptr->generic;
 492         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 493             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 494                 state->new_cycle_state ^= 0x1;
 495         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 496
 497         /*
 498          * If there is only one segment in a ring, find_trb_seg()'s while loop
 499          * will not run, and it will return before it has a chance to see if it
 500          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 501          * ended just before the link TRB on a one-segment ring, or if the TD
 502          * wrapped around the top of the ring, because it doesn't have the TD in
 503          * question.  Look for the one-segment case where stalled TRB's address
 504          * is greater than the new dequeue pointer address.
 505          */
 506         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 507                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 508                 state->new_cycle_state ^= 0x1;
 509         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 510
 511         /* Don't update the ring cycle state for the producer (us). */
 512         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 513                         state->new_deq_seg);
 514         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 515         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 516                         (unsigned long long) addr);
 517 }
 518
 519 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 520  * (The last TRB actually points to the ring enqueue pointer, which is not part
 521  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 522  */
 523 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 524                 struct xhci_td *cur_td, bool flip_cycle)
 525 {
 526         struct xhci_segment *cur_seg;
 527         union xhci_trb *cur_trb;
 528
 529         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 530                         true;
 531                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 532                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 533                         /* Unchain any chained Link TRBs, but
 534                          * leave the pointers intact.
 535                          */
 536                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 537                         /* Flip the cycle bit (link TRBs can't be the first
 538                          * or last TRB).
 539                          */
 540                         if (flip_cycle)
 541                                 cur_trb->generic.field[3] ^=
 542                                         cpu_to_le32(TRB_CYCLE);
 543                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 544                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 545                                         "in seg %p (0x%llx dma)\n",
 546                                         cur_trb,
 547                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 548                                         cur_seg,
 549                                         (unsigned long long)cur_seg->dma);
 550                 } else {
 551                         cur_trb->generic.field[0] = 0;
 552                         cur_trb->generic.field[1] = 0;
 553                         cur_trb->generic.field[2] = 0;
 554                         /* Preserve only the cycle bit of this TRB */
 555                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 556                         /* Flip the cycle bit except on the first or last TRB */
 557                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 558                                         cur_trb != cur_td->last_trb)
 559                                 cur_trb->generic.field[3] ^=
 560                                         cpu_to_le32(TRB_CYCLE);
 561                         cur_trb->generic.field[3] |= cpu_to_le32(
 562                                 TRB_TYPE(TRB_TR_NOOP));
 563                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 564                                         "in seg %p (0x%llx dma)\n",
 565                                         cur_trb,
 566                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 567                                         cur_seg,
 568                                         (unsigned long long)cur_seg->dma);
 569                 }
 570                 if (cur_trb == cur_td->last_trb)
 571                         break;
 572         }
 573 }
 574
 575 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 576                 unsigned int ep_index, unsigned int stream_id,
 577                 struct xhci_segment *deq_seg,
 578                 union xhci_trb *deq_ptr, u32 cycle_state);
 579
 580 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 581                 unsigned int slot_id, unsigned int ep_index,
 582                 unsigned int stream_id,
 583                 struct xhci_dequeue_state *deq_state)
 584 {
 585         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 586
 587         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 588                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 589                         deq_state->new_deq_seg,
 590                         (unsigned long long)deq_state->new_deq_seg->dma,
 591                         deq_state->new_deq_ptr,
 592                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 593                         deq_state->new_cycle_state);
 594         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 595                         deq_state->new_deq_seg,
 596                         deq_state->new_deq_ptr,
 597                         (u32) deq_state->new_cycle_state);
 598         /* Stop the TD queueing code from ringing the doorbell until
 599          * this command completes.  The HC won't set the dequeue pointer
 600          * if the ring is running, and ringing the doorbell starts the
 601          * ring running.
 602          */
 603         ep->ep_state |= SET_DEQ_PENDING;
 604 }
 605
 606 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 607                 struct xhci_virt_ep *ep)
 608 {
 609         ep->ep_state &= ~EP_HALT_PENDING;
 610         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 611          * timer is running on another CPU, we don't decrement stop_cmds_pending
 612          * (since we didn't successfully stop the watchdog timer).
 613          */
 614         if (del_timer(&ep->stop_cmd_timer))
 615                 ep->stop_cmds_pending--;
 616 }
 617
 618 /* Must be called with xhci->lock held in interrupt context */
 619 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 620                 struct xhci_td *cur_td, int status, char *adjective)
 621 {
 622         struct usb_hcd *hcd;
 623         struct urb      *urb;
 624         struct urb_priv *urb_priv;
 625
 626         urb = cur_td->urb;
 627         urb_priv = urb->hcpriv;
 628         urb_priv->td_cnt++;
 629         hcd = bus_to_hcd(urb->dev->bus);
 630
 631         /* Only giveback urb when this is the last td in urb */
 632         if (urb_priv->td_cnt == urb_priv->length) {
 633                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 634                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 635                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 636                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 637                                         usb_amd_quirk_pll_enable();
 638                         }
 639                 }
 640                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 641
 642                 spin_unlock(&xhci->lock);
 643                 usb_hcd_giveback_urb(hcd, urb, status);
 644                 xhci_urb_free_priv(xhci, urb_priv);
 645                 spin_lock(&xhci->lock);
 646         }
 647 }
 648
 649 /*
 650  * When we get a command completion for a Stop Endpoint Command, we need to
 651  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 652  *
 653  *  1. If the HW was in the middle of processing the TD that needs to be
 654  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 655  *     in the TD with a Set Dequeue Pointer Command.
 656  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 657  *     bit cleared) so that the HW will skip over them.
 658  */
 659 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 660                 union xhci_trb *trb, struct xhci_event_cmd *event)
 661 {
 662         unsigned int slot_id;
 663         unsigned int ep_index;
 664         struct xhci_virt_device *virt_dev;
 665         struct xhci_ring *ep_ring;
 666         struct xhci_virt_ep *ep;
 667         struct list_head *entry;
 668         struct xhci_td *cur_td = NULL;
 669         struct xhci_td *last_unlinked_td;
 670
 671         struct xhci_dequeue_state deq_state;
 672
 673         if (unlikely(TRB_TO_SUSPEND_PORT(
 674                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 675                 slot_id = TRB_TO_SLOT_ID(
 676                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 677                 virt_dev = xhci->devs[slot_id];
 678                 if (virt_dev)
 679                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 680                                 event);
 681                 else
 682                         xhci_warn(xhci, "Stop endpoint command "
 683                                 "completion for disabled slot %u\n",
 684                                 slot_id);
 685                 return;
 686         }
 687
 688         memset(&deq_state, 0, sizeof(deq_state));
 689         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 690         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 691         ep = &xhci->devs[slot_id]->eps[ep_index];
 692
 693         if (list_empty(&ep->cancelled_td_list)) {
 694                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 695                 ep->stopped_td = NULL;
 696                 ep->stopped_trb = NULL;
 697                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 698                 return;
 699         }
 700
 701         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 702          * We have the xHCI lock, so nothing can modify this list until we drop
 703          * it.  We're also in the event handler, so we can't get re-interrupted
 704          * if another Stop Endpoint command completes
 705          */
 706         list_for_each(entry, &ep->cancelled_td_list) {
 707                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 708                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 709                                 cur_td->first_trb,
 710                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 711                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 712                 if (!ep_ring) {
 713                         /* This shouldn't happen unless a driver is mucking
 714                          * with the stream ID after submission.  This will
 715                          * leave the TD on the hardware ring, and the hardware
 716                          * will try to execute it, and may access a buffer
 717                          * that has already been freed.  In the best case, the
 718                          * hardware will execute it, and the event handler will
 719                          * ignore the completion event for that TD, since it was
 720                          * removed from the td_list for that endpoint.  In
 721                          * short, don't muck with the stream ID after
 722                          * submission.
 723                          */
 724                         xhci_warn(xhci, "WARN Cancelled URB %p "
 725                                         "has invalid stream ID %u.\n",
 726                                         cur_td->urb,
 727                                         cur_td->urb->stream_id);
 728                         goto remove_finished_td;
 729                 }
 730                 /*
 731                  * If we stopped on the TD we need to cancel, then we have to
 732                  * move the xHC endpoint ring dequeue pointer past this TD.
 733                  */
 734                 if (cur_td == ep->stopped_td)
 735                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 736                                         cur_td->urb->stream_id,
 737                                         cur_td, &deq_state);
 738                 else
 739                         td_to_noop(xhci, ep_ring, cur_td, false);
 740 remove_finished_td:
 741                 /*
 742                  * The event handler won't see a completion for this TD anymore,
 743                  * so remove it from the endpoint ring's TD list.  Keep it in
 744                  * the cancelled TD list for URB completion later.
 745                  */
 746                 list_del_init(&cur_td->td_list);
 747         }
 748         last_unlinked_td = cur_td;
 749         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 750
 751         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 752         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 753                 xhci_queue_new_dequeue_state(xhci,
 754                                 slot_id, ep_index,
 755                                 ep->stopped_td->urb->stream_id,
 756                                 &deq_state);
 757                 xhci_ring_cmd_db(xhci);
 758         } else {
 759                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 760                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 761         }
 762         ep->stopped_td = NULL;
 763         ep->stopped_trb = NULL;
 764
 765         /*
 766          * Drop the lock and complete the URBs in the cancelled TD list.
 767          * New TDs to be cancelled might be added to the end of the list before
 768          * we can complete all the URBs for the TDs we already unlinked.
 769          * So stop when we've completed the URB for the last TD we unlinked.
 770          */
 771         do {
 772                 cur_td = list_entry(ep->cancelled_td_list.next,
 773                                 struct xhci_td, cancelled_td_list);
 774                 list_del_init(&cur_td->cancelled_td_list);
 775
 776                 /* Clean up the cancelled URB */
 777                 /* Doesn't matter what we pass for status, since the core will
 778                  * just overwrite it (because the URB has been unlinked).
 779                  */
 780                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 781
 782                 /* Stop processing the cancelled list if the watchdog timer is
 783                  * running.
 784                  */
 785                 if (xhci->xhc_state & XHCI_STATE_DYING)
 786                         return;
 787         } while (cur_td != last_unlinked_td);
 788
 789         /* Return to the event handler with xhci->lock re-acquired */
 790 }
 791
 792 /* Watchdog timer function for when a stop endpoint command fails to complete.
 793  * In this case, we assume the host controller is broken or dying or dead.  The
 794  * host may still be completing some other events, so we have to be careful to
 795  * let the event ring handler and the URB dequeueing/enqueueing functions know
 796  * through xhci->state.
 797  *
 798  * The timer may also fire if the host takes a very long time to respond to the
 799  * command, and the stop endpoint command completion handler cannot delete the
 800  * timer before the timer function is called.  Another endpoint cancellation may
 801  * sneak in before the timer function can grab the lock, and that may queue
 802  * another stop endpoint command and add the timer back.  So we cannot use a
 803  * simple flag to say whether there is a pending stop endpoint command for a
 804  * particular endpoint.
 805  *
 806  * Instead we use a combination of that flag and a counter for the number of
 807  * pending stop endpoint commands.  If the timer is the tail end of the last
 808  * stop endpoint command, and the endpoint's command is still pending, we assume
 809  * the host is dying.
 810  */
 811 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 812 {
 813         struct xhci_hcd *xhci;
 814         struct xhci_virt_ep *ep;
 815         struct xhci_virt_ep *temp_ep;
 816         struct xhci_ring *ring;
 817         struct xhci_td *cur_td;
 818         int ret, i, j;
 819         unsigned long flags;
 820
 821         ep = (struct xhci_virt_ep *) arg;
 822         xhci = ep->xhci;
 823
 824         spin_lock_irqsave(&xhci->lock, flags);
 825
 826         ep->stop_cmds_pending--;
 827         if (xhci->xhc_state & XHCI_STATE_DYING) {
 828                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 829                                 "xHCI as DYING, exiting.\n");
 830                 spin_unlock_irqrestore(&xhci->lock, flags);
 831                 return;
 832         }
 833         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 834                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 835                                 "exiting.\n");
 836                 spin_unlock_irqrestore(&xhci->lock, flags);
 837                 return;
 838         }
 839
 840         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 841         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 842         /* Oops, HC is dead or dying or at least not responding to the stop
 843          * endpoint command.
 844          */
 845         xhci->xhc_state |= XHCI_STATE_DYING;
 846         /* Disable interrupts from the host controller and start halting it */
 847         xhci_quiesce(xhci);
 848         spin_unlock_irqrestore(&xhci->lock, flags);
 849
 850         ret = xhci_halt(xhci);
 851
 852         spin_lock_irqsave(&xhci->lock, flags);
 853         if (ret < 0) {
 854                 /* This is bad; the host is not responding to commands and it's
 855                  * not allowing itself to be halted.  At least interrupts are
 856                  * disabled. If we call usb_hc_died(), it will attempt to
 857                  * disconnect all device drivers under this host.  Those
 858                  * disconnect() methods will wait for all URBs to be unlinked,
 859                  * so we must complete them.
 860                  */
 861                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 862                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 863                 /* We could turn all TDs on the rings to no-ops.  This won't
 864                  * help if the host has cached part of the ring, and is slow if
 865                  * we want to preserve the cycle bit.  Skip it and hope the host
 866                  * doesn't touch the memory.
 867                  */
 868         }
 869         for (i = 0; i < MAX_HC_SLOTS; i++) {
 870                 if (!xhci->devs[i])
 871                         continue;
 872                 for (j = 0; j < 31; j++) {
 873                         temp_ep = &xhci->devs[i]->eps[j];
 874                         ring = temp_ep->ring;
 875                         if (!ring)
 876                                 continue;
 877                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 878                                         "ep index %u\n", i, j);
 879                         while (!list_empty(&ring->td_list)) {
 880                                 cur_td = list_first_entry(&ring->td_list,
 881                                                 struct xhci_td,
 882                                                 td_list);
 883                                 list_del_init(&cur_td->td_list);
 884                                 if (!list_empty(&cur_td->cancelled_td_list))
 885                                         list_del_init(&cur_td->cancelled_td_list);
 886                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 887                                                 -ESHUTDOWN, "killed");
 888                         }
 889                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 890                                 cur_td = list_first_entry(
 891                                                 &temp_ep->cancelled_td_list,
 892                                                 struct xhci_td,
 893                                                 cancelled_td_list);
 894                                 list_del_init(&cur_td->cancelled_td_list);
 895                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 896                                                 -ESHUTDOWN, "killed");
 897                         }
 898                 }
 899         }
 900         spin_unlock_irqrestore(&xhci->lock, flags);
 901         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 902         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 903         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 904 }
 905
 906 /*
 907  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 908  * we need to clear the set deq pending flag in the endpoint ring state, so that
 909  * the TD queueing code can ring the doorbell again.  We also need to ring the
 910  * endpoint doorbell to restart the ring, but only if there aren't more
 911  * cancellations pending.
 912  */
 913 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 914                 struct xhci_event_cmd *event,
 915                 union xhci_trb *trb)
 916 {
 917         unsigned int slot_id;
 918         unsigned int ep_index;
 919         unsigned int stream_id;
 920         struct xhci_ring *ep_ring;
 921         struct xhci_virt_device *dev;
 922         struct xhci_ep_ctx *ep_ctx;
 923         struct xhci_slot_ctx *slot_ctx;
 924
 925         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 926         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 927         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 928         dev = xhci->devs[slot_id];
 929
 930         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 931         if (!ep_ring) {
 932                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 933                                 "freed stream ID %u\n",
 934                                 stream_id);
 935                 /* XXX: Harmless??? */
 936                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 937                 return;
 938         }
 939
 940         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 941         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 942
 943         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 944                 unsigned int ep_state;
 945                 unsigned int slot_state;
 946
 947                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 948                 case COMP_TRB_ERR:
 949                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 950                                         "of stream ID configuration\n");
 951                         break;
 952                 case COMP_CTX_STATE:
 953                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 954                                         "to incorrect slot or ep state.\n");
 955                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 956                         ep_state &= EP_STATE_MASK;
 957                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 958                         slot_state = GET_SLOT_STATE(slot_state);
 959                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 960                                         slot_state, ep_state);
 961                         break;
 962                 case COMP_EBADSLT:
 963                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 964                                         "slot %u was not enabled.\n", slot_id);
 965                         break;
 966                 default:
 967                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 968                                         "completion code of %u.\n",
 969                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 970                         break;
 971                 }
 972                 /* OK what do we do now?  The endpoint state is hosed, and we
 973                  * should never get to this point if the synchronization between
 974                  * queueing, and endpoint state are correct.  This might happen
 975                  * if the device gets disconnected after we've finished
 976                  * cancelling URBs, which might not be an error...
 977                  */
 978         } else {
 979                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 980                          le64_to_cpu(ep_ctx->deq));
 981                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 982                                          dev->eps[ep_index].queued_deq_ptr) ==
 983                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 984                         /* Update the ring's dequeue segment and dequeue pointer
 985                          * to reflect the new position.
 986                          */
 987                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 988                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 989                 } else {
 990                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 991                                         "Ptr command & xHCI internal state.\n");
 992                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 993                                         dev->eps[ep_index].queued_deq_seg,
 994                                         dev->eps[ep_index].queued_deq_ptr);
 995                 }
 996         }
 997
 998         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 999         dev->eps[ep_index].queued_deq_seg = NULL;
1000         dev->eps[ep_index].queued_deq_ptr = NULL;
1001         /* Restart any rings with pending URBs */
1002         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1003 }
1004
1005 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1006                 struct xhci_event_cmd *event,
1007                 union xhci_trb *trb)
1008 {
1009         int slot_id;
1010         unsigned int ep_index;
1011
1012         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1013         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1014         /* This command will only fail if the endpoint wasn't halted,
1015          * but we don't care.
1016          */
1017         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1018                  GET_COMP_CODE(le32_to_cpu(event->status)));
1019
1020         /* HW with the reset endpoint quirk needs to have a configure endpoint
1021          * command complete before the endpoint can be used.  Queue that here
1022          * because the HW can't handle two commands being queued in a row.
1023          */
1024         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1025                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1026                 xhci_queue_configure_endpoint(xhci,
1027                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1028                                 false);
1029                 xhci_ring_cmd_db(xhci);
1030         } else {
1031                 /* Clear our internal halted state and restart the ring(s) */
1032                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1033                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1034         }
1035 }
1036
1037 /* Check to see if a command in the device's command queue matches this one.
1038  * Signal the completion or free the command, and return 1.  Return 0 if the
1039  * completed command isn't at the head of the command list.
1040  */
1041 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1042                 struct xhci_virt_device *virt_dev,
1043                 struct xhci_event_cmd *event)
1044 {
1045         struct xhci_command *command;
1046
1047         if (list_empty(&virt_dev->cmd_list))
1048                 return 0;
1049
1050         command = list_entry(virt_dev->cmd_list.next,
1051                         struct xhci_command, cmd_list);
1052         if (xhci->cmd_ring->dequeue != command->command_trb)
1053                 return 0;
1054
1055         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1056         list_del(&command->cmd_list);
1057         if (command->completion)
1058                 complete(command->completion);
1059         else
1060                 xhci_free_command(xhci, command);
1061         return 1;
1062 }
1063
1064 static void handle_cmd_completion(struct xhci_hcd *xhci,
1065                 struct xhci_event_cmd *event)
1066 {
1067         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1068         u64 cmd_dma;
1069         dma_addr_t cmd_dequeue_dma;
1070         struct xhci_input_control_ctx *ctrl_ctx;
1071         struct xhci_virt_device *virt_dev;
1072         unsigned int ep_index;
1073         struct xhci_ring *ep_ring;
1074         unsigned int ep_state;
1075
1076         cmd_dma = le64_to_cpu(event->cmd_trb);
1077         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1078                         xhci->cmd_ring->dequeue);
1079         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1080         if (cmd_dequeue_dma == 0) {
1081                 xhci->error_bitmask |= 1 << 4;
1082                 return;
1083         }
1084         /* Does the DMA address match our internal dequeue pointer address? */
1085         if (cmd_dma != (u64) cmd_dequeue_dma) {
1086                 xhci->error_bitmask |= 1 << 5;
1087                 return;
1088         }
1089         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1090                 & TRB_TYPE_BITMASK) {
1091         case TRB_TYPE(TRB_ENABLE_SLOT):
1092                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1093                         xhci->slot_id = slot_id;
1094                 else
1095                         xhci->slot_id = 0;
1096                 complete(&xhci->addr_dev);
1097                 break;
1098         case TRB_TYPE(TRB_DISABLE_SLOT):
1099                 if (xhci->devs[slot_id]) {
1100                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1101                                 /* Delete default control endpoint resources */
1102                                 xhci_free_device_endpoint_resources(xhci,
1103                                                 xhci->devs[slot_id], true);
1104                         xhci_free_virt_device(xhci, slot_id);
1105                 }
1106                 break;
1107         case TRB_TYPE(TRB_CONFIG_EP):
1108                 virt_dev = xhci->devs[slot_id];
1109                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1110                         break;
1111                 /*
1112                  * Configure endpoint commands can come from the USB core
1113                  * configuration or alt setting changes, or because the HW
1114                  * needed an extra configure endpoint command after a reset
1115                  * endpoint command or streams were being configured.
1116                  * If the command was for a halted endpoint, the xHCI driver
1117                  * is not waiting on the configure endpoint command.
1118                  */
1119                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1120                                 virt_dev->in_ctx);
1121                 /* Input ctx add_flags are the endpoint index plus one */
1122                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1123                 /* A usb_set_interface() call directly after clearing a halted
1124                  * condition may race on this quirky hardware.  Not worth
1125                  * worrying about, since this is prototype hardware.  Not sure
1126                  * if this will work for streams, but streams support was
1127                  * untested on this prototype.
1128                  */
1129                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1130                                 ep_index != (unsigned int) -1 &&
1131                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1132                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1133                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1134                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1135                         if (!(ep_state & EP_HALTED))
1136                                 goto bandwidth_change;
1137                         xhci_dbg(xhci, "Completed config ep cmd - "
1138                                         "last ep index = %d, state = %d\n",
1139                                         ep_index, ep_state);
1140                         /* Clear internal halted state and restart ring(s) */
1141                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1142                                 ~EP_HALTED;
1143                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1144                         break;
1145                 }
1146 bandwidth_change:
1147                 xhci_dbg(xhci, "Completed config ep cmd\n");
1148                 xhci->devs[slot_id]->cmd_status =
1149                         GET_COMP_CODE(le32_to_cpu(event->status));
1150                 complete(&xhci->devs[slot_id]->cmd_completion);
1151                 break;
1152         case TRB_TYPE(TRB_EVAL_CONTEXT):
1153                 virt_dev = xhci->devs[slot_id];
1154                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1155                         break;
1156                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1157                 complete(&xhci->devs[slot_id]->cmd_completion);
1158                 break;
1159         case TRB_TYPE(TRB_ADDR_DEV):
1160                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1161                 complete(&xhci->addr_dev);
1162                 break;
1163         case TRB_TYPE(TRB_STOP_RING):
1164                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1165                 break;
1166         case TRB_TYPE(TRB_SET_DEQ):
1167                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1168                 break;
1169         case TRB_TYPE(TRB_CMD_NOOP):
1170                 break;
1171         case TRB_TYPE(TRB_RESET_EP):
1172                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1173                 break;
1174         case TRB_TYPE(TRB_RESET_DEV):
1175                 xhci_dbg(xhci, "Completed reset device command.\n");
1176                 slot_id = TRB_TO_SLOT_ID(
1177                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1178                 virt_dev = xhci->devs[slot_id];
1179                 if (virt_dev)
1180                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1181                 else
1182                         xhci_warn(xhci, "Reset device command completion "
1183                                         "for disabled slot %u\n", slot_id);
1184                 break;
1185         case TRB_TYPE(TRB_NEC_GET_FW):
1186                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1187                         xhci->error_bitmask |= 1 << 6;
1188                         break;
1189                 }
1190                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1191                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1192                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1193                 break;
1194         default:
1195                 /* Skip over unknown commands on the event ring */
1196                 xhci->error_bitmask |= 1 << 6;
1197                 break;
1198         }
1199         inc_deq(xhci, xhci->cmd_ring, false);
1200 }
1201
1202 static void handle_vendor_event(struct xhci_hcd *xhci,
1203                 union xhci_trb *event)
1204 {
1205         u32 trb_type;
1206
1207         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1208         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1209         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1210                 handle_cmd_completion(xhci, &event->event_cmd);
1211 }
1212
1213 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1214  * port registers -- USB 3.0 and USB 2.0).
1215  *
1216  * Returns a zero-based port number, which is suitable for indexing into each of
1217  * the split roothubs' port arrays and bus state arrays.
1218  * Add one to it in order to call xhci_find_slot_id_by_port.
1219  */
1220 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1221                 struct xhci_hcd *xhci, u32 port_id)
1222 {
1223         unsigned int i;
1224         unsigned int num_similar_speed_ports = 0;
1225
1226         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1227          * and usb2_ports are 0-based indexes.  Count the number of similar
1228          * speed ports, up to 1 port before this port.
1229          */
1230         for (i = 0; i < (port_id - 1); i++) {
1231                 u8 port_speed = xhci->port_array[i];
1232
1233                 /*
1234                  * Skip ports that don't have known speeds, or have duplicate
1235                  * Extended Capabilities port speed entries.
1236                  */
1237                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1238                         continue;
1239
1240                 /*
1241                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1242                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1243                  * matches the device speed, it's a similar speed port.
1244                  */
1245                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1246                         num_similar_speed_ports++;
1247         }
1248         return num_similar_speed_ports;
1249 }
1250
1251 static void handle_port_status(struct xhci_hcd *xhci,
1252                 union xhci_trb *event)
1253 {
1254         struct usb_hcd *hcd;
1255         u32 port_id;
1256         u32 temp, temp1;
1257         int max_ports;
1258         int slot_id;
1259         unsigned int faked_port_index;
1260         u8 major_revision;
1261         struct xhci_bus_state *bus_state;
1262         __le32 __iomem **port_array;
1263         bool bogus_port_status = false;
1264
1265         /* Port status change events always have a successful completion code */
1266         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1267                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1268                 xhci->error_bitmask |= 1 << 8;
1269         }
1270         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1271         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1272
1273         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1274         if ((port_id <= 0) || (port_id > max_ports)) {
1275                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1276                 bogus_port_status = true;
1277                 goto cleanup;
1278         }
1279
1280         /* Figure out which usb_hcd this port is attached to:
1281          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1282          */
1283         major_revision = xhci->port_array[port_id - 1];
1284         if (major_revision == 0) {
1285                 xhci_warn(xhci, "Event for port %u not in "
1286                                 "Extended Capabilities, ignoring.\n",
1287                                 port_id);
1288                 bogus_port_status = true;
1289                 goto cleanup;
1290         }
1291         if (major_revision == DUPLICATE_ENTRY) {
1292                 xhci_warn(xhci, "Event for port %u duplicated in"
1293                                 "Extended Capabilities, ignoring.\n",
1294                                 port_id);
1295                 bogus_port_status = true;
1296                 goto cleanup;
1297         }
1298
1299         /*
1300          * Hardware port IDs reported by a Port Status Change Event include USB
1301          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1302          * resume event, but we first need to translate the hardware port ID
1303          * into the index into the ports on the correct split roothub, and the
1304          * correct bus_state structure.
1305          */
1306         /* Find the right roothub. */
1307         hcd = xhci_to_hcd(xhci);
1308         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1309                 hcd = xhci->shared_hcd;
1310         bus_state = &xhci->bus_state[hcd_index(hcd)];
1311         if (hcd->speed == HCD_USB3)
1312                 port_array = xhci->usb3_ports;
1313         else
1314                 port_array = xhci->usb2_ports;
1315         /* Find the faked port hub number */
1316         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1317                         port_id);
1318
1319         temp = xhci_readl(xhci, port_array[faked_port_index]);
1320         if (hcd->state == HC_STATE_SUSPENDED) {
1321                 xhci_dbg(xhci, "resume root hub\n");
1322                 usb_hcd_resume_root_hub(hcd);
1323         }
1324
1325         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1326                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1327
1328                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1329                 if (!(temp1 & CMD_RUN)) {
1330                         xhci_warn(xhci, "xHC is not running.\n");
1331                         goto cleanup;
1332                 }
1333
1334                 if (DEV_SUPERSPEED(temp)) {
1335                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1336                         xhci_set_link_state(xhci, port_array, faked_port_index,
1337                                                 XDEV_U0);
1338                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1339                                         faked_port_index + 1);
1340                         if (!slot_id) {
1341                                 xhci_dbg(xhci, "slot_id is zero\n");
1342                                 goto cleanup;
1343                         }
1344                         xhci_ring_device(xhci, slot_id);
1345                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1346                         /* Clear PORT_PLC */
1347                         xhci_test_and_clear_bit(xhci, port_array,
1348                                                 faked_port_index, PORT_PLC);
1349                 } else {
1350                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1351                         bus_state->resume_done[faked_port_index] = jiffies +
1352                                 msecs_to_jiffies(20);
1353                         mod_timer(&hcd->rh_timer,
1354                                   bus_state->resume_done[faked_port_index]);
1355                         /* Do the rest in GetPortStatus */
1356                 }
1357         }
1358
1359         if (hcd->speed != HCD_USB3)
1360                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1361                                         PORT_PLC);
1362
1363 cleanup:
1364         /* Update event ring dequeue pointer before dropping the lock */
1365         inc_deq(xhci, xhci->event_ring, true);
1366
1367         /* Don't make the USB core poll the roothub if we got a bad port status
1368          * change event.  Besides, at that point we can't tell which roothub
1369          * (USB 2.0 or USB 3.0) to kick.
1370          */
1371         if (bogus_port_status)
1372                 return;
1373
1374         spin_unlock(&xhci->lock);
1375         /* Pass this up to the core */
1376         usb_hcd_poll_rh_status(hcd);
1377         spin_lock(&xhci->lock);
1378 }
1379
1380 /*
1381  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1382  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1383  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1384  * returns 0.
1385  */
1386 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1387                 union xhci_trb  *start_trb,
1388                 union xhci_trb  *end_trb,
1389                 dma_addr_t      suspect_dma)
1390 {
1391         dma_addr_t start_dma;
1392         dma_addr_t end_seg_dma;
1393         dma_addr_t end_trb_dma;
1394         struct xhci_segment *cur_seg;
1395
1396         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1397         cur_seg = start_seg;
1398
1399         do {
1400                 if (start_dma == 0)
1401                         return NULL;
1402                 /* We may get an event for a Link TRB in the middle of a TD */
1403                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1404                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1405                 /* If the end TRB isn't in this segment, this is set to 0 */
1406                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1407
1408                 if (end_trb_dma > 0) {
1409                         /* The end TRB is in this segment, so suspect should be here */
1410                         if (start_dma <= end_trb_dma) {
1411                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1412                                         return cur_seg;
1413                         } else {
1414                                 /* Case for one segment with
1415                                  * a TD wrapped around to the top
1416                                  */
1417                                 if ((suspect_dma >= start_dma &&
1418                                                         suspect_dma <= end_seg_dma) ||
1419                                                 (suspect_dma >= cur_seg->dma &&
1420                                                  suspect_dma <= end_trb_dma))
1421                                         return cur_seg;
1422                         }
1423                         return NULL;
1424                 } else {
1425                         /* Might still be somewhere in this segment */
1426                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1427                                 return cur_seg;
1428                 }
1429                 cur_seg = cur_seg->next;
1430                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1431         } while (cur_seg != start_seg);
1432
1433         return NULL;
1434 }
1435
1436 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1437                 unsigned int slot_id, unsigned int ep_index,
1438                 unsigned int stream_id,
1439                 struct xhci_td *td, union xhci_trb *event_trb)
1440 {
1441         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1442         ep->ep_state |= EP_HALTED;
1443         ep->stopped_td = td;
1444         ep->stopped_trb = event_trb;
1445         ep->stopped_stream = stream_id;
1446
1447         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1448         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1449
1450         ep->stopped_td = NULL;
1451         ep->stopped_trb = NULL;
1452         ep->stopped_stream = 0;
1453
1454         xhci_ring_cmd_db(xhci);
1455 }
1456
1457 /* Check if an error has halted the endpoint ring.  The class driver will
1458  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1459  * However, a babble and other errors also halt the endpoint ring, and the class
1460  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1461  * Ring Dequeue Pointer command manually.
1462  */
1463 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1464                 struct xhci_ep_ctx *ep_ctx,
1465                 unsigned int trb_comp_code)
1466 {
1467         /* TRB completion codes that may require a manual halt cleanup */
1468         if (trb_comp_code == COMP_TX_ERR ||
1469                         trb_comp_code == COMP_BABBLE ||
1470                         trb_comp_code == COMP_SPLIT_ERR)
1471                 /* The 0.96 spec says a babbling control endpoint
1472                  * is not halted. The 0.96 spec says it is.  Some HW
1473                  * claims to be 0.95 compliant, but it halts the control
1474                  * endpoint anyway.  Check if a babble halted the
1475                  * endpoint.
1476                  */
1477                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1478                     cpu_to_le32(EP_STATE_HALTED))
1479                         return 1;
1480
1481         return 0;
1482 }
1483
1484 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1485 {
1486         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1487                 /* Vendor defined "informational" completion code,
1488                  * treat as not-an-error.
1489                  */
1490                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1491                                 trb_comp_code);
1492                 xhci_dbg(xhci, "Treating code as success.\n");
1493                 return 1;
1494         }
1495         return 0;
1496 }
1497
1498 /*
1499  * Finish the td processing, remove the td from td list;
1500  * Return 1 if the urb can be given back.
1501  */
1502 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1503         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1504         struct xhci_virt_ep *ep, int *status, bool skip)
1505 {
1506         struct xhci_virt_device *xdev;
1507         struct xhci_ring *ep_ring;
1508         unsigned int slot_id;
1509         int ep_index;
1510         struct urb *urb = NULL;
1511         struct xhci_ep_ctx *ep_ctx;
1512         int ret = 0;
1513         struct urb_priv *urb_priv;
1514         u32 trb_comp_code;
1515
1516         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1517         xdev = xhci->devs[slot_id];
1518         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1519         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1520         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1521         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1522
1523         if (skip)
1524                 goto td_cleanup;
1525
1526         if (trb_comp_code == COMP_STOP_INVAL ||
1527                         trb_comp_code == COMP_STOP) {
1528                 /* The Endpoint Stop Command completion will take care of any
1529                  * stopped TDs.  A stopped TD may be restarted, so don't update
1530                  * the ring dequeue pointer or take this TD off any lists yet.
1531                  */
1532                 ep->stopped_td = td;
1533                 ep->stopped_trb = event_trb;
1534                 return 0;
1535         } else {
1536                 if (trb_comp_code == COMP_STALL) {
1537                         /* The transfer is completed from the driver's
1538                          * perspective, but we need to issue a set dequeue
1539                          * command for this stalled endpoint to move the dequeue
1540                          * pointer past the TD.  We can't do that here because
1541                          * the halt condition must be cleared first.  Let the
1542                          * USB class driver clear the stall later.
1543                          */
1544                         ep->stopped_td = td;
1545                         ep->stopped_trb = event_trb;
1546                         ep->stopped_stream = ep_ring->stream_id;
1547                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1548                                         ep_ctx, trb_comp_code)) {
1549                         /* Other types of errors halt the endpoint, but the
1550                          * class driver doesn't call usb_reset_endpoint() unless
1551                          * the error is -EPIPE.  Clear the halted status in the
1552                          * xHCI hardware manually.
1553                          */
1554                         xhci_cleanup_halted_endpoint(xhci,
1555                                         slot_id, ep_index, ep_ring->stream_id,
1556                                         td, event_trb);
1557                 } else {
1558                         /* Update ring dequeue pointer */
1559                         while (ep_ring->dequeue != td->last_trb)
1560                                 inc_deq(xhci, ep_ring, false);
1561                         inc_deq(xhci, ep_ring, false);
1562                 }
1563
1564 td_cleanup:
1565                 /* Clean up the endpoint's TD list */
1566                 urb = td->urb;
1567                 urb_priv = urb->hcpriv;
1568
1569                 /* Do one last check of the actual transfer length.
1570                  * If the host controller said we transferred more data than
1571                  * the buffer length, urb->actual_length will be a very big
1572                  * number (since it's unsigned).  Play it safe and say we didn't
1573                  * transfer anything.
1574                  */
1575                 if (urb->actual_length > urb->transfer_buffer_length) {
1576                         xhci_warn(xhci, "URB transfer length is wrong, "
1577                                         "xHC issue? req. len = %u, "
1578                                         "act. len = %u\n",
1579                                         urb->transfer_buffer_length,
1580                                         urb->actual_length);
1581                         urb->actual_length = 0;
1582                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1583                                 *status = -EREMOTEIO;
1584                         else
1585                                 *status = 0;
1586                 }
1587                 list_del_init(&td->td_list);
1588                 /* Was this TD slated to be cancelled but completed anyway? */
1589                 if (!list_empty(&td->cancelled_td_list))
1590                         list_del_init(&td->cancelled_td_list);
1591
1592                 urb_priv->td_cnt++;
1593                 /* Giveback the urb when all the tds are completed */
1594                 if (urb_priv->td_cnt == urb_priv->length) {
1595                         ret = 1;
1596                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1597                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1598                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1599                                         == 0) {
1600                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1601                                                 usb_amd_quirk_pll_enable();
1602                                 }
1603                         }
1604                 }
1605         }
1606
1607         return ret;
1608 }
1609
1610 /*
1611  * Process control tds, update urb status and actual_length.
1612  */
1613 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1614         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1615         struct xhci_virt_ep *ep, int *status)
1616 {
1617         struct xhci_virt_device *xdev;
1618         struct xhci_ring *ep_ring;
1619         unsigned int slot_id;
1620         int ep_index;
1621         struct xhci_ep_ctx *ep_ctx;
1622         u32 trb_comp_code;
1623
1624         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1625         xdev = xhci->devs[slot_id];
1626         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1627         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1628         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1629         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1630
1631         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1632         switch (trb_comp_code) {
1633         case COMP_SUCCESS:
1634                 if (event_trb == ep_ring->dequeue) {
1635                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1636                                         "without IOC set??\n");
1637                         *status = -ESHUTDOWN;
1638                 } else if (event_trb != td->last_trb) {
1639                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1640                                         "without IOC set??\n");
1641                         *status = -ESHUTDOWN;
1642                 } else {
1643                         *status = 0;
1644                 }
1645                 break;
1646         case COMP_SHORT_TX:
1647                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1648                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1649                         *status = -EREMOTEIO;
1650                 else
1651                         *status = 0;
1652                 break;
1653         case COMP_STOP_INVAL:
1654         case COMP_STOP:
1655                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1656         default:
1657                 if (!xhci_requires_manual_halt_cleanup(xhci,
1658                                         ep_ctx, trb_comp_code))
1659                         break;
1660                 xhci_dbg(xhci, "TRB error code %u, "
1661                                 "halted endpoint index = %u\n",
1662                                 trb_comp_code, ep_index);
1663                 /* else fall through */
1664         case COMP_STALL:
1665                 /* Did we transfer part of the data (middle) phase? */
1666                 if (event_trb != ep_ring->dequeue &&
1667                                 event_trb != td->last_trb)
1668                         td->urb->actual_length =
1669                                 td->urb->transfer_buffer_length
1670                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1671                 else
1672                         td->urb->actual_length = 0;
1673
1674                 xhci_cleanup_halted_endpoint(xhci,
1675                         slot_id, ep_index, 0, td, event_trb);
1676                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1677         }
1678         /*
1679          * Did we transfer any data, despite the errors that might have
1680          * happened?  I.e. did we get past the setup stage?
1681          */
1682         if (event_trb != ep_ring->dequeue) {
1683                 /* The event was for the status stage */
1684                 if (event_trb == td->last_trb) {
1685                         if (td->urb->actual_length != 0) {
1686                                 /* Don't overwrite a previously set error code
1687                                  */
1688                                 if ((*status == -EINPROGRESS || *status == 0) &&
1689                                                 (td->urb->transfer_flags
1690                                                  & URB_SHORT_NOT_OK))
1691                                         /* Did we already see a short data
1692                                          * stage? */
1693                                         *status = -EREMOTEIO;
1694                         } else {
1695                                 td->urb->actual_length =
1696                                         td->urb->transfer_buffer_length;
1697                         }
1698                 } else {
1699                 /* Maybe the event was for the data stage? */
1700                         td->urb->actual_length =
1701                                 td->urb->transfer_buffer_length -
1702                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1703                         xhci_dbg(xhci, "Waiting for status "
1704                                         "stage event\n");
1705                         return 0;
1706                 }
1707         }
1708
1709         return finish_td(xhci, td, event_trb, event, ep, status, false);
1710 }
1711
1712 /*
1713  * Process isochronous tds, update urb packet status and actual_length.
1714  */
1715 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1716         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1717         struct xhci_virt_ep *ep, int *status)
1718 {
1719         struct xhci_ring *ep_ring;
1720         struct urb_priv *urb_priv;
1721         int idx;
1722         int len = 0;
1723         union xhci_trb *cur_trb;
1724         struct xhci_segment *cur_seg;
1725         struct usb_iso_packet_descriptor *frame;
1726         u32 trb_comp_code;
1727         bool skip_td = false;
1728
1729         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1730         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1731         urb_priv = td->urb->hcpriv;
1732         idx = urb_priv->td_cnt;
1733         frame = &td->urb->iso_frame_desc[idx];
1734
1735         /* handle completion code */
1736         switch (trb_comp_code) {
1737         case COMP_SUCCESS:
1738                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
1739                         frame->status = 0;
1740                         break;
1741                 }
1742                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1743                         trb_comp_code = COMP_SHORT_TX;
1744         case COMP_SHORT_TX:
1745                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1746                                 -EREMOTEIO : 0;
1747                 break;
1748         case COMP_BW_OVER:
1749                 frame->status = -ECOMM;
1750                 skip_td = true;
1751                 break;
1752         case COMP_BUFF_OVER:
1753         case COMP_BABBLE:
1754                 frame->status = -EOVERFLOW;
1755                 skip_td = true;
1756                 break;
1757         case COMP_DEV_ERR:
1758         case COMP_STALL:
1759         case COMP_TX_ERR:
1760                 frame->status = -EPROTO;
1761                 skip_td = true;
1762                 break;
1763         case COMP_STOP:
1764         case COMP_STOP_INVAL:
1765                 break;
1766         default:
1767                 frame->status = -1;
1768                 break;
1769         }
1770
1771         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1772                 frame->actual_length = frame->length;
1773                 td->urb->actual_length += frame->length;
1774         } else {
1775                 for (cur_trb = ep_ring->dequeue,
1776                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1777                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1778                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1779                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1780                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1781                 }
1782                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1783                         TRB_LEN(le32_to_cpu(event->transfer_len));
1784
1785                 if (trb_comp_code != COMP_STOP_INVAL) {
1786                         frame->actual_length = len;
1787                         td->urb->actual_length += len;
1788                 }
1789         }
1790
1791         return finish_td(xhci, td, event_trb, event, ep, status, false);
1792 }
1793
1794 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1795                         struct xhci_transfer_event *event,
1796                         struct xhci_virt_ep *ep, int *status)
1797 {
1798         struct xhci_ring *ep_ring;
1799         struct urb_priv *urb_priv;
1800         struct usb_iso_packet_descriptor *frame;
1801         int idx;
1802
1803         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1804         urb_priv = td->urb->hcpriv;
1805         idx = urb_priv->td_cnt;
1806         frame = &td->urb->iso_frame_desc[idx];
1807
1808         /* The transfer is partly done. */
1809         frame->status = -EXDEV;
1810
1811         /* calc actual length */
1812         frame->actual_length = 0;
1813
1814         /* Update ring dequeue pointer */
1815         while (ep_ring->dequeue != td->last_trb)
1816                 inc_deq(xhci, ep_ring, false);
1817         inc_deq(xhci, ep_ring, false);
1818
1819         return finish_td(xhci, td, NULL, event, ep, status, true);
1820 }
1821
1822 /*
1823  * Process bulk and interrupt tds, update urb status and actual_length.
1824  */
1825 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1826         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1827         struct xhci_virt_ep *ep, int *status)
1828 {
1829         struct xhci_ring *ep_ring;
1830         union xhci_trb *cur_trb;
1831         struct xhci_segment *cur_seg;
1832         u32 trb_comp_code;
1833
1834         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1835         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1836
1837         switch (trb_comp_code) {
1838         case COMP_SUCCESS:
1839                 /* Double check that the HW transferred everything. */
1840                 if (event_trb != td->last_trb ||
1841                                 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1842                         xhci_warn(xhci, "WARN Successful completion "
1843                                         "on short TX\n");
1844                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1845                                 *status = -EREMOTEIO;
1846                         else
1847                                 *status = 0;
1848                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1849                                 trb_comp_code = COMP_SHORT_TX;
1850                 } else {
1851                         *status = 0;
1852                 }
1853                 break;
1854         case COMP_SHORT_TX:
1855                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1856                         *status = -EREMOTEIO;
1857                 else
1858                         *status = 0;
1859                 break;
1860         default:
1861                 /* Others already handled above */
1862                 break;
1863         }
1864         if (trb_comp_code == COMP_SHORT_TX)
1865                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1866                                 "%d bytes untransferred\n",
1867                                 td->urb->ep->desc.bEndpointAddress,
1868                                 td->urb->transfer_buffer_length,
1869                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1870         /* Fast path - was this the last TRB in the TD for this URB? */
1871         if (event_trb == td->last_trb) {
1872                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1873                         td->urb->actual_length =
1874                                 td->urb->transfer_buffer_length -
1875                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1876                         if (td->urb->transfer_buffer_length <
1877                                         td->urb->actual_length) {
1878                                 xhci_warn(xhci, "HC gave bad length "
1879                                                 "of %d bytes left\n",
1880                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1881                                 td->urb->actual_length = 0;
1882                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1883                                         *status = -EREMOTEIO;
1884                                 else
1885                                         *status = 0;
1886                         }
1887                         /* Don't overwrite a previously set error code */
1888                         if (*status == -EINPROGRESS) {
1889                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1890                                         *status = -EREMOTEIO;
1891                                 else
1892                                         *status = 0;
1893                         }
1894                 } else {
1895                         td->urb->actual_length =
1896                                 td->urb->transfer_buffer_length;
1897                         /* Ignore a short packet completion if the
1898                          * untransferred length was zero.
1899                          */
1900                         if (*status == -EREMOTEIO)
1901                                 *status = 0;
1902                 }
1903         } else {
1904                 /* Slow path - walk the list, starting from the dequeue
1905                  * pointer, to get the actual length transferred.
1906                  */
1907                 td->urb->actual_length = 0;
1908                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1909                                 cur_trb != event_trb;
1910                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1911                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1912                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1913                                 td->urb->actual_length +=
1914                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1915                 }
1916                 /* If the ring didn't stop on a Link or No-op TRB, add
1917                  * in the actual bytes transferred from the Normal TRB
1918                  */
1919                 if (trb_comp_code != COMP_STOP_INVAL)
1920                         td->urb->actual_length +=
1921                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1922                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1923         }
1924
1925         return finish_td(xhci, td, event_trb, event, ep, status, false);
1926 }
1927
1928 /*
1929  * If this function returns an error condition, it means it got a Transfer
1930  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1931  * At this point, the host controller is probably hosed and should be reset.
1932  */
1933 static int handle_tx_event(struct xhci_hcd *xhci,
1934                 struct xhci_transfer_event *event)
1935 {
1936         struct xhci_virt_device *xdev;
1937         struct xhci_virt_ep *ep;
1938         struct xhci_ring *ep_ring;
1939         unsigned int slot_id;
1940         int ep_index;
1941         struct xhci_td *td = NULL;
1942         dma_addr_t event_dma;
1943         struct xhci_segment *event_seg;
1944         union xhci_trb *event_trb;
1945         struct urb *urb = NULL;
1946         int status = -EINPROGRESS;
1947         struct urb_priv *urb_priv;
1948         struct xhci_ep_ctx *ep_ctx;
1949         struct list_head *tmp;
1950         u32 trb_comp_code;
1951         int ret = 0;
1952         int td_num = 0;
1953
1954         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1955         xdev = xhci->devs[slot_id];
1956         if (!xdev) {
1957                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1958                 return -ENODEV;
1959         }
1960
1961         /* Endpoint ID is 1 based, our index is zero based */
1962         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1963         ep = &xdev->eps[ep_index];
1964         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1965         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1966         if (!ep_ring ||
1967             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1968             EP_STATE_DISABLED) {
1969                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1970                                 "or incorrect stream ring\n");
1971                 return -ENODEV;
1972         }
1973
1974         /* Count current td numbers if ep->skip is set */
1975         if (ep->skip) {
1976                 list_for_each(tmp, &ep_ring->td_list)
1977                         td_num++;
1978         }
1979
1980         event_dma = le64_to_cpu(event->buffer);
1981         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1982         /* Look for common error cases */
1983         switch (trb_comp_code) {
1984         /* Skip codes that require special handling depending on
1985          * transfer type
1986          */
1987         case COMP_SUCCESS:
1988                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
1989                         break;
1990                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
1991                         trb_comp_code = COMP_SHORT_TX;
1992                 else
1993                         xhci_warn(xhci, "WARN Successful completion on short TX: "
1994                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
1995         case COMP_SHORT_TX:
1996                 break;
1997         case COMP_STOP:
1998                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1999                 break;
2000         case COMP_STOP_INVAL:
2001                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2002                 break;
2003         case COMP_STALL:
2004                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
2005                 ep->ep_state |= EP_HALTED;
2006                 status = -EPIPE;
2007                 break;
2008         case COMP_TRB_ERR:
2009                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2010                 status = -EILSEQ;
2011                 break;
2012         case COMP_SPLIT_ERR:
2013         case COMP_TX_ERR:
2014                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
2015                 status = -EPROTO;
2016                 break;
2017         case COMP_BABBLE:
2018                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2019                 status = -EOVERFLOW;
2020                 break;
2021         case COMP_DB_ERR:
2022                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2023                 status = -ENOSR;
2024                 break;
2025         case COMP_BW_OVER:
2026                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2027                 break;
2028         case COMP_BUFF_OVER:
2029                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2030                 break;
2031         case COMP_UNDERRUN:
2032                 /*
2033                  * When the Isoch ring is empty, the xHC will generate
2034                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2035                  * Underrun Event for OUT Isoch endpoint.
2036                  */
2037                 xhci_dbg(xhci, "underrun event on endpoint\n");
2038                 if (!list_empty(&ep_ring->td_list))
2039                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2040                                         "still with TDs queued?\n",
2041                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2042                                  ep_index);
2043                 goto cleanup;
2044         case COMP_OVERRUN:
2045                 xhci_dbg(xhci, "overrun event on endpoint\n");
2046                 if (!list_empty(&ep_ring->td_list))
2047                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2048                                         "still with TDs queued?\n",
2049                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2050                                  ep_index);
2051                 goto cleanup;
2052         case COMP_DEV_ERR:
2053                 xhci_warn(xhci, "WARN: detect an incompatible device");
2054                 status = -EPROTO;
2055                 break;
2056         case COMP_MISSED_INT:
2057                 /*
2058                  * When encounter missed service error, one or more isoc tds
2059                  * may be missed by xHC.
2060                  * Set skip flag of the ep_ring; Complete the missed tds as
2061                  * short transfer when process the ep_ring next time.
2062                  */
2063                 ep->skip = true;
2064                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2065                 goto cleanup;
2066         default:
2067                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2068                         status = 0;
2069                         break;
2070                 }
2071                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2072                                 "busted\n");
2073                 goto cleanup;
2074         }
2075
2076         do {
2077                 /* This TRB should be in the TD at the head of this ring's
2078                  * TD list.
2079                  */
2080                 if (list_empty(&ep_ring->td_list)) {
2081                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2082                                         "with no TDs queued?\n",
2083                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2084                                   ep_index);
2085                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2086                                  (le32_to_cpu(event->flags) &
2087                                   TRB_TYPE_BITMASK)>>10);
2088                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2089                         if (ep->skip) {
2090                                 ep->skip = false;
2091                                 xhci_dbg(xhci, "td_list is empty while skip "
2092                                                 "flag set. Clear skip flag.\n");
2093                         }
2094                         ret = 0;
2095                         goto cleanup;
2096                 }
2097
2098                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2099                 if (ep->skip && td_num == 0) {
2100                         ep->skip = false;
2101                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2102                                                 "Clear skip flag.\n");
2103                         ret = 0;
2104                         goto cleanup;
2105                 }
2106
2107                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2108                 if (ep->skip)
2109                         td_num--;
2110
2111                 /* Is this a TRB in the currently executing TD? */
2112                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2113                                 td->last_trb, event_dma);
2114
2115                 /*
2116                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2117                  * is not in the current TD pointed by ep_ring->dequeue because
2118                  * that the hardware dequeue pointer still at the previous TRB
2119                  * of the current TD. The previous TRB maybe a Link TD or the
2120                  * last TRB of the previous TD. The command completion handle
2121                  * will take care the rest.
2122                  */
2123                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2124                         ret = 0;
2125                         goto cleanup;
2126                 }
2127
2128                 if (!event_seg) {
2129                         if (!ep->skip ||
2130                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2131                                 /* Some host controllers give a spurious
2132                                  * successful event after a short transfer.
2133                                  * Ignore it.
2134                                  */
2135                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2136                                                 ep_ring->last_td_was_short) {
2137                                         ep_ring->last_td_was_short = false;
2138                                         ret = 0;
2139                                         goto cleanup;
2140                                 }
2141                                 /* HC is busted, give up! */
2142                                 xhci_err(xhci,
2143                                         "ERROR Transfer event TRB DMA ptr not "
2144                                         "part of current TD\n");
2145                                 return -ESHUTDOWN;
2146                         }
2147
2148                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2149                         goto cleanup;
2150                 }
2151                 if (trb_comp_code == COMP_SHORT_TX)
2152                         ep_ring->last_td_was_short = true;
2153                 else
2154                         ep_ring->last_td_was_short = false;
2155
2156                 if (ep->skip) {
2157                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2158                         ep->skip = false;
2159                 }
2160
2161                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2162                                                 sizeof(*event_trb)];
2163                 /*
2164                  * No-op TRB should not trigger interrupts.
2165                  * If event_trb is a no-op TRB, it means the
2166                  * corresponding TD has been cancelled. Just ignore
2167                  * the TD.
2168                  */
2169                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2170                         xhci_dbg(xhci,
2171                                  "event_trb is a no-op TRB. Skip it\n");
2172                         goto cleanup;
2173                 }
2174
2175                 /* Now update the urb's actual_length and give back to
2176                  * the core
2177                  */
2178                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2179                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2180                                                  &status);
2181                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2182                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2183                                                  &status);
2184                 else
2185                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2186                                                  ep, &status);
2187
2188 cleanup:
2189                 /*
2190                  * Do not update event ring dequeue pointer if ep->skip is set.
2191                  * Will roll back to continue process missed tds.
2192                  */
2193                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2194                         inc_deq(xhci, xhci->event_ring, true);
2195                 }
2196
2197                 if (ret) {
2198                         urb = td->urb;
2199                         urb_priv = urb->hcpriv;
2200                         /* Leave the TD around for the reset endpoint function
2201                          * to use(but only if it's not a control endpoint,
2202                          * since we already queued the Set TR dequeue pointer
2203                          * command for stalled control endpoints).
2204                          */
2205                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2206                                 (trb_comp_code != COMP_STALL &&
2207                                         trb_comp_code != COMP_BABBLE))
2208                                 xhci_urb_free_priv(xhci, urb_priv);
2209
2210                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2211                         if ((urb->actual_length != urb->transfer_buffer_length &&
2212                                                 (urb->transfer_flags &
2213                                                  URB_SHORT_NOT_OK)) ||
2214                                         (status != 0 &&
2215                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2216                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2217                                                 "expected = %x, status = %d\n",
2218                                                 urb, urb->actual_length,
2219                                                 urb->transfer_buffer_length,
2220                                                 status);
2221                         spin_unlock(&xhci->lock);
2222                         /* EHCI, UHCI, and OHCI always unconditionally set the
2223                          * urb->status of an isochronous endpoint to 0.
2224                          */
2225                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2226                                 status = 0;
2227                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2228                         spin_lock(&xhci->lock);
2229                 }
2230
2231         /*
2232          * If ep->skip is set, it means there are missed tds on the
2233          * endpoint ring need to take care of.
2234          * Process them as short transfer until reach the td pointed by
2235          * the event.
2236          */
2237         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2238
2239         return 0;
2240 }
2241
2242 /*
2243  * This function handles all OS-owned events on the event ring.  It may drop
2244  * xhci->lock between event processing (e.g. to pass up port status changes).
2245  * Returns >0 for "possibly more events to process" (caller should call again),
2246  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2247  */
2248 static int xhci_handle_event(struct xhci_hcd *xhci)
2249 {
2250         union xhci_trb *event;
2251         int update_ptrs = 1;
2252         int ret;
2253
2254         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2255                 xhci->error_bitmask |= 1 << 1;
2256                 return 0;
2257         }
2258
2259         event = xhci->event_ring->dequeue;
2260         /* Does the HC or OS own the TRB? */
2261         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2262             xhci->event_ring->cycle_state) {
2263                 xhci->error_bitmask |= 1 << 2;
2264                 return 0;
2265         }
2266
2267         /*
2268          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2269          * speculative reads of the event's flags/data below.
2270          */
2271         rmb();
2272         /* FIXME: Handle more event types. */
2273         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2274         case TRB_TYPE(TRB_COMPLETION):
2275                 handle_cmd_completion(xhci, &event->event_cmd);
2276                 break;
2277         case TRB_TYPE(TRB_PORT_STATUS):
2278                 handle_port_status(xhci, event);
2279                 update_ptrs = 0;
2280                 break;
2281         case TRB_TYPE(TRB_TRANSFER):
2282                 ret = handle_tx_event(xhci, &event->trans_event);
2283                 if (ret < 0)
2284                         xhci->error_bitmask |= 1 << 9;
2285                 else
2286                         update_ptrs = 0;
2287                 break;
2288         default:
2289                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2290                     TRB_TYPE(48))
2291                         handle_vendor_event(xhci, event);
2292                 else
2293                         xhci->error_bitmask |= 1 << 3;
2294         }
2295         /* Any of the above functions may drop and re-acquire the lock, so check
2296          * to make sure a watchdog timer didn't mark the host as non-responsive.
2297          */
2298         if (xhci->xhc_state & XHCI_STATE_DYING) {
2299                 xhci_dbg(xhci, "xHCI host dying, returning from "
2300                                 "event handler.\n");
2301                 return 0;
2302         }
2303
2304         if (update_ptrs)
2305                 /* Update SW event ring dequeue pointer */
2306                 inc_deq(xhci, xhci->event_ring, true);
2307
2308         /* Are there more items on the event ring?  Caller will call us again to
2309          * check.
2310          */
2311         return 1;
2312 }
2313
2314 /*
2315  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2316  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2317  * indicators of an event TRB error, but we check the status *first* to be safe.
2318  */
2319 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2320 {
2321         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2322         u32 status;
2323         union xhci_trb *trb;
2324         u64 temp_64;
2325         union xhci_trb *event_ring_deq;
2326         dma_addr_t deq;
2327
2328         spin_lock(&xhci->lock);
2329         trb = xhci->event_ring->dequeue;
2330         /* Check if the xHC generated the interrupt, or the irq is shared */
2331         status = xhci_readl(xhci, &xhci->op_regs->status);
2332         if (status == 0xffffffff)
2333                 goto hw_died;
2334
2335         if (!(status & STS_EINT)) {
2336                 spin_unlock(&xhci->lock);
2337                 return IRQ_NONE;
2338         }
2339         if (status & STS_FATAL) {
2340                 xhci_warn(xhci, "WARNING: Host System Error\n");
2341                 xhci_halt(xhci);
2342 hw_died:
2343                 spin_unlock(&xhci->lock);
2344                 return -ESHUTDOWN;
2345         }
2346
2347         /*
2348          * Clear the op reg interrupt status first,
2349          * so we can receive interrupts from other MSI-X interrupters.
2350          * Write 1 to clear the interrupt status.
2351          */
2352         status |= STS_EINT;
2353         xhci_writel(xhci, status, &xhci->op_regs->status);
2354         /* FIXME when MSI-X is supported and there are multiple vectors */
2355         /* Clear the MSI-X event interrupt status */
2356
2357         if (hcd->irq != -1) {
2358                 u32 irq_pending;
2359                 /* Acknowledge the PCI interrupt */
2360                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2361                 irq_pending |= IMAN_IP;
2362                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2363         }
2364
2365         if (xhci->xhc_state & XHCI_STATE_DYING) {
2366                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2367                                 "Shouldn't IRQs be disabled?\n");
2368                 /* Clear the event handler busy flag (RW1C);
2369                  * the event ring should be empty.
2370                  */
2371                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2372                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2373                                 &xhci->ir_set->erst_dequeue);
2374                 spin_unlock(&xhci->lock);
2375
2376                 return IRQ_HANDLED;
2377         }
2378
2379         event_ring_deq = xhci->event_ring->dequeue;
2380         /* FIXME this should be a delayed service routine
2381          * that clears the EHB.
2382          */
2383         while (xhci_handle_event(xhci) > 0) {}
2384
2385         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2386         /* If necessary, update the HW's version of the event ring deq ptr. */
2387         if (event_ring_deq != xhci->event_ring->dequeue) {
2388                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2389                                 xhci->event_ring->dequeue);
2390                 if (deq == 0)
2391                         xhci_warn(xhci, "WARN something wrong with SW event "
2392                                         "ring dequeue ptr.\n");
2393                 /* Update HC event ring dequeue pointer */
2394                 temp_64 &= ERST_PTR_MASK;
2395                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2396         }
2397
2398         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2399         temp_64 |= ERST_EHB;
2400         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2401
2402         spin_unlock(&xhci->lock);
2403
2404         return IRQ_HANDLED;
2405 }
2406
2407 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2408 {
2409         irqreturn_t ret;
2410         struct xhci_hcd *xhci;
2411
2412         xhci = hcd_to_xhci(hcd);
2413         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2414         if (xhci->shared_hcd)
2415                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2416
2417         ret = xhci_irq(hcd);
2418
2419         return ret;
2420 }
2421
2422 /****           Endpoint Ring Operations        ****/
2423
2424 /*
2425  * Generic function for queueing a TRB on a ring.
2426  * The caller must have checked to make sure there's room on the ring.
2427  *
2428  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2429  *                      prepare_transfer()?
2430  */
2431 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2432                 bool consumer, bool more_trbs_coming, bool isoc,
2433                 u32 field1, u32 field2, u32 field3, u32 field4)
2434 {
2435         struct xhci_generic_trb *trb;
2436
2437         trb = &ring->enqueue->generic;
2438         trb->field[0] = cpu_to_le32(field1);
2439         trb->field[1] = cpu_to_le32(field2);
2440         trb->field[2] = cpu_to_le32(field3);
2441         trb->field[3] = cpu_to_le32(field4);
2442         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2443 }
2444
2445 /*
2446  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2447  * FIXME allocate segments if the ring is full.
2448  */
2449 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2450                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2451 {
2452         /* Make sure the endpoint has been added to xHC schedule */
2453         switch (ep_state) {
2454         case EP_STATE_DISABLED:
2455                 /*
2456                  * USB core changed config/interfaces without notifying us,
2457                  * or hardware is reporting the wrong state.
2458                  */
2459                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2460                 return -ENOENT;
2461         case EP_STATE_ERROR:
2462                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2463                 /* FIXME event handling code for error needs to clear it */
2464                 /* XXX not sure if this should be -ENOENT or not */
2465                 return -EINVAL;
2466         case EP_STATE_HALTED:
2467                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2468         case EP_STATE_STOPPED:
2469         case EP_STATE_RUNNING:
2470                 break;
2471         default:
2472                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2473                 /*
2474                  * FIXME issue Configure Endpoint command to try to get the HC
2475                  * back into a known state.
2476                  */
2477                 return -EINVAL;
2478         }
2479         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2480                 /* FIXME allocate more room */
2481                 xhci_err(xhci, "ERROR no room on ep ring\n");
2482                 return -ENOMEM;
2483         }
2484
2485         if (enqueue_is_link_trb(ep_ring)) {
2486                 struct xhci_ring *ring = ep_ring;
2487                 union xhci_trb *next;
2488
2489                 next = ring->enqueue;
2490
2491                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2492                         /* If we're not dealing with 0.95 hardware or isoc rings
2493                          * on AMD 0.96 host, clear the chain bit.
2494                          */
2495                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2496                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2497                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2498                         else
2499                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2500
2501                         wmb();
2502                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2503
2504                         /* Toggle the cycle bit after the last ring segment. */
2505                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2506                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2507                                 if (!in_interrupt()) {
2508                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2509                                                 "state for ring %p = %i\n",
2510                                                 ring, (unsigned int)ring->cycle_state);
2511                                 }
2512                         }
2513                         ring->enq_seg = ring->enq_seg->next;
2514                         ring->enqueue = ring->enq_seg->trbs;
2515                         next = ring->enqueue;
2516                 }
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int prepare_transfer(struct xhci_hcd *xhci,
2523                 struct xhci_virt_device *xdev,
2524                 unsigned int ep_index,
2525                 unsigned int stream_id,
2526                 unsigned int num_trbs,
2527                 struct urb *urb,
2528                 unsigned int td_index,
2529                 bool isoc,
2530                 gfp_t mem_flags)
2531 {
2532         int ret;
2533         struct urb_priv *urb_priv;
2534         struct xhci_td  *td;
2535         struct xhci_ring *ep_ring;
2536         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2537
2538         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2539         if (!ep_ring) {
2540                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2541                                 stream_id);
2542                 return -EINVAL;
2543         }
2544
2545         ret = prepare_ring(xhci, ep_ring,
2546                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2547                            num_trbs, isoc, mem_flags);
2548         if (ret)
2549                 return ret;
2550
2551         urb_priv = urb->hcpriv;
2552         td = urb_priv->td[td_index];
2553
2554         INIT_LIST_HEAD(&td->td_list);
2555         INIT_LIST_HEAD(&td->cancelled_td_list);
2556
2557         if (td_index == 0) {
2558                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2559                 if (unlikely(ret))
2560                         return ret;
2561         }
2562
2563         td->urb = urb;
2564         /* Add this TD to the tail of the endpoint ring's TD list */
2565         list_add_tail(&td->td_list, &ep_ring->td_list);
2566         td->start_seg = ep_ring->enq_seg;
2567         td->first_trb = ep_ring->enqueue;
2568
2569         urb_priv->td[td_index] = td;
2570
2571         return 0;
2572 }
2573
2574 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2575 {
2576         int num_sgs, num_trbs, running_total, temp, i;
2577         struct scatterlist *sg;
2578
2579         sg = NULL;
2580         num_sgs = urb->num_mapped_sgs;
2581         temp = urb->transfer_buffer_length;
2582
2583         xhci_dbg(xhci, "count sg list trbs: \n");
2584         num_trbs = 0;
2585         for_each_sg(urb->sg, sg, num_sgs, i) {
2586                 unsigned int previous_total_trbs = num_trbs;
2587                 unsigned int len = sg_dma_len(sg);
2588
2589                 /* Scatter gather list entries may cross 64KB boundaries */
2590                 running_total = TRB_MAX_BUFF_SIZE -
2591                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2592                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2593                 if (running_total != 0)
2594                         num_trbs++;
2595
2596                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2597                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2598                         num_trbs++;
2599                         running_total += TRB_MAX_BUFF_SIZE;
2600                 }
2601                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2602                                 i, (unsigned long long)sg_dma_address(sg),
2603                                 len, len, num_trbs - previous_total_trbs);
2604
2605                 len = min_t(int, len, temp);
2606                 temp -= len;
2607                 if (temp == 0)
2608                         break;
2609         }
2610         xhci_dbg(xhci, "\n");
2611         if (!in_interrupt())
2612                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2613                                 "num_trbs = %d\n",
2614                                 urb->ep->desc.bEndpointAddress,
2615                                 urb->transfer_buffer_length,
2616                                 num_trbs);
2617         return num_trbs;
2618 }
2619
2620 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2621 {
2622         if (num_trbs != 0)
2623                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2624                                 "TRBs, %d left\n", __func__,
2625                                 urb->ep->desc.bEndpointAddress, num_trbs);
2626         if (running_total != urb->transfer_buffer_length)
2627                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2628                                 "queued %#x (%d), asked for %#x (%d)\n",
2629                                 __func__,
2630                                 urb->ep->desc.bEndpointAddress,
2631                                 running_total, running_total,
2632                                 urb->transfer_buffer_length,
2633                                 urb->transfer_buffer_length);
2634 }
2635
2636 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2637                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2638                 struct xhci_generic_trb *start_trb)
2639 {
2640         /*
2641          * Pass all the TRBs to the hardware at once and make sure this write
2642          * isn't reordered.
2643          */
2644         wmb();
2645         if (start_cycle)
2646                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2647         else
2648                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2649         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2650 }
2651
2652 /*
2653  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2654  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2655  * (comprised of sg list entries) can take several service intervals to
2656  * transmit.
2657  */
2658 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2659                 struct urb *urb, int slot_id, unsigned int ep_index)
2660 {
2661         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2662                         xhci->devs[slot_id]->out_ctx, ep_index);
2663         int xhci_interval;
2664         int ep_interval;
2665
2666         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2667         ep_interval = urb->interval;
2668         /* Convert to microframes */
2669         if (urb->dev->speed == USB_SPEED_LOW ||
2670                         urb->dev->speed == USB_SPEED_FULL)
2671                 ep_interval *= 8;
2672         /* FIXME change this to a warning and a suggestion to use the new API
2673          * to set the polling interval (once the API is added).
2674          */
2675         if (xhci_interval != ep_interval) {
2676                 if (printk_ratelimit())
2677                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2678                                         " (%d microframe%s) than xHCI "
2679                                         "(%d microframe%s)\n",
2680                                         ep_interval,
2681                                         ep_interval == 1 ? "" : "s",
2682                                         xhci_interval,
2683                                         xhci_interval == 1 ? "" : "s");
2684                 urb->interval = xhci_interval;
2685                 /* Convert back to frames for LS/FS devices */
2686                 if (urb->dev->speed == USB_SPEED_LOW ||
2687                                 urb->dev->speed == USB_SPEED_FULL)
2688                         urb->interval /= 8;
2689         }
2690         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2691 }
2692
2693 /*
2694  * The TD size is the number of bytes remaining in the TD (including this TRB),
2695  * right shifted by 10.
2696  * It must fit in bits 21:17, so it can't be bigger than 31.
2697  */
2698 static u32 xhci_td_remainder(unsigned int remainder)
2699 {
2700         u32 max = (1 << (21 - 17 + 1)) - 1;
2701
2702         if ((remainder >> 10) >= max)
2703                 return max << 17;
2704         else
2705                 return (remainder >> 10) << 17;
2706 }
2707
2708 /*
2709  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2710  * the TD (*not* including this TRB).
2711  *
2712  * Total TD packet count = total_packet_count =
2713  *     roundup(TD size in bytes / wMaxPacketSize)
2714  *
2715  * Packets transferred up to and including this TRB = packets_transferred =
2716  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2717  *
2718  * TD size = total_packet_count - packets_transferred
2719  *
2720  * It must fit in bits 21:17, so it can't be bigger than 31.
2721  */
2722
2723 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2724                 unsigned int total_packet_count, struct urb *urb)
2725 {
2726         int packets_transferred;
2727
2728         /* One TRB with a zero-length data packet. */
2729         if (running_total == 0 && trb_buff_len == 0)
2730                 return 0;
2731
2732         /* All the TRB queueing functions don't count the current TRB in
2733          * running_total.
2734          */
2735         packets_transferred = (running_total + trb_buff_len) /
2736                 usb_endpoint_maxp(&urb->ep->desc);
2737
2738         return xhci_td_remainder(total_packet_count - packets_transferred);
2739 }
2740
2741 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2742                 struct urb *urb, int slot_id, unsigned int ep_index)
2743 {
2744         struct xhci_ring *ep_ring;
2745         unsigned int num_trbs;
2746         struct urb_priv *urb_priv;
2747         struct xhci_td *td;
2748         struct scatterlist *sg;
2749         int num_sgs;
2750         int trb_buff_len, this_sg_len, running_total;
2751         unsigned int total_packet_count;
2752         bool first_trb;
2753         u64 addr;
2754         bool more_trbs_coming;
2755
2756         struct xhci_generic_trb *start_trb;
2757         int start_cycle;
2758
2759         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2760         if (!ep_ring)
2761                 return -EINVAL;
2762
2763         num_trbs = count_sg_trbs_needed(xhci, urb);
2764         num_sgs = urb->num_mapped_sgs;
2765         total_packet_count = roundup(urb->transfer_buffer_length,
2766                         usb_endpoint_maxp(&urb->ep->desc));
2767
2768         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2769                         ep_index, urb->stream_id,
2770                         num_trbs, urb, 0, false, mem_flags);
2771         if (trb_buff_len < 0)
2772                 return trb_buff_len;
2773
2774         urb_priv = urb->hcpriv;
2775         td = urb_priv->td[0];
2776
2777         /*
2778          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2779          * until we've finished creating all the other TRBs.  The ring's cycle
2780          * state may change as we enqueue the other TRBs, so save it too.
2781          */
2782         start_trb = &ep_ring->enqueue->generic;
2783         start_cycle = ep_ring->cycle_state;
2784
2785         running_total = 0;
2786         /*
2787          * How much data is in the first TRB?
2788          *
2789          * There are three forces at work for TRB buffer pointers and lengths:
2790          * 1. We don't want to walk off the end of this sg-list entry buffer.
2791          * 2. The transfer length that the driver requested may be smaller than
2792          *    the amount of memory allocated for this scatter-gather list.
2793          * 3. TRBs buffers can't cross 64KB boundaries.
2794          */
2795         sg = urb->sg;
2796         addr = (u64) sg_dma_address(sg);
2797         this_sg_len = sg_dma_len(sg);
2798         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2799         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2800         if (trb_buff_len > urb->transfer_buffer_length)
2801                 trb_buff_len = urb->transfer_buffer_length;
2802         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2803                         trb_buff_len);
2804
2805         first_trb = true;
2806         /* Queue the first TRB, even if it's zero-length */
2807         do {
2808                 u32 field = 0;
2809                 u32 length_field = 0;
2810                 u32 remainder = 0;
2811
2812                 /* Don't change the cycle bit of the first TRB until later */
2813                 if (first_trb) {
2814                         first_trb = false;
2815                         if (start_cycle == 0)
2816                                 field |= 0x1;
2817                 } else
2818                         field |= ep_ring->cycle_state;
2819
2820                 /* Chain all the TRBs together; clear the chain bit in the last
2821                  * TRB to indicate it's the last TRB in the chain.
2822                  */
2823                 if (num_trbs > 1) {
2824                         field |= TRB_CHAIN;
2825                 } else {
2826                         /* FIXME - add check for ZERO_PACKET flag before this */
2827                         td->last_trb = ep_ring->enqueue;
2828                         field |= TRB_IOC;
2829                 }
2830
2831                 /* Only set interrupt on short packet for IN endpoints */
2832                 if (usb_urb_dir_in(urb))
2833                         field |= TRB_ISP;
2834
2835                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2836                                 "64KB boundary at %#x, end dma = %#x\n",
2837                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2838                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2839                                 (unsigned int) addr + trb_buff_len);
2840                 if (TRB_MAX_BUFF_SIZE -
2841                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2842                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2843                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2844                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2845                                         (unsigned int) addr + trb_buff_len);
2846                 }
2847
2848                 /* Set the TRB length, TD size, and interrupter fields. */
2849                 if (xhci->hci_version < 0x100) {
2850                         remainder = xhci_td_remainder(
2851                                         urb->transfer_buffer_length -
2852                                         running_total);
2853                 } else {
2854                         remainder = xhci_v1_0_td_remainder(running_total,
2855                                         trb_buff_len, total_packet_count, urb);
2856                 }
2857                 length_field = TRB_LEN(trb_buff_len) |
2858                         remainder |
2859                         TRB_INTR_TARGET(0);
2860
2861                 if (num_trbs > 1)
2862                         more_trbs_coming = true;
2863                 else
2864                         more_trbs_coming = false;
2865                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2866                                 lower_32_bits(addr),
2867                                 upper_32_bits(addr),
2868                                 length_field,
2869                                 field | TRB_TYPE(TRB_NORMAL));
2870                 --num_trbs;
2871                 running_total += trb_buff_len;
2872
2873                 /* Calculate length for next transfer --
2874                  * Are we done queueing all the TRBs for this sg entry?
2875                  */
2876                 this_sg_len -= trb_buff_len;
2877                 if (this_sg_len == 0) {
2878                         --num_sgs;
2879                         if (num_sgs == 0)
2880                                 break;
2881                         sg = sg_next(sg);
2882                         addr = (u64) sg_dma_address(sg);
2883                         this_sg_len = sg_dma_len(sg);
2884                 } else {
2885                         addr += trb_buff_len;
2886                 }
2887
2888                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2889                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2890                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2891                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2892                         trb_buff_len =
2893                                 urb->transfer_buffer_length - running_total;
2894         } while (running_total < urb->transfer_buffer_length);
2895
2896         check_trb_math(urb, num_trbs, running_total);
2897         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2898                         start_cycle, start_trb);
2899         return 0;
2900 }
2901
2902 /* This is very similar to what ehci-q.c qtd_fill() does */
2903 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2904                 struct urb *urb, int slot_id, unsigned int ep_index)
2905 {
2906         struct xhci_ring *ep_ring;
2907         struct urb_priv *urb_priv;
2908         struct xhci_td *td;
2909         int num_trbs;
2910         struct xhci_generic_trb *start_trb;
2911         bool first_trb;
2912         bool more_trbs_coming;
2913         int start_cycle;
2914         u32 field, length_field;
2915
2916         int running_total, trb_buff_len, ret;
2917         unsigned int total_packet_count;
2918         u64 addr;
2919
2920         if (urb->num_sgs)
2921                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2922
2923         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2924         if (!ep_ring)
2925                 return -EINVAL;
2926
2927         num_trbs = 0;
2928         /* How much data is (potentially) left before the 64KB boundary? */
2929         running_total = TRB_MAX_BUFF_SIZE -
2930                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2931         running_total &= TRB_MAX_BUFF_SIZE - 1;
2932
2933         /* If there's some data on this 64KB chunk, or we have to send a
2934          * zero-length transfer, we need at least one TRB
2935          */
2936         if (running_total != 0 || urb->transfer_buffer_length == 0)
2937                 num_trbs++;
2938         /* How many more 64KB chunks to transfer, how many more TRBs? */
2939         while (running_total < urb->transfer_buffer_length) {
2940                 num_trbs++;
2941                 running_total += TRB_MAX_BUFF_SIZE;
2942         }
2943         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2944
2945         if (!in_interrupt())
2946                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2947                                 "addr = %#llx, num_trbs = %d\n",
2948                                 urb->ep->desc.bEndpointAddress,
2949                                 urb->transfer_buffer_length,
2950                                 urb->transfer_buffer_length,
2951                                 (unsigned long long)urb->transfer_dma,
2952                                 num_trbs);
2953
2954         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2955                         ep_index, urb->stream_id,
2956                         num_trbs, urb, 0, false, mem_flags);
2957         if (ret < 0)
2958                 return ret;
2959
2960         urb_priv = urb->hcpriv;
2961         td = urb_priv->td[0];
2962
2963         /*
2964          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2965          * until we've finished creating all the other TRBs.  The ring's cycle
2966          * state may change as we enqueue the other TRBs, so save it too.
2967          */
2968         start_trb = &ep_ring->enqueue->generic;
2969         start_cycle = ep_ring->cycle_state;
2970
2971         running_total = 0;
2972         total_packet_count = roundup(urb->transfer_buffer_length,
2973                         usb_endpoint_maxp(&urb->ep->desc));
2974         /* How much data is in the first TRB? */
2975         addr = (u64) urb->transfer_dma;
2976         trb_buff_len = TRB_MAX_BUFF_SIZE -
2977                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2978         if (trb_buff_len > urb->transfer_buffer_length)
2979                 trb_buff_len = urb->transfer_buffer_length;
2980
2981         first_trb = true;
2982
2983         /* Queue the first TRB, even if it's zero-length */
2984         do {
2985                 u32 remainder = 0;
2986                 field = 0;
2987
2988                 /* Don't change the cycle bit of the first TRB until later */
2989                 if (first_trb) {
2990                         first_trb = false;
2991                         if (start_cycle == 0)
2992                                 field |= 0x1;
2993                 } else
2994                         field |= ep_ring->cycle_state;
2995
2996                 /* Chain all the TRBs together; clear the chain bit in the last
2997                  * TRB to indicate it's the last TRB in the chain.
2998                  */
2999                 if (num_trbs > 1) {
3000                         field |= TRB_CHAIN;
3001                 } else {
3002                         /* FIXME - add check for ZERO_PACKET flag before this */
3003                         td->last_trb = ep_ring->enqueue;
3004                         field |= TRB_IOC;
3005                 }
3006
3007                 /* Only set interrupt on short packet for IN endpoints */
3008                 if (usb_urb_dir_in(urb))
3009                         field |= TRB_ISP;
3010
3011                 /* Set the TRB length, TD size, and interrupter fields. */
3012                 if (xhci->hci_version < 0x100) {
3013                         remainder = xhci_td_remainder(
3014                                         urb->transfer_buffer_length -
3015                                         running_total);
3016                 } else {
3017                         remainder = xhci_v1_0_td_remainder(running_total,
3018                                         trb_buff_len, total_packet_count, urb);
3019                 }
3020                 length_field = TRB_LEN(trb_buff_len) |
3021                         remainder |
3022                         TRB_INTR_TARGET(0);
3023
3024                 if (num_trbs > 1)
3025                         more_trbs_coming = true;
3026                 else
3027                         more_trbs_coming = false;
3028                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3029                                 lower_32_bits(addr),
3030                                 upper_32_bits(addr),
3031                                 length_field,
3032                                 field | TRB_TYPE(TRB_NORMAL));
3033                 --num_trbs;
3034                 running_total += trb_buff_len;
3035
3036                 /* Calculate length for next transfer */
3037                 addr += trb_buff_len;
3038                 trb_buff_len = urb->transfer_buffer_length - running_total;
3039                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3040                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3041         } while (running_total < urb->transfer_buffer_length);
3042
3043         check_trb_math(urb, num_trbs, running_total);
3044         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3045                         start_cycle, start_trb);
3046         return 0;
3047 }
3048
3049 /* Caller must have locked xhci->lock */
3050 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3051                 struct urb *urb, int slot_id, unsigned int ep_index)
3052 {
3053         struct xhci_ring *ep_ring;
3054         int num_trbs;
3055         int ret;
3056         struct usb_ctrlrequest *setup;
3057         struct xhci_generic_trb *start_trb;
3058         int start_cycle;
3059         u32 field, length_field;
3060         struct urb_priv *urb_priv;
3061         struct xhci_td *td;
3062
3063         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3064         if (!ep_ring)
3065                 return -EINVAL;
3066
3067         /*
3068          * Need to copy setup packet into setup TRB, so we can't use the setup
3069          * DMA address.
3070          */
3071         if (!urb->setup_packet)
3072                 return -EINVAL;
3073
3074         if (!in_interrupt())
3075                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3076                                 slot_id, ep_index);
3077         /* 1 TRB for setup, 1 for status */
3078         num_trbs = 2;
3079         /*
3080          * Don't need to check if we need additional event data and normal TRBs,
3081          * since data in control transfers will never get bigger than 16MB
3082          * XXX: can we get a buffer that crosses 64KB boundaries?
3083          */
3084         if (urb->transfer_buffer_length > 0)
3085                 num_trbs++;
3086         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3087                         ep_index, urb->stream_id,
3088                         num_trbs, urb, 0, false, mem_flags);
3089         if (ret < 0)
3090                 return ret;
3091
3092         urb_priv = urb->hcpriv;
3093         td = urb_priv->td[0];
3094
3095         /*
3096          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3097          * until we've finished creating all the other TRBs.  The ring's cycle
3098          * state may change as we enqueue the other TRBs, so save it too.
3099          */
3100         start_trb = &ep_ring->enqueue->generic;
3101         start_cycle = ep_ring->cycle_state;
3102
3103         /* Queue setup TRB - see section 6.4.1.2.1 */
3104         /* FIXME better way to translate setup_packet into two u32 fields? */
3105         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3106         field = 0;
3107         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3108         if (start_cycle == 0)
3109                 field |= 0x1;
3110
3111         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3112         if (xhci->hci_version == 0x100) {
3113                 if (urb->transfer_buffer_length > 0) {
3114                         if (setup->bRequestType & USB_DIR_IN)
3115                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3116                         else
3117                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3118                 }
3119         }
3120
3121         queue_trb(xhci, ep_ring, false, true, false,
3122                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3123                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3124                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3125                   /* Immediate data in pointer */
3126                   field);
3127
3128         /* If there's data, queue data TRBs */
3129         /* Only set interrupt on short packet for IN endpoints */
3130         if (usb_urb_dir_in(urb))
3131                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3132         else
3133                 field = TRB_TYPE(TRB_DATA);
3134
3135         length_field = TRB_LEN(urb->transfer_buffer_length) |
3136                 xhci_td_remainder(urb->transfer_buffer_length) |
3137                 TRB_INTR_TARGET(0);
3138         if (urb->transfer_buffer_length > 0) {
3139                 if (setup->bRequestType & USB_DIR_IN)
3140                         field |= TRB_DIR_IN;
3141                 queue_trb(xhci, ep_ring, false, true, false,
3142                                 lower_32_bits(urb->transfer_dma),
3143                                 upper_32_bits(urb->transfer_dma),
3144                                 length_field,
3145                                 field | ep_ring->cycle_state);
3146         }
3147
3148         /* Save the DMA address of the last TRB in the TD */
3149         td->last_trb = ep_ring->enqueue;
3150
3151         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3152         /* If the device sent data, the status stage is an OUT transfer */
3153         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3154                 field = 0;
3155         else
3156                 field = TRB_DIR_IN;
3157         queue_trb(xhci, ep_ring, false, false, false,
3158                         0,
3159                         0,
3160                         TRB_INTR_TARGET(0),
3161                         /* Event on completion */
3162                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3163
3164         giveback_first_trb(xhci, slot_id, ep_index, 0,
3165                         start_cycle, start_trb);
3166         return 0;
3167 }
3168
3169 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3170                 struct urb *urb, int i)
3171 {
3172         int num_trbs = 0;
3173         u64 addr, td_len;
3174
3175         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3176         td_len = urb->iso_frame_desc[i].length;
3177
3178         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3179                         TRB_MAX_BUFF_SIZE);
3180         if (num_trbs == 0)
3181                 num_trbs++;
3182
3183         return num_trbs;
3184 }
3185
3186 /*
3187  * The transfer burst count field of the isochronous TRB defines the number of
3188  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3189  * devices can burst up to bMaxBurst number of packets per service interval.
3190  * This field is zero based, meaning a value of zero in the field means one
3191  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3192  * zero.  Only xHCI 1.0 host controllers support this field.
3193  */
3194 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3195                 struct usb_device *udev,
3196                 struct urb *urb, unsigned int total_packet_count)
3197 {
3198         unsigned int max_burst;
3199
3200         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3201                 return 0;
3202
3203         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3204         return roundup(total_packet_count, max_burst + 1) - 1;
3205 }
3206
3207 /*
3208  * Returns the number of packets in the last "burst" of packets.  This field is
3209  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3210  * the last burst packet count is equal to the total number of packets in the
3211  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3212  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3213  * contain 1 to (bMaxBurst + 1) packets.
3214  */
3215 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3216                 struct usb_device *udev,
3217                 struct urb *urb, unsigned int total_packet_count)
3218 {
3219         unsigned int max_burst;
3220         unsigned int residue;
3221
3222         if (xhci->hci_version < 0x100)
3223                 return 0;
3224
3225         switch (udev->speed) {
3226         case USB_SPEED_SUPER:
3227                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3228                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3229                 residue = total_packet_count % (max_burst + 1);
3230                 /* If residue is zero, the last burst contains (max_burst + 1)
3231                  * number of packets, but the TLBPC field is zero-based.
3232                  */
3233                 if (residue == 0)
3234                         return max_burst;
3235                 return residue - 1;
3236         default:
3237                 if (total_packet_count == 0)
3238                         return 0;
3239                 return total_packet_count - 1;
3240         }
3241 }
3242
3243 /* This is for isoc transfer */
3244 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3245                 struct urb *urb, int slot_id, unsigned int ep_index)
3246 {
3247         struct xhci_ring *ep_ring;
3248         struct urb_priv *urb_priv;
3249         struct xhci_td *td;
3250         int num_tds, trbs_per_td;
3251         struct xhci_generic_trb *start_trb;
3252         bool first_trb;
3253         int start_cycle;
3254         u32 field, length_field;
3255         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3256         u64 start_addr, addr;
3257         int i, j;
3258         bool more_trbs_coming;
3259
3260         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3261
3262         num_tds = urb->number_of_packets;
3263         if (num_tds < 1) {
3264                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3265                 return -EINVAL;
3266         }
3267
3268         if (!in_interrupt())
3269                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3270                                 " addr = %#llx, num_tds = %d\n",
3271                                 urb->ep->desc.bEndpointAddress,
3272                                 urb->transfer_buffer_length,
3273                                 urb->transfer_buffer_length,
3274                                 (unsigned long long)urb->transfer_dma,
3275                                 num_tds);
3276
3277         start_addr = (u64) urb->transfer_dma;
3278         start_trb = &ep_ring->enqueue->generic;
3279         start_cycle = ep_ring->cycle_state;
3280
3281         urb_priv = urb->hcpriv;
3282         /* Queue the first TRB, even if it's zero-length */
3283         for (i = 0; i < num_tds; i++) {
3284                 unsigned int total_packet_count;
3285                 unsigned int burst_count;
3286                 unsigned int residue;
3287
3288                 first_trb = true;
3289                 running_total = 0;
3290                 addr = start_addr + urb->iso_frame_desc[i].offset;
3291                 td_len = urb->iso_frame_desc[i].length;
3292                 td_remain_len = td_len;
3293                 total_packet_count = roundup(td_len,
3294                                 usb_endpoint_maxp(&urb->ep->desc));
3295                 /* A zero-length transfer still involves at least one packet. */
3296                 if (total_packet_count == 0)
3297                         total_packet_count++;
3298                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3299                                 total_packet_count);
3300                 residue = xhci_get_last_burst_packet_count(xhci,
3301                                 urb->dev, urb, total_packet_count);
3302
3303                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3304
3305                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3306                                 urb->stream_id, trbs_per_td, urb, i, true,
3307                                 mem_flags);
3308                 if (ret < 0) {
3309                         if (i == 0)
3310                                 return ret;
3311                         goto cleanup;
3312                 }
3313
3314                 td = urb_priv->td[i];
3315                 for (j = 0; j < trbs_per_td; j++) {
3316                         u32 remainder = 0;
3317                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3318
3319                         if (first_trb) {
3320                                 /* Queue the isoc TRB */
3321                                 field |= TRB_TYPE(TRB_ISOC);
3322                                 /* Assume URB_ISO_ASAP is set */
3323                                 field |= TRB_SIA;
3324                                 if (i == 0) {
3325                                         if (start_cycle == 0)
3326                                                 field |= 0x1;
3327                                 } else
3328                                         field |= ep_ring->cycle_state;
3329                                 first_trb = false;
3330                         } else {
3331                                 /* Queue other normal TRBs */
3332                                 field |= TRB_TYPE(TRB_NORMAL);
3333                                 field |= ep_ring->cycle_state;
3334                         }
3335
3336                         /* Only set interrupt on short packet for IN EPs */
3337                         if (usb_urb_dir_in(urb))
3338                                 field |= TRB_ISP;
3339
3340                         /* Chain all the TRBs together; clear the chain bit in
3341                          * the last TRB to indicate it's the last TRB in the
3342                          * chain.
3343                          */
3344                         if (j < trbs_per_td - 1) {
3345                                 field |= TRB_CHAIN;
3346                                 more_trbs_coming = true;
3347                         } else {
3348                                 td->last_trb = ep_ring->enqueue;
3349                                 field |= TRB_IOC;
3350                                 if (xhci->hci_version == 0x100) {
3351                                         /* Set BEI bit except for the last td */
3352                                         if (i < num_tds - 1)
3353                                                 field |= TRB_BEI;
3354                                 }
3355                                 more_trbs_coming = false;
3356                         }
3357
3358                         /* Calculate TRB length */
3359                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3360                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3361                         if (trb_buff_len > td_remain_len)
3362                                 trb_buff_len = td_remain_len;
3363
3364                         /* Set the TRB length, TD size, & interrupter fields. */
3365                         if (xhci->hci_version < 0x100) {
3366                                 remainder = xhci_td_remainder(
3367                                                 td_len - running_total);
3368                         } else {
3369                                 remainder = xhci_v1_0_td_remainder(
3370                                                 running_total, trb_buff_len,
3371                                                 total_packet_count, urb);
3372                         }
3373                         length_field = TRB_LEN(trb_buff_len) |
3374                                 remainder |
3375                                 TRB_INTR_TARGET(0);
3376
3377                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3378                                 lower_32_bits(addr),
3379                                 upper_32_bits(addr),
3380                                 length_field,
3381                                 field);
3382                         running_total += trb_buff_len;
3383
3384                         addr += trb_buff_len;
3385                         td_remain_len -= trb_buff_len;
3386                 }
3387
3388                 /* Check TD length */
3389                 if (running_total != td_len) {
3390                         xhci_err(xhci, "ISOC TD length unmatch\n");
3391                         ret = -EINVAL;
3392                         goto cleanup;
3393                 }
3394         }
3395
3396         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3397                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3398                         usb_amd_quirk_pll_disable();
3399         }
3400         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3401
3402         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3403                         start_cycle, start_trb);
3404         return 0;
3405 cleanup:
3406         /* Clean up a partially enqueued isoc transfer. */
3407
3408         for (i--; i >= 0; i--)
3409                 list_del_init(&urb_priv->td[i]->td_list);
3410
3411         /* Use the first TD as a temporary variable to turn the TDs we've queued
3412          * into No-ops with a software-owned cycle bit. That way the hardware
3413          * won't accidentally start executing bogus TDs when we partially
3414          * overwrite them.  td->first_trb and td->start_seg are already set.
3415          */
3416         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3417         /* Every TRB except the first & last will have its cycle bit flipped. */
3418         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3419
3420         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3421         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3422         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3423         ep_ring->cycle_state = start_cycle;
3424         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3425         return ret;
3426 }
3427
3428 /*
3429  * Check transfer ring to guarantee there is enough room for the urb.
3430  * Update ISO URB start_frame and interval.
3431  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3432  * update the urb->start_frame by now.
3433  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3434  */
3435 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3436                 struct urb *urb, int slot_id, unsigned int ep_index)
3437 {
3438         struct xhci_virt_device *xdev;
3439         struct xhci_ring *ep_ring;
3440         struct xhci_ep_ctx *ep_ctx;
3441         int start_frame;
3442         int xhci_interval;
3443         int ep_interval;
3444         int num_tds, num_trbs, i;
3445         int ret;
3446
3447         xdev = xhci->devs[slot_id];
3448         ep_ring = xdev->eps[ep_index].ring;
3449         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3450
3451         num_trbs = 0;
3452         num_tds = urb->number_of_packets;
3453         for (i = 0; i < num_tds; i++)
3454                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3455
3456         /* Check the ring to guarantee there is enough room for the whole urb.
3457          * Do not insert any td of the urb to the ring if the check failed.
3458          */
3459         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3460                            num_trbs, true, mem_flags);
3461         if (ret)
3462                 return ret;
3463
3464         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3465         start_frame &= 0x3fff;
3466
3467         urb->start_frame = start_frame;
3468         if (urb->dev->speed == USB_SPEED_LOW ||
3469                         urb->dev->speed == USB_SPEED_FULL)
3470                 urb->start_frame >>= 3;
3471
3472         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3473         ep_interval = urb->interval;
3474         /* Convert to microframes */
3475         if (urb->dev->speed == USB_SPEED_LOW ||
3476                         urb->dev->speed == USB_SPEED_FULL)
3477                 ep_interval *= 8;
3478         /* FIXME change this to a warning and a suggestion to use the new API
3479          * to set the polling interval (once the API is added).
3480          */
3481         if (xhci_interval != ep_interval) {
3482                 if (printk_ratelimit())
3483                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3484                                         " (%d microframe%s) than xHCI "
3485                                         "(%d microframe%s)\n",
3486                                         ep_interval,
3487                                         ep_interval == 1 ? "" : "s",
3488                                         xhci_interval,
3489                                         xhci_interval == 1 ? "" : "s");
3490                 urb->interval = xhci_interval;
3491                 /* Convert back to frames for LS/FS devices */
3492                 if (urb->dev->speed == USB_SPEED_LOW ||
3493                                 urb->dev->speed == USB_SPEED_FULL)
3494                         urb->interval /= 8;
3495         }
3496         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3497 }
3498
3499 /****           Command Ring Operations         ****/
3500
3501 /* Generic function for queueing a command TRB on the command ring.
3502  * Check to make sure there's room on the command ring for one command TRB.
3503  * Also check that there's room reserved for commands that must not fail.
3504  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3505  * then only check for the number of reserved spots.
3506  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3507  * because the command event handler may want to resubmit a failed command.
3508  */
3509 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3510                 u32 field3, u32 field4, bool command_must_succeed)
3511 {
3512         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3513         int ret;
3514
3515         if (!command_must_succeed)
3516                 reserved_trbs++;
3517
3518         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3519                         reserved_trbs, false, GFP_ATOMIC);
3520         if (ret < 0) {
3521                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3522                 if (command_must_succeed)
3523                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3524                                         "unfailable commands failed.\n");
3525                 return ret;
3526         }
3527         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3528                         field3, field4 | xhci->cmd_ring->cycle_state);
3529         return 0;
3530 }
3531
3532 /* Queue a slot enable or disable request on the command ring */
3533 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3534 {
3535         return queue_command(xhci, 0, 0, 0,
3536                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3537 }
3538
3539 /* Queue an address device command TRB */
3540 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3541                 u32 slot_id)
3542 {
3543         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3544                         upper_32_bits(in_ctx_ptr), 0,
3545                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3546                         false);
3547 }
3548
3549 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3550                 u32 field1, u32 field2, u32 field3, u32 field4)
3551 {
3552         return queue_command(xhci, field1, field2, field3, field4, false);
3553 }
3554
3555 /* Queue a reset device command TRB */
3556 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3557 {
3558         return queue_command(xhci, 0, 0, 0,
3559                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3560                         false);
3561 }
3562
3563 /* Queue a configure endpoint command TRB */
3564 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3565                 u32 slot_id, bool command_must_succeed)
3566 {
3567         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3568                         upper_32_bits(in_ctx_ptr), 0,
3569                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3570                         command_must_succeed);
3571 }
3572
3573 /* Queue an evaluate context command TRB */
3574 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3575                 u32 slot_id)
3576 {
3577         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3578                         upper_32_bits(in_ctx_ptr), 0,
3579                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3580                         false);
3581 }
3582
3583 /*
3584  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3585  * activity on an endpoint that is about to be suspended.
3586  */
3587 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3588                 unsigned int ep_index, int suspend)
3589 {
3590         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3591         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3592         u32 type = TRB_TYPE(TRB_STOP_RING);
3593         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3594
3595         return queue_command(xhci, 0, 0, 0,
3596                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3597 }
3598
3599 /* Set Transfer Ring Dequeue Pointer command.
3600  * This should not be used for endpoints that have streams enabled.
3601  */
3602 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3603                 unsigned int ep_index, unsigned int stream_id,
3604                 struct xhci_segment *deq_seg,
3605                 union xhci_trb *deq_ptr, u32 cycle_state)
3606 {
3607         dma_addr_t addr;
3608         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3609         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3610         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3611         u32 type = TRB_TYPE(TRB_SET_DEQ);
3612         struct xhci_virt_ep *ep;
3613
3614         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3615         if (addr == 0) {
3616                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3617                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3618                                 deq_seg, deq_ptr);
3619                 return 0;
3620         }
3621         ep = &xhci->devs[slot_id]->eps[ep_index];
3622         if ((ep->ep_state & SET_DEQ_PENDING)) {
3623                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3624                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3625                 return 0;
3626         }
3627         ep->queued_deq_seg = deq_seg;
3628         ep->queued_deq_ptr = deq_ptr;
3629         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3630                         upper_32_bits(addr), trb_stream_id,
3631                         trb_slot_id | trb_ep_index | type, false);
3632 }
3633
3634 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3635                 unsigned int ep_index)
3636 {
3637         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3638         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3639         u32 type = TRB_TYPE(TRB_RESET_EP);
3640
3641         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3642                         false);
3643 }