drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                 }
 159                 ring->deq_seg = ring->deq_seg->next;
 160                 ring->dequeue = ring->deq_seg->trbs;
 161                 next = ring->dequeue;
 162         }
 163         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 164 }
 165
 166 /*
 167  * See Cycle bit rules. SW is the consumer for the event ring only.
 168  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 169  *
 170  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 171  * chain bit is set), then set the chain bit in all the following link TRBs.
 172  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 173  * have their chain bit cleared (so that each Link TRB is a separate TD).
 174  *
 175  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 176  * set, but other sections talk about dealing with the chain bit set.  This was
 177  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 178  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 179  *
 180  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 181  *                      prepare_transfer()?
 182  */
 183 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 184                 bool consumer, bool more_trbs_coming, bool isoc)
 185 {
 186         u32 chain;
 187         union xhci_trb *next;
 188         unsigned long long addr;
 189
 190         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 191         next = ++(ring->enqueue);
 192
 193         ring->enq_updates++;
 194         /* Update the dequeue pointer further if that was a link TRB or we're at
 195          * the end of an event ring segment (which doesn't have link TRBS)
 196          */
 197         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 198                 if (!consumer) {
 199                         if (ring != xhci->event_ring) {
 200                                 /*
 201                                  * If the caller doesn't plan on enqueueing more
 202                                  * TDs before ringing the doorbell, then we
 203                                  * don't want to give the link TRB to the
 204                                  * hardware just yet.  We'll give the link TRB
 205                                  * back in prepare_ring() just before we enqueue
 206                                  * the TD at the top of the ring.
 207                                  */
 208                                 if (!chain && !more_trbs_coming)
 209                                         break;
 210
 211                                 /* If we're not dealing with 0.95 hardware or
 212                                  * isoc rings on AMD 0.96 host,
 213                                  * carry over the chain bit of the previous TRB
 214                                  * (which may mean the chain bit is cleared).
 215                                  */
 216                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 217                                                 && !xhci_link_trb_quirk(xhci)) {
 218                                         next->link.control &=
 219                                                 cpu_to_le32(~TRB_CHAIN);
 220                                         next->link.control |=
 221                                                 cpu_to_le32(chain);
 222                                 }
 223                                 /* Give this link TRB to the hardware */
 224                                 wmb();
 225                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 226                         }
 227                         /* Toggle the cycle bit after the last ring segment. */
 228                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 229                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 230                         }
 231                 }
 232                 ring->enq_seg = ring->enq_seg->next;
 233                 ring->enqueue = ring->enq_seg->trbs;
 234                 next = ring->enqueue;
 235         }
 236         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 237 }
 238
 239 /*
 240  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 241  * above.
 242  * FIXME: this would be simpler and faster if we just kept track of the number
 243  * of free TRBs in a ring.
 244  */
 245 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 246                 unsigned int num_trbs)
 247 {
 248         int i;
 249         union xhci_trb *enq = ring->enqueue;
 250         struct xhci_segment *enq_seg = ring->enq_seg;
 251         struct xhci_segment *cur_seg;
 252         unsigned int left_on_ring;
 253
 254         /* If we are currently pointing to a link TRB, advance the
 255          * enqueue pointer before checking for space */
 256         while (last_trb(xhci, ring, enq_seg, enq)) {
 257                 enq_seg = enq_seg->next;
 258                 enq = enq_seg->trbs;
 259         }
 260
 261         /* Check if ring is empty */
 262         if (enq == ring->dequeue) {
 263                 /* Can't use link trbs */
 264                 left_on_ring = TRBS_PER_SEGMENT - 1;
 265                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 266                                 cur_seg = cur_seg->next)
 267                         left_on_ring += TRBS_PER_SEGMENT - 1;
 268
 269                 /* Always need one TRB free in the ring. */
 270                 left_on_ring -= 1;
 271                 if (num_trbs > left_on_ring) {
 272                         xhci_warn(xhci, "Not enough room on ring; "
 273                                         "need %u TRBs, %u TRBs left\n",
 274                                         num_trbs, left_on_ring);
 275                         return 0;
 276                 }
 277                 return 1;
 278         }
 279         /* Make sure there's an extra empty TRB available */
 280         for (i = 0; i <= num_trbs; ++i) {
 281                 if (enq == ring->dequeue)
 282                         return 0;
 283                 enq++;
 284                 while (last_trb(xhci, ring, enq_seg, enq)) {
 285                         enq_seg = enq_seg->next;
 286                         enq = enq_seg->trbs;
 287                 }
 288         }
 289         return 1;
 290 }
 291
 292 /* Ring the host controller doorbell after placing a command on the ring */
 293 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 294 {
 295         xhci_dbg(xhci, "// Ding dong!\n");
 296         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 297         /* Flush PCI posted writes */
 298         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 299 }
 300
 301 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 302                 unsigned int slot_id,
 303                 unsigned int ep_index,
 304                 unsigned int stream_id)
 305 {
 306         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 307         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 308         unsigned int ep_state = ep->ep_state;
 309
 310         /* Don't ring the doorbell for this endpoint if there are pending
 311          * cancellations because we don't want to interrupt processing.
 312          * We don't want to restart any stream rings if there's a set dequeue
 313          * pointer command pending because the device can choose to start any
 314          * stream once the endpoint is on the HW schedule.
 315          * FIXME - check all the stream rings for pending cancellations.
 316          */
 317         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 318             (ep_state & EP_HALTED))
 319                 return;
 320         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 321         /* The CPU has better things to do at this point than wait for a
 322          * write-posting flush.  It'll get there soon enough.
 323          */
 324 }
 325
 326 /* Ring the doorbell for any rings with pending URBs */
 327 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 328                 unsigned int slot_id,
 329                 unsigned int ep_index)
 330 {
 331         unsigned int stream_id;
 332         struct xhci_virt_ep *ep;
 333
 334         ep = &xhci->devs[slot_id]->eps[ep_index];
 335
 336         /* A ring has pending URBs if its TD list is not empty */
 337         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 338                 if (!(list_empty(&ep->ring->td_list)))
 339                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 340                 return;
 341         }
 342
 343         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 344                         stream_id++) {
 345                 struct xhci_stream_info *stream_info = ep->stream_info;
 346                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 347                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 348                                                 stream_id);
 349         }
 350 }
 351
 352 /*
 353  * Find the segment that trb is in.  Start searching in start_seg.
 354  * If we must move past a segment that has a link TRB with a toggle cycle state
 355  * bit set, then we will toggle the value pointed at by cycle_state.
 356  */
 357 static struct xhci_segment *find_trb_seg(
 358                 struct xhci_segment *start_seg,
 359                 union xhci_trb  *trb, int *cycle_state)
 360 {
 361         struct xhci_segment *cur_seg = start_seg;
 362         struct xhci_generic_trb *generic_trb;
 363
 364         while (cur_seg->trbs > trb ||
 365                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 366                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 367                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 368                         *cycle_state ^= 0x1;
 369                 cur_seg = cur_seg->next;
 370                 if (cur_seg == start_seg)
 371                         /* Looped over the entire list.  Oops! */
 372                         return NULL;
 373         }
 374         return cur_seg;
 375 }
 376
 377
 378 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 379                 unsigned int slot_id, unsigned int ep_index,
 380                 unsigned int stream_id)
 381 {
 382         struct xhci_virt_ep *ep;
 383
 384         ep = &xhci->devs[slot_id]->eps[ep_index];
 385         /* Common case: no streams */
 386         if (!(ep->ep_state & EP_HAS_STREAMS))
 387                 return ep->ring;
 388
 389         if (stream_id == 0) {
 390                 xhci_warn(xhci,
 391                                 "WARN: Slot ID %u, ep index %u has streams, "
 392                                 "but URB has no stream ID.\n",
 393                                 slot_id, ep_index);
 394                 return NULL;
 395         }
 396
 397         if (stream_id < ep->stream_info->num_streams)
 398                 return ep->stream_info->stream_rings[stream_id];
 399
 400         xhci_warn(xhci,
 401                         "WARN: Slot ID %u, ep index %u has "
 402                         "stream IDs 1 to %u allocated, "
 403                         "but stream ID %u is requested.\n",
 404                         slot_id, ep_index,
 405                         ep->stream_info->num_streams - 1,
 406                         stream_id);
 407         return NULL;
 408 }
 409
 410 /* Get the right ring for the given URB.
 411  * If the endpoint supports streams, boundary check the URB's stream ID.
 412  * If the endpoint doesn't support streams, return the singular endpoint ring.
 413  */
 414 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 415                 struct urb *urb)
 416 {
 417         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 418                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 419 }
 420
 421 /*
 422  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 423  * Record the new state of the xHC's endpoint ring dequeue segment,
 424  * dequeue pointer, and new consumer cycle state in state.
 425  * Update our internal representation of the ring's dequeue pointer.
 426  *
 427  * We do this in three jumps:
 428  *  - First we update our new ring state to be the same as when the xHC stopped.
 429  *  - Then we traverse the ring to find the segment that contains
 430  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 431  *    any link TRBs with the toggle cycle bit set.
 432  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 433  *    if we've moved it past a link TRB with the toggle cycle bit set.
 434  *
 435  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 436  * with correct __le32 accesses they should work fine.  Only users of this are
 437  * in here.
 438  */
 439 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 440                 unsigned int slot_id, unsigned int ep_index,
 441                 unsigned int stream_id, struct xhci_td *cur_td,
 442                 struct xhci_dequeue_state *state)
 443 {
 444         struct xhci_virt_device *dev = xhci->devs[slot_id];
 445         struct xhci_ring *ep_ring;
 446         struct xhci_generic_trb *trb;
 447         struct xhci_ep_ctx *ep_ctx;
 448         dma_addr_t addr;
 449
 450         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 451                         ep_index, stream_id);
 452         if (!ep_ring) {
 453                 xhci_warn(xhci, "WARN can't find new dequeue state "
 454                                 "for invalid stream ID %u.\n",
 455                                 stream_id);
 456                 return;
 457         }
 458         state->new_cycle_state = 0;
 459         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 460         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 461                         dev->eps[ep_index].stopped_trb,
 462                         &state->new_cycle_state);
 463         if (!state->new_deq_seg) {
 464                 WARN_ON(1);
 465                 return;
 466         }
 467
 468         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 469         xhci_dbg(xhci, "Finding endpoint context\n");
 470         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 471         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 472
 473         state->new_deq_ptr = cur_td->last_trb;
 474         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 475         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 476                         state->new_deq_ptr,
 477                         &state->new_cycle_state);
 478         if (!state->new_deq_seg) {
 479                 WARN_ON(1);
 480                 return;
 481         }
 482
 483         trb = &state->new_deq_ptr->generic;
 484         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 485             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 486                 state->new_cycle_state ^= 0x1;
 487         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 488
 489         /*
 490          * If there is only one segment in a ring, find_trb_seg()'s while loop
 491          * will not run, and it will return before it has a chance to see if it
 492          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 493          * ended just before the link TRB on a one-segment ring, or if the TD
 494          * wrapped around the top of the ring, because it doesn't have the TD in
 495          * question.  Look for the one-segment case where stalled TRB's address
 496          * is greater than the new dequeue pointer address.
 497          */
 498         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 499                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 500                 state->new_cycle_state ^= 0x1;
 501         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 502
 503         /* Don't update the ring cycle state for the producer (us). */
 504         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 505                         state->new_deq_seg);
 506         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 507         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 508                         (unsigned long long) addr);
 509 }
 510
 511 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 512  * (The last TRB actually points to the ring enqueue pointer, which is not part
 513  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 514  */
 515 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 516                 struct xhci_td *cur_td, bool flip_cycle)
 517 {
 518         struct xhci_segment *cur_seg;
 519         union xhci_trb *cur_trb;
 520
 521         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 522                         true;
 523                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 524                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 525                         /* Unchain any chained Link TRBs, but
 526                          * leave the pointers intact.
 527                          */
 528                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 529                         /* Flip the cycle bit (link TRBs can't be the first
 530                          * or last TRB).
 531                          */
 532                         if (flip_cycle)
 533                                 cur_trb->generic.field[3] ^=
 534                                         cpu_to_le32(TRB_CYCLE);
 535                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 536                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 537                                         "in seg %p (0x%llx dma)\n",
 538                                         cur_trb,
 539                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 540                                         cur_seg,
 541                                         (unsigned long long)cur_seg->dma);
 542                 } else {
 543                         cur_trb->generic.field[0] = 0;
 544                         cur_trb->generic.field[1] = 0;
 545                         cur_trb->generic.field[2] = 0;
 546                         /* Preserve only the cycle bit of this TRB */
 547                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 548                         /* Flip the cycle bit except on the first or last TRB */
 549                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 550                                         cur_trb != cur_td->last_trb)
 551                                 cur_trb->generic.field[3] ^=
 552                                         cpu_to_le32(TRB_CYCLE);
 553                         cur_trb->generic.field[3] |= cpu_to_le32(
 554                                 TRB_TYPE(TRB_TR_NOOP));
 555                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 556                                         (unsigned long long)
 557                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 558                 }
 559                 if (cur_trb == cur_td->last_trb)
 560                         break;
 561         }
 562 }
 563
 564 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 565                 unsigned int ep_index, unsigned int stream_id,
 566                 struct xhci_segment *deq_seg,
 567                 union xhci_trb *deq_ptr, u32 cycle_state);
 568
 569 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 570                 unsigned int slot_id, unsigned int ep_index,
 571                 unsigned int stream_id,
 572                 struct xhci_dequeue_state *deq_state)
 573 {
 574         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 575
 576         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 577                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 578                         deq_state->new_deq_seg,
 579                         (unsigned long long)deq_state->new_deq_seg->dma,
 580                         deq_state->new_deq_ptr,
 581                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 582                         deq_state->new_cycle_state);
 583         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 584                         deq_state->new_deq_seg,
 585                         deq_state->new_deq_ptr,
 586                         (u32) deq_state->new_cycle_state);
 587         /* Stop the TD queueing code from ringing the doorbell until
 588          * this command completes.  The HC won't set the dequeue pointer
 589          * if the ring is running, and ringing the doorbell starts the
 590          * ring running.
 591          */
 592         ep->ep_state |= SET_DEQ_PENDING;
 593 }
 594
 595 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 596                 struct xhci_virt_ep *ep)
 597 {
 598         ep->ep_state &= ~EP_HALT_PENDING;
 599         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 600          * timer is running on another CPU, we don't decrement stop_cmds_pending
 601          * (since we didn't successfully stop the watchdog timer).
 602          */
 603         if (del_timer(&ep->stop_cmd_timer))
 604                 ep->stop_cmds_pending--;
 605 }
 606
 607 /* Must be called with xhci->lock held in interrupt context */
 608 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 609                 struct xhci_td *cur_td, int status, char *adjective)
 610 {
 611         struct usb_hcd *hcd;
 612         struct urb      *urb;
 613         struct urb_priv *urb_priv;
 614
 615         urb = cur_td->urb;
 616         urb_priv = urb->hcpriv;
 617         urb_priv->td_cnt++;
 618         hcd = bus_to_hcd(urb->dev->bus);
 619
 620         /* Only giveback urb when this is the last td in urb */
 621         if (urb_priv->td_cnt == urb_priv->length) {
 622                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 623                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 624                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 625                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 626                                         usb_amd_quirk_pll_enable();
 627                         }
 628                 }
 629                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 630
 631                 spin_unlock(&xhci->lock);
 632                 usb_hcd_giveback_urb(hcd, urb, status);
 633                 xhci_urb_free_priv(xhci, urb_priv);
 634                 spin_lock(&xhci->lock);
 635         }
 636 }
 637
 638 /*
 639  * When we get a command completion for a Stop Endpoint Command, we need to
 640  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 641  *
 642  *  1. If the HW was in the middle of processing the TD that needs to be
 643  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 644  *     in the TD with a Set Dequeue Pointer Command.
 645  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 646  *     bit cleared) so that the HW will skip over them.
 647  */
 648 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 649                 union xhci_trb *trb, struct xhci_event_cmd *event)
 650 {
 651         unsigned int slot_id;
 652         unsigned int ep_index;
 653         struct xhci_virt_device *virt_dev;
 654         struct xhci_ring *ep_ring;
 655         struct xhci_virt_ep *ep;
 656         struct list_head *entry;
 657         struct xhci_td *cur_td = NULL;
 658         struct xhci_td *last_unlinked_td;
 659
 660         struct xhci_dequeue_state deq_state;
 661
 662         if (unlikely(TRB_TO_SUSPEND_PORT(
 663                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 664                 slot_id = TRB_TO_SLOT_ID(
 665                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 666                 virt_dev = xhci->devs[slot_id];
 667                 if (virt_dev)
 668                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 669                                 event);
 670                 else
 671                         xhci_warn(xhci, "Stop endpoint command "
 672                                 "completion for disabled slot %u\n",
 673                                 slot_id);
 674                 return;
 675         }
 676
 677         memset(&deq_state, 0, sizeof(deq_state));
 678         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 679         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 680         ep = &xhci->devs[slot_id]->eps[ep_index];
 681
 682         if (list_empty(&ep->cancelled_td_list)) {
 683                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 684                 ep->stopped_td = NULL;
 685                 ep->stopped_trb = NULL;
 686                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 687                 return;
 688         }
 689
 690         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 691          * We have the xHCI lock, so nothing can modify this list until we drop
 692          * it.  We're also in the event handler, so we can't get re-interrupted
 693          * if another Stop Endpoint command completes
 694          */
 695         list_for_each(entry, &ep->cancelled_td_list) {
 696                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 697                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 698                                 (unsigned long long)xhci_trb_virt_to_dma(
 699                                         cur_td->start_seg, cur_td->first_trb));
 700                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 701                 if (!ep_ring) {
 702                         /* This shouldn't happen unless a driver is mucking
 703                          * with the stream ID after submission.  This will
 704                          * leave the TD on the hardware ring, and the hardware
 705                          * will try to execute it, and may access a buffer
 706                          * that has already been freed.  In the best case, the
 707                          * hardware will execute it, and the event handler will
 708                          * ignore the completion event for that TD, since it was
 709                          * removed from the td_list for that endpoint.  In
 710                          * short, don't muck with the stream ID after
 711                          * submission.
 712                          */
 713                         xhci_warn(xhci, "WARN Cancelled URB %p "
 714                                         "has invalid stream ID %u.\n",
 715                                         cur_td->urb,
 716                                         cur_td->urb->stream_id);
 717                         goto remove_finished_td;
 718                 }
 719                 /*
 720                  * If we stopped on the TD we need to cancel, then we have to
 721                  * move the xHC endpoint ring dequeue pointer past this TD.
 722                  */
 723                 if (cur_td == ep->stopped_td)
 724                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 725                                         cur_td->urb->stream_id,
 726                                         cur_td, &deq_state);
 727                 else
 728                         td_to_noop(xhci, ep_ring, cur_td, false);
 729 remove_finished_td:
 730                 /*
 731                  * The event handler won't see a completion for this TD anymore,
 732                  * so remove it from the endpoint ring's TD list.  Keep it in
 733                  * the cancelled TD list for URB completion later.
 734                  */
 735                 list_del_init(&cur_td->td_list);
 736         }
 737         last_unlinked_td = cur_td;
 738         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 739
 740         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 741         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 742                 xhci_queue_new_dequeue_state(xhci,
 743                                 slot_id, ep_index,
 744                                 ep->stopped_td->urb->stream_id,
 745                                 &deq_state);
 746                 xhci_ring_cmd_db(xhci);
 747         } else {
 748                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 749                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 750         }
 751         ep->stopped_td = NULL;
 752         ep->stopped_trb = NULL;
 753
 754         /*
 755          * Drop the lock and complete the URBs in the cancelled TD list.
 756          * New TDs to be cancelled might be added to the end of the list before
 757          * we can complete all the URBs for the TDs we already unlinked.
 758          * So stop when we've completed the URB for the last TD we unlinked.
 759          */
 760         do {
 761                 cur_td = list_entry(ep->cancelled_td_list.next,
 762                                 struct xhci_td, cancelled_td_list);
 763                 list_del_init(&cur_td->cancelled_td_list);
 764
 765                 /* Clean up the cancelled URB */
 766                 /* Doesn't matter what we pass for status, since the core will
 767                  * just overwrite it (because the URB has been unlinked).
 768                  */
 769                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 770
 771                 /* Stop processing the cancelled list if the watchdog timer is
 772                  * running.
 773                  */
 774                 if (xhci->xhc_state & XHCI_STATE_DYING)
 775                         return;
 776         } while (cur_td != last_unlinked_td);
 777
 778         /* Return to the event handler with xhci->lock re-acquired */
 779 }
 780
 781 /* Watchdog timer function for when a stop endpoint command fails to complete.
 782  * In this case, we assume the host controller is broken or dying or dead.  The
 783  * host may still be completing some other events, so we have to be careful to
 784  * let the event ring handler and the URB dequeueing/enqueueing functions know
 785  * through xhci->state.
 786  *
 787  * The timer may also fire if the host takes a very long time to respond to the
 788  * command, and the stop endpoint command completion handler cannot delete the
 789  * timer before the timer function is called.  Another endpoint cancellation may
 790  * sneak in before the timer function can grab the lock, and that may queue
 791  * another stop endpoint command and add the timer back.  So we cannot use a
 792  * simple flag to say whether there is a pending stop endpoint command for a
 793  * particular endpoint.
 794  *
 795  * Instead we use a combination of that flag and a counter for the number of
 796  * pending stop endpoint commands.  If the timer is the tail end of the last
 797  * stop endpoint command, and the endpoint's command is still pending, we assume
 798  * the host is dying.
 799  */
 800 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 801 {
 802         struct xhci_hcd *xhci;
 803         struct xhci_virt_ep *ep;
 804         struct xhci_virt_ep *temp_ep;
 805         struct xhci_ring *ring;
 806         struct xhci_td *cur_td;
 807         int ret, i, j;
 808         unsigned long flags;
 809
 810         ep = (struct xhci_virt_ep *) arg;
 811         xhci = ep->xhci;
 812
 813         spin_lock_irqsave(&xhci->lock, flags);
 814
 815         ep->stop_cmds_pending--;
 816         if (xhci->xhc_state & XHCI_STATE_DYING) {
 817                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 818                                 "xHCI as DYING, exiting.\n");
 819                 spin_unlock_irqrestore(&xhci->lock, flags);
 820                 return;
 821         }
 822         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 823                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 824                                 "exiting.\n");
 825                 spin_unlock_irqrestore(&xhci->lock, flags);
 826                 return;
 827         }
 828
 829         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 830         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 831         /* Oops, HC is dead or dying or at least not responding to the stop
 832          * endpoint command.
 833          */
 834         xhci->xhc_state |= XHCI_STATE_DYING;
 835         /* Disable interrupts from the host controller and start halting it */
 836         xhci_quiesce(xhci);
 837         spin_unlock_irqrestore(&xhci->lock, flags);
 838
 839         ret = xhci_halt(xhci);
 840
 841         spin_lock_irqsave(&xhci->lock, flags);
 842         if (ret < 0) {
 843                 /* This is bad; the host is not responding to commands and it's
 844                  * not allowing itself to be halted.  At least interrupts are
 845                  * disabled. If we call usb_hc_died(), it will attempt to
 846                  * disconnect all device drivers under this host.  Those
 847                  * disconnect() methods will wait for all URBs to be unlinked,
 848                  * so we must complete them.
 849                  */
 850                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 851                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 852                 /* We could turn all TDs on the rings to no-ops.  This won't
 853                  * help if the host has cached part of the ring, and is slow if
 854                  * we want to preserve the cycle bit.  Skip it and hope the host
 855                  * doesn't touch the memory.
 856                  */
 857         }
 858         for (i = 0; i < MAX_HC_SLOTS; i++) {
 859                 if (!xhci->devs[i])
 860                         continue;
 861                 for (j = 0; j < 31; j++) {
 862                         temp_ep = &xhci->devs[i]->eps[j];
 863                         ring = temp_ep->ring;
 864                         if (!ring)
 865                                 continue;
 866                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 867                                         "ep index %u\n", i, j);
 868                         while (!list_empty(&ring->td_list)) {
 869                                 cur_td = list_first_entry(&ring->td_list,
 870                                                 struct xhci_td,
 871                                                 td_list);
 872                                 list_del_init(&cur_td->td_list);
 873                                 if (!list_empty(&cur_td->cancelled_td_list))
 874                                         list_del_init(&cur_td->cancelled_td_list);
 875                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 876                                                 -ESHUTDOWN, "killed");
 877                         }
 878                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 879                                 cur_td = list_first_entry(
 880                                                 &temp_ep->cancelled_td_list,
 881                                                 struct xhci_td,
 882                                                 cancelled_td_list);
 883                                 list_del_init(&cur_td->cancelled_td_list);
 884                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 885                                                 -ESHUTDOWN, "killed");
 886                         }
 887                 }
 888         }
 889         spin_unlock_irqrestore(&xhci->lock, flags);
 890         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 891         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 892         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 893 }
 894
 895 /*
 896  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 897  * we need to clear the set deq pending flag in the endpoint ring state, so that
 898  * the TD queueing code can ring the doorbell again.  We also need to ring the
 899  * endpoint doorbell to restart the ring, but only if there aren't more
 900  * cancellations pending.
 901  */
 902 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 903                 struct xhci_event_cmd *event,
 904                 union xhci_trb *trb)
 905 {
 906         unsigned int slot_id;
 907         unsigned int ep_index;
 908         unsigned int stream_id;
 909         struct xhci_ring *ep_ring;
 910         struct xhci_virt_device *dev;
 911         struct xhci_ep_ctx *ep_ctx;
 912         struct xhci_slot_ctx *slot_ctx;
 913
 914         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 915         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 916         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 917         dev = xhci->devs[slot_id];
 918
 919         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 920         if (!ep_ring) {
 921                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 922                                 "freed stream ID %u\n",
 923                                 stream_id);
 924                 /* XXX: Harmless??? */
 925                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 926                 return;
 927         }
 928
 929         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 930         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 931
 932         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 933                 unsigned int ep_state;
 934                 unsigned int slot_state;
 935
 936                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 937                 case COMP_TRB_ERR:
 938                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 939                                         "of stream ID configuration\n");
 940                         break;
 941                 case COMP_CTX_STATE:
 942                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 943                                         "to incorrect slot or ep state.\n");
 944                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 945                         ep_state &= EP_STATE_MASK;
 946                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 947                         slot_state = GET_SLOT_STATE(slot_state);
 948                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 949                                         slot_state, ep_state);
 950                         break;
 951                 case COMP_EBADSLT:
 952                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 953                                         "slot %u was not enabled.\n", slot_id);
 954                         break;
 955                 default:
 956                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 957                                         "completion code of %u.\n",
 958                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 959                         break;
 960                 }
 961                 /* OK what do we do now?  The endpoint state is hosed, and we
 962                  * should never get to this point if the synchronization between
 963                  * queueing, and endpoint state are correct.  This might happen
 964                  * if the device gets disconnected after we've finished
 965                  * cancelling URBs, which might not be an error...
 966                  */
 967         } else {
 968                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 969                          le64_to_cpu(ep_ctx->deq));
 970                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 971                                          dev->eps[ep_index].queued_deq_ptr) ==
 972                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 973                         /* Update the ring's dequeue segment and dequeue pointer
 974                          * to reflect the new position.
 975                          */
 976                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 977                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 978                 } else {
 979                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 980                                         "Ptr command & xHCI internal state.\n");
 981                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 982                                         dev->eps[ep_index].queued_deq_seg,
 983                                         dev->eps[ep_index].queued_deq_ptr);
 984                 }
 985         }
 986
 987         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 988         dev->eps[ep_index].queued_deq_seg = NULL;
 989         dev->eps[ep_index].queued_deq_ptr = NULL;
 990         /* Restart any rings with pending URBs */
 991         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 992 }
 993
 994 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 995                 struct xhci_event_cmd *event,
 996                 union xhci_trb *trb)
 997 {
 998         int slot_id;
 999         unsigned int ep_index;
1000
1001         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1002         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1003         /* This command will only fail if the endpoint wasn't halted,
1004          * but we don't care.
1005          */
1006         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1007                  GET_COMP_CODE(le32_to_cpu(event->status)));
1008
1009         /* HW with the reset endpoint quirk needs to have a configure endpoint
1010          * command complete before the endpoint can be used.  Queue that here
1011          * because the HW can't handle two commands being queued in a row.
1012          */
1013         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1014                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1015                 xhci_queue_configure_endpoint(xhci,
1016                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1017                                 false);
1018                 xhci_ring_cmd_db(xhci);
1019         } else {
1020                 /* Clear our internal halted state and restart the ring(s) */
1021                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1022                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1023         }
1024 }
1025
1026 /* Check to see if a command in the device's command queue matches this one.
1027  * Signal the completion or free the command, and return 1.  Return 0 if the
1028  * completed command isn't at the head of the command list.
1029  */
1030 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1031                 struct xhci_virt_device *virt_dev,
1032                 struct xhci_event_cmd *event)
1033 {
1034         struct xhci_command *command;
1035
1036         if (list_empty(&virt_dev->cmd_list))
1037                 return 0;
1038
1039         command = list_entry(virt_dev->cmd_list.next,
1040                         struct xhci_command, cmd_list);
1041         if (xhci->cmd_ring->dequeue != command->command_trb)
1042                 return 0;
1043
1044         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1045         list_del(&command->cmd_list);
1046         if (command->completion)
1047                 complete(command->completion);
1048         else
1049                 xhci_free_command(xhci, command);
1050         return 1;
1051 }
1052
1053 static void handle_cmd_completion(struct xhci_hcd *xhci,
1054                 struct xhci_event_cmd *event)
1055 {
1056         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1057         u64 cmd_dma;
1058         dma_addr_t cmd_dequeue_dma;
1059         struct xhci_input_control_ctx *ctrl_ctx;
1060         struct xhci_virt_device *virt_dev;
1061         unsigned int ep_index;
1062         struct xhci_ring *ep_ring;
1063         unsigned int ep_state;
1064
1065         cmd_dma = le64_to_cpu(event->cmd_trb);
1066         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1067                         xhci->cmd_ring->dequeue);
1068         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1069         if (cmd_dequeue_dma == 0) {
1070                 xhci->error_bitmask |= 1 << 4;
1071                 return;
1072         }
1073         /* Does the DMA address match our internal dequeue pointer address? */
1074         if (cmd_dma != (u64) cmd_dequeue_dma) {
1075                 xhci->error_bitmask |= 1 << 5;
1076                 return;
1077         }
1078         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1079                 & TRB_TYPE_BITMASK) {
1080         case TRB_TYPE(TRB_ENABLE_SLOT):
1081                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1082                         xhci->slot_id = slot_id;
1083                 else
1084                         xhci->slot_id = 0;
1085                 complete(&xhci->addr_dev);
1086                 break;
1087         case TRB_TYPE(TRB_DISABLE_SLOT):
1088                 if (xhci->devs[slot_id]) {
1089                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1090                                 /* Delete default control endpoint resources */
1091                                 xhci_free_device_endpoint_resources(xhci,
1092                                                 xhci->devs[slot_id], true);
1093                         xhci_free_virt_device(xhci, slot_id);
1094                 }
1095                 break;
1096         case TRB_TYPE(TRB_CONFIG_EP):
1097                 virt_dev = xhci->devs[slot_id];
1098                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1099                         break;
1100                 /*
1101                  * Configure endpoint commands can come from the USB core
1102                  * configuration or alt setting changes, or because the HW
1103                  * needed an extra configure endpoint command after a reset
1104                  * endpoint command or streams were being configured.
1105                  * If the command was for a halted endpoint, the xHCI driver
1106                  * is not waiting on the configure endpoint command.
1107                  */
1108                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1109                                 virt_dev->in_ctx);
1110                 /* Input ctx add_flags are the endpoint index plus one */
1111                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1112                 /* A usb_set_interface() call directly after clearing a halted
1113                  * condition may race on this quirky hardware.  Not worth
1114                  * worrying about, since this is prototype hardware.  Not sure
1115                  * if this will work for streams, but streams support was
1116                  * untested on this prototype.
1117                  */
1118                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1119                                 ep_index != (unsigned int) -1 &&
1120                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1121                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1122                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1123                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1124                         if (!(ep_state & EP_HALTED))
1125                                 goto bandwidth_change;
1126                         xhci_dbg(xhci, "Completed config ep cmd - "
1127                                         "last ep index = %d, state = %d\n",
1128                                         ep_index, ep_state);
1129                         /* Clear internal halted state and restart ring(s) */
1130                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1131                                 ~EP_HALTED;
1132                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1133                         break;
1134                 }
1135 bandwidth_change:
1136                 xhci_dbg(xhci, "Completed config ep cmd\n");
1137                 xhci->devs[slot_id]->cmd_status =
1138                         GET_COMP_CODE(le32_to_cpu(event->status));
1139                 complete(&xhci->devs[slot_id]->cmd_completion);
1140                 break;
1141         case TRB_TYPE(TRB_EVAL_CONTEXT):
1142                 virt_dev = xhci->devs[slot_id];
1143                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1144                         break;
1145                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1146                 complete(&xhci->devs[slot_id]->cmd_completion);
1147                 break;
1148         case TRB_TYPE(TRB_ADDR_DEV):
1149                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1150                 complete(&xhci->addr_dev);
1151                 break;
1152         case TRB_TYPE(TRB_STOP_RING):
1153                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1154                 break;
1155         case TRB_TYPE(TRB_SET_DEQ):
1156                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1157                 break;
1158         case TRB_TYPE(TRB_CMD_NOOP):
1159                 break;
1160         case TRB_TYPE(TRB_RESET_EP):
1161                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1162                 break;
1163         case TRB_TYPE(TRB_RESET_DEV):
1164                 xhci_dbg(xhci, "Completed reset device command.\n");
1165                 slot_id = TRB_TO_SLOT_ID(
1166                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1167                 virt_dev = xhci->devs[slot_id];
1168                 if (virt_dev)
1169                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1170                 else
1171                         xhci_warn(xhci, "Reset device command completion "
1172                                         "for disabled slot %u\n", slot_id);
1173                 break;
1174         case TRB_TYPE(TRB_NEC_GET_FW):
1175                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1176                         xhci->error_bitmask |= 1 << 6;
1177                         break;
1178                 }
1179                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1180                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1181                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1182                 break;
1183         default:
1184                 /* Skip over unknown commands on the event ring */
1185                 xhci->error_bitmask |= 1 << 6;
1186                 break;
1187         }
1188         inc_deq(xhci, xhci->cmd_ring, false);
1189 }
1190
1191 static void handle_vendor_event(struct xhci_hcd *xhci,
1192                 union xhci_trb *event)
1193 {
1194         u32 trb_type;
1195
1196         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1197         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1198         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1199                 handle_cmd_completion(xhci, &event->event_cmd);
1200 }
1201
1202 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1203  * port registers -- USB 3.0 and USB 2.0).
1204  *
1205  * Returns a zero-based port number, which is suitable for indexing into each of
1206  * the split roothubs' port arrays and bus state arrays.
1207  * Add one to it in order to call xhci_find_slot_id_by_port.
1208  */
1209 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1210                 struct xhci_hcd *xhci, u32 port_id)
1211 {
1212         unsigned int i;
1213         unsigned int num_similar_speed_ports = 0;
1214
1215         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1216          * and usb2_ports are 0-based indexes.  Count the number of similar
1217          * speed ports, up to 1 port before this port.
1218          */
1219         for (i = 0; i < (port_id - 1); i++) {
1220                 u8 port_speed = xhci->port_array[i];
1221
1222                 /*
1223                  * Skip ports that don't have known speeds, or have duplicate
1224                  * Extended Capabilities port speed entries.
1225                  */
1226                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1227                         continue;
1228
1229                 /*
1230                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1231                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1232                  * matches the device speed, it's a similar speed port.
1233                  */
1234                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1235                         num_similar_speed_ports++;
1236         }
1237         return num_similar_speed_ports;
1238 }
1239
1240 static void handle_port_status(struct xhci_hcd *xhci,
1241                 union xhci_trb *event)
1242 {
1243         struct usb_hcd *hcd;
1244         u32 port_id;
1245         u32 temp, temp1;
1246         int max_ports;
1247         int slot_id;
1248         unsigned int faked_port_index;
1249         u8 major_revision;
1250         struct xhci_bus_state *bus_state;
1251         __le32 __iomem **port_array;
1252         bool bogus_port_status = false;
1253
1254         /* Port status change events always have a successful completion code */
1255         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1256                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1257                 xhci->error_bitmask |= 1 << 8;
1258         }
1259         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1260         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1261
1262         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1263         if ((port_id <= 0) || (port_id > max_ports)) {
1264                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1265                 bogus_port_status = true;
1266                 goto cleanup;
1267         }
1268
1269         /* Figure out which usb_hcd this port is attached to:
1270          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1271          */
1272         major_revision = xhci->port_array[port_id - 1];
1273         if (major_revision == 0) {
1274                 xhci_warn(xhci, "Event for port %u not in "
1275                                 "Extended Capabilities, ignoring.\n",
1276                                 port_id);
1277                 bogus_port_status = true;
1278                 goto cleanup;
1279         }
1280         if (major_revision == DUPLICATE_ENTRY) {
1281                 xhci_warn(xhci, "Event for port %u duplicated in"
1282                                 "Extended Capabilities, ignoring.\n",
1283                                 port_id);
1284                 bogus_port_status = true;
1285                 goto cleanup;
1286         }
1287
1288         /*
1289          * Hardware port IDs reported by a Port Status Change Event include USB
1290          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1291          * resume event, but we first need to translate the hardware port ID
1292          * into the index into the ports on the correct split roothub, and the
1293          * correct bus_state structure.
1294          */
1295         /* Find the right roothub. */
1296         hcd = xhci_to_hcd(xhci);
1297         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1298                 hcd = xhci->shared_hcd;
1299         bus_state = &xhci->bus_state[hcd_index(hcd)];
1300         if (hcd->speed == HCD_USB3)
1301                 port_array = xhci->usb3_ports;
1302         else
1303                 port_array = xhci->usb2_ports;
1304         /* Find the faked port hub number */
1305         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1306                         port_id);
1307
1308         temp = xhci_readl(xhci, port_array[faked_port_index]);
1309         if (hcd->state == HC_STATE_SUSPENDED) {
1310                 xhci_dbg(xhci, "resume root hub\n");
1311                 usb_hcd_resume_root_hub(hcd);
1312         }
1313
1314         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1315                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1316
1317                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1318                 if (!(temp1 & CMD_RUN)) {
1319                         xhci_warn(xhci, "xHC is not running.\n");
1320                         goto cleanup;
1321                 }
1322
1323                 if (DEV_SUPERSPEED(temp)) {
1324                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1325                         xhci_set_link_state(xhci, port_array, faked_port_index,
1326                                                 XDEV_U0);
1327                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1328                                         faked_port_index + 1);
1329                         if (!slot_id) {
1330                                 xhci_dbg(xhci, "slot_id is zero\n");
1331                                 goto cleanup;
1332                         }
1333                         xhci_ring_device(xhci, slot_id);
1334                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1335                         /* Clear PORT_PLC */
1336                         xhci_test_and_clear_bit(xhci, port_array,
1337                                                 faked_port_index, PORT_PLC);
1338                 } else {
1339                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1340                         bus_state->resume_done[faked_port_index] = jiffies +
1341                                 msecs_to_jiffies(20);
1342                         mod_timer(&hcd->rh_timer,
1343                                   bus_state->resume_done[faked_port_index]);
1344                         /* Do the rest in GetPortStatus */
1345                 }
1346         }
1347
1348         if (hcd->speed != HCD_USB3)
1349                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1350                                         PORT_PLC);
1351
1352 cleanup:
1353         /* Update event ring dequeue pointer before dropping the lock */
1354         inc_deq(xhci, xhci->event_ring, true);
1355
1356         /* Don't make the USB core poll the roothub if we got a bad port status
1357          * change event.  Besides, at that point we can't tell which roothub
1358          * (USB 2.0 or USB 3.0) to kick.
1359          */
1360         if (bogus_port_status)
1361                 return;
1362
1363         spin_unlock(&xhci->lock);
1364         /* Pass this up to the core */
1365         usb_hcd_poll_rh_status(hcd);
1366         spin_lock(&xhci->lock);
1367 }
1368
1369 /*
1370  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1371  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1372  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1373  * returns 0.
1374  */
1375 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1376                 union xhci_trb  *start_trb,
1377                 union xhci_trb  *end_trb,
1378                 dma_addr_t      suspect_dma)
1379 {
1380         dma_addr_t start_dma;
1381         dma_addr_t end_seg_dma;
1382         dma_addr_t end_trb_dma;
1383         struct xhci_segment *cur_seg;
1384
1385         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1386         cur_seg = start_seg;
1387
1388         do {
1389                 if (start_dma == 0)
1390                         return NULL;
1391                 /* We may get an event for a Link TRB in the middle of a TD */
1392                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1393                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1394                 /* If the end TRB isn't in this segment, this is set to 0 */
1395                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1396
1397                 if (end_trb_dma > 0) {
1398                         /* The end TRB is in this segment, so suspect should be here */
1399                         if (start_dma <= end_trb_dma) {
1400                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1401                                         return cur_seg;
1402                         } else {
1403                                 /* Case for one segment with
1404                                  * a TD wrapped around to the top
1405                                  */
1406                                 if ((suspect_dma >= start_dma &&
1407                                                         suspect_dma <= end_seg_dma) ||
1408                                                 (suspect_dma >= cur_seg->dma &&
1409                                                  suspect_dma <= end_trb_dma))
1410                                         return cur_seg;
1411                         }
1412                         return NULL;
1413                 } else {
1414                         /* Might still be somewhere in this segment */
1415                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1416                                 return cur_seg;
1417                 }
1418                 cur_seg = cur_seg->next;
1419                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1420         } while (cur_seg != start_seg);
1421
1422         return NULL;
1423 }
1424
1425 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1426                 unsigned int slot_id, unsigned int ep_index,
1427                 unsigned int stream_id,
1428                 struct xhci_td *td, union xhci_trb *event_trb)
1429 {
1430         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1431         ep->ep_state |= EP_HALTED;
1432         ep->stopped_td = td;
1433         ep->stopped_trb = event_trb;
1434         ep->stopped_stream = stream_id;
1435
1436         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1437         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1438
1439         ep->stopped_td = NULL;
1440         ep->stopped_trb = NULL;
1441         ep->stopped_stream = 0;
1442
1443         xhci_ring_cmd_db(xhci);
1444 }
1445
1446 /* Check if an error has halted the endpoint ring.  The class driver will
1447  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1448  * However, a babble and other errors also halt the endpoint ring, and the class
1449  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1450  * Ring Dequeue Pointer command manually.
1451  */
1452 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1453                 struct xhci_ep_ctx *ep_ctx,
1454                 unsigned int trb_comp_code)
1455 {
1456         /* TRB completion codes that may require a manual halt cleanup */
1457         if (trb_comp_code == COMP_TX_ERR ||
1458                         trb_comp_code == COMP_BABBLE ||
1459                         trb_comp_code == COMP_SPLIT_ERR)
1460                 /* The 0.96 spec says a babbling control endpoint
1461                  * is not halted. The 0.96 spec says it is.  Some HW
1462                  * claims to be 0.95 compliant, but it halts the control
1463                  * endpoint anyway.  Check if a babble halted the
1464                  * endpoint.
1465                  */
1466                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1467                     cpu_to_le32(EP_STATE_HALTED))
1468                         return 1;
1469
1470         return 0;
1471 }
1472
1473 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1474 {
1475         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1476                 /* Vendor defined "informational" completion code,
1477                  * treat as not-an-error.
1478                  */
1479                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1480                                 trb_comp_code);
1481                 xhci_dbg(xhci, "Treating code as success.\n");
1482                 return 1;
1483         }
1484         return 0;
1485 }
1486
1487 /*
1488  * Finish the td processing, remove the td from td list;
1489  * Return 1 if the urb can be given back.
1490  */
1491 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1492         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1493         struct xhci_virt_ep *ep, int *status, bool skip)
1494 {
1495         struct xhci_virt_device *xdev;
1496         struct xhci_ring *ep_ring;
1497         unsigned int slot_id;
1498         int ep_index;
1499         struct urb *urb = NULL;
1500         struct xhci_ep_ctx *ep_ctx;
1501         int ret = 0;
1502         struct urb_priv *urb_priv;
1503         u32 trb_comp_code;
1504
1505         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1506         xdev = xhci->devs[slot_id];
1507         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1508         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1509         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1510         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1511
1512         if (skip)
1513                 goto td_cleanup;
1514
1515         if (trb_comp_code == COMP_STOP_INVAL ||
1516                         trb_comp_code == COMP_STOP) {
1517                 /* The Endpoint Stop Command completion will take care of any
1518                  * stopped TDs.  A stopped TD may be restarted, so don't update
1519                  * the ring dequeue pointer or take this TD off any lists yet.
1520                  */
1521                 ep->stopped_td = td;
1522                 ep->stopped_trb = event_trb;
1523                 return 0;
1524         } else {
1525                 if (trb_comp_code == COMP_STALL) {
1526                         /* The transfer is completed from the driver's
1527                          * perspective, but we need to issue a set dequeue
1528                          * command for this stalled endpoint to move the dequeue
1529                          * pointer past the TD.  We can't do that here because
1530                          * the halt condition must be cleared first.  Let the
1531                          * USB class driver clear the stall later.
1532                          */
1533                         ep->stopped_td = td;
1534                         ep->stopped_trb = event_trb;
1535                         ep->stopped_stream = ep_ring->stream_id;
1536                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1537                                         ep_ctx, trb_comp_code)) {
1538                         /* Other types of errors halt the endpoint, but the
1539                          * class driver doesn't call usb_reset_endpoint() unless
1540                          * the error is -EPIPE.  Clear the halted status in the
1541                          * xHCI hardware manually.
1542                          */
1543                         xhci_cleanup_halted_endpoint(xhci,
1544                                         slot_id, ep_index, ep_ring->stream_id,
1545                                         td, event_trb);
1546                 } else {
1547                         /* Update ring dequeue pointer */
1548                         while (ep_ring->dequeue != td->last_trb)
1549                                 inc_deq(xhci, ep_ring, false);
1550                         inc_deq(xhci, ep_ring, false);
1551                 }
1552
1553 td_cleanup:
1554                 /* Clean up the endpoint's TD list */
1555                 urb = td->urb;
1556                 urb_priv = urb->hcpriv;
1557
1558                 /* Do one last check of the actual transfer length.
1559                  * If the host controller said we transferred more data than
1560                  * the buffer length, urb->actual_length will be a very big
1561                  * number (since it's unsigned).  Play it safe and say we didn't
1562                  * transfer anything.
1563                  */
1564                 if (urb->actual_length > urb->transfer_buffer_length) {
1565                         xhci_warn(xhci, "URB transfer length is wrong, "
1566                                         "xHC issue? req. len = %u, "
1567                                         "act. len = %u\n",
1568                                         urb->transfer_buffer_length,
1569                                         urb->actual_length);
1570                         urb->actual_length = 0;
1571                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1572                                 *status = -EREMOTEIO;
1573                         else
1574                                 *status = 0;
1575                 }
1576                 list_del_init(&td->td_list);
1577                 /* Was this TD slated to be cancelled but completed anyway? */
1578                 if (!list_empty(&td->cancelled_td_list))
1579                         list_del_init(&td->cancelled_td_list);
1580
1581                 urb_priv->td_cnt++;
1582                 /* Giveback the urb when all the tds are completed */
1583                 if (urb_priv->td_cnt == urb_priv->length) {
1584                         ret = 1;
1585                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1586                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1587                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1588                                         == 0) {
1589                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1590                                                 usb_amd_quirk_pll_enable();
1591                                 }
1592                         }
1593                 }
1594         }
1595
1596         return ret;
1597 }
1598
1599 /*
1600  * Process control tds, update urb status and actual_length.
1601  */
1602 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1603         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1604         struct xhci_virt_ep *ep, int *status)
1605 {
1606         struct xhci_virt_device *xdev;
1607         struct xhci_ring *ep_ring;
1608         unsigned int slot_id;
1609         int ep_index;
1610         struct xhci_ep_ctx *ep_ctx;
1611         u32 trb_comp_code;
1612
1613         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1614         xdev = xhci->devs[slot_id];
1615         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1616         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1617         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1618         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1619
1620         switch (trb_comp_code) {
1621         case COMP_SUCCESS:
1622                 if (event_trb == ep_ring->dequeue) {
1623                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1624                                         "without IOC set??\n");
1625                         *status = -ESHUTDOWN;
1626                 } else if (event_trb != td->last_trb) {
1627                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1628                                         "without IOC set??\n");
1629                         *status = -ESHUTDOWN;
1630                 } else {
1631                         *status = 0;
1632                 }
1633                 break;
1634         case COMP_SHORT_TX:
1635                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1636                         *status = -EREMOTEIO;
1637                 else
1638                         *status = 0;
1639                 break;
1640         case COMP_STOP_INVAL:
1641         case COMP_STOP:
1642                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1643         default:
1644                 if (!xhci_requires_manual_halt_cleanup(xhci,
1645                                         ep_ctx, trb_comp_code))
1646                         break;
1647                 xhci_dbg(xhci, "TRB error code %u, "
1648                                 "halted endpoint index = %u\n",
1649                                 trb_comp_code, ep_index);
1650                 /* else fall through */
1651         case COMP_STALL:
1652                 /* Did we transfer part of the data (middle) phase? */
1653                 if (event_trb != ep_ring->dequeue &&
1654                                 event_trb != td->last_trb)
1655                         td->urb->actual_length =
1656                                 td->urb->transfer_buffer_length
1657                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1658                 else
1659                         td->urb->actual_length = 0;
1660
1661                 xhci_cleanup_halted_endpoint(xhci,
1662                         slot_id, ep_index, 0, td, event_trb);
1663                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1664         }
1665         /*
1666          * Did we transfer any data, despite the errors that might have
1667          * happened?  I.e. did we get past the setup stage?
1668          */
1669         if (event_trb != ep_ring->dequeue) {
1670                 /* The event was for the status stage */
1671                 if (event_trb == td->last_trb) {
1672                         if (td->urb->actual_length != 0) {
1673                                 /* Don't overwrite a previously set error code
1674                                  */
1675                                 if ((*status == -EINPROGRESS || *status == 0) &&
1676                                                 (td->urb->transfer_flags
1677                                                  & URB_SHORT_NOT_OK))
1678                                         /* Did we already see a short data
1679                                          * stage? */
1680                                         *status = -EREMOTEIO;
1681                         } else {
1682                                 td->urb->actual_length =
1683                                         td->urb->transfer_buffer_length;
1684                         }
1685                 } else {
1686                 /* Maybe the event was for the data stage? */
1687                         td->urb->actual_length =
1688                                 td->urb->transfer_buffer_length -
1689                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1690                         xhci_dbg(xhci, "Waiting for status "
1691                                         "stage event\n");
1692                         return 0;
1693                 }
1694         }
1695
1696         return finish_td(xhci, td, event_trb, event, ep, status, false);
1697 }
1698
1699 /*
1700  * Process isochronous tds, update urb packet status and actual_length.
1701  */
1702 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1703         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1704         struct xhci_virt_ep *ep, int *status)
1705 {
1706         struct xhci_ring *ep_ring;
1707         struct urb_priv *urb_priv;
1708         int idx;
1709         int len = 0;
1710         union xhci_trb *cur_trb;
1711         struct xhci_segment *cur_seg;
1712         struct usb_iso_packet_descriptor *frame;
1713         u32 trb_comp_code;
1714         bool skip_td = false;
1715
1716         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1717         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1718         urb_priv = td->urb->hcpriv;
1719         idx = urb_priv->td_cnt;
1720         frame = &td->urb->iso_frame_desc[idx];
1721
1722         /* handle completion code */
1723         switch (trb_comp_code) {
1724         case COMP_SUCCESS:
1725                 frame->status = 0;
1726                 break;
1727         case COMP_SHORT_TX:
1728                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1729                                 -EREMOTEIO : 0;
1730                 break;
1731         case COMP_BW_OVER:
1732                 frame->status = -ECOMM;
1733                 skip_td = true;
1734                 break;
1735         case COMP_BUFF_OVER:
1736         case COMP_BABBLE:
1737                 frame->status = -EOVERFLOW;
1738                 skip_td = true;
1739                 break;
1740         case COMP_DEV_ERR:
1741         case COMP_STALL:
1742                 frame->status = -EPROTO;
1743                 skip_td = true;
1744                 break;
1745         case COMP_STOP:
1746         case COMP_STOP_INVAL:
1747                 break;
1748         default:
1749                 frame->status = -1;
1750                 break;
1751         }
1752
1753         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1754                 frame->actual_length = frame->length;
1755                 td->urb->actual_length += frame->length;
1756         } else {
1757                 for (cur_trb = ep_ring->dequeue,
1758                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1759                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1760                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1761                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1762                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1763                 }
1764                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1765                         TRB_LEN(le32_to_cpu(event->transfer_len));
1766
1767                 if (trb_comp_code != COMP_STOP_INVAL) {
1768                         frame->actual_length = len;
1769                         td->urb->actual_length += len;
1770                 }
1771         }
1772
1773         return finish_td(xhci, td, event_trb, event, ep, status, false);
1774 }
1775
1776 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1777                         struct xhci_transfer_event *event,
1778                         struct xhci_virt_ep *ep, int *status)
1779 {
1780         struct xhci_ring *ep_ring;
1781         struct urb_priv *urb_priv;
1782         struct usb_iso_packet_descriptor *frame;
1783         int idx;
1784
1785         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1786         urb_priv = td->urb->hcpriv;
1787         idx = urb_priv->td_cnt;
1788         frame = &td->urb->iso_frame_desc[idx];
1789
1790         /* The transfer is partly done. */
1791         frame->status = -EXDEV;
1792
1793         /* calc actual length */
1794         frame->actual_length = 0;
1795
1796         /* Update ring dequeue pointer */
1797         while (ep_ring->dequeue != td->last_trb)
1798                 inc_deq(xhci, ep_ring, false);
1799         inc_deq(xhci, ep_ring, false);
1800
1801         return finish_td(xhci, td, NULL, event, ep, status, true);
1802 }
1803
1804 /*
1805  * Process bulk and interrupt tds, update urb status and actual_length.
1806  */
1807 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1808         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1809         struct xhci_virt_ep *ep, int *status)
1810 {
1811         struct xhci_ring *ep_ring;
1812         union xhci_trb *cur_trb;
1813         struct xhci_segment *cur_seg;
1814         u32 trb_comp_code;
1815
1816         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1817         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1818
1819         switch (trb_comp_code) {
1820         case COMP_SUCCESS:
1821                 /* Double check that the HW transferred everything. */
1822                 if (event_trb != td->last_trb) {
1823                         xhci_warn(xhci, "WARN Successful completion "
1824                                         "on short TX\n");
1825                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1826                                 *status = -EREMOTEIO;
1827                         else
1828                                 *status = 0;
1829                 } else {
1830                         *status = 0;
1831                 }
1832                 break;
1833         case COMP_SHORT_TX:
1834                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1835                         *status = -EREMOTEIO;
1836                 else
1837                         *status = 0;
1838                 break;
1839         default:
1840                 /* Others already handled above */
1841                 break;
1842         }
1843         if (trb_comp_code == COMP_SHORT_TX)
1844                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1845                                 "%d bytes untransferred\n",
1846                                 td->urb->ep->desc.bEndpointAddress,
1847                                 td->urb->transfer_buffer_length,
1848                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1849         /* Fast path - was this the last TRB in the TD for this URB? */
1850         if (event_trb == td->last_trb) {
1851                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1852                         td->urb->actual_length =
1853                                 td->urb->transfer_buffer_length -
1854                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1855                         if (td->urb->transfer_buffer_length <
1856                                         td->urb->actual_length) {
1857                                 xhci_warn(xhci, "HC gave bad length "
1858                                                 "of %d bytes left\n",
1859                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1860                                 td->urb->actual_length = 0;
1861                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1862                                         *status = -EREMOTEIO;
1863                                 else
1864                                         *status = 0;
1865                         }
1866                         /* Don't overwrite a previously set error code */
1867                         if (*status == -EINPROGRESS) {
1868                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1869                                         *status = -EREMOTEIO;
1870                                 else
1871                                         *status = 0;
1872                         }
1873                 } else {
1874                         td->urb->actual_length =
1875                                 td->urb->transfer_buffer_length;
1876                         /* Ignore a short packet completion if the
1877                          * untransferred length was zero.
1878                          */
1879                         if (*status == -EREMOTEIO)
1880                                 *status = 0;
1881                 }
1882         } else {
1883                 /* Slow path - walk the list, starting from the dequeue
1884                  * pointer, to get the actual length transferred.
1885                  */
1886                 td->urb->actual_length = 0;
1887                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1888                                 cur_trb != event_trb;
1889                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1890                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1891                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1892                                 td->urb->actual_length +=
1893                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1894                 }
1895                 /* If the ring didn't stop on a Link or No-op TRB, add
1896                  * in the actual bytes transferred from the Normal TRB
1897                  */
1898                 if (trb_comp_code != COMP_STOP_INVAL)
1899                         td->urb->actual_length +=
1900                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1901                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1902         }
1903
1904         return finish_td(xhci, td, event_trb, event, ep, status, false);
1905 }
1906
1907 /*
1908  * If this function returns an error condition, it means it got a Transfer
1909  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1910  * At this point, the host controller is probably hosed and should be reset.
1911  */
1912 static int handle_tx_event(struct xhci_hcd *xhci,
1913                 struct xhci_transfer_event *event)
1914 {
1915         struct xhci_virt_device *xdev;
1916         struct xhci_virt_ep *ep;
1917         struct xhci_ring *ep_ring;
1918         unsigned int slot_id;
1919         int ep_index;
1920         struct xhci_td *td = NULL;
1921         dma_addr_t event_dma;
1922         struct xhci_segment *event_seg;
1923         union xhci_trb *event_trb;
1924         struct urb *urb = NULL;
1925         int status = -EINPROGRESS;
1926         struct urb_priv *urb_priv;
1927         struct xhci_ep_ctx *ep_ctx;
1928         struct list_head *tmp;
1929         u32 trb_comp_code;
1930         int ret = 0;
1931         int td_num = 0;
1932
1933         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1934         xdev = xhci->devs[slot_id];
1935         if (!xdev) {
1936                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1937                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
1938                          (unsigned long long) xhci_trb_virt_to_dma(
1939                                  xhci->event_ring->deq_seg,
1940                                  xhci->event_ring->dequeue),
1941                          lower_32_bits(le64_to_cpu(event->buffer)),
1942                          upper_32_bits(le64_to_cpu(event->buffer)),
1943                          le32_to_cpu(event->transfer_len),
1944                          le32_to_cpu(event->flags));
1945                 xhci_dbg(xhci, "Event ring:\n");
1946                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
1947                 return -ENODEV;
1948         }
1949
1950         /* Endpoint ID is 1 based, our index is zero based */
1951         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1952         ep = &xdev->eps[ep_index];
1953         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1954         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1955         if (!ep_ring ||
1956             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1957             EP_STATE_DISABLED) {
1958                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1959                                 "or incorrect stream ring\n");
1960                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
1961                          (unsigned long long) xhci_trb_virt_to_dma(
1962                                  xhci->event_ring->deq_seg,
1963                                  xhci->event_ring->dequeue),
1964                          lower_32_bits(le64_to_cpu(event->buffer)),
1965                          upper_32_bits(le64_to_cpu(event->buffer)),
1966                          le32_to_cpu(event->transfer_len),
1967                          le32_to_cpu(event->flags));
1968                 xhci_dbg(xhci, "Event ring:\n");
1969                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
1970                 return -ENODEV;
1971         }
1972
1973         /* Count current td numbers if ep->skip is set */
1974         if (ep->skip) {
1975                 list_for_each(tmp, &ep_ring->td_list)
1976                         td_num++;
1977         }
1978
1979         event_dma = le64_to_cpu(event->buffer);
1980         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1981         /* Look for common error cases */
1982         switch (trb_comp_code) {
1983         /* Skip codes that require special handling depending on
1984          * transfer type
1985          */
1986         case COMP_SUCCESS:
1987         case COMP_SHORT_TX:
1988                 break;
1989         case COMP_STOP:
1990                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1991                 break;
1992         case COMP_STOP_INVAL:
1993                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1994                 break;
1995         case COMP_STALL:
1996                 xhci_dbg(xhci, "Stalled endpoint\n");
1997                 ep->ep_state |= EP_HALTED;
1998                 status = -EPIPE;
1999                 break;
2000         case COMP_TRB_ERR:
2001                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2002                 status = -EILSEQ;
2003                 break;
2004         case COMP_SPLIT_ERR:
2005         case COMP_TX_ERR:
2006                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2007                 status = -EPROTO;
2008                 break;
2009         case COMP_BABBLE:
2010                 xhci_dbg(xhci, "Babble error on endpoint\n");
2011                 status = -EOVERFLOW;
2012                 break;
2013         case COMP_DB_ERR:
2014                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2015                 status = -ENOSR;
2016                 break;
2017         case COMP_BW_OVER:
2018                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2019                 break;
2020         case COMP_BUFF_OVER:
2021                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2022                 break;
2023         case COMP_UNDERRUN:
2024                 /*
2025                  * When the Isoch ring is empty, the xHC will generate
2026                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2027                  * Underrun Event for OUT Isoch endpoint.
2028                  */
2029                 xhci_dbg(xhci, "underrun event on endpoint\n");
2030                 if (!list_empty(&ep_ring->td_list))
2031                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2032                                         "still with TDs queued?\n",
2033                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2034                                  ep_index);
2035                 goto cleanup;
2036         case COMP_OVERRUN:
2037                 xhci_dbg(xhci, "overrun event on endpoint\n");
2038                 if (!list_empty(&ep_ring->td_list))
2039                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2040                                         "still with TDs queued?\n",
2041                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2042                                  ep_index);
2043                 goto cleanup;
2044         case COMP_DEV_ERR:
2045                 xhci_warn(xhci, "WARN: detect an incompatible device");
2046                 status = -EPROTO;
2047                 break;
2048         case COMP_MISSED_INT:
2049                 /*
2050                  * When encounter missed service error, one or more isoc tds
2051                  * may be missed by xHC.
2052                  * Set skip flag of the ep_ring; Complete the missed tds as
2053                  * short transfer when process the ep_ring next time.
2054                  */
2055                 ep->skip = true;
2056                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2057                 goto cleanup;
2058         default:
2059                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2060                         status = 0;
2061                         break;
2062                 }
2063                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2064                                 "busted\n");
2065                 goto cleanup;
2066         }
2067
2068         do {
2069                 /* This TRB should be in the TD at the head of this ring's
2070                  * TD list.
2071                  */
2072                 if (list_empty(&ep_ring->td_list)) {
2073                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2074                                         "with no TDs queued?\n",
2075                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2076                                   ep_index);
2077                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2078                                  (le32_to_cpu(event->flags) &
2079                                   TRB_TYPE_BITMASK)>>10);
2080                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2081                         if (ep->skip) {
2082                                 ep->skip = false;
2083                                 xhci_dbg(xhci, "td_list is empty while skip "
2084                                                 "flag set. Clear skip flag.\n");
2085                         }
2086                         ret = 0;
2087                         goto cleanup;
2088                 }
2089
2090                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2091                 if (ep->skip && td_num == 0) {
2092                         ep->skip = false;
2093                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2094                                                 "Clear skip flag.\n");
2095                         ret = 0;
2096                         goto cleanup;
2097                 }
2098
2099                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2100                 if (ep->skip)
2101                         td_num--;
2102
2103                 /* Is this a TRB in the currently executing TD? */
2104                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2105                                 td->last_trb, event_dma);
2106
2107                 /*
2108                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2109                  * is not in the current TD pointed by ep_ring->dequeue because
2110                  * that the hardware dequeue pointer still at the previous TRB
2111                  * of the current TD. The previous TRB maybe a Link TD or the
2112                  * last TRB of the previous TD. The command completion handle
2113                  * will take care the rest.
2114                  */
2115                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2116                         ret = 0;
2117                         goto cleanup;
2118                 }
2119
2120                 if (!event_seg) {
2121                         if (!ep->skip ||
2122                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2123                                 /* Some host controllers give a spurious
2124                                  * successful event after a short transfer.
2125                                  * Ignore it.
2126                                  */
2127                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2128                                                 ep_ring->last_td_was_short) {
2129                                         ep_ring->last_td_was_short = false;
2130                                         ret = 0;
2131                                         goto cleanup;
2132                                 }
2133                                 /* HC is busted, give up! */
2134                                 xhci_err(xhci,
2135                                         "ERROR Transfer event TRB DMA ptr not "
2136                                         "part of current TD\n");
2137                                 return -ESHUTDOWN;
2138                         }
2139
2140                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2141                         goto cleanup;
2142                 }
2143                 if (trb_comp_code == COMP_SHORT_TX)
2144                         ep_ring->last_td_was_short = true;
2145                 else
2146                         ep_ring->last_td_was_short = false;
2147
2148                 if (ep->skip) {
2149                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2150                         ep->skip = false;
2151                 }
2152
2153                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2154                                                 sizeof(*event_trb)];
2155                 /*
2156                  * No-op TRB should not trigger interrupts.
2157                  * If event_trb is a no-op TRB, it means the
2158                  * corresponding TD has been cancelled. Just ignore
2159                  * the TD.
2160                  */
2161                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2162                         xhci_dbg(xhci,
2163                                  "event_trb is a no-op TRB. Skip it\n");
2164                         goto cleanup;
2165                 }
2166
2167                 /* Now update the urb's actual_length and give back to
2168                  * the core
2169                  */
2170                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2171                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2172                                                  &status);
2173                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2174                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2175                                                  &status);
2176                 else
2177                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2178                                                  ep, &status);
2179
2180 cleanup:
2181                 /*
2182                  * Do not update event ring dequeue pointer if ep->skip is set.
2183                  * Will roll back to continue process missed tds.
2184                  */
2185                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2186                         inc_deq(xhci, xhci->event_ring, true);
2187                 }
2188
2189                 if (ret) {
2190                         urb = td->urb;
2191                         urb_priv = urb->hcpriv;
2192                         /* Leave the TD around for the reset endpoint function
2193                          * to use(but only if it's not a control endpoint,
2194                          * since we already queued the Set TR dequeue pointer
2195                          * command for stalled control endpoints).
2196                          */
2197                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2198                                 (trb_comp_code != COMP_STALL &&
2199                                         trb_comp_code != COMP_BABBLE))
2200                                 xhci_urb_free_priv(xhci, urb_priv);
2201
2202                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2203                         if ((urb->actual_length != urb->transfer_buffer_length &&
2204                                                 (urb->transfer_flags &
2205                                                  URB_SHORT_NOT_OK)) ||
2206                                         (status != 0 &&
2207                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2208                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2209                                                 "expected = %x, status = %d\n",
2210                                                 urb, urb->actual_length,
2211                                                 urb->transfer_buffer_length,
2212                                                 status);
2213                         spin_unlock(&xhci->lock);
2214                         /* EHCI, UHCI, and OHCI always unconditionally set the
2215                          * urb->status of an isochronous endpoint to 0.
2216                          */
2217                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2218                                 status = 0;
2219                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2220                         spin_lock(&xhci->lock);
2221                 }
2222
2223         /*
2224          * If ep->skip is set, it means there are missed tds on the
2225          * endpoint ring need to take care of.
2226          * Process them as short transfer until reach the td pointed by
2227          * the event.
2228          */
2229         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2230
2231         return 0;
2232 }
2233
2234 /*
2235  * This function handles all OS-owned events on the event ring.  It may drop
2236  * xhci->lock between event processing (e.g. to pass up port status changes).
2237  * Returns >0 for "possibly more events to process" (caller should call again),
2238  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2239  */
2240 static int xhci_handle_event(struct xhci_hcd *xhci)
2241 {
2242         union xhci_trb *event;
2243         int update_ptrs = 1;
2244         int ret;
2245
2246         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2247                 xhci->error_bitmask |= 1 << 1;
2248                 return 0;
2249         }
2250
2251         event = xhci->event_ring->dequeue;
2252         /* Does the HC or OS own the TRB? */
2253         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2254             xhci->event_ring->cycle_state) {
2255                 xhci->error_bitmask |= 1 << 2;
2256                 return 0;
2257         }
2258
2259         /*
2260          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2261          * speculative reads of the event's flags/data below.
2262          */
2263         rmb();
2264         /* FIXME: Handle more event types. */
2265         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2266         case TRB_TYPE(TRB_COMPLETION):
2267                 handle_cmd_completion(xhci, &event->event_cmd);
2268                 break;
2269         case TRB_TYPE(TRB_PORT_STATUS):
2270                 handle_port_status(xhci, event);
2271                 update_ptrs = 0;
2272                 break;
2273         case TRB_TYPE(TRB_TRANSFER):
2274                 ret = handle_tx_event(xhci, &event->trans_event);
2275                 if (ret < 0)
2276                         xhci->error_bitmask |= 1 << 9;
2277                 else
2278                         update_ptrs = 0;
2279                 break;
2280         default:
2281                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2282                     TRB_TYPE(48))
2283                         handle_vendor_event(xhci, event);
2284                 else
2285                         xhci->error_bitmask |= 1 << 3;
2286         }
2287         /* Any of the above functions may drop and re-acquire the lock, so check
2288          * to make sure a watchdog timer didn't mark the host as non-responsive.
2289          */
2290         if (xhci->xhc_state & XHCI_STATE_DYING) {
2291                 xhci_dbg(xhci, "xHCI host dying, returning from "
2292                                 "event handler.\n");
2293                 return 0;
2294         }
2295
2296         if (update_ptrs)
2297                 /* Update SW event ring dequeue pointer */
2298                 inc_deq(xhci, xhci->event_ring, true);
2299
2300         /* Are there more items on the event ring?  Caller will call us again to
2301          * check.
2302          */
2303         return 1;
2304 }
2305
2306 /*
2307  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2308  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2309  * indicators of an event TRB error, but we check the status *first* to be safe.
2310  */
2311 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2312 {
2313         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2314         u32 status;
2315         union xhci_trb *trb;
2316         u64 temp_64;
2317         union xhci_trb *event_ring_deq;
2318         dma_addr_t deq;
2319
2320         spin_lock(&xhci->lock);
2321         trb = xhci->event_ring->dequeue;
2322         /* Check if the xHC generated the interrupt, or the irq is shared */
2323         status = xhci_readl(xhci, &xhci->op_regs->status);
2324         if (status == 0xffffffff)
2325                 goto hw_died;
2326
2327         if (!(status & STS_EINT)) {
2328                 spin_unlock(&xhci->lock);
2329                 return IRQ_NONE;
2330         }
2331         if (status & STS_FATAL) {
2332                 xhci_warn(xhci, "WARNING: Host System Error\n");
2333                 xhci_halt(xhci);
2334 hw_died:
2335                 spin_unlock(&xhci->lock);
2336                 return -ESHUTDOWN;
2337         }
2338
2339         /*
2340          * Clear the op reg interrupt status first,
2341          * so we can receive interrupts from other MSI-X interrupters.
2342          * Write 1 to clear the interrupt status.
2343          */
2344         status |= STS_EINT;
2345         xhci_writel(xhci, status, &xhci->op_regs->status);
2346         /* FIXME when MSI-X is supported and there are multiple vectors */
2347         /* Clear the MSI-X event interrupt status */
2348
2349         if (hcd->irq != -1) {
2350                 u32 irq_pending;
2351                 /* Acknowledge the PCI interrupt */
2352                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2353                 irq_pending |= 0x3;
2354                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2355         }
2356
2357         if (xhci->xhc_state & XHCI_STATE_DYING) {
2358                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2359                                 "Shouldn't IRQs be disabled?\n");
2360                 /* Clear the event handler busy flag (RW1C);
2361                  * the event ring should be empty.
2362                  */
2363                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2364                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2365                                 &xhci->ir_set->erst_dequeue);
2366                 spin_unlock(&xhci->lock);
2367
2368                 return IRQ_HANDLED;
2369         }
2370
2371         event_ring_deq = xhci->event_ring->dequeue;
2372         /* FIXME this should be a delayed service routine
2373          * that clears the EHB.
2374          */
2375         while (xhci_handle_event(xhci) > 0) {}
2376
2377         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2378         /* If necessary, update the HW's version of the event ring deq ptr. */
2379         if (event_ring_deq != xhci->event_ring->dequeue) {
2380                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2381                                 xhci->event_ring->dequeue);
2382                 if (deq == 0)
2383                         xhci_warn(xhci, "WARN something wrong with SW event "
2384                                         "ring dequeue ptr.\n");
2385                 /* Update HC event ring dequeue pointer */
2386                 temp_64 &= ERST_PTR_MASK;
2387                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2388         }
2389
2390         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2391         temp_64 |= ERST_EHB;
2392         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2393
2394         spin_unlock(&xhci->lock);
2395
2396         return IRQ_HANDLED;
2397 }
2398
2399 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2400 {
2401         return xhci_irq(hcd);
2402 }
2403
2404 /****           Endpoint Ring Operations        ****/
2405
2406 /*
2407  * Generic function for queueing a TRB on a ring.
2408  * The caller must have checked to make sure there's room on the ring.
2409  *
2410  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2411  *                      prepare_transfer()?
2412  */
2413 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2414                 bool consumer, bool more_trbs_coming, bool isoc,
2415                 u32 field1, u32 field2, u32 field3, u32 field4)
2416 {
2417         struct xhci_generic_trb *trb;
2418
2419         trb = &ring->enqueue->generic;
2420         trb->field[0] = cpu_to_le32(field1);
2421         trb->field[1] = cpu_to_le32(field2);
2422         trb->field[2] = cpu_to_le32(field3);
2423         trb->field[3] = cpu_to_le32(field4);
2424         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2425 }
2426
2427 /*
2428  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2429  * FIXME allocate segments if the ring is full.
2430  */
2431 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2432                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2433 {
2434         /* Make sure the endpoint has been added to xHC schedule */
2435         switch (ep_state) {
2436         case EP_STATE_DISABLED:
2437                 /*
2438                  * USB core changed config/interfaces without notifying us,
2439                  * or hardware is reporting the wrong state.
2440                  */
2441                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2442                 return -ENOENT;
2443         case EP_STATE_ERROR:
2444                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2445                 /* FIXME event handling code for error needs to clear it */
2446                 /* XXX not sure if this should be -ENOENT or not */
2447                 return -EINVAL;
2448         case EP_STATE_HALTED:
2449                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2450         case EP_STATE_STOPPED:
2451         case EP_STATE_RUNNING:
2452                 break;
2453         default:
2454                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2455                 /*
2456                  * FIXME issue Configure Endpoint command to try to get the HC
2457                  * back into a known state.
2458                  */
2459                 return -EINVAL;
2460         }
2461         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2462                 /* FIXME allocate more room */
2463                 xhci_err(xhci, "ERROR no room on ep ring\n");
2464                 return -ENOMEM;
2465         }
2466
2467         if (enqueue_is_link_trb(ep_ring)) {
2468                 struct xhci_ring *ring = ep_ring;
2469                 union xhci_trb *next;
2470
2471                 next = ring->enqueue;
2472
2473                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2474                         /* If we're not dealing with 0.95 hardware or isoc rings
2475                          * on AMD 0.96 host, clear the chain bit.
2476                          */
2477                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2478                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2479                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2480                         else
2481                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2482
2483                         wmb();
2484                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2485
2486                         /* Toggle the cycle bit after the last ring segment. */
2487                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2488                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2489                         }
2490                         ring->enq_seg = ring->enq_seg->next;
2491                         ring->enqueue = ring->enq_seg->trbs;
2492                         next = ring->enqueue;
2493                 }
2494         }
2495
2496         return 0;
2497 }
2498
2499 static int prepare_transfer(struct xhci_hcd *xhci,
2500                 struct xhci_virt_device *xdev,
2501                 unsigned int ep_index,
2502                 unsigned int stream_id,
2503                 unsigned int num_trbs,
2504                 struct urb *urb,
2505                 unsigned int td_index,
2506                 bool isoc,
2507                 gfp_t mem_flags)
2508 {
2509         int ret;
2510         struct urb_priv *urb_priv;
2511         struct xhci_td  *td;
2512         struct xhci_ring *ep_ring;
2513         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2514
2515         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2516         if (!ep_ring) {
2517                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2518                                 stream_id);
2519                 return -EINVAL;
2520         }
2521
2522         ret = prepare_ring(xhci, ep_ring,
2523                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2524                            num_trbs, isoc, mem_flags);
2525         if (ret)
2526                 return ret;
2527
2528         urb_priv = urb->hcpriv;
2529         td = urb_priv->td[td_index];
2530
2531         INIT_LIST_HEAD(&td->td_list);
2532         INIT_LIST_HEAD(&td->cancelled_td_list);
2533
2534         if (td_index == 0) {
2535                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2536                 if (unlikely(ret))
2537                         return ret;
2538         }
2539
2540         td->urb = urb;
2541         /* Add this TD to the tail of the endpoint ring's TD list */
2542         list_add_tail(&td->td_list, &ep_ring->td_list);
2543         td->start_seg = ep_ring->enq_seg;
2544         td->first_trb = ep_ring->enqueue;
2545
2546         urb_priv->td[td_index] = td;
2547
2548         return 0;
2549 }
2550
2551 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2552 {
2553         int num_sgs, num_trbs, running_total, temp, i;
2554         struct scatterlist *sg;
2555
2556         sg = NULL;
2557         num_sgs = urb->num_mapped_sgs;
2558         temp = urb->transfer_buffer_length;
2559
2560         num_trbs = 0;
2561         for_each_sg(urb->sg, sg, num_sgs, i) {
2562                 unsigned int len = sg_dma_len(sg);
2563
2564                 /* Scatter gather list entries may cross 64KB boundaries */
2565                 running_total = TRB_MAX_BUFF_SIZE -
2566                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2567                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2568                 if (running_total != 0)
2569                         num_trbs++;
2570
2571                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2572                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2573                         num_trbs++;
2574                         running_total += TRB_MAX_BUFF_SIZE;
2575                 }
2576                 len = min_t(int, len, temp);
2577                 temp -= len;
2578                 if (temp == 0)
2579                         break;
2580         }
2581         return num_trbs;
2582 }
2583
2584 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2585 {
2586         if (num_trbs != 0)
2587                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2588                                 "TRBs, %d left\n", __func__,
2589                                 urb->ep->desc.bEndpointAddress, num_trbs);
2590         if (running_total != urb->transfer_buffer_length)
2591                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2592                                 "queued %#x (%d), asked for %#x (%d)\n",
2593                                 __func__,
2594                                 urb->ep->desc.bEndpointAddress,
2595                                 running_total, running_total,
2596                                 urb->transfer_buffer_length,
2597                                 urb->transfer_buffer_length);
2598 }
2599
2600 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2601                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2602                 struct xhci_generic_trb *start_trb)
2603 {
2604         /*
2605          * Pass all the TRBs to the hardware at once and make sure this write
2606          * isn't reordered.
2607          */
2608         wmb();
2609         if (start_cycle)
2610                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2611         else
2612                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2613         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2614 }
2615
2616 /*
2617  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2618  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2619  * (comprised of sg list entries) can take several service intervals to
2620  * transmit.
2621  */
2622 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2623                 struct urb *urb, int slot_id, unsigned int ep_index)
2624 {
2625         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2626                         xhci->devs[slot_id]->out_ctx, ep_index);
2627         int xhci_interval;
2628         int ep_interval;
2629
2630         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2631         ep_interval = urb->interval;
2632         /* Convert to microframes */
2633         if (urb->dev->speed == USB_SPEED_LOW ||
2634                         urb->dev->speed == USB_SPEED_FULL)
2635                 ep_interval *= 8;
2636         /* FIXME change this to a warning and a suggestion to use the new API
2637          * to set the polling interval (once the API is added).
2638          */
2639         if (xhci_interval != ep_interval) {
2640                 if (printk_ratelimit())
2641                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2642                                         " (%d microframe%s) than xHCI "
2643                                         "(%d microframe%s)\n",
2644                                         ep_interval,
2645                                         ep_interval == 1 ? "" : "s",
2646                                         xhci_interval,
2647                                         xhci_interval == 1 ? "" : "s");
2648                 urb->interval = xhci_interval;
2649                 /* Convert back to frames for LS/FS devices */
2650                 if (urb->dev->speed == USB_SPEED_LOW ||
2651                                 urb->dev->speed == USB_SPEED_FULL)
2652                         urb->interval /= 8;
2653         }
2654         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2655 }
2656
2657 /*
2658  * The TD size is the number of bytes remaining in the TD (including this TRB),
2659  * right shifted by 10.
2660  * It must fit in bits 21:17, so it can't be bigger than 31.
2661  */
2662 static u32 xhci_td_remainder(unsigned int remainder)
2663 {
2664         u32 max = (1 << (21 - 17 + 1)) - 1;
2665
2666         if ((remainder >> 10) >= max)
2667                 return max << 17;
2668         else
2669                 return (remainder >> 10) << 17;
2670 }
2671
2672 /*
2673  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2674  * the TD (*not* including this TRB).
2675  *
2676  * Total TD packet count = total_packet_count =
2677  *     roundup(TD size in bytes / wMaxPacketSize)
2678  *
2679  * Packets transferred up to and including this TRB = packets_transferred =
2680  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2681  *
2682  * TD size = total_packet_count - packets_transferred
2683  *
2684  * It must fit in bits 21:17, so it can't be bigger than 31.
2685  */
2686
2687 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2688                 unsigned int total_packet_count, struct urb *urb)
2689 {
2690         int packets_transferred;
2691
2692         /* One TRB with a zero-length data packet. */
2693         if (running_total == 0 && trb_buff_len == 0)
2694                 return 0;
2695
2696         /* All the TRB queueing functions don't count the current TRB in
2697          * running_total.
2698          */
2699         packets_transferred = (running_total + trb_buff_len) /
2700                 usb_endpoint_maxp(&urb->ep->desc);
2701
2702         return xhci_td_remainder(total_packet_count - packets_transferred);
2703 }
2704
2705 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2706                 struct urb *urb, int slot_id, unsigned int ep_index)
2707 {
2708         struct xhci_ring *ep_ring;
2709         unsigned int num_trbs;
2710         struct urb_priv *urb_priv;
2711         struct xhci_td *td;
2712         struct scatterlist *sg;
2713         int num_sgs;
2714         int trb_buff_len, this_sg_len, running_total;
2715         unsigned int total_packet_count;
2716         bool first_trb;
2717         u64 addr;
2718         bool more_trbs_coming;
2719
2720         struct xhci_generic_trb *start_trb;
2721         int start_cycle;
2722
2723         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2724         if (!ep_ring)
2725                 return -EINVAL;
2726
2727         num_trbs = count_sg_trbs_needed(xhci, urb);
2728         num_sgs = urb->num_mapped_sgs;
2729         total_packet_count = roundup(urb->transfer_buffer_length,
2730                         usb_endpoint_maxp(&urb->ep->desc));
2731
2732         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2733                         ep_index, urb->stream_id,
2734                         num_trbs, urb, 0, false, mem_flags);
2735         if (trb_buff_len < 0)
2736                 return trb_buff_len;
2737
2738         urb_priv = urb->hcpriv;
2739         td = urb_priv->td[0];
2740
2741         /*
2742          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2743          * until we've finished creating all the other TRBs.  The ring's cycle
2744          * state may change as we enqueue the other TRBs, so save it too.
2745          */
2746         start_trb = &ep_ring->enqueue->generic;
2747         start_cycle = ep_ring->cycle_state;
2748
2749         running_total = 0;
2750         /*
2751          * How much data is in the first TRB?
2752          *
2753          * There are three forces at work for TRB buffer pointers and lengths:
2754          * 1. We don't want to walk off the end of this sg-list entry buffer.
2755          * 2. The transfer length that the driver requested may be smaller than
2756          *    the amount of memory allocated for this scatter-gather list.
2757          * 3. TRBs buffers can't cross 64KB boundaries.
2758          */
2759         sg = urb->sg;
2760         addr = (u64) sg_dma_address(sg);
2761         this_sg_len = sg_dma_len(sg);
2762         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2763         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2764         if (trb_buff_len > urb->transfer_buffer_length)
2765                 trb_buff_len = urb->transfer_buffer_length;
2766
2767         first_trb = true;
2768         /* Queue the first TRB, even if it's zero-length */
2769         do {
2770                 u32 field = 0;
2771                 u32 length_field = 0;
2772                 u32 remainder = 0;
2773
2774                 /* Don't change the cycle bit of the first TRB until later */
2775                 if (first_trb) {
2776                         first_trb = false;
2777                         if (start_cycle == 0)
2778                                 field |= 0x1;
2779                 } else
2780                         field |= ep_ring->cycle_state;
2781
2782                 /* Chain all the TRBs together; clear the chain bit in the last
2783                  * TRB to indicate it's the last TRB in the chain.
2784                  */
2785                 if (num_trbs > 1) {
2786                         field |= TRB_CHAIN;
2787                 } else {
2788                         /* FIXME - add check for ZERO_PACKET flag before this */
2789                         td->last_trb = ep_ring->enqueue;
2790                         field |= TRB_IOC;
2791                 }
2792
2793                 /* Only set interrupt on short packet for IN endpoints */
2794                 if (usb_urb_dir_in(urb))
2795                         field |= TRB_ISP;
2796
2797                 if (TRB_MAX_BUFF_SIZE -
2798                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2799                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2800                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2801                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2802                                         (unsigned int) addr + trb_buff_len);
2803                 }
2804
2805                 /* Set the TRB length, TD size, and interrupter fields. */
2806                 if (xhci->hci_version < 0x100) {
2807                         remainder = xhci_td_remainder(
2808                                         urb->transfer_buffer_length -
2809                                         running_total);
2810                 } else {
2811                         remainder = xhci_v1_0_td_remainder(running_total,
2812                                         trb_buff_len, total_packet_count, urb);
2813                 }
2814                 length_field = TRB_LEN(trb_buff_len) |
2815                         remainder |
2816                         TRB_INTR_TARGET(0);
2817
2818                 if (num_trbs > 1)
2819                         more_trbs_coming = true;
2820                 else
2821                         more_trbs_coming = false;
2822                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2823                                 lower_32_bits(addr),
2824                                 upper_32_bits(addr),
2825                                 length_field,
2826                                 field | TRB_TYPE(TRB_NORMAL));
2827                 --num_trbs;
2828                 running_total += trb_buff_len;
2829
2830                 /* Calculate length for next transfer --
2831                  * Are we done queueing all the TRBs for this sg entry?
2832                  */
2833                 this_sg_len -= trb_buff_len;
2834                 if (this_sg_len == 0) {
2835                         --num_sgs;
2836                         if (num_sgs == 0)
2837                                 break;
2838                         sg = sg_next(sg);
2839                         addr = (u64) sg_dma_address(sg);
2840                         this_sg_len = sg_dma_len(sg);
2841                 } else {
2842                         addr += trb_buff_len;
2843                 }
2844
2845                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2846                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2847                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2848                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2849                         trb_buff_len =
2850                                 urb->transfer_buffer_length - running_total;
2851         } while (running_total < urb->transfer_buffer_length);
2852
2853         check_trb_math(urb, num_trbs, running_total);
2854         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2855                         start_cycle, start_trb);
2856         return 0;
2857 }
2858
2859 /* This is very similar to what ehci-q.c qtd_fill() does */
2860 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2861                 struct urb *urb, int slot_id, unsigned int ep_index)
2862 {
2863         struct xhci_ring *ep_ring;
2864         struct urb_priv *urb_priv;
2865         struct xhci_td *td;
2866         int num_trbs;
2867         struct xhci_generic_trb *start_trb;
2868         bool first_trb;
2869         bool more_trbs_coming;
2870         int start_cycle;
2871         u32 field, length_field;
2872
2873         int running_total, trb_buff_len, ret;
2874         unsigned int total_packet_count;
2875         u64 addr;
2876
2877         if (urb->num_sgs)
2878                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2879
2880         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2881         if (!ep_ring)
2882                 return -EINVAL;
2883
2884         num_trbs = 0;
2885         /* How much data is (potentially) left before the 64KB boundary? */
2886         running_total = TRB_MAX_BUFF_SIZE -
2887                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2888         running_total &= TRB_MAX_BUFF_SIZE - 1;
2889
2890         /* If there's some data on this 64KB chunk, or we have to send a
2891          * zero-length transfer, we need at least one TRB
2892          */
2893         if (running_total != 0 || urb->transfer_buffer_length == 0)
2894                 num_trbs++;
2895         /* How many more 64KB chunks to transfer, how many more TRBs? */
2896         while (running_total < urb->transfer_buffer_length) {
2897                 num_trbs++;
2898                 running_total += TRB_MAX_BUFF_SIZE;
2899         }
2900         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2901
2902         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2903                         ep_index, urb->stream_id,
2904                         num_trbs, urb, 0, false, mem_flags);
2905         if (ret < 0)
2906                 return ret;
2907
2908         urb_priv = urb->hcpriv;
2909         td = urb_priv->td[0];
2910
2911         /*
2912          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2913          * until we've finished creating all the other TRBs.  The ring's cycle
2914          * state may change as we enqueue the other TRBs, so save it too.
2915          */
2916         start_trb = &ep_ring->enqueue->generic;
2917         start_cycle = ep_ring->cycle_state;
2918
2919         running_total = 0;
2920         total_packet_count = roundup(urb->transfer_buffer_length,
2921                         usb_endpoint_maxp(&urb->ep->desc));
2922         /* How much data is in the first TRB? */
2923         addr = (u64) urb->transfer_dma;
2924         trb_buff_len = TRB_MAX_BUFF_SIZE -
2925                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2926         if (trb_buff_len > urb->transfer_buffer_length)
2927                 trb_buff_len = urb->transfer_buffer_length;
2928
2929         first_trb = true;
2930
2931         /* Queue the first TRB, even if it's zero-length */
2932         do {
2933                 u32 remainder = 0;
2934                 field = 0;
2935
2936                 /* Don't change the cycle bit of the first TRB until later */
2937                 if (first_trb) {
2938                         first_trb = false;
2939                         if (start_cycle == 0)
2940                                 field |= 0x1;
2941                 } else
2942                         field |= ep_ring->cycle_state;
2943
2944                 /* Chain all the TRBs together; clear the chain bit in the last
2945                  * TRB to indicate it's the last TRB in the chain.
2946                  */
2947                 if (num_trbs > 1) {
2948                         field |= TRB_CHAIN;
2949                 } else {
2950                         /* FIXME - add check for ZERO_PACKET flag before this */
2951                         td->last_trb = ep_ring->enqueue;
2952                         field |= TRB_IOC;
2953                 }
2954
2955                 /* Only set interrupt on short packet for IN endpoints */
2956                 if (usb_urb_dir_in(urb))
2957                         field |= TRB_ISP;
2958
2959                 /* Set the TRB length, TD size, and interrupter fields. */
2960                 if (xhci->hci_version < 0x100) {
2961                         remainder = xhci_td_remainder(
2962                                         urb->transfer_buffer_length -
2963                                         running_total);
2964                 } else {
2965                         remainder = xhci_v1_0_td_remainder(running_total,
2966                                         trb_buff_len, total_packet_count, urb);
2967                 }
2968                 length_field = TRB_LEN(trb_buff_len) |
2969                         remainder |
2970                         TRB_INTR_TARGET(0);
2971
2972                 if (num_trbs > 1)
2973                         more_trbs_coming = true;
2974                 else
2975                         more_trbs_coming = false;
2976                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2977                                 lower_32_bits(addr),
2978                                 upper_32_bits(addr),
2979                                 length_field,
2980                                 field | TRB_TYPE(TRB_NORMAL));
2981                 --num_trbs;
2982                 running_total += trb_buff_len;
2983
2984                 /* Calculate length for next transfer */
2985                 addr += trb_buff_len;
2986                 trb_buff_len = urb->transfer_buffer_length - running_total;
2987                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2988                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2989         } while (running_total < urb->transfer_buffer_length);
2990
2991         check_trb_math(urb, num_trbs, running_total);
2992         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2993                         start_cycle, start_trb);
2994         return 0;
2995 }
2996
2997 /* Caller must have locked xhci->lock */
2998 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2999                 struct urb *urb, int slot_id, unsigned int ep_index)
3000 {
3001         struct xhci_ring *ep_ring;
3002         int num_trbs;
3003         int ret;
3004         struct usb_ctrlrequest *setup;
3005         struct xhci_generic_trb *start_trb;
3006         int start_cycle;
3007         u32 field, length_field;
3008         struct urb_priv *urb_priv;
3009         struct xhci_td *td;
3010
3011         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3012         if (!ep_ring)
3013                 return -EINVAL;
3014
3015         /*
3016          * Need to copy setup packet into setup TRB, so we can't use the setup
3017          * DMA address.
3018          */
3019         if (!urb->setup_packet)
3020                 return -EINVAL;
3021
3022         /* 1 TRB for setup, 1 for status */
3023         num_trbs = 2;
3024         /*
3025          * Don't need to check if we need additional event data and normal TRBs,
3026          * since data in control transfers will never get bigger than 16MB
3027          * XXX: can we get a buffer that crosses 64KB boundaries?
3028          */
3029         if (urb->transfer_buffer_length > 0)
3030                 num_trbs++;
3031         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3032                         ep_index, urb->stream_id,
3033                         num_trbs, urb, 0, false, mem_flags);
3034         if (ret < 0)
3035                 return ret;
3036
3037         urb_priv = urb->hcpriv;
3038         td = urb_priv->td[0];
3039
3040         /*
3041          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3042          * until we've finished creating all the other TRBs.  The ring's cycle
3043          * state may change as we enqueue the other TRBs, so save it too.
3044          */
3045         start_trb = &ep_ring->enqueue->generic;
3046         start_cycle = ep_ring->cycle_state;
3047
3048         /* Queue setup TRB - see section 6.4.1.2.1 */
3049         /* FIXME better way to translate setup_packet into two u32 fields? */
3050         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3051         field = 0;
3052         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3053         if (start_cycle == 0)
3054                 field |= 0x1;
3055
3056         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3057         if (xhci->hci_version == 0x100) {
3058                 if (urb->transfer_buffer_length > 0) {
3059                         if (setup->bRequestType & USB_DIR_IN)
3060                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3061                         else
3062                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3063                 }
3064         }
3065
3066         queue_trb(xhci, ep_ring, false, true, false,
3067                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3068                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3069                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3070                   /* Immediate data in pointer */
3071                   field);
3072
3073         /* If there's data, queue data TRBs */
3074         /* Only set interrupt on short packet for IN endpoints */
3075         if (usb_urb_dir_in(urb))
3076                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3077         else
3078                 field = TRB_TYPE(TRB_DATA);
3079
3080         length_field = TRB_LEN(urb->transfer_buffer_length) |
3081                 xhci_td_remainder(urb->transfer_buffer_length) |
3082                 TRB_INTR_TARGET(0);
3083         if (urb->transfer_buffer_length > 0) {
3084                 if (setup->bRequestType & USB_DIR_IN)
3085                         field |= TRB_DIR_IN;
3086                 queue_trb(xhci, ep_ring, false, true, false,
3087                                 lower_32_bits(urb->transfer_dma),
3088                                 upper_32_bits(urb->transfer_dma),
3089                                 length_field,
3090                                 field | ep_ring->cycle_state);
3091         }
3092
3093         /* Save the DMA address of the last TRB in the TD */
3094         td->last_trb = ep_ring->enqueue;
3095
3096         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3097         /* If the device sent data, the status stage is an OUT transfer */
3098         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3099                 field = 0;
3100         else
3101                 field = TRB_DIR_IN;
3102         queue_trb(xhci, ep_ring, false, false, false,
3103                         0,
3104                         0,
3105                         TRB_INTR_TARGET(0),
3106                         /* Event on completion */
3107                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3108
3109         giveback_first_trb(xhci, slot_id, ep_index, 0,
3110                         start_cycle, start_trb);
3111         return 0;
3112 }
3113
3114 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3115                 struct urb *urb, int i)
3116 {
3117         int num_trbs = 0;
3118         u64 addr, td_len;
3119
3120         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3121         td_len = urb->iso_frame_desc[i].length;
3122
3123         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3124                         TRB_MAX_BUFF_SIZE);
3125         if (num_trbs == 0)
3126                 num_trbs++;
3127
3128         return num_trbs;
3129 }
3130
3131 /*
3132  * The transfer burst count field of the isochronous TRB defines the number of
3133  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3134  * devices can burst up to bMaxBurst number of packets per service interval.
3135  * This field is zero based, meaning a value of zero in the field means one
3136  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3137  * zero.  Only xHCI 1.0 host controllers support this field.
3138  */
3139 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3140                 struct usb_device *udev,
3141                 struct urb *urb, unsigned int total_packet_count)
3142 {
3143         unsigned int max_burst;
3144
3145         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3146                 return 0;
3147
3148         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3149         return roundup(total_packet_count, max_burst + 1) - 1;
3150 }
3151
3152 /*
3153  * Returns the number of packets in the last "burst" of packets.  This field is
3154  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3155  * the last burst packet count is equal to the total number of packets in the
3156  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3157  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3158  * contain 1 to (bMaxBurst + 1) packets.
3159  */
3160 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3161                 struct usb_device *udev,
3162                 struct urb *urb, unsigned int total_packet_count)
3163 {
3164         unsigned int max_burst;
3165         unsigned int residue;
3166
3167         if (xhci->hci_version < 0x100)
3168                 return 0;
3169
3170         switch (udev->speed) {
3171         case USB_SPEED_SUPER:
3172                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3173                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3174                 residue = total_packet_count % (max_burst + 1);
3175                 /* If residue is zero, the last burst contains (max_burst + 1)
3176                  * number of packets, but the TLBPC field is zero-based.
3177                  */
3178                 if (residue == 0)
3179                         return max_burst;
3180                 return residue - 1;
3181         default:
3182                 if (total_packet_count == 0)
3183                         return 0;
3184                 return total_packet_count - 1;
3185         }
3186 }
3187
3188 /* This is for isoc transfer */
3189 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3190                 struct urb *urb, int slot_id, unsigned int ep_index)
3191 {
3192         struct xhci_ring *ep_ring;
3193         struct urb_priv *urb_priv;
3194         struct xhci_td *td;
3195         int num_tds, trbs_per_td;
3196         struct xhci_generic_trb *start_trb;
3197         bool first_trb;
3198         int start_cycle;
3199         u32 field, length_field;
3200         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3201         u64 start_addr, addr;
3202         int i, j;
3203         bool more_trbs_coming;
3204
3205         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3206
3207         num_tds = urb->number_of_packets;
3208         if (num_tds < 1) {
3209                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3210                 return -EINVAL;
3211         }
3212
3213         start_addr = (u64) urb->transfer_dma;
3214         start_trb = &ep_ring->enqueue->generic;
3215         start_cycle = ep_ring->cycle_state;
3216
3217         urb_priv = urb->hcpriv;
3218         /* Queue the first TRB, even if it's zero-length */
3219         for (i = 0; i < num_tds; i++) {
3220                 unsigned int total_packet_count;
3221                 unsigned int burst_count;
3222                 unsigned int residue;
3223
3224                 first_trb = true;
3225                 running_total = 0;
3226                 addr = start_addr + urb->iso_frame_desc[i].offset;
3227                 td_len = urb->iso_frame_desc[i].length;
3228                 td_remain_len = td_len;
3229                 total_packet_count = roundup(td_len,
3230                                 usb_endpoint_maxp(&urb->ep->desc));
3231                 /* A zero-length transfer still involves at least one packet. */
3232                 if (total_packet_count == 0)
3233                         total_packet_count++;
3234                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3235                                 total_packet_count);
3236                 residue = xhci_get_last_burst_packet_count(xhci,
3237                                 urb->dev, urb, total_packet_count);
3238
3239                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3240
3241                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3242                                 urb->stream_id, trbs_per_td, urb, i, true,
3243                                 mem_flags);
3244                 if (ret < 0) {
3245                         if (i == 0)
3246                                 return ret;
3247                         goto cleanup;
3248                 }
3249
3250                 td = urb_priv->td[i];
3251                 for (j = 0; j < trbs_per_td; j++) {
3252                         u32 remainder = 0;
3253                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3254
3255                         if (first_trb) {
3256                                 /* Queue the isoc TRB */
3257                                 field |= TRB_TYPE(TRB_ISOC);
3258                                 /* Assume URB_ISO_ASAP is set */
3259                                 field |= TRB_SIA;
3260                                 if (i == 0) {
3261                                         if (start_cycle == 0)
3262                                                 field |= 0x1;
3263                                 } else
3264                                         field |= ep_ring->cycle_state;
3265                                 first_trb = false;
3266                         } else {
3267                                 /* Queue other normal TRBs */
3268                                 field |= TRB_TYPE(TRB_NORMAL);
3269                                 field |= ep_ring->cycle_state;
3270                         }
3271
3272                         /* Only set interrupt on short packet for IN EPs */
3273                         if (usb_urb_dir_in(urb))
3274                                 field |= TRB_ISP;
3275
3276                         /* Chain all the TRBs together; clear the chain bit in
3277                          * the last TRB to indicate it's the last TRB in the
3278                          * chain.
3279                          */
3280                         if (j < trbs_per_td - 1) {
3281                                 field |= TRB_CHAIN;
3282                                 more_trbs_coming = true;
3283                         } else {
3284                                 td->last_trb = ep_ring->enqueue;
3285                                 field |= TRB_IOC;
3286                                 if (xhci->hci_version == 0x100) {
3287                                         /* Set BEI bit except for the last td */
3288                                         if (i < num_tds - 1)
3289                                                 field |= TRB_BEI;
3290                                 }
3291                                 more_trbs_coming = false;
3292                         }
3293
3294                         /* Calculate TRB length */
3295                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3296                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3297                         if (trb_buff_len > td_remain_len)
3298                                 trb_buff_len = td_remain_len;
3299
3300                         /* Set the TRB length, TD size, & interrupter fields. */
3301                         if (xhci->hci_version < 0x100) {
3302                                 remainder = xhci_td_remainder(
3303                                                 td_len - running_total);
3304                         } else {
3305                                 remainder = xhci_v1_0_td_remainder(
3306                                                 running_total, trb_buff_len,
3307                                                 total_packet_count, urb);
3308                         }
3309                         length_field = TRB_LEN(trb_buff_len) |
3310                                 remainder |
3311                                 TRB_INTR_TARGET(0);
3312
3313                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3314                                 lower_32_bits(addr),
3315                                 upper_32_bits(addr),
3316                                 length_field,
3317                                 field);
3318                         running_total += trb_buff_len;
3319
3320                         addr += trb_buff_len;
3321                         td_remain_len -= trb_buff_len;
3322                 }
3323
3324                 /* Check TD length */
3325                 if (running_total != td_len) {
3326                         xhci_err(xhci, "ISOC TD length unmatch\n");
3327                         ret = -EINVAL;
3328                         goto cleanup;
3329                 }
3330         }
3331
3332         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3333                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3334                         usb_amd_quirk_pll_disable();
3335         }
3336         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3337
3338         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3339                         start_cycle, start_trb);
3340         return 0;
3341 cleanup:
3342         /* Clean up a partially enqueued isoc transfer. */
3343
3344         for (i--; i >= 0; i--)
3345                 list_del_init(&urb_priv->td[i]->td_list);
3346
3347         /* Use the first TD as a temporary variable to turn the TDs we've queued
3348          * into No-ops with a software-owned cycle bit. That way the hardware
3349          * won't accidentally start executing bogus TDs when we partially
3350          * overwrite them.  td->first_trb and td->start_seg are already set.
3351          */
3352         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3353         /* Every TRB except the first & last will have its cycle bit flipped. */
3354         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3355
3356         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3357         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3358         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3359         ep_ring->cycle_state = start_cycle;
3360         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3361         return ret;
3362 }
3363
3364 /*
3365  * Check transfer ring to guarantee there is enough room for the urb.
3366  * Update ISO URB start_frame and interval.
3367  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3368  * update the urb->start_frame by now.
3369  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3370  */
3371 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3372                 struct urb *urb, int slot_id, unsigned int ep_index)
3373 {
3374         struct xhci_virt_device *xdev;
3375         struct xhci_ring *ep_ring;
3376         struct xhci_ep_ctx *ep_ctx;
3377         int start_frame;
3378         int xhci_interval;
3379         int ep_interval;
3380         int num_tds, num_trbs, i;
3381         int ret;
3382
3383         xdev = xhci->devs[slot_id];
3384         ep_ring = xdev->eps[ep_index].ring;
3385         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3386
3387         num_trbs = 0;
3388         num_tds = urb->number_of_packets;
3389         for (i = 0; i < num_tds; i++)
3390                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3391
3392         /* Check the ring to guarantee there is enough room for the whole urb.
3393          * Do not insert any td of the urb to the ring if the check failed.
3394          */
3395         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3396                            num_trbs, true, mem_flags);
3397         if (ret)
3398                 return ret;
3399
3400         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3401         start_frame &= 0x3fff;
3402
3403         urb->start_frame = start_frame;
3404         if (urb->dev->speed == USB_SPEED_LOW ||
3405                         urb->dev->speed == USB_SPEED_FULL)
3406                 urb->start_frame >>= 3;
3407
3408         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3409         ep_interval = urb->interval;
3410         /* Convert to microframes */
3411         if (urb->dev->speed == USB_SPEED_LOW ||
3412                         urb->dev->speed == USB_SPEED_FULL)
3413                 ep_interval *= 8;
3414         /* FIXME change this to a warning and a suggestion to use the new API
3415          * to set the polling interval (once the API is added).
3416          */
3417         if (xhci_interval != ep_interval) {
3418                 if (printk_ratelimit())
3419                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3420                                         " (%d microframe%s) than xHCI "
3421                                         "(%d microframe%s)\n",
3422                                         ep_interval,
3423                                         ep_interval == 1 ? "" : "s",
3424                                         xhci_interval,
3425                                         xhci_interval == 1 ? "" : "s");
3426                 urb->interval = xhci_interval;
3427                 /* Convert back to frames for LS/FS devices */
3428                 if (urb->dev->speed == USB_SPEED_LOW ||
3429                                 urb->dev->speed == USB_SPEED_FULL)
3430                         urb->interval /= 8;
3431         }
3432         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3433 }
3434
3435 /****           Command Ring Operations         ****/
3436
3437 /* Generic function for queueing a command TRB on the command ring.
3438  * Check to make sure there's room on the command ring for one command TRB.
3439  * Also check that there's room reserved for commands that must not fail.
3440  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3441  * then only check for the number of reserved spots.
3442  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3443  * because the command event handler may want to resubmit a failed command.
3444  */
3445 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3446                 u32 field3, u32 field4, bool command_must_succeed)
3447 {
3448         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3449         int ret;
3450
3451         if (!command_must_succeed)
3452                 reserved_trbs++;
3453
3454         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3455                         reserved_trbs, false, GFP_ATOMIC);
3456         if (ret < 0) {
3457                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3458                 if (command_must_succeed)
3459                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3460                                         "unfailable commands failed.\n");
3461                 return ret;
3462         }
3463         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3464                         field3, field4 | xhci->cmd_ring->cycle_state);
3465         return 0;
3466 }
3467
3468 /* Queue a slot enable or disable request on the command ring */
3469 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3470 {
3471         return queue_command(xhci, 0, 0, 0,
3472                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3473 }
3474
3475 /* Queue an address device command TRB */
3476 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3477                 u32 slot_id)
3478 {
3479         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3480                         upper_32_bits(in_ctx_ptr), 0,
3481                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3482                         false);
3483 }
3484
3485 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3486                 u32 field1, u32 field2, u32 field3, u32 field4)
3487 {
3488         return queue_command(xhci, field1, field2, field3, field4, false);
3489 }
3490
3491 /* Queue a reset device command TRB */
3492 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3493 {
3494         return queue_command(xhci, 0, 0, 0,
3495                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3496                         false);
3497 }
3498
3499 /* Queue a configure endpoint command TRB */
3500 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3501                 u32 slot_id, bool command_must_succeed)
3502 {
3503         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3504                         upper_32_bits(in_ctx_ptr), 0,
3505                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3506                         command_must_succeed);
3507 }
3508
3509 /* Queue an evaluate context command TRB */
3510 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3511                 u32 slot_id)
3512 {
3513         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3514                         upper_32_bits(in_ctx_ptr), 0,
3515                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3516                         false);
3517 }
3518
3519 /*
3520  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3521  * activity on an endpoint that is about to be suspended.
3522  */
3523 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3524                 unsigned int ep_index, int suspend)
3525 {
3526         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3527         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3528         u32 type = TRB_TYPE(TRB_STOP_RING);
3529         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3530
3531         return queue_command(xhci, 0, 0, 0,
3532                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3533 }
3534
3535 /* Set Transfer Ring Dequeue Pointer command.
3536  * This should not be used for endpoints that have streams enabled.
3537  */
3538 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3539                 unsigned int ep_index, unsigned int stream_id,
3540                 struct xhci_segment *deq_seg,
3541                 union xhci_trb *deq_ptr, u32 cycle_state)
3542 {
3543         dma_addr_t addr;
3544         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3545         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3546         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3547         u32 type = TRB_TYPE(TRB_SET_DEQ);
3548         struct xhci_virt_ep *ep;
3549
3550         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3551         if (addr == 0) {
3552                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3553                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3554                                 deq_seg, deq_ptr);
3555                 return 0;
3556         }
3557         ep = &xhci->devs[slot_id]->eps[ep_index];
3558         if ((ep->ep_state & SET_DEQ_PENDING)) {
3559                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3560                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3561                 return 0;
3562         }
3563         ep->queued_deq_seg = deq_seg;
3564         ep->queued_deq_ptr = deq_ptr;
3565         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3566                         upper_32_bits(addr), trb_stream_id,
3567                         trb_slot_id | trb_ep_index | type, false);
3568 }
3569
3570 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3571                 unsigned int ep_index)
3572 {
3573         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3574         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3575         u32 type = TRB_TYPE(TRB_RESET_EP);
3576
3577         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3578                         false);
3579 }