2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
28 /* Device for a quirk */
29 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
30 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_VENDOR_ID_ETRON 0x1b6f
33 #define PCI_DEVICE_ID_ASROCK_P67 0x7023
35 static const char hcd_name[] = "xhci_hcd";
37 /* called after powerup, by probe or system-pm "wakeup" */
38 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
41 * TODO: Implement finding debug ports later.
42 * TODO: see if there are any quirks that need to be added to handle
43 * new extended capabilities.
46 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
47 if (!pci_set_mwi(pdev))
48 xhci_dbg(xhci, "MWI active\n");
50 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
54 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
56 static int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
58 struct xhci_hcd *xhci;
59 struct device *dev = hcd->self.controller;
63 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
65 if (usb_hcd_is_primary_hcd(hcd)) {
66 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
69 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
71 /* Mark the first roothub as being USB 2.0.
72 * The xHCI driver will register the USB 3.0 roothub.
74 hcd->speed = HCD_USB2;
75 hcd->self.root_hub->speed = USB_SPEED_HIGH;
77 * USB 2.0 roothub under xHCI has an integrated TT,
78 * (rate matching hub) as opposed to having an OHCI/UHCI
79 * companion controller.
83 /* xHCI private pointer was set in xhci_pci_probe for the second
86 xhci = hcd_to_xhci(hcd);
87 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
88 if (HCC_64BIT_ADDR(temp)) {
89 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
90 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
92 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
97 xhci->cap_regs = hcd->regs;
98 xhci->op_regs = hcd->regs +
99 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
100 xhci->run_regs = hcd->regs +
101 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
102 /* Cache read-only capability registers */
103 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
104 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
105 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
106 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
107 xhci->hci_version = HC_VERSION(xhci->hcc_params);
108 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
109 xhci_print_registers(xhci);
111 get_quirks(dev, xhci);
113 /* Make sure the HC is halted. */
114 retval = xhci_halt(xhci);
118 xhci_dbg(xhci, "Resetting HCD\n");
119 /* Reset the internal HC memory state and registers. */
120 retval = xhci_reset(xhci);
123 xhci_dbg(xhci, "Reset complete\n");
125 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
126 if (HCC_64BIT_ADDR(temp)) {
127 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
128 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
130 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
133 xhci_dbg(xhci, "Calling HCD init\n");
134 /* Initialize HCD and host controller data structures. */
135 retval = xhci_init(hcd);
138 xhci_dbg(xhci, "Called HCD init\n");
145 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
147 struct pci_dev *pdev = to_pci_dev(dev);
149 /* Look for vendor-specific quirks */
150 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
151 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
152 if (pdev->revision == 0x0) {
153 xhci->quirks |= XHCI_RESET_EP_QUIRK;
154 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
155 " endpoint cmd after reset endpoint\n");
157 /* Fresco Logic confirms: all revisions of this chip do not
158 * support MSI, even though some of them claim to in their PCI
161 xhci->quirks |= XHCI_BROKEN_MSI;
162 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
163 "has broken MSI implementation\n",
167 if (pdev->vendor == PCI_VENDOR_ID_NEC)
168 xhci->quirks |= XHCI_NEC_HOST;
170 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
171 xhci->quirks |= XHCI_AMD_0x96_HOST;
174 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
175 xhci->quirks |= XHCI_AMD_PLL_FIX;
176 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
177 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
178 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
179 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
180 xhci->limit_active_eps = 64;
181 xhci->quirks |= XHCI_SW_BW_CHECKING;
183 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
184 pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
185 xhci->quirks |= XHCI_RESET_ON_RESUME;
186 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
190 /* called during probe() after chip reset completes */
191 static int xhci_pci_setup(struct usb_hcd *hcd)
193 struct xhci_hcd *xhci;
194 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
197 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
201 xhci = hcd_to_xhci(hcd);
202 if (!usb_hcd_is_primary_hcd(hcd))
205 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
206 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
208 /* Find any debug ports */
209 retval = xhci_pci_reinit(xhci, pdev);
218 * We need to register our own PCI probe function (instead of the USB core's
219 * function) in order to create a second roothub under xHCI.
221 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
224 struct xhci_hcd *xhci;
225 struct hc_driver *driver;
228 driver = (struct hc_driver *)id->driver_data;
229 /* Register the USB 2.0 roothub.
230 * FIXME: USB core must know to register the USB 2.0 roothub first.
231 * This is sort of silly, because we could just set the HCD driver flags
232 * to say USB 2.0, but I'm not sure what the implications would be in
233 * the other parts of the HCD code.
235 retval = usb_hcd_pci_probe(dev, id);
240 /* USB 2.0 roothub is stored in the PCI device now. */
241 hcd = dev_get_drvdata(&dev->dev);
242 xhci = hcd_to_xhci(hcd);
243 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
245 if (!xhci->shared_hcd) {
247 goto dealloc_usb2_hcd;
250 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
251 * is called by usb_add_hcd().
253 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
255 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
259 /* Roothub already marked as USB 3.0 speed */
263 usb_put_hcd(xhci->shared_hcd);
265 usb_hcd_pci_remove(dev);
269 static void xhci_pci_remove(struct pci_dev *dev)
271 struct xhci_hcd *xhci;
273 xhci = hcd_to_xhci(pci_get_drvdata(dev));
274 if (xhci->shared_hcd) {
275 usb_remove_hcd(xhci->shared_hcd);
276 usb_put_hcd(xhci->shared_hcd);
278 usb_hcd_pci_remove(dev);
283 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
285 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
288 if (hcd->state != HC_STATE_SUSPENDED ||
289 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
292 retval = xhci_suspend(xhci);
297 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
299 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
300 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
303 /* The BIOS on systems with the Intel Panther Point chipset may or may
304 * not support xHCI natively. That means that during system resume, it
305 * may switch the ports back to EHCI so that users can use their
306 * keyboard to select a kernel from GRUB after resume from hibernate.
308 * The BIOS is supposed to remember whether the OS had xHCI ports
309 * enabled before resume, and switch the ports back to xHCI when the
310 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
313 * Unconditionally switch the ports back to xHCI after a system resume.
314 * We can't tell whether the EHCI or xHCI controller will be resumed
315 * first, so we have to do the port switchover in both drivers. Writing
316 * a '1' to the port switchover registers should have no effect if the
317 * port was already switched over.
319 if (usb_is_intel_switchable_xhci(pdev))
320 usb_enable_xhci_ports(pdev);
322 retval = xhci_resume(xhci, hibernated);
325 #endif /* CONFIG_PM */
327 static const struct hc_driver xhci_pci_hc_driver = {
328 .description = hcd_name,
329 .product_desc = "xHCI Host Controller",
330 .hcd_priv_size = sizeof(struct xhci_hcd *),
333 * generic hardware linkage
336 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
339 * basic lifecycle operations
341 .reset = xhci_pci_setup,
344 .pci_suspend = xhci_pci_suspend,
345 .pci_resume = xhci_pci_resume,
348 .shutdown = xhci_shutdown,
351 * managing i/o requests and associated device resources
353 .urb_enqueue = xhci_urb_enqueue,
354 .urb_dequeue = xhci_urb_dequeue,
355 .alloc_dev = xhci_alloc_dev,
356 .free_dev = xhci_free_dev,
357 .alloc_streams = xhci_alloc_streams,
358 .free_streams = xhci_free_streams,
359 .add_endpoint = xhci_add_endpoint,
360 .drop_endpoint = xhci_drop_endpoint,
361 .endpoint_reset = xhci_endpoint_reset,
362 .check_bandwidth = xhci_check_bandwidth,
363 .reset_bandwidth = xhci_reset_bandwidth,
364 .address_device = xhci_address_device,
365 .update_hub_device = xhci_update_hub_device,
366 .reset_device = xhci_discover_or_reset_device,
371 .get_frame_number = xhci_get_frame,
373 /* Root hub support */
374 .hub_control = xhci_hub_control,
375 .hub_status_data = xhci_hub_status_data,
376 .bus_suspend = xhci_bus_suspend,
377 .bus_resume = xhci_bus_resume,
379 * call back when device connected and addressed
381 .update_device = xhci_update_device,
382 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
385 /*-------------------------------------------------------------------------*/
387 /* PCI driver selection metadata; PCI hotplugging uses this */
388 static const struct pci_device_id pci_ids[] = { {
389 /* handle any USB 3.0 xHCI controller */
390 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
391 .driver_data = (unsigned long) &xhci_pci_hc_driver,
393 { /* end: all zeroes */ }
395 MODULE_DEVICE_TABLE(pci, pci_ids);
397 /* pci driver glue; this is a "new style" PCI driver module */
398 static struct pci_driver xhci_pci_driver = {
399 .name = (char *) hcd_name,
402 .probe = xhci_pci_probe,
403 .remove = xhci_pci_remove,
404 /* suspend and resume implemented later */
406 .shutdown = usb_hcd_pci_shutdown,
407 #ifdef CONFIG_PM_SLEEP
409 .pm = &usb_hcd_pci_pm_ops
414 int xhci_register_pci(void)
416 return pci_register_driver(&xhci_pci_driver);
419 void xhci_unregister_pci(void)
421 pci_unregister_driver(&xhci_pci_driver);