drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  38 {
  39         struct xhci_segment *seg;
  40         dma_addr_t      dma;
  41
  42         seg = kzalloc(sizeof *seg, flags);
  43         if (!seg)
  44                 return NULL;
  45         xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  46
  47         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  48         if (!seg->trbs) {
  49                 kfree(seg);
  50                 return NULL;
  51         }
  52         xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  53                         seg->trbs, (unsigned long long)dma);
  54
  55         memset(seg->trbs, 0, SEGMENT_SIZE);
  56         seg->dma = dma;
  57         seg->next = NULL;
  58
  59         return seg;
  60 }
  61
  62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  63 {
  64         if (!seg)
  65                 return;
  66         if (seg->trbs) {
  67                 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  68                                 seg->trbs, (unsigned long long)seg->dma);
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  73         kfree(seg);
  74 }
  75
  76 /*
  77  * Make the prev segment point to the next segment.
  78  *
  79  * Change the last TRB in the prev segment to be a Link TRB which points to the
  80  * DMA address of the next segment.  The caller needs to set any Link TRB
  81  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  82  */
  83 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  84                 struct xhci_segment *next, bool link_trbs)
  85 {
  86         u32 val;
  87
  88         if (!prev || !next)
  89                 return;
  90         prev->next = next;
  91         if (link_trbs) {
  92                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  93                         cpu_to_le64(next->dma);
  94
  95                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  96                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  97                 val &= ~TRB_TYPE_BITMASK;
  98                 val |= TRB_TYPE(TRB_LINK);
  99                 /* Always set the chain bit with 0.95 hardware */
 100                 if (xhci_link_trb_quirk(xhci))
 101                         val |= TRB_CHAIN;
 102                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 103         }
 104         xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
 105                         (unsigned long long)prev->dma,
 106                         (unsigned long long)next->dma);
 107 }
 108
 109 /* XXX: Do we need the hcd structure in all these functions? */
 110 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 111 {
 112         struct xhci_segment *seg;
 113         struct xhci_segment *first_seg;
 114
 115         if (!ring || !ring->first_seg)
 116                 return;
 117         first_seg = ring->first_seg;
 118         seg = first_seg->next;
 119         xhci_dbg(xhci, "Freeing ring at %p\n", ring);
 120         while (seg != first_seg) {
 121                 struct xhci_segment *next = seg->next;
 122                 xhci_segment_free(xhci, seg);
 123                 seg = next;
 124         }
 125         xhci_segment_free(xhci, first_seg);
 126         ring->first_seg = NULL;
 127         kfree(ring);
 128 }
 129
 130 static void xhci_initialize_ring_info(struct xhci_ring *ring)
 131 {
 132         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 133         ring->enqueue = ring->first_seg->trbs;
 134         ring->enq_seg = ring->first_seg;
 135         ring->dequeue = ring->enqueue;
 136         ring->deq_seg = ring->first_seg;
 137         /* The ring is initialized to 0. The producer must write 1 to the cycle
 138          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 139          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 140          */
 141         ring->cycle_state = 1;
 142         /* Not necessary for new rings, but needed for re-initialized rings */
 143         ring->enq_updates = 0;
 144         ring->deq_updates = 0;
 145 }
 146
 147 /**
 148  * Create a new ring with zero or more segments.
 149  *
 150  * Link each segment together into a ring.
 151  * Set the end flag and the cycle toggle bit on the last segment.
 152  * See section 4.9.1 and figures 15 and 16.
 153  */
 154 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 155                 unsigned int num_segs, bool link_trbs, gfp_t flags)
 156 {
 157         struct xhci_ring        *ring;
 158         struct xhci_segment     *prev;
 159
 160         ring = kzalloc(sizeof *(ring), flags);
 161         xhci_dbg(xhci, "Allocating ring at %p\n", ring);
 162         if (!ring)
 163                 return NULL;
 164
 165         INIT_LIST_HEAD(&ring->td_list);
 166         if (num_segs == 0)
 167                 return ring;
 168
 169         ring->first_seg = xhci_segment_alloc(xhci, flags);
 170         if (!ring->first_seg)
 171                 goto fail;
 172         num_segs--;
 173
 174         prev = ring->first_seg;
 175         while (num_segs > 0) {
 176                 struct xhci_segment     *next;
 177
 178                 next = xhci_segment_alloc(xhci, flags);
 179                 if (!next)
 180                         goto fail;
 181                 xhci_link_segments(xhci, prev, next, link_trbs);
 182
 183                 prev = next;
 184                 num_segs--;
 185         }
 186         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
 187
 188         if (link_trbs) {
 189                 /* See section 4.9.2.1 and 6.4.4.1 */
 190                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
 191                         cpu_to_le32(LINK_TOGGLE);
 192                 xhci_dbg(xhci, "Wrote link toggle flag to"
 193                                 " segment %p (virtual), 0x%llx (DMA)\n",
 194                                 prev, (unsigned long long)prev->dma);
 195         }
 196         xhci_initialize_ring_info(ring);
 197         return ring;
 198
 199 fail:
 200         xhci_ring_free(xhci, ring);
 201         return NULL;
 202 }
 203
 204 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 205                 struct xhci_virt_device *virt_dev,
 206                 unsigned int ep_index)
 207 {
 208         int rings_cached;
 209
 210         rings_cached = virt_dev->num_rings_cached;
 211         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 212                 virt_dev->ring_cache[rings_cached] =
 213                         virt_dev->eps[ep_index].ring;
 214                 virt_dev->num_rings_cached++;
 215                 xhci_dbg(xhci, "Cached old ring, "
 216                                 "%d ring%s cached\n",
 217                                 virt_dev->num_rings_cached,
 218                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 219         } else {
 220                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 221                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 222                                 "freeing ring\n",
 223                                 virt_dev->num_rings_cached);
 224         }
 225         virt_dev->eps[ep_index].ring = NULL;
 226 }
 227
 228 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 229  * pointers to the beginning of the ring.
 230  */
 231 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 232                 struct xhci_ring *ring)
 233 {
 234         struct xhci_segment     *seg = ring->first_seg;
 235         do {
 236                 memset(seg->trbs, 0,
 237                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 238                 /* All endpoint rings have link TRBs */
 239                 xhci_link_segments(xhci, seg, seg->next, 1);
 240                 seg = seg->next;
 241         } while (seg != ring->first_seg);
 242         xhci_initialize_ring_info(ring);
 243         /* td list should be empty since all URBs have been cancelled,
 244          * but just in case...
 245          */
 246         INIT_LIST_HEAD(&ring->td_list);
 247 }
 248
 249 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 250
 251 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 252                                                     int type, gfp_t flags)
 253 {
 254         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 255         if (!ctx)
 256                 return NULL;
 257
 258         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 259         ctx->type = type;
 260         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 261         if (type == XHCI_CTX_TYPE_INPUT)
 262                 ctx->size += CTX_SIZE(xhci->hcc_params);
 263
 264         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 265         memset(ctx->bytes, 0, ctx->size);
 266         return ctx;
 267 }
 268
 269 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 270                              struct xhci_container_ctx *ctx)
 271 {
 272         if (!ctx)
 273                 return;
 274         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 275         kfree(ctx);
 276 }
 277
 278 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 279                                               struct xhci_container_ctx *ctx)
 280 {
 281         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 282         return (struct xhci_input_control_ctx *)ctx->bytes;
 283 }
 284
 285 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 286                                         struct xhci_container_ctx *ctx)
 287 {
 288         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 289                 return (struct xhci_slot_ctx *)ctx->bytes;
 290
 291         return (struct xhci_slot_ctx *)
 292                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 293 }
 294
 295 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 296                                     struct xhci_container_ctx *ctx,
 297                                     unsigned int ep_index)
 298 {
 299         /* increment ep index by offset of start of ep ctx array */
 300         ep_index++;
 301         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 302                 ep_index++;
 303
 304         return (struct xhci_ep_ctx *)
 305                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 306 }
 307
 308
 309 /***************** Streams structures manipulation *************************/
 310
 311 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 312                 unsigned int num_stream_ctxs,
 313                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 314 {
 315         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 316
 317         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 318                 pci_free_consistent(pdev,
 319                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 320                                 stream_ctx, dma);
 321         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 322                 return dma_pool_free(xhci->small_streams_pool,
 323                                 stream_ctx, dma);
 324         else
 325                 return dma_pool_free(xhci->medium_streams_pool,
 326                                 stream_ctx, dma);
 327 }
 328
 329 /*
 330  * The stream context array for each endpoint with bulk streams enabled can
 331  * vary in size, based on:
 332  *  - how many streams the endpoint supports,
 333  *  - the maximum primary stream array size the host controller supports,
 334  *  - and how many streams the device driver asks for.
 335  *
 336  * The stream context array must be a power of 2, and can be as small as
 337  * 64 bytes or as large as 1MB.
 338  */
 339 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 340                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 341                 gfp_t mem_flags)
 342 {
 343         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 344
 345         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 346                 return pci_alloc_consistent(pdev,
 347                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 348                                 dma);
 349         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 350                 return dma_pool_alloc(xhci->small_streams_pool,
 351                                 mem_flags, dma);
 352         else
 353                 return dma_pool_alloc(xhci->medium_streams_pool,
 354                                 mem_flags, dma);
 355 }
 356
 357 struct xhci_ring *xhci_dma_to_transfer_ring(
 358                 struct xhci_virt_ep *ep,
 359                 u64 address)
 360 {
 361         if (ep->ep_state & EP_HAS_STREAMS)
 362                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 363                                 address >> SEGMENT_SHIFT);
 364         return ep->ring;
 365 }
 366
 367 /* Only use this when you know stream_info is valid */
 368 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 369 static struct xhci_ring *dma_to_stream_ring(
 370                 struct xhci_stream_info *stream_info,
 371                 u64 address)
 372 {
 373         return radix_tree_lookup(&stream_info->trb_address_map,
 374                         address >> SEGMENT_SHIFT);
 375 }
 376 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 377
 378 struct xhci_ring *xhci_stream_id_to_ring(
 379                 struct xhci_virt_device *dev,
 380                 unsigned int ep_index,
 381                 unsigned int stream_id)
 382 {
 383         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 384
 385         if (stream_id == 0)
 386                 return ep->ring;
 387         if (!ep->stream_info)
 388                 return NULL;
 389
 390         if (stream_id > ep->stream_info->num_streams)
 391                 return NULL;
 392         return ep->stream_info->stream_rings[stream_id];
 393 }
 394
 395 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 396 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 397                 unsigned int num_streams,
 398                 struct xhci_stream_info *stream_info)
 399 {
 400         u32 cur_stream;
 401         struct xhci_ring *cur_ring;
 402         u64 addr;
 403
 404         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 405                 struct xhci_ring *mapped_ring;
 406                 int trb_size = sizeof(union xhci_trb);
 407
 408                 cur_ring = stream_info->stream_rings[cur_stream];
 409                 for (addr = cur_ring->first_seg->dma;
 410                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 411                                 addr += trb_size) {
 412                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 413                         if (cur_ring != mapped_ring) {
 414                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 415                                                 "didn't map to stream ID %u; "
 416                                                 "mapped to ring %p\n",
 417                                                 (unsigned long long) addr,
 418                                                 cur_stream,
 419                                                 mapped_ring);
 420                                 return -EINVAL;
 421                         }
 422                 }
 423                 /* One TRB after the end of the ring segment shouldn't return a
 424                  * pointer to the current ring (although it may be a part of a
 425                  * different ring).
 426                  */
 427                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 428                 if (mapped_ring != cur_ring) {
 429                         /* One TRB before should also fail */
 430                         addr = cur_ring->first_seg->dma - trb_size;
 431                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 432                 }
 433                 if (mapped_ring == cur_ring) {
 434                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 435                                         "mapped to valid stream ID %u; "
 436                                         "mapped ring = %p\n",
 437                                         (unsigned long long) addr,
 438                                         cur_stream,
 439                                         mapped_ring);
 440                         return -EINVAL;
 441                 }
 442         }
 443         return 0;
 444 }
 445 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 446
 447 /*
 448  * Change an endpoint's internal structure so it supports stream IDs.  The
 449  * number of requested streams includes stream 0, which cannot be used by device
 450  * drivers.
 451  *
 452  * The number of stream contexts in the stream context array may be bigger than
 453  * the number of streams the driver wants to use.  This is because the number of
 454  * stream context array entries must be a power of two.
 455  *
 456  * We need a radix tree for mapping physical addresses of TRBs to which stream
 457  * ID they belong to.  We need to do this because the host controller won't tell
 458  * us which stream ring the TRB came from.  We could store the stream ID in an
 459  * event data TRB, but that doesn't help us for the cancellation case, since the
 460  * endpoint may stop before it reaches that event data TRB.
 461  *
 462  * The radix tree maps the upper portion of the TRB DMA address to a ring
 463  * segment that has the same upper portion of DMA addresses.  For example, say I
 464  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 465  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 466  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 467  * pass the radix tree a key to get the right stream ID:
 468  *
 469  *      0x10c90fff >> 10 = 0x43243
 470  *      0x10c912c0 >> 10 = 0x43244
 471  *      0x10c91400 >> 10 = 0x43245
 472  *
 473  * Obviously, only those TRBs with DMA addresses that are within the segment
 474  * will make the radix tree return the stream ID for that ring.
 475  *
 476  * Caveats for the radix tree:
 477  *
 478  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 479  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 480  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 481  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 482  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 483  * extended systems (where the DMA address can be bigger than 32-bits),
 484  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 485  */
 486 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 487                 unsigned int num_stream_ctxs,
 488                 unsigned int num_streams, gfp_t mem_flags)
 489 {
 490         struct xhci_stream_info *stream_info;
 491         u32 cur_stream;
 492         struct xhci_ring *cur_ring;
 493         unsigned long key;
 494         u64 addr;
 495         int ret;
 496
 497         xhci_dbg(xhci, "Allocating %u streams and %u "
 498                         "stream context array entries.\n",
 499                         num_streams, num_stream_ctxs);
 500         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 501                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 502                 return NULL;
 503         }
 504         xhci->cmd_ring_reserved_trbs++;
 505
 506         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 507         if (!stream_info)
 508                 goto cleanup_trbs;
 509
 510         stream_info->num_streams = num_streams;
 511         stream_info->num_stream_ctxs = num_stream_ctxs;
 512
 513         /* Initialize the array of virtual pointers to stream rings. */
 514         stream_info->stream_rings = kzalloc(
 515                         sizeof(struct xhci_ring *)*num_streams,
 516                         mem_flags);
 517         if (!stream_info->stream_rings)
 518                 goto cleanup_info;
 519
 520         /* Initialize the array of DMA addresses for stream rings for the HW. */
 521         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 522                         num_stream_ctxs, &stream_info->ctx_array_dma,
 523                         mem_flags);
 524         if (!stream_info->stream_ctx_array)
 525                 goto cleanup_ctx;
 526         memset(stream_info->stream_ctx_array, 0,
 527                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 528
 529         /* Allocate everything needed to free the stream rings later */
 530         stream_info->free_streams_command =
 531                 xhci_alloc_command(xhci, true, true, mem_flags);
 532         if (!stream_info->free_streams_command)
 533                 goto cleanup_ctx;
 534
 535         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 536
 537         /* Allocate rings for all the streams that the driver will use,
 538          * and add their segment DMA addresses to the radix tree.
 539          * Stream 0 is reserved.
 540          */
 541         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 542                 stream_info->stream_rings[cur_stream] =
 543                         xhci_ring_alloc(xhci, 1, true, mem_flags);
 544                 cur_ring = stream_info->stream_rings[cur_stream];
 545                 if (!cur_ring)
 546                         goto cleanup_rings;
 547                 cur_ring->stream_id = cur_stream;
 548                 /* Set deq ptr, cycle bit, and stream context type */
 549                 addr = cur_ring->first_seg->dma |
 550                         SCT_FOR_CTX(SCT_PRI_TR) |
 551                         cur_ring->cycle_state;
 552                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 553                         cpu_to_le64(addr);
 554                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 555                                 cur_stream, (unsigned long long) addr);
 556
 557                 key = (unsigned long)
 558                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 559                 ret = radix_tree_insert(&stream_info->trb_address_map,
 560                                 key, cur_ring);
 561                 if (ret) {
 562                         xhci_ring_free(xhci, cur_ring);
 563                         stream_info->stream_rings[cur_stream] = NULL;
 564                         goto cleanup_rings;
 565                 }
 566         }
 567         /* Leave the other unused stream ring pointers in the stream context
 568          * array initialized to zero.  This will cause the xHC to give us an
 569          * error if the device asks for a stream ID we don't have setup (if it
 570          * was any other way, the host controller would assume the ring is
 571          * "empty" and wait forever for data to be queued to that stream ID).
 572          */
 573 #if XHCI_DEBUG
 574         /* Do a little test on the radix tree to make sure it returns the
 575          * correct values.
 576          */
 577         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 578                 goto cleanup_rings;
 579 #endif
 580
 581         return stream_info;
 582
 583 cleanup_rings:
 584         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 585                 cur_ring = stream_info->stream_rings[cur_stream];
 586                 if (cur_ring) {
 587                         addr = cur_ring->first_seg->dma;
 588                         radix_tree_delete(&stream_info->trb_address_map,
 589                                         addr >> SEGMENT_SHIFT);
 590                         xhci_ring_free(xhci, cur_ring);
 591                         stream_info->stream_rings[cur_stream] = NULL;
 592                 }
 593         }
 594         xhci_free_command(xhci, stream_info->free_streams_command);
 595 cleanup_ctx:
 596         kfree(stream_info->stream_rings);
 597 cleanup_info:
 598         kfree(stream_info);
 599 cleanup_trbs:
 600         xhci->cmd_ring_reserved_trbs--;
 601         return NULL;
 602 }
 603 /*
 604  * Sets the MaxPStreams field and the Linear Stream Array field.
 605  * Sets the dequeue pointer to the stream context array.
 606  */
 607 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 608                 struct xhci_ep_ctx *ep_ctx,
 609                 struct xhci_stream_info *stream_info)
 610 {
 611         u32 max_primary_streams;
 612         /* MaxPStreams is the number of stream context array entries, not the
 613          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 614          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 615          */
 616         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 617         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 618                         1 << (max_primary_streams + 1));
 619         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 620         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 621                                        | EP_HAS_LSA);
 622         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 623 }
 624
 625 /*
 626  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 627  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 628  * not at the beginning of the ring).
 629  */
 630 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 631                 struct xhci_ep_ctx *ep_ctx,
 632                 struct xhci_virt_ep *ep)
 633 {
 634         dma_addr_t addr;
 635         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 636         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 637         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 638 }
 639
 640 /* Frees all stream contexts associated with the endpoint,
 641  *
 642  * Caller should fix the endpoint context streams fields.
 643  */
 644 void xhci_free_stream_info(struct xhci_hcd *xhci,
 645                 struct xhci_stream_info *stream_info)
 646 {
 647         int cur_stream;
 648         struct xhci_ring *cur_ring;
 649         dma_addr_t addr;
 650
 651         if (!stream_info)
 652                 return;
 653
 654         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 655                         cur_stream++) {
 656                 cur_ring = stream_info->stream_rings[cur_stream];
 657                 if (cur_ring) {
 658                         addr = cur_ring->first_seg->dma;
 659                         radix_tree_delete(&stream_info->trb_address_map,
 660                                         addr >> SEGMENT_SHIFT);
 661                         xhci_ring_free(xhci, cur_ring);
 662                         stream_info->stream_rings[cur_stream] = NULL;
 663                 }
 664         }
 665         xhci_free_command(xhci, stream_info->free_streams_command);
 666         xhci->cmd_ring_reserved_trbs--;
 667         if (stream_info->stream_ctx_array)
 668                 xhci_free_stream_ctx(xhci,
 669                                 stream_info->num_stream_ctxs,
 670                                 stream_info->stream_ctx_array,
 671                                 stream_info->ctx_array_dma);
 672
 673         if (stream_info)
 674                 kfree(stream_info->stream_rings);
 675         kfree(stream_info);
 676 }
 677
 678
 679 /***************** Device context manipulation *************************/
 680
 681 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 682                 struct xhci_virt_ep *ep)
 683 {
 684         init_timer(&ep->stop_cmd_timer);
 685         ep->stop_cmd_timer.data = (unsigned long) ep;
 686         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 687         ep->xhci = xhci;
 688 }
 689
 690 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 691                 struct xhci_virt_device *virt_dev,
 692                 int slot_id)
 693 {
 694         struct list_head *tt;
 695         struct list_head *tt_list_head;
 696         struct list_head *tt_next;
 697         struct xhci_tt_bw_info *tt_info;
 698
 699         /* If the device never made it past the Set Address stage,
 700          * it may not have the real_port set correctly.
 701          */
 702         if (virt_dev->real_port == 0 ||
 703                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 704                 xhci_dbg(xhci, "Bad real port.\n");
 705                 return;
 706         }
 707
 708         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 709         if (list_empty(tt_list_head))
 710                 return;
 711
 712         list_for_each(tt, tt_list_head) {
 713                 tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
 714                 if (tt_info->slot_id == slot_id)
 715                         break;
 716         }
 717         /* Cautionary measure in case the hub was disconnected before we
 718          * stored the TT information.
 719          */
 720         if (tt_info->slot_id != slot_id)
 721                 return;
 722
 723         tt_next = tt->next;
 724         tt_info = list_entry(tt, struct xhci_tt_bw_info,
 725                         tt_list);
 726         /* Multi-TT hubs will have more than one entry */
 727         do {
 728                 list_del(tt);
 729                 kfree(tt_info);
 730                 tt = tt_next;
 731                 if (list_empty(tt_list_head))
 732                         break;
 733                 tt_next = tt->next;
 734                 tt_info = list_entry(tt, struct xhci_tt_bw_info,
 735                                 tt_list);
 736         } while (tt_info->slot_id == slot_id);
 737 }
 738
 739 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 740                 struct xhci_virt_device *virt_dev,
 741                 struct usb_device *hdev,
 742                 struct usb_tt *tt, gfp_t mem_flags)
 743 {
 744         struct xhci_tt_bw_info          *tt_info;
 745         unsigned int                    num_ports;
 746         int                             i, j;
 747
 748         if (!tt->multi)
 749                 num_ports = 1;
 750         else
 751                 num_ports = hdev->maxchild;
 752
 753         for (i = 0; i < num_ports; i++, tt_info++) {
 754                 struct xhci_interval_bw_table *bw_table;
 755
 756                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 757                 if (!tt_info)
 758                         goto free_tts;
 759                 INIT_LIST_HEAD(&tt_info->tt_list);
 760                 list_add(&tt_info->tt_list,
 761                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 762                 tt_info->slot_id = virt_dev->udev->slot_id;
 763                 if (tt->multi)
 764                         tt_info->ttport = i+1;
 765                 bw_table = &tt_info->bw_table;
 766                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 767                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 768         }
 769         return 0;
 770
 771 free_tts:
 772         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 773         return -ENOMEM;
 774 }
 775
 776
 777 /* All the xhci_tds in the ring's TD list should be freed at this point.
 778  * Should be called with xhci->lock held if there is any chance the TT lists
 779  * will be manipulated by the configure endpoint, allocate device, or update
 780  * hub functions while this function is removing the TT entries from the list.
 781  */
 782 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 783 {
 784         struct xhci_virt_device *dev;
 785         int i;
 786
 787         /* Slot ID 0 is reserved */
 788         if (slot_id == 0 || !xhci->devs[slot_id])
 789                 return;
 790
 791         dev = xhci->devs[slot_id];
 792         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 793         if (!dev)
 794                 return;
 795
 796         for (i = 0; i < 31; ++i) {
 797                 if (dev->eps[i].ring)
 798                         xhci_ring_free(xhci, dev->eps[i].ring);
 799                 if (dev->eps[i].stream_info)
 800                         xhci_free_stream_info(xhci,
 801                                         dev->eps[i].stream_info);
 802         }
 803         /* If this is a hub, free the TT(s) from the TT list */
 804         xhci_free_tt_info(xhci, dev, slot_id);
 805
 806         if (dev->ring_cache) {
 807                 for (i = 0; i < dev->num_rings_cached; i++)
 808                         xhci_ring_free(xhci, dev->ring_cache[i]);
 809                 kfree(dev->ring_cache);
 810         }
 811
 812         if (dev->in_ctx)
 813                 xhci_free_container_ctx(xhci, dev->in_ctx);
 814         if (dev->out_ctx)
 815                 xhci_free_container_ctx(xhci, dev->out_ctx);
 816
 817         kfree(xhci->devs[slot_id]);
 818         xhci->devs[slot_id] = NULL;
 819 }
 820
 821 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 822                 struct usb_device *udev, gfp_t flags)
 823 {
 824         struct xhci_virt_device *dev;
 825         int i;
 826
 827         /* Slot ID 0 is reserved */
 828         if (slot_id == 0 || xhci->devs[slot_id]) {
 829                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 830                 return 0;
 831         }
 832
 833         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 834         if (!xhci->devs[slot_id])
 835                 return 0;
 836         dev = xhci->devs[slot_id];
 837
 838         /* Allocate the (output) device context that will be used in the HC. */
 839         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 840         if (!dev->out_ctx)
 841                 goto fail;
 842
 843         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 844                         (unsigned long long)dev->out_ctx->dma);
 845
 846         /* Allocate the (input) device context for address device command */
 847         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 848         if (!dev->in_ctx)
 849                 goto fail;
 850
 851         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 852                         (unsigned long long)dev->in_ctx->dma);
 853
 854         /* Initialize the cancellation list and watchdog timers for each ep */
 855         for (i = 0; i < 31; i++) {
 856                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 857                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 858         }
 859
 860         /* Allocate endpoint 0 ring */
 861         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
 862         if (!dev->eps[0].ring)
 863                 goto fail;
 864
 865         /* Allocate pointers to the ring cache */
 866         dev->ring_cache = kzalloc(
 867                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 868                         flags);
 869         if (!dev->ring_cache)
 870                 goto fail;
 871         dev->num_rings_cached = 0;
 872
 873         init_completion(&dev->cmd_completion);
 874         INIT_LIST_HEAD(&dev->cmd_list);
 875         dev->udev = udev;
 876
 877         /* Point to output device context in dcbaa. */
 878         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 879         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 880                  slot_id,
 881                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 882                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 883
 884         return 1;
 885 fail:
 886         xhci_free_virt_device(xhci, slot_id);
 887         return 0;
 888 }
 889
 890 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 891                 struct usb_device *udev)
 892 {
 893         struct xhci_virt_device *virt_dev;
 894         struct xhci_ep_ctx      *ep0_ctx;
 895         struct xhci_ring        *ep_ring;
 896
 897         virt_dev = xhci->devs[udev->slot_id];
 898         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 899         ep_ring = virt_dev->eps[0].ring;
 900         /*
 901          * FIXME we don't keep track of the dequeue pointer very well after a
 902          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 903          * host to our enqueue pointer.  This should only be called after a
 904          * configured device has reset, so all control transfers should have
 905          * been completed or cancelled before the reset.
 906          */
 907         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
 908                                                         ep_ring->enqueue)
 909                                    | ep_ring->cycle_state);
 910 }
 911
 912 /*
 913  * The xHCI roothub may have ports of differing speeds in any order in the port
 914  * status registers.  xhci->port_array provides an array of the port speed for
 915  * each offset into the port status registers.
 916  *
 917  * The xHCI hardware wants to know the roothub port number that the USB device
 918  * is attached to (or the roothub port its ancestor hub is attached to).  All we
 919  * know is the index of that port under either the USB 2.0 or the USB 3.0
 920  * roothub, but that doesn't give us the real index into the HW port status
 921  * registers.  Scan through the xHCI roothub port array, looking for the Nth
 922  * entry of the correct port speed.  Return the port number of that entry.
 923  */
 924 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
 925                 struct usb_device *udev)
 926 {
 927         struct usb_device *top_dev;
 928         unsigned int num_similar_speed_ports;
 929         unsigned int faked_port_num;
 930         int i;
 931
 932         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 933                         top_dev = top_dev->parent)
 934                 /* Found device below root hub */;
 935         faked_port_num = top_dev->portnum;
 936         for (i = 0, num_similar_speed_ports = 0;
 937                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 938                 u8 port_speed = xhci->port_array[i];
 939
 940                 /*
 941                  * Skip ports that don't have known speeds, or have duplicate
 942                  * Extended Capabilities port speed entries.
 943                  */
 944                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
 945                         continue;
 946
 947                 /*
 948                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
 949                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
 950                  * matches the device speed, it's a similar speed port.
 951                  */
 952                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
 953                         num_similar_speed_ports++;
 954                 if (num_similar_speed_ports == faked_port_num)
 955                         /* Roothub ports are numbered from 1 to N */
 956                         return i+1;
 957         }
 958         return 0;
 959 }
 960
 961 /* Setup an xHCI virtual device for a Set Address command */
 962 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 963 {
 964         struct xhci_virt_device *dev;
 965         struct xhci_ep_ctx      *ep0_ctx;
 966         struct xhci_slot_ctx    *slot_ctx;
 967         struct xhci_input_control_ctx *ctrl_ctx;
 968         u32                     port_num;
 969         struct usb_device *top_dev;
 970
 971         dev = xhci->devs[udev->slot_id];
 972         /* Slot ID 0 is reserved */
 973         if (udev->slot_id == 0 || !dev) {
 974                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 975                                 udev->slot_id);
 976                 return -EINVAL;
 977         }
 978         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
 979         ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
 980         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
 981
 982         /* 2) New slot context and endpoint 0 context are valid*/
 983         ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
 984
 985         /* 3) Only the control endpoint is valid - one endpoint context */
 986         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
 987         switch (udev->speed) {
 988         case USB_SPEED_SUPER:
 989                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
 990                 break;
 991         case USB_SPEED_HIGH:
 992                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
 993                 break;
 994         case USB_SPEED_FULL:
 995                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
 996                 break;
 997         case USB_SPEED_LOW:
 998                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
 999                 break;
1000         case USB_SPEED_WIRELESS:
1001                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1002                 return -EINVAL;
1003                 break;
1004         default:
1005                 /* Speed was set earlier, this shouldn't happen. */
1006                 BUG();
1007         }
1008         /* Find the root hub port this device is under */
1009         port_num = xhci_find_real_port_number(xhci, udev);
1010         if (!port_num)
1011                 return -EINVAL;
1012         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1013         /* Set the port number in the virtual_device to the faked port number */
1014         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1015                         top_dev = top_dev->parent)
1016                 /* Found device below root hub */;
1017         dev->fake_port = top_dev->portnum;
1018         dev->real_port = port_num;
1019         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1020         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1021
1022         /* Find the right bandwidth table that this device will be a part of.
1023          * If this is a full speed device attached directly to a root port (or a
1024          * decendent of one), it counts as a primary bandwidth domain, not a
1025          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1026          * will never be created for the HS root hub.
1027          */
1028         if (!udev->tt || !udev->tt->hub->parent) {
1029                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1030         } else {
1031                 struct xhci_root_port_bw_info *rh_bw;
1032                 struct xhci_tt_bw_info *tt_bw;
1033
1034                 rh_bw = &xhci->rh_bw[port_num - 1];
1035                 /* Find the right TT. */
1036                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1037                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1038                                 continue;
1039
1040                         if (!dev->udev->tt->multi ||
1041                                         (udev->tt->multi &&
1042                                          tt_bw->ttport == dev->udev->ttport)) {
1043                                 dev->bw_table = &tt_bw->bw_table;
1044                                 dev->tt_info = tt_bw;
1045                                 break;
1046                         }
1047                 }
1048                 if (!dev->tt_info)
1049                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1050         }
1051
1052         /* Is this a LS/FS device under an external HS hub? */
1053         if (udev->tt && udev->tt->hub->parent) {
1054                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1055                                                 (udev->ttport << 8));
1056                 if (udev->tt->multi)
1057                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1058         }
1059         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1060         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1061
1062         /* Step 4 - ring already allocated */
1063         /* Step 5 */
1064         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1065         /*
1066          * XXX: Not sure about wireless USB devices.
1067          */
1068         switch (udev->speed) {
1069         case USB_SPEED_SUPER:
1070                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1071                 break;
1072         case USB_SPEED_HIGH:
1073         /* USB core guesses at a 64-byte max packet first for FS devices */
1074         case USB_SPEED_FULL:
1075                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1076                 break;
1077         case USB_SPEED_LOW:
1078                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1079                 break;
1080         case USB_SPEED_WIRELESS:
1081                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1082                 return -EINVAL;
1083                 break;
1084         default:
1085                 /* New speed? */
1086                 BUG();
1087         }
1088         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1089         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1090
1091         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1092                                    dev->eps[0].ring->cycle_state);
1093
1094         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1095
1096         return 0;
1097 }
1098
1099 /*
1100  * Convert interval expressed as 2^(bInterval - 1) == interval into
1101  * straight exponent value 2^n == interval.
1102  *
1103  */
1104 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1105                 struct usb_host_endpoint *ep)
1106 {
1107         unsigned int interval;
1108
1109         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1110         if (interval != ep->desc.bInterval - 1)
1111                 dev_warn(&udev->dev,
1112                          "ep %#x - rounding interval to %d %sframes\n",
1113                          ep->desc.bEndpointAddress,
1114                          1 << interval,
1115                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1116
1117         if (udev->speed == USB_SPEED_FULL) {
1118                 /*
1119                  * Full speed isoc endpoints specify interval in frames,
1120                  * not microframes. We are using microframes everywhere,
1121                  * so adjust accordingly.
1122                  */
1123                 interval += 3;  /* 1 frame = 2^3 uframes */
1124         }
1125
1126         return interval;
1127 }
1128
1129 /*
1130  * Convert bInterval expressed in frames (in 1-255 range) to exponent of
1131  * microframes, rounded down to nearest power of 2.
1132  */
1133 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1134                 struct usb_host_endpoint *ep)
1135 {
1136         unsigned int interval;
1137
1138         interval = fls(8 * ep->desc.bInterval) - 1;
1139         interval = clamp_val(interval, 3, 10);
1140         if ((1 << interval) != 8 * ep->desc.bInterval)
1141                 dev_warn(&udev->dev,
1142                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1143                          ep->desc.bEndpointAddress,
1144                          1 << interval,
1145                          8 * ep->desc.bInterval);
1146
1147         return interval;
1148 }
1149
1150 /* Return the polling or NAK interval.
1151  *
1152  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1153  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1154  *
1155  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1156  * is set to 0.
1157  */
1158 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1159                 struct usb_host_endpoint *ep)
1160 {
1161         unsigned int interval = 0;
1162
1163         switch (udev->speed) {
1164         case USB_SPEED_HIGH:
1165                 /* Max NAK rate */
1166                 if (usb_endpoint_xfer_control(&ep->desc) ||
1167                     usb_endpoint_xfer_bulk(&ep->desc)) {
1168                         interval = ep->desc.bInterval;
1169                         break;
1170                 }
1171                 /* Fall through - SS and HS isoc/int have same decoding */
1172
1173         case USB_SPEED_SUPER:
1174                 if (usb_endpoint_xfer_int(&ep->desc) ||
1175                     usb_endpoint_xfer_isoc(&ep->desc)) {
1176                         interval = xhci_parse_exponent_interval(udev, ep);
1177                 }
1178                 break;
1179
1180         case USB_SPEED_FULL:
1181                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1182                         interval = xhci_parse_exponent_interval(udev, ep);
1183                         break;
1184                 }
1185                 /*
1186                  * Fall through for interrupt endpoint interval decoding
1187                  * since it uses the same rules as low speed interrupt
1188                  * endpoints.
1189                  */
1190
1191         case USB_SPEED_LOW:
1192                 if (usb_endpoint_xfer_int(&ep->desc) ||
1193                     usb_endpoint_xfer_isoc(&ep->desc)) {
1194
1195                         interval = xhci_parse_frame_interval(udev, ep);
1196                 }
1197                 break;
1198
1199         default:
1200                 BUG();
1201         }
1202         return EP_INTERVAL(interval);
1203 }
1204
1205 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1206  * High speed endpoint descriptors can define "the number of additional
1207  * transaction opportunities per microframe", but that goes in the Max Burst
1208  * endpoint context field.
1209  */
1210 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1211                 struct usb_host_endpoint *ep)
1212 {
1213         if (udev->speed != USB_SPEED_SUPER ||
1214                         !usb_endpoint_xfer_isoc(&ep->desc))
1215                 return 0;
1216         return ep->ss_ep_comp.bmAttributes;
1217 }
1218
1219 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1220                 struct usb_host_endpoint *ep)
1221 {
1222         int in;
1223         u32 type;
1224
1225         in = usb_endpoint_dir_in(&ep->desc);
1226         if (usb_endpoint_xfer_control(&ep->desc)) {
1227                 type = EP_TYPE(CTRL_EP);
1228         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1229                 if (in)
1230                         type = EP_TYPE(BULK_IN_EP);
1231                 else
1232                         type = EP_TYPE(BULK_OUT_EP);
1233         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1234                 if (in)
1235                         type = EP_TYPE(ISOC_IN_EP);
1236                 else
1237                         type = EP_TYPE(ISOC_OUT_EP);
1238         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1239                 if (in)
1240                         type = EP_TYPE(INT_IN_EP);
1241                 else
1242                         type = EP_TYPE(INT_OUT_EP);
1243         } else {
1244                 BUG();
1245         }
1246         return type;
1247 }
1248
1249 /* Return the maximum endpoint service interval time (ESIT) payload.
1250  * Basically, this is the maxpacket size, multiplied by the burst size
1251  * and mult size.
1252  */
1253 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1254                 struct usb_device *udev,
1255                 struct usb_host_endpoint *ep)
1256 {
1257         int max_burst;
1258         int max_packet;
1259
1260         /* Only applies for interrupt or isochronous endpoints */
1261         if (usb_endpoint_xfer_control(&ep->desc) ||
1262                         usb_endpoint_xfer_bulk(&ep->desc))
1263                 return 0;
1264
1265         if (udev->speed == USB_SPEED_SUPER)
1266                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1267
1268         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1269         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1270         /* A 0 in max burst means 1 transfer per ESIT */
1271         return max_packet * (max_burst + 1);
1272 }
1273
1274 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1275  * Drivers will have to call usb_alloc_streams() to do that.
1276  */
1277 int xhci_endpoint_init(struct xhci_hcd *xhci,
1278                 struct xhci_virt_device *virt_dev,
1279                 struct usb_device *udev,
1280                 struct usb_host_endpoint *ep,
1281                 gfp_t mem_flags)
1282 {
1283         unsigned int ep_index;
1284         struct xhci_ep_ctx *ep_ctx;
1285         struct xhci_ring *ep_ring;
1286         unsigned int max_packet;
1287         unsigned int max_burst;
1288         u32 max_esit_payload;
1289
1290         ep_index = xhci_get_endpoint_index(&ep->desc);
1291         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1292
1293         /* Set up the endpoint ring */
1294         /*
1295          * Isochronous endpoint ring needs bigger size because one isoc URB
1296          * carries multiple packets and it will insert multiple tds to the
1297          * ring.
1298          * This should be replaced with dynamic ring resizing in the future.
1299          */
1300         if (usb_endpoint_xfer_isoc(&ep->desc))
1301                 virt_dev->eps[ep_index].new_ring =
1302                         xhci_ring_alloc(xhci, 8, true, mem_flags);
1303         else
1304                 virt_dev->eps[ep_index].new_ring =
1305                         xhci_ring_alloc(xhci, 1, true, mem_flags);
1306         if (!virt_dev->eps[ep_index].new_ring) {
1307                 /* Attempt to use the ring cache */
1308                 if (virt_dev->num_rings_cached == 0)
1309                         return -ENOMEM;
1310                 virt_dev->eps[ep_index].new_ring =
1311                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1312                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1313                 virt_dev->num_rings_cached--;
1314                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
1315         }
1316         virt_dev->eps[ep_index].skip = false;
1317         ep_ring = virt_dev->eps[ep_index].new_ring;
1318         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1319
1320         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1321                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1322
1323         /* FIXME dig Mult and streams info out of ep companion desc */
1324
1325         /* Allow 3 retries for everything but isoc;
1326          * CErr shall be set to 0 for Isoch endpoints.
1327          */
1328         if (!usb_endpoint_xfer_isoc(&ep->desc))
1329                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1330         else
1331                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1332
1333         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1334
1335         /* Set the max packet size and max burst */
1336         switch (udev->speed) {
1337         case USB_SPEED_SUPER:
1338                 max_packet = usb_endpoint_maxp(&ep->desc);
1339                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1340                 /* dig out max burst from ep companion desc */
1341                 max_packet = ep->ss_ep_comp.bMaxBurst;
1342                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1343                 break;
1344         case USB_SPEED_HIGH:
1345                 /* bits 11:12 specify the number of additional transaction
1346                  * opportunities per microframe (USB 2.0, section 9.6.6)
1347                  */
1348                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1349                                 usb_endpoint_xfer_int(&ep->desc)) {
1350                         max_burst = (usb_endpoint_maxp(&ep->desc)
1351                                      & 0x1800) >> 11;
1352                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1353                 }
1354                 /* Fall through */
1355         case USB_SPEED_FULL:
1356         case USB_SPEED_LOW:
1357                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1358                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1359                 break;
1360         default:
1361                 BUG();
1362         }
1363         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1364         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1365
1366         /*
1367          * XXX no idea how to calculate the average TRB buffer length for bulk
1368          * endpoints, as the driver gives us no clue how big each scatter gather
1369          * list entry (or buffer) is going to be.
1370          *
1371          * For isochronous and interrupt endpoints, we set it to the max
1372          * available, until we have new API in the USB core to allow drivers to
1373          * declare how much bandwidth they actually need.
1374          *
1375          * Normally, it would be calculated by taking the total of the buffer
1376          * lengths in the TD and then dividing by the number of TRBs in a TD,
1377          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1378          * use Event Data TRBs, and we don't chain in a link TRB on short
1379          * transfers, we're basically dividing by 1.
1380          *
1381          * xHCI 1.0 specification indicates that the Average TRB Length should
1382          * be set to 8 for control endpoints.
1383          */
1384         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1385                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1386         else
1387                 ep_ctx->tx_info |=
1388                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1389
1390         /* FIXME Debug endpoint context */
1391         return 0;
1392 }
1393
1394 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1395                 struct xhci_virt_device *virt_dev,
1396                 struct usb_host_endpoint *ep)
1397 {
1398         unsigned int ep_index;
1399         struct xhci_ep_ctx *ep_ctx;
1400
1401         ep_index = xhci_get_endpoint_index(&ep->desc);
1402         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1403
1404         ep_ctx->ep_info = 0;
1405         ep_ctx->ep_info2 = 0;
1406         ep_ctx->deq = 0;
1407         ep_ctx->tx_info = 0;
1408         /* Don't free the endpoint ring until the set interface or configuration
1409          * request succeeds.
1410          */
1411 }
1412
1413 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1414 {
1415         bw_info->ep_interval = 0;
1416         bw_info->mult = 0;
1417         bw_info->num_packets = 0;
1418         bw_info->max_packet_size = 0;
1419         bw_info->type = 0;
1420         bw_info->max_esit_payload = 0;
1421 }
1422
1423 void xhci_update_bw_info(struct xhci_hcd *xhci,
1424                 struct xhci_container_ctx *in_ctx,
1425                 struct xhci_input_control_ctx *ctrl_ctx,
1426                 struct xhci_virt_device *virt_dev)
1427 {
1428         struct xhci_bw_info *bw_info;
1429         struct xhci_ep_ctx *ep_ctx;
1430         unsigned int ep_type;
1431         int i;
1432
1433         for (i = 1; i < 31; ++i) {
1434                 bw_info = &virt_dev->eps[i].bw_info;
1435
1436                 /* We can't tell what endpoint type is being dropped, but
1437                  * unconditionally clearing the bandwidth info for non-periodic
1438                  * endpoints should be harmless because the info will never be
1439                  * set in the first place.
1440                  */
1441                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1442                         /* Dropped endpoint */
1443                         xhci_clear_endpoint_bw_info(bw_info);
1444                         continue;
1445                 }
1446
1447                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1448                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1449                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1450
1451                         /* Ignore non-periodic endpoints */
1452                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1453                                         ep_type != ISOC_IN_EP &&
1454                                         ep_type != INT_IN_EP)
1455                                 continue;
1456
1457                         /* Added or changed endpoint */
1458                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1459                                         le32_to_cpu(ep_ctx->ep_info));
1460                         bw_info->mult = CTX_TO_EP_MULT(
1461                                         le32_to_cpu(ep_ctx->ep_info));
1462                         /* Number of packets is zero-based in the input context,
1463                          * but we want one-based for the interval table.
1464                          */
1465                         bw_info->num_packets = CTX_TO_MAX_BURST(
1466                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1467                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1468                                         le32_to_cpu(ep_ctx->ep_info2));
1469                         bw_info->type = ep_type;
1470                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1471                                         le32_to_cpu(ep_ctx->tx_info));
1472                 }
1473         }
1474 }
1475
1476 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1477  * Useful when you want to change one particular aspect of the endpoint and then
1478  * issue a configure endpoint command.
1479  */
1480 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1481                 struct xhci_container_ctx *in_ctx,
1482                 struct xhci_container_ctx *out_ctx,
1483                 unsigned int ep_index)
1484 {
1485         struct xhci_ep_ctx *out_ep_ctx;
1486         struct xhci_ep_ctx *in_ep_ctx;
1487
1488         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1489         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1490
1491         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1492         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1493         in_ep_ctx->deq = out_ep_ctx->deq;
1494         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1495 }
1496
1497 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1498  * Useful when you want to change one particular aspect of the endpoint and then
1499  * issue a configure endpoint command.  Only the context entries field matters,
1500  * but we'll copy the whole thing anyway.
1501  */
1502 void xhci_slot_copy(struct xhci_hcd *xhci,
1503                 struct xhci_container_ctx *in_ctx,
1504                 struct xhci_container_ctx *out_ctx)
1505 {
1506         struct xhci_slot_ctx *in_slot_ctx;
1507         struct xhci_slot_ctx *out_slot_ctx;
1508
1509         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1510         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1511
1512         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1513         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1514         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1515         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1516 }
1517
1518 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1519 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1520 {
1521         int i;
1522         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1523         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1524
1525         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1526
1527         if (!num_sp)
1528                 return 0;
1529
1530         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1531         if (!xhci->scratchpad)
1532                 goto fail_sp;
1533
1534         xhci->scratchpad->sp_array =
1535                 pci_alloc_consistent(to_pci_dev(dev),
1536                                      num_sp * sizeof(u64),
1537                                      &xhci->scratchpad->sp_dma);
1538         if (!xhci->scratchpad->sp_array)
1539                 goto fail_sp2;
1540
1541         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1542         if (!xhci->scratchpad->sp_buffers)
1543                 goto fail_sp3;
1544
1545         xhci->scratchpad->sp_dma_buffers =
1546                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1547
1548         if (!xhci->scratchpad->sp_dma_buffers)
1549                 goto fail_sp4;
1550
1551         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1552         for (i = 0; i < num_sp; i++) {
1553                 dma_addr_t dma;
1554                 void *buf = pci_alloc_consistent(to_pci_dev(dev),
1555                                                  xhci->page_size, &dma);
1556                 if (!buf)
1557                         goto fail_sp5;
1558
1559                 xhci->scratchpad->sp_array[i] = dma;
1560                 xhci->scratchpad->sp_buffers[i] = buf;
1561                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1562         }
1563
1564         return 0;
1565
1566  fail_sp5:
1567         for (i = i - 1; i >= 0; i--) {
1568                 pci_free_consistent(to_pci_dev(dev), xhci->page_size,
1569                                     xhci->scratchpad->sp_buffers[i],
1570                                     xhci->scratchpad->sp_dma_buffers[i]);
1571         }
1572         kfree(xhci->scratchpad->sp_dma_buffers);
1573
1574  fail_sp4:
1575         kfree(xhci->scratchpad->sp_buffers);
1576
1577  fail_sp3:
1578         pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
1579                             xhci->scratchpad->sp_array,
1580                             xhci->scratchpad->sp_dma);
1581
1582  fail_sp2:
1583         kfree(xhci->scratchpad);
1584         xhci->scratchpad = NULL;
1585
1586  fail_sp:
1587         return -ENOMEM;
1588 }
1589
1590 static void scratchpad_free(struct xhci_hcd *xhci)
1591 {
1592         int num_sp;
1593         int i;
1594         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1595
1596         if (!xhci->scratchpad)
1597                 return;
1598
1599         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1600
1601         for (i = 0; i < num_sp; i++) {
1602                 pci_free_consistent(pdev, xhci->page_size,
1603                                     xhci->scratchpad->sp_buffers[i],
1604                                     xhci->scratchpad->sp_dma_buffers[i]);
1605         }
1606         kfree(xhci->scratchpad->sp_dma_buffers);
1607         kfree(xhci->scratchpad->sp_buffers);
1608         pci_free_consistent(pdev, num_sp * sizeof(u64),
1609                             xhci->scratchpad->sp_array,
1610                             xhci->scratchpad->sp_dma);
1611         kfree(xhci->scratchpad);
1612         xhci->scratchpad = NULL;
1613 }
1614
1615 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1616                 bool allocate_in_ctx, bool allocate_completion,
1617                 gfp_t mem_flags)
1618 {
1619         struct xhci_command *command;
1620
1621         command = kzalloc(sizeof(*command), mem_flags);
1622         if (!command)
1623                 return NULL;
1624
1625         if (allocate_in_ctx) {
1626                 command->in_ctx =
1627                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1628                                         mem_flags);
1629                 if (!command->in_ctx) {
1630                         kfree(command);
1631                         return NULL;
1632                 }
1633         }
1634
1635         if (allocate_completion) {
1636                 command->completion =
1637                         kzalloc(sizeof(struct completion), mem_flags);
1638                 if (!command->completion) {
1639                         xhci_free_container_ctx(xhci, command->in_ctx);
1640                         kfree(command);
1641                         return NULL;
1642                 }
1643                 init_completion(command->completion);
1644         }
1645
1646         command->status = 0;
1647         INIT_LIST_HEAD(&command->cmd_list);
1648         return command;
1649 }
1650
1651 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1652 {
1653         int last;
1654
1655         if (!urb_priv)
1656                 return;
1657
1658         last = urb_priv->length - 1;
1659         if (last >= 0) {
1660                 int     i;
1661                 for (i = 0; i <= last; i++)
1662                         kfree(urb_priv->td[i]);
1663         }
1664         kfree(urb_priv);
1665 }
1666
1667 void xhci_free_command(struct xhci_hcd *xhci,
1668                 struct xhci_command *command)
1669 {
1670         xhci_free_container_ctx(xhci,
1671                         command->in_ctx);
1672         kfree(command->completion);
1673         kfree(command);
1674 }
1675
1676 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1677 {
1678         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1679         int size;
1680         int i;
1681
1682         /* Free the Event Ring Segment Table and the actual Event Ring */
1683         if (xhci->ir_set) {
1684                 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
1685                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
1686                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
1687         }
1688         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1689         if (xhci->erst.entries)
1690                 pci_free_consistent(pdev, size,
1691                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1692         xhci->erst.entries = NULL;
1693         xhci_dbg(xhci, "Freed ERST\n");
1694         if (xhci->event_ring)
1695                 xhci_ring_free(xhci, xhci->event_ring);
1696         xhci->event_ring = NULL;
1697         xhci_dbg(xhci, "Freed event ring\n");
1698
1699         xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
1700         if (xhci->cmd_ring)
1701                 xhci_ring_free(xhci, xhci->cmd_ring);
1702         xhci->cmd_ring = NULL;
1703         xhci_dbg(xhci, "Freed command ring\n");
1704
1705         for (i = 1; i < MAX_HC_SLOTS; ++i)
1706                 xhci_free_virt_device(xhci, i);
1707
1708         if (xhci->segment_pool)
1709                 dma_pool_destroy(xhci->segment_pool);
1710         xhci->segment_pool = NULL;
1711         xhci_dbg(xhci, "Freed segment pool\n");
1712
1713         if (xhci->device_pool)
1714                 dma_pool_destroy(xhci->device_pool);
1715         xhci->device_pool = NULL;
1716         xhci_dbg(xhci, "Freed device context pool\n");
1717
1718         if (xhci->small_streams_pool)
1719                 dma_pool_destroy(xhci->small_streams_pool);
1720         xhci->small_streams_pool = NULL;
1721         xhci_dbg(xhci, "Freed small stream array pool\n");
1722
1723         if (xhci->medium_streams_pool)
1724                 dma_pool_destroy(xhci->medium_streams_pool);
1725         xhci->medium_streams_pool = NULL;
1726         xhci_dbg(xhci, "Freed medium stream array pool\n");
1727
1728         xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
1729         if (xhci->dcbaa)
1730                 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
1731                                 xhci->dcbaa, xhci->dcbaa->dma);
1732         xhci->dcbaa = NULL;
1733
1734         scratchpad_free(xhci);
1735
1736         xhci->num_usb2_ports = 0;
1737         xhci->num_usb3_ports = 0;
1738         kfree(xhci->usb2_ports);
1739         kfree(xhci->usb3_ports);
1740         kfree(xhci->port_array);
1741         kfree(xhci->rh_bw);
1742
1743         xhci->page_size = 0;
1744         xhci->page_shift = 0;
1745         xhci->bus_state[0].bus_suspended = 0;
1746         xhci->bus_state[1].bus_suspended = 0;
1747 }
1748
1749 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1750                 struct xhci_segment *input_seg,
1751                 union xhci_trb *start_trb,
1752                 union xhci_trb *end_trb,
1753                 dma_addr_t input_dma,
1754                 struct xhci_segment *result_seg,
1755                 char *test_name, int test_number)
1756 {
1757         unsigned long long start_dma;
1758         unsigned long long end_dma;
1759         struct xhci_segment *seg;
1760
1761         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1762         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1763
1764         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1765         if (seg != result_seg) {
1766                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1767                                 test_name, test_number);
1768                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1769                                 "input DMA 0x%llx\n",
1770                                 input_seg,
1771                                 (unsigned long long) input_dma);
1772                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1773                                 "ending TRB %p (0x%llx DMA)\n",
1774                                 start_trb, start_dma,
1775                                 end_trb, end_dma);
1776                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1777                                 result_seg, seg);
1778                 return -1;
1779         }
1780         return 0;
1781 }
1782
1783 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1784 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1785 {
1786         struct {
1787                 dma_addr_t              input_dma;
1788                 struct xhci_segment     *result_seg;
1789         } simple_test_vector [] = {
1790                 /* A zeroed DMA field should fail */
1791                 { 0, NULL },
1792                 /* One TRB before the ring start should fail */
1793                 { xhci->event_ring->first_seg->dma - 16, NULL },
1794                 /* One byte before the ring start should fail */
1795                 { xhci->event_ring->first_seg->dma - 1, NULL },
1796                 /* Starting TRB should succeed */
1797                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1798                 /* Ending TRB should succeed */
1799                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1800                         xhci->event_ring->first_seg },
1801                 /* One byte after the ring end should fail */
1802                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1803                 /* One TRB after the ring end should fail */
1804                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1805                 /* An address of all ones should fail */
1806                 { (dma_addr_t) (~0), NULL },
1807         };
1808         struct {
1809                 struct xhci_segment     *input_seg;
1810                 union xhci_trb          *start_trb;
1811                 union xhci_trb          *end_trb;
1812                 dma_addr_t              input_dma;
1813                 struct xhci_segment     *result_seg;
1814         } complex_test_vector [] = {
1815                 /* Test feeding a valid DMA address from a different ring */
1816                 {       .input_seg = xhci->event_ring->first_seg,
1817                         .start_trb = xhci->event_ring->first_seg->trbs,
1818                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1819                         .input_dma = xhci->cmd_ring->first_seg->dma,
1820                         .result_seg = NULL,
1821                 },
1822                 /* Test feeding a valid end TRB from a different ring */
1823                 {       .input_seg = xhci->event_ring->first_seg,
1824                         .start_trb = xhci->event_ring->first_seg->trbs,
1825                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1826                         .input_dma = xhci->cmd_ring->first_seg->dma,
1827                         .result_seg = NULL,
1828                 },
1829                 /* Test feeding a valid start and end TRB from a different ring */
1830                 {       .input_seg = xhci->event_ring->first_seg,
1831                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1832                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1833                         .input_dma = xhci->cmd_ring->first_seg->dma,
1834                         .result_seg = NULL,
1835                 },
1836                 /* TRB in this ring, but after this TD */
1837                 {       .input_seg = xhci->event_ring->first_seg,
1838                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1839                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1840                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1841                         .result_seg = NULL,
1842                 },
1843                 /* TRB in this ring, but before this TD */
1844                 {       .input_seg = xhci->event_ring->first_seg,
1845                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1846                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1847                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1848                         .result_seg = NULL,
1849                 },
1850                 /* TRB in this ring, but after this wrapped TD */
1851                 {       .input_seg = xhci->event_ring->first_seg,
1852                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1853                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1854                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1855                         .result_seg = NULL,
1856                 },
1857                 /* TRB in this ring, but before this wrapped TD */
1858                 {       .input_seg = xhci->event_ring->first_seg,
1859                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1860                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1861                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1862                         .result_seg = NULL,
1863                 },
1864                 /* TRB not in this ring, and we have a wrapped TD */
1865                 {       .input_seg = xhci->event_ring->first_seg,
1866                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1867                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1868                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1869                         .result_seg = NULL,
1870                 },
1871         };
1872
1873         unsigned int num_tests;
1874         int i, ret;
1875
1876         num_tests = ARRAY_SIZE(simple_test_vector);
1877         for (i = 0; i < num_tests; i++) {
1878                 ret = xhci_test_trb_in_td(xhci,
1879                                 xhci->event_ring->first_seg,
1880                                 xhci->event_ring->first_seg->trbs,
1881                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1882                                 simple_test_vector[i].input_dma,
1883                                 simple_test_vector[i].result_seg,
1884                                 "Simple", i);
1885                 if (ret < 0)
1886                         return ret;
1887         }
1888
1889         num_tests = ARRAY_SIZE(complex_test_vector);
1890         for (i = 0; i < num_tests; i++) {
1891                 ret = xhci_test_trb_in_td(xhci,
1892                                 complex_test_vector[i].input_seg,
1893                                 complex_test_vector[i].start_trb,
1894                                 complex_test_vector[i].end_trb,
1895                                 complex_test_vector[i].input_dma,
1896                                 complex_test_vector[i].result_seg,
1897                                 "Complex", i);
1898                 if (ret < 0)
1899                         return ret;
1900         }
1901         xhci_dbg(xhci, "TRB math tests passed.\n");
1902         return 0;
1903 }
1904
1905 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1906 {
1907         u64 temp;
1908         dma_addr_t deq;
1909
1910         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1911                         xhci->event_ring->dequeue);
1912         if (deq == 0 && !in_interrupt())
1913                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1914                                 "dequeue ptr.\n");
1915         /* Update HC event ring dequeue pointer */
1916         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1917         temp &= ERST_PTR_MASK;
1918         /* Don't clear the EHB bit (which is RW1C) because
1919          * there might be more events to service.
1920          */
1921         temp &= ~ERST_EHB;
1922         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1923                         "preserving EHB bit\n");
1924         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1925                         &xhci->ir_set->erst_dequeue);
1926 }
1927
1928 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1929                 __le32 __iomem *addr, u8 major_revision)
1930 {
1931         u32 temp, port_offset, port_count;
1932         int i;
1933
1934         if (major_revision > 0x03) {
1935                 xhci_warn(xhci, "Ignoring unknown port speed, "
1936                                 "Ext Cap %p, revision = 0x%x\n",
1937                                 addr, major_revision);
1938                 /* Ignoring port protocol we can't understand. FIXME */
1939                 return;
1940         }
1941
1942         /* Port offset and count in the third dword, see section 7.2 */
1943         temp = xhci_readl(xhci, addr + 2);
1944         port_offset = XHCI_EXT_PORT_OFF(temp);
1945         port_count = XHCI_EXT_PORT_COUNT(temp);
1946         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
1947                         "count = %u, revision = 0x%x\n",
1948                         addr, port_offset, port_count, major_revision);
1949         /* Port count includes the current port offset */
1950         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
1951                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1952                 return;
1953         port_offset--;
1954         for (i = port_offset; i < (port_offset + port_count); i++) {
1955                 /* Duplicate entry.  Ignore the port if the revisions differ. */
1956                 if (xhci->port_array[i] != 0) {
1957                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
1958                                         " port %u\n", addr, i);
1959                         xhci_warn(xhci, "Port was marked as USB %u, "
1960                                         "duplicated as USB %u\n",
1961                                         xhci->port_array[i], major_revision);
1962                         /* Only adjust the roothub port counts if we haven't
1963                          * found a similar duplicate.
1964                          */
1965                         if (xhci->port_array[i] != major_revision &&
1966                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
1967                                 if (xhci->port_array[i] == 0x03)
1968                                         xhci->num_usb3_ports--;
1969                                 else
1970                                         xhci->num_usb2_ports--;
1971                                 xhci->port_array[i] = DUPLICATE_ENTRY;
1972                         }
1973                         /* FIXME: Should we disable the port? */
1974                         continue;
1975                 }
1976                 xhci->port_array[i] = major_revision;
1977                 if (major_revision == 0x03)
1978                         xhci->num_usb3_ports++;
1979                 else
1980                         xhci->num_usb2_ports++;
1981         }
1982         /* FIXME: Should we disable ports not in the Extended Capabilities? */
1983 }
1984
1985 /*
1986  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1987  * specify what speeds each port is supposed to be.  We can't count on the port
1988  * speed bits in the PORTSC register being correct until a device is connected,
1989  * but we need to set up the two fake roothubs with the correct number of USB
1990  * 3.0 and USB 2.0 ports at host controller initialization time.
1991  */
1992 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
1993 {
1994         __le32 __iomem *addr;
1995         u32 offset;
1996         unsigned int num_ports;
1997         int i, port_index;
1998
1999         addr = &xhci->cap_regs->hcc_params;
2000         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2001         if (offset == 0) {
2002                 xhci_err(xhci, "No Extended Capability registers, "
2003                                 "unable to set up roothub.\n");
2004                 return -ENODEV;
2005         }
2006
2007         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2008         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2009         if (!xhci->port_array)
2010                 return -ENOMEM;
2011
2012         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2013         if (!xhci->rh_bw)
2014                 return -ENOMEM;
2015         for (i = 0; i < num_ports; i++)
2016                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2017
2018         /*
2019          * For whatever reason, the first capability offset is from the
2020          * capability register base, not from the HCCPARAMS register.
2021          * See section 5.3.6 for offset calculation.
2022          */
2023         addr = &xhci->cap_regs->hc_capbase + offset;
2024         while (1) {
2025                 u32 cap_id;
2026
2027                 cap_id = xhci_readl(xhci, addr);
2028                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2029                         xhci_add_in_port(xhci, num_ports, addr,
2030                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2031                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2032                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2033                                 == num_ports)
2034                         break;
2035                 /*
2036                  * Once you're into the Extended Capabilities, the offset is
2037                  * always relative to the register holding the offset.
2038                  */
2039                 addr += offset;
2040         }
2041
2042         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2043                 xhci_warn(xhci, "No ports on the roothubs?\n");
2044                 return -ENODEV;
2045         }
2046         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2047                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2048
2049         /* Place limits on the number of roothub ports so that the hub
2050          * descriptors aren't longer than the USB core will allocate.
2051          */
2052         if (xhci->num_usb3_ports > 15) {
2053                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2054                 xhci->num_usb3_ports = 15;
2055         }
2056         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2057                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2058                                 USB_MAXCHILDREN);
2059                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2060         }
2061
2062         /*
2063          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2064          * Not sure how the USB core will handle a hub with no ports...
2065          */
2066         if (xhci->num_usb2_ports) {
2067                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2068                                 xhci->num_usb2_ports, flags);
2069                 if (!xhci->usb2_ports)
2070                         return -ENOMEM;
2071
2072                 port_index = 0;
2073                 for (i = 0; i < num_ports; i++) {
2074                         if (xhci->port_array[i] == 0x03 ||
2075                                         xhci->port_array[i] == 0 ||
2076                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2077                                 continue;
2078
2079                         xhci->usb2_ports[port_index] =
2080                                 &xhci->op_regs->port_status_base +
2081                                 NUM_PORT_REGS*i;
2082                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2083                                         "addr = %p\n", i,
2084                                         xhci->usb2_ports[port_index]);
2085                         port_index++;
2086                         if (port_index == xhci->num_usb2_ports)
2087                                 break;
2088                 }
2089         }
2090         if (xhci->num_usb3_ports) {
2091                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2092                                 xhci->num_usb3_ports, flags);
2093                 if (!xhci->usb3_ports)
2094                         return -ENOMEM;
2095
2096                 port_index = 0;
2097                 for (i = 0; i < num_ports; i++)
2098                         if (xhci->port_array[i] == 0x03) {
2099                                 xhci->usb3_ports[port_index] =
2100                                         &xhci->op_regs->port_status_base +
2101                                         NUM_PORT_REGS*i;
2102                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2103                                                 "addr = %p\n", i,
2104                                                 xhci->usb3_ports[port_index]);
2105                                 port_index++;
2106                                 if (port_index == xhci->num_usb3_ports)
2107                                         break;
2108                         }
2109         }
2110         return 0;
2111 }
2112
2113 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2114 {
2115         dma_addr_t      dma;
2116         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2117         unsigned int    val, val2;
2118         u64             val_64;
2119         struct xhci_segment     *seg;
2120         u32 page_size;
2121         int i;
2122
2123         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2124         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2125         for (i = 0; i < 16; i++) {
2126                 if ((0x1 & page_size) != 0)
2127                         break;
2128                 page_size = page_size >> 1;
2129         }
2130         if (i < 16)
2131                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2132         else
2133                 xhci_warn(xhci, "WARN: no supported page size\n");
2134         /* Use 4K pages, since that's common and the minimum the HC supports */
2135         xhci->page_shift = 12;
2136         xhci->page_size = 1 << xhci->page_shift;
2137         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2138
2139         /*
2140          * Program the Number of Device Slots Enabled field in the CONFIG
2141          * register with the max value of slots the HC can handle.
2142          */
2143         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2144         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2145                         (unsigned int) val);
2146         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2147         val |= (val2 & ~HCS_SLOTS_MASK);
2148         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2149                         (unsigned int) val);
2150         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2151
2152         /*
2153          * Section 5.4.8 - doorbell array must be
2154          * "physically contiguous and 64-byte (cache line) aligned".
2155          */
2156         xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
2157                         sizeof(*xhci->dcbaa), &dma);
2158         if (!xhci->dcbaa)
2159                 goto fail;
2160         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2161         xhci->dcbaa->dma = dma;
2162         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2163                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2164         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2165
2166         /*
2167          * Initialize the ring segment pool.  The ring must be a contiguous
2168          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2169          * however, the command ring segment needs 64-byte aligned segments,
2170          * so we pick the greater alignment need.
2171          */
2172         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2173                         SEGMENT_SIZE, 64, xhci->page_size);
2174
2175         /* See Table 46 and Note on Figure 55 */
2176         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2177                         2112, 64, xhci->page_size);
2178         if (!xhci->segment_pool || !xhci->device_pool)
2179                 goto fail;
2180
2181         /* Linear stream context arrays don't have any boundary restrictions,
2182          * and only need to be 16-byte aligned.
2183          */
2184         xhci->small_streams_pool =
2185                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2186                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2187         xhci->medium_streams_pool =
2188                 dma_pool_create("xHCI 1KB stream ctx arrays",
2189                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2190         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2191          * will be allocated with pci_alloc_consistent()
2192          */
2193
2194         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2195                 goto fail;
2196
2197         /* Set up the command ring to have one segments for now. */
2198         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
2199         if (!xhci->cmd_ring)
2200                 goto fail;
2201         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2202         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2203                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2204
2205         /* Set the address in the Command Ring Control register */
2206         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2207         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2208                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2209                 xhci->cmd_ring->cycle_state;
2210         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2211         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2212         xhci_dbg_cmd_ptrs(xhci);
2213
2214         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2215         val &= DBOFF_MASK;
2216         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2217                         " from cap regs base addr\n", val);
2218         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2219         xhci_dbg_regs(xhci);
2220         xhci_print_run_regs(xhci);
2221         /* Set ir_set to interrupt register set 0 */
2222         xhci->ir_set = &xhci->run_regs->ir_set[0];
2223
2224         /*
2225          * Event ring setup: Allocate a normal ring, but also setup
2226          * the event ring segment table (ERST).  Section 4.9.3.
2227          */
2228         xhci_dbg(xhci, "// Allocating event ring\n");
2229         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
2230         if (!xhci->event_ring)
2231                 goto fail;
2232         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2233                 goto fail;
2234
2235         xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
2236                         sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
2237         if (!xhci->erst.entries)
2238                 goto fail;
2239         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2240                         (unsigned long long)dma);
2241
2242         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2243         xhci->erst.num_entries = ERST_NUM_SEGS;
2244         xhci->erst.erst_dma_addr = dma;
2245         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2246                         xhci->erst.num_entries,
2247                         xhci->erst.entries,
2248                         (unsigned long long)xhci->erst.erst_dma_addr);
2249
2250         /* set ring base address and size for each segment table entry */
2251         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2252                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2253                 entry->seg_addr = cpu_to_le64(seg->dma);
2254                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2255                 entry->rsvd = 0;
2256                 seg = seg->next;
2257         }
2258
2259         /* set ERST count with the number of entries in the segment table */
2260         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2261         val &= ERST_SIZE_MASK;
2262         val |= ERST_NUM_SEGS;
2263         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2264                         val);
2265         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2266
2267         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2268         /* set the segment table base address */
2269         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2270                         (unsigned long long)xhci->erst.erst_dma_addr);
2271         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2272         val_64 &= ERST_PTR_MASK;
2273         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2274         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2275
2276         /* Set the event ring dequeue address */
2277         xhci_set_hc_event_deq(xhci);
2278         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2279         xhci_print_ir_set(xhci, 0);
2280
2281         /*
2282          * XXX: Might need to set the Interrupter Moderation Register to
2283          * something other than the default (~1ms minimum between interrupts).
2284          * See section 5.5.1.2.
2285          */
2286         init_completion(&xhci->addr_dev);
2287         for (i = 0; i < MAX_HC_SLOTS; ++i)
2288                 xhci->devs[i] = NULL;
2289         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2290                 xhci->bus_state[0].resume_done[i] = 0;
2291                 xhci->bus_state[1].resume_done[i] = 0;
2292         }
2293
2294         if (scratchpad_alloc(xhci, flags))
2295                 goto fail;
2296         if (xhci_setup_port_arrays(xhci, flags))
2297                 goto fail;
2298
2299         return 0;
2300
2301 fail:
2302         xhci_warn(xhci, "Couldn't initialize memory\n");
2303         xhci_mem_cleanup(xhci);
2304         return -ENOMEM;
2305 }