xhci-mem.c: xhci_segment_free: No need for checking seg argument
[pandora-kernel.git] / drivers / usb / host / xhci-mem.c
1 /*
2  * xHCI host controller driver
3  *
4  * Copyright (C) 2008 Intel Corp.
5  *
6  * Author: Sarah Sharp
7  * Some code borrowed from the Linux EHCI driver.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16  * for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software Foundation,
20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
27
28 #include "xhci.h"
29
30 /*
31  * Allocates a generic ring segment from the ring pool, sets the dma address,
32  * initializes the segment to zero, and sets the private next pointer to NULL.
33  *
34  * Section 4.11.1.1:
35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
36  */
37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
38 {
39         struct xhci_segment *seg;
40         dma_addr_t      dma;
41
42         seg = kzalloc(sizeof *seg, flags);
43         if (!seg)
44                 return NULL;
45         xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
46
47         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
48         if (!seg->trbs) {
49                 kfree(seg);
50                 return NULL;
51         }
52         xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
53                         seg->trbs, (unsigned long long)dma);
54
55         memset(seg->trbs, 0, SEGMENT_SIZE);
56         seg->dma = dma;
57         seg->next = NULL;
58
59         return seg;
60 }
61
62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
63 {
64         if (seg->trbs) {
65                 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
66                                 seg->trbs, (unsigned long long)seg->dma);
67                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
68                 seg->trbs = NULL;
69         }
70         xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
71         kfree(seg);
72 }
73
74 /*
75  * Make the prev segment point to the next segment.
76  *
77  * Change the last TRB in the prev segment to be a Link TRB which points to the
78  * DMA address of the next segment.  The caller needs to set any Link TRB
79  * related flags, such as End TRB, Toggle Cycle, and no snoop.
80  */
81 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
82                 struct xhci_segment *next, bool link_trbs)
83 {
84         u32 val;
85
86         if (!prev || !next)
87                 return;
88         prev->next = next;
89         if (link_trbs) {
90                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
91                         cpu_to_le64(next->dma);
92
93                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
94                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
95                 val &= ~TRB_TYPE_BITMASK;
96                 val |= TRB_TYPE(TRB_LINK);
97                 /* Always set the chain bit with 0.95 hardware */
98                 if (xhci_link_trb_quirk(xhci))
99                         val |= TRB_CHAIN;
100                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
101         }
102         xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
103                         (unsigned long long)prev->dma,
104                         (unsigned long long)next->dma);
105 }
106
107 /* XXX: Do we need the hcd structure in all these functions? */
108 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
109 {
110         struct xhci_segment *seg;
111         struct xhci_segment *first_seg;
112
113         if (!ring)
114                 return;
115         if (ring->first_seg) {
116                 first_seg = ring->first_seg;
117                 seg = first_seg->next;
118                 xhci_dbg(xhci, "Freeing ring at %p\n", ring);
119                 while (seg != first_seg) {
120                         struct xhci_segment *next = seg->next;
121                         xhci_segment_free(xhci, seg);
122                         seg = next;
123                 }
124                 xhci_segment_free(xhci, first_seg);
125                 ring->first_seg = NULL;
126         }
127         kfree(ring);
128 }
129
130 static void xhci_initialize_ring_info(struct xhci_ring *ring)
131 {
132         /* The ring is empty, so the enqueue pointer == dequeue pointer */
133         ring->enqueue = ring->first_seg->trbs;
134         ring->enq_seg = ring->first_seg;
135         ring->dequeue = ring->enqueue;
136         ring->deq_seg = ring->first_seg;
137         /* The ring is initialized to 0. The producer must write 1 to the cycle
138          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
139          * compare CCS to the cycle bit to check ownership, so CCS = 1.
140          */
141         ring->cycle_state = 1;
142         /* Not necessary for new rings, but needed for re-initialized rings */
143         ring->enq_updates = 0;
144         ring->deq_updates = 0;
145 }
146
147 /**
148  * Create a new ring with zero or more segments.
149  *
150  * Link each segment together into a ring.
151  * Set the end flag and the cycle toggle bit on the last segment.
152  * See section 4.9.1 and figures 15 and 16.
153  */
154 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
155                 unsigned int num_segs, bool link_trbs, gfp_t flags)
156 {
157         struct xhci_ring        *ring;
158         struct xhci_segment     *prev;
159
160         ring = kzalloc(sizeof *(ring), flags);
161         xhci_dbg(xhci, "Allocating ring at %p\n", ring);
162         if (!ring)
163                 return NULL;
164
165         INIT_LIST_HEAD(&ring->td_list);
166         if (num_segs == 0)
167                 return ring;
168
169         ring->first_seg = xhci_segment_alloc(xhci, flags);
170         if (!ring->first_seg)
171                 goto fail;
172         num_segs--;
173
174         prev = ring->first_seg;
175         while (num_segs > 0) {
176                 struct xhci_segment     *next;
177
178                 next = xhci_segment_alloc(xhci, flags);
179                 if (!next)
180                         goto fail;
181                 xhci_link_segments(xhci, prev, next, link_trbs);
182
183                 prev = next;
184                 num_segs--;
185         }
186         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
187
188         if (link_trbs) {
189                 /* See section 4.9.2.1 and 6.4.4.1 */
190                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
191                         cpu_to_le32(LINK_TOGGLE);
192                 xhci_dbg(xhci, "Wrote link toggle flag to"
193                                 " segment %p (virtual), 0x%llx (DMA)\n",
194                                 prev, (unsigned long long)prev->dma);
195         }
196         xhci_initialize_ring_info(ring);
197         return ring;
198
199 fail:
200         xhci_ring_free(xhci, ring);
201         return NULL;
202 }
203
204 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
205                 struct xhci_virt_device *virt_dev,
206                 unsigned int ep_index)
207 {
208         int rings_cached;
209
210         rings_cached = virt_dev->num_rings_cached;
211         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
212                 virt_dev->ring_cache[rings_cached] =
213                         virt_dev->eps[ep_index].ring;
214                 virt_dev->num_rings_cached++;
215                 xhci_dbg(xhci, "Cached old ring, "
216                                 "%d ring%s cached\n",
217                                 virt_dev->num_rings_cached,
218                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
219         } else {
220                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
221                 xhci_dbg(xhci, "Ring cache full (%d rings), "
222                                 "freeing ring\n",
223                                 virt_dev->num_rings_cached);
224         }
225         virt_dev->eps[ep_index].ring = NULL;
226 }
227
228 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
229  * pointers to the beginning of the ring.
230  */
231 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
232                 struct xhci_ring *ring)
233 {
234         struct xhci_segment     *seg = ring->first_seg;
235         do {
236                 memset(seg->trbs, 0,
237                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
238                 /* All endpoint rings have link TRBs */
239                 xhci_link_segments(xhci, seg, seg->next, 1);
240                 seg = seg->next;
241         } while (seg != ring->first_seg);
242         xhci_initialize_ring_info(ring);
243         /* td list should be empty since all URBs have been cancelled,
244          * but just in case...
245          */
246         INIT_LIST_HEAD(&ring->td_list);
247 }
248
249 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
250
251 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
252                                                     int type, gfp_t flags)
253 {
254         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
255         if (!ctx)
256                 return NULL;
257
258         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
259         ctx->type = type;
260         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
261         if (type == XHCI_CTX_TYPE_INPUT)
262                 ctx->size += CTX_SIZE(xhci->hcc_params);
263
264         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
265         memset(ctx->bytes, 0, ctx->size);
266         return ctx;
267 }
268
269 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
270                              struct xhci_container_ctx *ctx)
271 {
272         if (!ctx)
273                 return;
274         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
275         kfree(ctx);
276 }
277
278 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
279                                               struct xhci_container_ctx *ctx)
280 {
281         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
282         return (struct xhci_input_control_ctx *)ctx->bytes;
283 }
284
285 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
286                                         struct xhci_container_ctx *ctx)
287 {
288         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
289                 return (struct xhci_slot_ctx *)ctx->bytes;
290
291         return (struct xhci_slot_ctx *)
292                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
293 }
294
295 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
296                                     struct xhci_container_ctx *ctx,
297                                     unsigned int ep_index)
298 {
299         /* increment ep index by offset of start of ep ctx array */
300         ep_index++;
301         if (ctx->type == XHCI_CTX_TYPE_INPUT)
302                 ep_index++;
303
304         return (struct xhci_ep_ctx *)
305                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
306 }
307
308
309 /***************** Streams structures manipulation *************************/
310
311 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
312                 unsigned int num_stream_ctxs,
313                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
314 {
315         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
316
317         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
318                 pci_free_consistent(pdev,
319                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
320                                 stream_ctx, dma);
321         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
322                 return dma_pool_free(xhci->small_streams_pool,
323                                 stream_ctx, dma);
324         else
325                 return dma_pool_free(xhci->medium_streams_pool,
326                                 stream_ctx, dma);
327 }
328
329 /*
330  * The stream context array for each endpoint with bulk streams enabled can
331  * vary in size, based on:
332  *  - how many streams the endpoint supports,
333  *  - the maximum primary stream array size the host controller supports,
334  *  - and how many streams the device driver asks for.
335  *
336  * The stream context array must be a power of 2, and can be as small as
337  * 64 bytes or as large as 1MB.
338  */
339 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
340                 unsigned int num_stream_ctxs, dma_addr_t *dma,
341                 gfp_t mem_flags)
342 {
343         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
344
345         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
346                 return pci_alloc_consistent(pdev,
347                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
348                                 dma);
349         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
350                 return dma_pool_alloc(xhci->small_streams_pool,
351                                 mem_flags, dma);
352         else
353                 return dma_pool_alloc(xhci->medium_streams_pool,
354                                 mem_flags, dma);
355 }
356
357 struct xhci_ring *xhci_dma_to_transfer_ring(
358                 struct xhci_virt_ep *ep,
359                 u64 address)
360 {
361         if (ep->ep_state & EP_HAS_STREAMS)
362                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
363                                 address >> SEGMENT_SHIFT);
364         return ep->ring;
365 }
366
367 /* Only use this when you know stream_info is valid */
368 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
369 static struct xhci_ring *dma_to_stream_ring(
370                 struct xhci_stream_info *stream_info,
371                 u64 address)
372 {
373         return radix_tree_lookup(&stream_info->trb_address_map,
374                         address >> SEGMENT_SHIFT);
375 }
376 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
377
378 struct xhci_ring *xhci_stream_id_to_ring(
379                 struct xhci_virt_device *dev,
380                 unsigned int ep_index,
381                 unsigned int stream_id)
382 {
383         struct xhci_virt_ep *ep = &dev->eps[ep_index];
384
385         if (stream_id == 0)
386                 return ep->ring;
387         if (!ep->stream_info)
388                 return NULL;
389
390         if (stream_id > ep->stream_info->num_streams)
391                 return NULL;
392         return ep->stream_info->stream_rings[stream_id];
393 }
394
395 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
396 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
397                 unsigned int num_streams,
398                 struct xhci_stream_info *stream_info)
399 {
400         u32 cur_stream;
401         struct xhci_ring *cur_ring;
402         u64 addr;
403
404         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
405                 struct xhci_ring *mapped_ring;
406                 int trb_size = sizeof(union xhci_trb);
407
408                 cur_ring = stream_info->stream_rings[cur_stream];
409                 for (addr = cur_ring->first_seg->dma;
410                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
411                                 addr += trb_size) {
412                         mapped_ring = dma_to_stream_ring(stream_info, addr);
413                         if (cur_ring != mapped_ring) {
414                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
415                                                 "didn't map to stream ID %u; "
416                                                 "mapped to ring %p\n",
417                                                 (unsigned long long) addr,
418                                                 cur_stream,
419                                                 mapped_ring);
420                                 return -EINVAL;
421                         }
422                 }
423                 /* One TRB after the end of the ring segment shouldn't return a
424                  * pointer to the current ring (although it may be a part of a
425                  * different ring).
426                  */
427                 mapped_ring = dma_to_stream_ring(stream_info, addr);
428                 if (mapped_ring != cur_ring) {
429                         /* One TRB before should also fail */
430                         addr = cur_ring->first_seg->dma - trb_size;
431                         mapped_ring = dma_to_stream_ring(stream_info, addr);
432                 }
433                 if (mapped_ring == cur_ring) {
434                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
435                                         "mapped to valid stream ID %u; "
436                                         "mapped ring = %p\n",
437                                         (unsigned long long) addr,
438                                         cur_stream,
439                                         mapped_ring);
440                         return -EINVAL;
441                 }
442         }
443         return 0;
444 }
445 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
446
447 /*
448  * Change an endpoint's internal structure so it supports stream IDs.  The
449  * number of requested streams includes stream 0, which cannot be used by device
450  * drivers.
451  *
452  * The number of stream contexts in the stream context array may be bigger than
453  * the number of streams the driver wants to use.  This is because the number of
454  * stream context array entries must be a power of two.
455  *
456  * We need a radix tree for mapping physical addresses of TRBs to which stream
457  * ID they belong to.  We need to do this because the host controller won't tell
458  * us which stream ring the TRB came from.  We could store the stream ID in an
459  * event data TRB, but that doesn't help us for the cancellation case, since the
460  * endpoint may stop before it reaches that event data TRB.
461  *
462  * The radix tree maps the upper portion of the TRB DMA address to a ring
463  * segment that has the same upper portion of DMA addresses.  For example, say I
464  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
465  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
466  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
467  * pass the radix tree a key to get the right stream ID:
468  *
469  *      0x10c90fff >> 10 = 0x43243
470  *      0x10c912c0 >> 10 = 0x43244
471  *      0x10c91400 >> 10 = 0x43245
472  *
473  * Obviously, only those TRBs with DMA addresses that are within the segment
474  * will make the radix tree return the stream ID for that ring.
475  *
476  * Caveats for the radix tree:
477  *
478  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
479  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
480  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
481  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
482  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
483  * extended systems (where the DMA address can be bigger than 32-bits),
484  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
485  */
486 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
487                 unsigned int num_stream_ctxs,
488                 unsigned int num_streams, gfp_t mem_flags)
489 {
490         struct xhci_stream_info *stream_info;
491         u32 cur_stream;
492         struct xhci_ring *cur_ring;
493         unsigned long key;
494         u64 addr;
495         int ret;
496
497         xhci_dbg(xhci, "Allocating %u streams and %u "
498                         "stream context array entries.\n",
499                         num_streams, num_stream_ctxs);
500         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
501                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
502                 return NULL;
503         }
504         xhci->cmd_ring_reserved_trbs++;
505
506         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
507         if (!stream_info)
508                 goto cleanup_trbs;
509
510         stream_info->num_streams = num_streams;
511         stream_info->num_stream_ctxs = num_stream_ctxs;
512
513         /* Initialize the array of virtual pointers to stream rings. */
514         stream_info->stream_rings = kzalloc(
515                         sizeof(struct xhci_ring *)*num_streams,
516                         mem_flags);
517         if (!stream_info->stream_rings)
518                 goto cleanup_info;
519
520         /* Initialize the array of DMA addresses for stream rings for the HW. */
521         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
522                         num_stream_ctxs, &stream_info->ctx_array_dma,
523                         mem_flags);
524         if (!stream_info->stream_ctx_array)
525                 goto cleanup_ctx;
526         memset(stream_info->stream_ctx_array, 0,
527                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
528
529         /* Allocate everything needed to free the stream rings later */
530         stream_info->free_streams_command =
531                 xhci_alloc_command(xhci, true, true, mem_flags);
532         if (!stream_info->free_streams_command)
533                 goto cleanup_ctx;
534
535         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
536
537         /* Allocate rings for all the streams that the driver will use,
538          * and add their segment DMA addresses to the radix tree.
539          * Stream 0 is reserved.
540          */
541         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
542                 stream_info->stream_rings[cur_stream] =
543                         xhci_ring_alloc(xhci, 1, true, mem_flags);
544                 cur_ring = stream_info->stream_rings[cur_stream];
545                 if (!cur_ring)
546                         goto cleanup_rings;
547                 cur_ring->stream_id = cur_stream;
548                 /* Set deq ptr, cycle bit, and stream context type */
549                 addr = cur_ring->first_seg->dma |
550                         SCT_FOR_CTX(SCT_PRI_TR) |
551                         cur_ring->cycle_state;
552                 stream_info->stream_ctx_array[cur_stream].stream_ring =
553                         cpu_to_le64(addr);
554                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
555                                 cur_stream, (unsigned long long) addr);
556
557                 key = (unsigned long)
558                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
559                 ret = radix_tree_insert(&stream_info->trb_address_map,
560                                 key, cur_ring);
561                 if (ret) {
562                         xhci_ring_free(xhci, cur_ring);
563                         stream_info->stream_rings[cur_stream] = NULL;
564                         goto cleanup_rings;
565                 }
566         }
567         /* Leave the other unused stream ring pointers in the stream context
568          * array initialized to zero.  This will cause the xHC to give us an
569          * error if the device asks for a stream ID we don't have setup (if it
570          * was any other way, the host controller would assume the ring is
571          * "empty" and wait forever for data to be queued to that stream ID).
572          */
573 #if XHCI_DEBUG
574         /* Do a little test on the radix tree to make sure it returns the
575          * correct values.
576          */
577         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
578                 goto cleanup_rings;
579 #endif
580
581         return stream_info;
582
583 cleanup_rings:
584         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
585                 cur_ring = stream_info->stream_rings[cur_stream];
586                 if (cur_ring) {
587                         addr = cur_ring->first_seg->dma;
588                         radix_tree_delete(&stream_info->trb_address_map,
589                                         addr >> SEGMENT_SHIFT);
590                         xhci_ring_free(xhci, cur_ring);
591                         stream_info->stream_rings[cur_stream] = NULL;
592                 }
593         }
594         xhci_free_command(xhci, stream_info->free_streams_command);
595 cleanup_ctx:
596         kfree(stream_info->stream_rings);
597 cleanup_info:
598         kfree(stream_info);
599 cleanup_trbs:
600         xhci->cmd_ring_reserved_trbs--;
601         return NULL;
602 }
603 /*
604  * Sets the MaxPStreams field and the Linear Stream Array field.
605  * Sets the dequeue pointer to the stream context array.
606  */
607 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
608                 struct xhci_ep_ctx *ep_ctx,
609                 struct xhci_stream_info *stream_info)
610 {
611         u32 max_primary_streams;
612         /* MaxPStreams is the number of stream context array entries, not the
613          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
614          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
615          */
616         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
617         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
618                         1 << (max_primary_streams + 1));
619         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
620         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
621                                        | EP_HAS_LSA);
622         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
623 }
624
625 /*
626  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
627  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
628  * not at the beginning of the ring).
629  */
630 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
631                 struct xhci_ep_ctx *ep_ctx,
632                 struct xhci_virt_ep *ep)
633 {
634         dma_addr_t addr;
635         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
636         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
637         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
638 }
639
640 /* Frees all stream contexts associated with the endpoint,
641  *
642  * Caller should fix the endpoint context streams fields.
643  */
644 void xhci_free_stream_info(struct xhci_hcd *xhci,
645                 struct xhci_stream_info *stream_info)
646 {
647         int cur_stream;
648         struct xhci_ring *cur_ring;
649         dma_addr_t addr;
650
651         if (!stream_info)
652                 return;
653
654         for (cur_stream = 1; cur_stream < stream_info->num_streams;
655                         cur_stream++) {
656                 cur_ring = stream_info->stream_rings[cur_stream];
657                 if (cur_ring) {
658                         addr = cur_ring->first_seg->dma;
659                         radix_tree_delete(&stream_info->trb_address_map,
660                                         addr >> SEGMENT_SHIFT);
661                         xhci_ring_free(xhci, cur_ring);
662                         stream_info->stream_rings[cur_stream] = NULL;
663                 }
664         }
665         xhci_free_command(xhci, stream_info->free_streams_command);
666         xhci->cmd_ring_reserved_trbs--;
667         if (stream_info->stream_ctx_array)
668                 xhci_free_stream_ctx(xhci,
669                                 stream_info->num_stream_ctxs,
670                                 stream_info->stream_ctx_array,
671                                 stream_info->ctx_array_dma);
672
673         if (stream_info)
674                 kfree(stream_info->stream_rings);
675         kfree(stream_info);
676 }
677
678
679 /***************** Device context manipulation *************************/
680
681 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
682                 struct xhci_virt_ep *ep)
683 {
684         init_timer(&ep->stop_cmd_timer);
685         ep->stop_cmd_timer.data = (unsigned long) ep;
686         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
687         ep->xhci = xhci;
688 }
689
690 static void xhci_free_tt_info(struct xhci_hcd *xhci,
691                 struct xhci_virt_device *virt_dev,
692                 int slot_id)
693 {
694         struct list_head *tt;
695         struct list_head *tt_list_head;
696         struct list_head *tt_next;
697         struct xhci_tt_bw_info *tt_info;
698
699         /* If the device never made it past the Set Address stage,
700          * it may not have the real_port set correctly.
701          */
702         if (virt_dev->real_port == 0 ||
703                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
704                 xhci_dbg(xhci, "Bad real port.\n");
705                 return;
706         }
707
708         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
709         if (list_empty(tt_list_head))
710                 return;
711
712         list_for_each(tt, tt_list_head) {
713                 tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
714                 if (tt_info->slot_id == slot_id)
715                         break;
716         }
717         /* Cautionary measure in case the hub was disconnected before we
718          * stored the TT information.
719          */
720         if (tt_info->slot_id != slot_id)
721                 return;
722
723         tt_next = tt->next;
724         tt_info = list_entry(tt, struct xhci_tt_bw_info,
725                         tt_list);
726         /* Multi-TT hubs will have more than one entry */
727         do {
728                 list_del(tt);
729                 kfree(tt_info);
730                 tt = tt_next;
731                 if (list_empty(tt_list_head))
732                         break;
733                 tt_next = tt->next;
734                 tt_info = list_entry(tt, struct xhci_tt_bw_info,
735                                 tt_list);
736         } while (tt_info->slot_id == slot_id);
737 }
738
739 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
740                 struct xhci_virt_device *virt_dev,
741                 struct usb_device *hdev,
742                 struct usb_tt *tt, gfp_t mem_flags)
743 {
744         struct xhci_tt_bw_info          *tt_info;
745         unsigned int                    num_ports;
746         int                             i, j;
747
748         if (!tt->multi)
749                 num_ports = 1;
750         else
751                 num_ports = hdev->maxchild;
752
753         for (i = 0; i < num_ports; i++, tt_info++) {
754                 struct xhci_interval_bw_table *bw_table;
755
756                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
757                 if (!tt_info)
758                         goto free_tts;
759                 INIT_LIST_HEAD(&tt_info->tt_list);
760                 list_add(&tt_info->tt_list,
761                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
762                 tt_info->slot_id = virt_dev->udev->slot_id;
763                 if (tt->multi)
764                         tt_info->ttport = i+1;
765                 bw_table = &tt_info->bw_table;
766                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
767                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
768         }
769         return 0;
770
771 free_tts:
772         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
773         return -ENOMEM;
774 }
775
776
777 /* All the xhci_tds in the ring's TD list should be freed at this point.
778  * Should be called with xhci->lock held if there is any chance the TT lists
779  * will be manipulated by the configure endpoint, allocate device, or update
780  * hub functions while this function is removing the TT entries from the list.
781  */
782 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
783 {
784         struct xhci_virt_device *dev;
785         int i;
786         int old_active_eps = 0;
787
788         /* Slot ID 0 is reserved */
789         if (slot_id == 0 || !xhci->devs[slot_id])
790                 return;
791
792         dev = xhci->devs[slot_id];
793         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
794         if (!dev)
795                 return;
796
797         if (dev->tt_info)
798                 old_active_eps = dev->tt_info->active_eps;
799
800         for (i = 0; i < 31; ++i) {
801                 if (dev->eps[i].ring)
802                         xhci_ring_free(xhci, dev->eps[i].ring);
803                 if (dev->eps[i].stream_info)
804                         xhci_free_stream_info(xhci,
805                                         dev->eps[i].stream_info);
806                 /* Endpoints on the TT/root port lists should have been removed
807                  * when usb_disable_device() was called for the device.
808                  * We can't drop them anyway, because the udev might have gone
809                  * away by this point, and we can't tell what speed it was.
810                  */
811                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
812                         xhci_warn(xhci, "Slot %u endpoint %u "
813                                         "not removed from BW list!\n",
814                                         slot_id, i);
815         }
816         /* If this is a hub, free the TT(s) from the TT list */
817         xhci_free_tt_info(xhci, dev, slot_id);
818         /* If necessary, update the number of active TTs on this root port */
819         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
820
821         if (dev->ring_cache) {
822                 for (i = 0; i < dev->num_rings_cached; i++)
823                         xhci_ring_free(xhci, dev->ring_cache[i]);
824                 kfree(dev->ring_cache);
825         }
826
827         if (dev->in_ctx)
828                 xhci_free_container_ctx(xhci, dev->in_ctx);
829         if (dev->out_ctx)
830                 xhci_free_container_ctx(xhci, dev->out_ctx);
831
832         kfree(xhci->devs[slot_id]);
833         xhci->devs[slot_id] = NULL;
834 }
835
836 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
837                 struct usb_device *udev, gfp_t flags)
838 {
839         struct xhci_virt_device *dev;
840         int i;
841
842         /* Slot ID 0 is reserved */
843         if (slot_id == 0 || xhci->devs[slot_id]) {
844                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
845                 return 0;
846         }
847
848         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
849         if (!xhci->devs[slot_id])
850                 return 0;
851         dev = xhci->devs[slot_id];
852
853         /* Allocate the (output) device context that will be used in the HC. */
854         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
855         if (!dev->out_ctx)
856                 goto fail;
857
858         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
859                         (unsigned long long)dev->out_ctx->dma);
860
861         /* Allocate the (input) device context for address device command */
862         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
863         if (!dev->in_ctx)
864                 goto fail;
865
866         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
867                         (unsigned long long)dev->in_ctx->dma);
868
869         /* Initialize the cancellation list and watchdog timers for each ep */
870         for (i = 0; i < 31; i++) {
871                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
872                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
873                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
874         }
875
876         /* Allocate endpoint 0 ring */
877         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
878         if (!dev->eps[0].ring)
879                 goto fail;
880
881         /* Allocate pointers to the ring cache */
882         dev->ring_cache = kzalloc(
883                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
884                         flags);
885         if (!dev->ring_cache)
886                 goto fail;
887         dev->num_rings_cached = 0;
888
889         init_completion(&dev->cmd_completion);
890         INIT_LIST_HEAD(&dev->cmd_list);
891         dev->udev = udev;
892
893         /* Point to output device context in dcbaa. */
894         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
895         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
896                  slot_id,
897                  &xhci->dcbaa->dev_context_ptrs[slot_id],
898                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
899
900         return 1;
901 fail:
902         xhci_free_virt_device(xhci, slot_id);
903         return 0;
904 }
905
906 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
907                 struct usb_device *udev)
908 {
909         struct xhci_virt_device *virt_dev;
910         struct xhci_ep_ctx      *ep0_ctx;
911         struct xhci_ring        *ep_ring;
912
913         virt_dev = xhci->devs[udev->slot_id];
914         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
915         ep_ring = virt_dev->eps[0].ring;
916         /*
917          * FIXME we don't keep track of the dequeue pointer very well after a
918          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
919          * host to our enqueue pointer.  This should only be called after a
920          * configured device has reset, so all control transfers should have
921          * been completed or cancelled before the reset.
922          */
923         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
924                                                         ep_ring->enqueue)
925                                    | ep_ring->cycle_state);
926 }
927
928 /*
929  * The xHCI roothub may have ports of differing speeds in any order in the port
930  * status registers.  xhci->port_array provides an array of the port speed for
931  * each offset into the port status registers.
932  *
933  * The xHCI hardware wants to know the roothub port number that the USB device
934  * is attached to (or the roothub port its ancestor hub is attached to).  All we
935  * know is the index of that port under either the USB 2.0 or the USB 3.0
936  * roothub, but that doesn't give us the real index into the HW port status
937  * registers.  Scan through the xHCI roothub port array, looking for the Nth
938  * entry of the correct port speed.  Return the port number of that entry.
939  */
940 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
941                 struct usb_device *udev)
942 {
943         struct usb_device *top_dev;
944         unsigned int num_similar_speed_ports;
945         unsigned int faked_port_num;
946         int i;
947
948         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
949                         top_dev = top_dev->parent)
950                 /* Found device below root hub */;
951         faked_port_num = top_dev->portnum;
952         for (i = 0, num_similar_speed_ports = 0;
953                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
954                 u8 port_speed = xhci->port_array[i];
955
956                 /*
957                  * Skip ports that don't have known speeds, or have duplicate
958                  * Extended Capabilities port speed entries.
959                  */
960                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
961                         continue;
962
963                 /*
964                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
965                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
966                  * matches the device speed, it's a similar speed port.
967                  */
968                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
969                         num_similar_speed_ports++;
970                 if (num_similar_speed_ports == faked_port_num)
971                         /* Roothub ports are numbered from 1 to N */
972                         return i+1;
973         }
974         return 0;
975 }
976
977 /* Setup an xHCI virtual device for a Set Address command */
978 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
979 {
980         struct xhci_virt_device *dev;
981         struct xhci_ep_ctx      *ep0_ctx;
982         struct xhci_slot_ctx    *slot_ctx;
983         struct xhci_input_control_ctx *ctrl_ctx;
984         u32                     port_num;
985         struct usb_device *top_dev;
986
987         dev = xhci->devs[udev->slot_id];
988         /* Slot ID 0 is reserved */
989         if (udev->slot_id == 0 || !dev) {
990                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
991                                 udev->slot_id);
992                 return -EINVAL;
993         }
994         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
995         ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
996         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
997
998         /* 2) New slot context and endpoint 0 context are valid*/
999         ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
1000
1001         /* 3) Only the control endpoint is valid - one endpoint context */
1002         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1003         switch (udev->speed) {
1004         case USB_SPEED_SUPER:
1005                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1006                 break;
1007         case USB_SPEED_HIGH:
1008                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1009                 break;
1010         case USB_SPEED_FULL:
1011                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1012                 break;
1013         case USB_SPEED_LOW:
1014                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1015                 break;
1016         case USB_SPEED_WIRELESS:
1017                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1018                 return -EINVAL;
1019                 break;
1020         default:
1021                 /* Speed was set earlier, this shouldn't happen. */
1022                 BUG();
1023         }
1024         /* Find the root hub port this device is under */
1025         port_num = xhci_find_real_port_number(xhci, udev);
1026         if (!port_num)
1027                 return -EINVAL;
1028         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1029         /* Set the port number in the virtual_device to the faked port number */
1030         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1031                         top_dev = top_dev->parent)
1032                 /* Found device below root hub */;
1033         dev->fake_port = top_dev->portnum;
1034         dev->real_port = port_num;
1035         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1036         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1037
1038         /* Find the right bandwidth table that this device will be a part of.
1039          * If this is a full speed device attached directly to a root port (or a
1040          * decendent of one), it counts as a primary bandwidth domain, not a
1041          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1042          * will never be created for the HS root hub.
1043          */
1044         if (!udev->tt || !udev->tt->hub->parent) {
1045                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1046         } else {
1047                 struct xhci_root_port_bw_info *rh_bw;
1048                 struct xhci_tt_bw_info *tt_bw;
1049
1050                 rh_bw = &xhci->rh_bw[port_num - 1];
1051                 /* Find the right TT. */
1052                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1053                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1054                                 continue;
1055
1056                         if (!dev->udev->tt->multi ||
1057                                         (udev->tt->multi &&
1058                                          tt_bw->ttport == dev->udev->ttport)) {
1059                                 dev->bw_table = &tt_bw->bw_table;
1060                                 dev->tt_info = tt_bw;
1061                                 break;
1062                         }
1063                 }
1064                 if (!dev->tt_info)
1065                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1066         }
1067
1068         /* Is this a LS/FS device under an external HS hub? */
1069         if (udev->tt && udev->tt->hub->parent) {
1070                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1071                                                 (udev->ttport << 8));
1072                 if (udev->tt->multi)
1073                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1074         }
1075         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1076         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1077
1078         /* Step 4 - ring already allocated */
1079         /* Step 5 */
1080         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1081         /*
1082          * XXX: Not sure about wireless USB devices.
1083          */
1084         switch (udev->speed) {
1085         case USB_SPEED_SUPER:
1086                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1087                 break;
1088         case USB_SPEED_HIGH:
1089         /* USB core guesses at a 64-byte max packet first for FS devices */
1090         case USB_SPEED_FULL:
1091                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1092                 break;
1093         case USB_SPEED_LOW:
1094                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1095                 break;
1096         case USB_SPEED_WIRELESS:
1097                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1098                 return -EINVAL;
1099                 break;
1100         default:
1101                 /* New speed? */
1102                 BUG();
1103         }
1104         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1105         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1106
1107         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1108                                    dev->eps[0].ring->cycle_state);
1109
1110         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1111
1112         return 0;
1113 }
1114
1115 /*
1116  * Convert interval expressed as 2^(bInterval - 1) == interval into
1117  * straight exponent value 2^n == interval.
1118  *
1119  */
1120 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1121                 struct usb_host_endpoint *ep)
1122 {
1123         unsigned int interval;
1124
1125         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1126         if (interval != ep->desc.bInterval - 1)
1127                 dev_warn(&udev->dev,
1128                          "ep %#x - rounding interval to %d %sframes\n",
1129                          ep->desc.bEndpointAddress,
1130                          1 << interval,
1131                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1132
1133         if (udev->speed == USB_SPEED_FULL) {
1134                 /*
1135                  * Full speed isoc endpoints specify interval in frames,
1136                  * not microframes. We are using microframes everywhere,
1137                  * so adjust accordingly.
1138                  */
1139                 interval += 3;  /* 1 frame = 2^3 uframes */
1140         }
1141
1142         return interval;
1143 }
1144
1145 /*
1146  * Convert bInterval expressed in frames (in 1-255 range) to exponent of
1147  * microframes, rounded down to nearest power of 2.
1148  */
1149 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1150                 struct usb_host_endpoint *ep)
1151 {
1152         unsigned int interval;
1153
1154         interval = fls(8 * ep->desc.bInterval) - 1;
1155         interval = clamp_val(interval, 3, 10);
1156         if ((1 << interval) != 8 * ep->desc.bInterval)
1157                 dev_warn(&udev->dev,
1158                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1159                          ep->desc.bEndpointAddress,
1160                          1 << interval,
1161                          8 * ep->desc.bInterval);
1162
1163         return interval;
1164 }
1165
1166 /* Return the polling or NAK interval.
1167  *
1168  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1169  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1170  *
1171  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1172  * is set to 0.
1173  */
1174 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1175                 struct usb_host_endpoint *ep)
1176 {
1177         unsigned int interval = 0;
1178
1179         switch (udev->speed) {
1180         case USB_SPEED_HIGH:
1181                 /* Max NAK rate */
1182                 if (usb_endpoint_xfer_control(&ep->desc) ||
1183                     usb_endpoint_xfer_bulk(&ep->desc)) {
1184                         interval = ep->desc.bInterval;
1185                         break;
1186                 }
1187                 /* Fall through - SS and HS isoc/int have same decoding */
1188
1189         case USB_SPEED_SUPER:
1190                 if (usb_endpoint_xfer_int(&ep->desc) ||
1191                     usb_endpoint_xfer_isoc(&ep->desc)) {
1192                         interval = xhci_parse_exponent_interval(udev, ep);
1193                 }
1194                 break;
1195
1196         case USB_SPEED_FULL:
1197                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1198                         interval = xhci_parse_exponent_interval(udev, ep);
1199                         break;
1200                 }
1201                 /*
1202                  * Fall through for interrupt endpoint interval decoding
1203                  * since it uses the same rules as low speed interrupt
1204                  * endpoints.
1205                  */
1206
1207         case USB_SPEED_LOW:
1208                 if (usb_endpoint_xfer_int(&ep->desc) ||
1209                     usb_endpoint_xfer_isoc(&ep->desc)) {
1210
1211                         interval = xhci_parse_frame_interval(udev, ep);
1212                 }
1213                 break;
1214
1215         default:
1216                 BUG();
1217         }
1218         return EP_INTERVAL(interval);
1219 }
1220
1221 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1222  * High speed endpoint descriptors can define "the number of additional
1223  * transaction opportunities per microframe", but that goes in the Max Burst
1224  * endpoint context field.
1225  */
1226 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1227                 struct usb_host_endpoint *ep)
1228 {
1229         if (udev->speed != USB_SPEED_SUPER ||
1230                         !usb_endpoint_xfer_isoc(&ep->desc))
1231                 return 0;
1232         return ep->ss_ep_comp.bmAttributes;
1233 }
1234
1235 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1236                 struct usb_host_endpoint *ep)
1237 {
1238         int in;
1239         u32 type;
1240
1241         in = usb_endpoint_dir_in(&ep->desc);
1242         if (usb_endpoint_xfer_control(&ep->desc)) {
1243                 type = EP_TYPE(CTRL_EP);
1244         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1245                 if (in)
1246                         type = EP_TYPE(BULK_IN_EP);
1247                 else
1248                         type = EP_TYPE(BULK_OUT_EP);
1249         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1250                 if (in)
1251                         type = EP_TYPE(ISOC_IN_EP);
1252                 else
1253                         type = EP_TYPE(ISOC_OUT_EP);
1254         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1255                 if (in)
1256                         type = EP_TYPE(INT_IN_EP);
1257                 else
1258                         type = EP_TYPE(INT_OUT_EP);
1259         } else {
1260                 BUG();
1261         }
1262         return type;
1263 }
1264
1265 /* Return the maximum endpoint service interval time (ESIT) payload.
1266  * Basically, this is the maxpacket size, multiplied by the burst size
1267  * and mult size.
1268  */
1269 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1270                 struct usb_device *udev,
1271                 struct usb_host_endpoint *ep)
1272 {
1273         int max_burst;
1274         int max_packet;
1275
1276         /* Only applies for interrupt or isochronous endpoints */
1277         if (usb_endpoint_xfer_control(&ep->desc) ||
1278                         usb_endpoint_xfer_bulk(&ep->desc))
1279                 return 0;
1280
1281         if (udev->speed == USB_SPEED_SUPER)
1282                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1283
1284         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1285         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1286         /* A 0 in max burst means 1 transfer per ESIT */
1287         return max_packet * (max_burst + 1);
1288 }
1289
1290 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1291  * Drivers will have to call usb_alloc_streams() to do that.
1292  */
1293 int xhci_endpoint_init(struct xhci_hcd *xhci,
1294                 struct xhci_virt_device *virt_dev,
1295                 struct usb_device *udev,
1296                 struct usb_host_endpoint *ep,
1297                 gfp_t mem_flags)
1298 {
1299         unsigned int ep_index;
1300         struct xhci_ep_ctx *ep_ctx;
1301         struct xhci_ring *ep_ring;
1302         unsigned int max_packet;
1303         unsigned int max_burst;
1304         u32 max_esit_payload;
1305
1306         ep_index = xhci_get_endpoint_index(&ep->desc);
1307         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1308
1309         /* Set up the endpoint ring */
1310         /*
1311          * Isochronous endpoint ring needs bigger size because one isoc URB
1312          * carries multiple packets and it will insert multiple tds to the
1313          * ring.
1314          * This should be replaced with dynamic ring resizing in the future.
1315          */
1316         if (usb_endpoint_xfer_isoc(&ep->desc))
1317                 virt_dev->eps[ep_index].new_ring =
1318                         xhci_ring_alloc(xhci, 8, true, mem_flags);
1319         else
1320                 virt_dev->eps[ep_index].new_ring =
1321                         xhci_ring_alloc(xhci, 1, true, mem_flags);
1322         if (!virt_dev->eps[ep_index].new_ring) {
1323                 /* Attempt to use the ring cache */
1324                 if (virt_dev->num_rings_cached == 0)
1325                         return -ENOMEM;
1326                 virt_dev->eps[ep_index].new_ring =
1327                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1328                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1329                 virt_dev->num_rings_cached--;
1330                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
1331         }
1332         virt_dev->eps[ep_index].skip = false;
1333         ep_ring = virt_dev->eps[ep_index].new_ring;
1334         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1335
1336         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1337                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1338
1339         /* FIXME dig Mult and streams info out of ep companion desc */
1340
1341         /* Allow 3 retries for everything but isoc;
1342          * CErr shall be set to 0 for Isoch endpoints.
1343          */
1344         if (!usb_endpoint_xfer_isoc(&ep->desc))
1345                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1346         else
1347                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1348
1349         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1350
1351         /* Set the max packet size and max burst */
1352         switch (udev->speed) {
1353         case USB_SPEED_SUPER:
1354                 max_packet = usb_endpoint_maxp(&ep->desc);
1355                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1356                 /* dig out max burst from ep companion desc */
1357                 max_packet = ep->ss_ep_comp.bMaxBurst;
1358                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1359                 break;
1360         case USB_SPEED_HIGH:
1361                 /* bits 11:12 specify the number of additional transaction
1362                  * opportunities per microframe (USB 2.0, section 9.6.6)
1363                  */
1364                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1365                                 usb_endpoint_xfer_int(&ep->desc)) {
1366                         max_burst = (usb_endpoint_maxp(&ep->desc)
1367                                      & 0x1800) >> 11;
1368                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1369                 }
1370                 /* Fall through */
1371         case USB_SPEED_FULL:
1372         case USB_SPEED_LOW:
1373                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1374                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1375                 break;
1376         default:
1377                 BUG();
1378         }
1379         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1380         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1381
1382         /*
1383          * XXX no idea how to calculate the average TRB buffer length for bulk
1384          * endpoints, as the driver gives us no clue how big each scatter gather
1385          * list entry (or buffer) is going to be.
1386          *
1387          * For isochronous and interrupt endpoints, we set it to the max
1388          * available, until we have new API in the USB core to allow drivers to
1389          * declare how much bandwidth they actually need.
1390          *
1391          * Normally, it would be calculated by taking the total of the buffer
1392          * lengths in the TD and then dividing by the number of TRBs in a TD,
1393          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1394          * use Event Data TRBs, and we don't chain in a link TRB on short
1395          * transfers, we're basically dividing by 1.
1396          *
1397          * xHCI 1.0 specification indicates that the Average TRB Length should
1398          * be set to 8 for control endpoints.
1399          */
1400         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1401                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1402         else
1403                 ep_ctx->tx_info |=
1404                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1405
1406         /* FIXME Debug endpoint context */
1407         return 0;
1408 }
1409
1410 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1411                 struct xhci_virt_device *virt_dev,
1412                 struct usb_host_endpoint *ep)
1413 {
1414         unsigned int ep_index;
1415         struct xhci_ep_ctx *ep_ctx;
1416
1417         ep_index = xhci_get_endpoint_index(&ep->desc);
1418         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1419
1420         ep_ctx->ep_info = 0;
1421         ep_ctx->ep_info2 = 0;
1422         ep_ctx->deq = 0;
1423         ep_ctx->tx_info = 0;
1424         /* Don't free the endpoint ring until the set interface or configuration
1425          * request succeeds.
1426          */
1427 }
1428
1429 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1430 {
1431         bw_info->ep_interval = 0;
1432         bw_info->mult = 0;
1433         bw_info->num_packets = 0;
1434         bw_info->max_packet_size = 0;
1435         bw_info->type = 0;
1436         bw_info->max_esit_payload = 0;
1437 }
1438
1439 void xhci_update_bw_info(struct xhci_hcd *xhci,
1440                 struct xhci_container_ctx *in_ctx,
1441                 struct xhci_input_control_ctx *ctrl_ctx,
1442                 struct xhci_virt_device *virt_dev)
1443 {
1444         struct xhci_bw_info *bw_info;
1445         struct xhci_ep_ctx *ep_ctx;
1446         unsigned int ep_type;
1447         int i;
1448
1449         for (i = 1; i < 31; ++i) {
1450                 bw_info = &virt_dev->eps[i].bw_info;
1451
1452                 /* We can't tell what endpoint type is being dropped, but
1453                  * unconditionally clearing the bandwidth info for non-periodic
1454                  * endpoints should be harmless because the info will never be
1455                  * set in the first place.
1456                  */
1457                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1458                         /* Dropped endpoint */
1459                         xhci_clear_endpoint_bw_info(bw_info);
1460                         continue;
1461                 }
1462
1463                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1464                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1465                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1466
1467                         /* Ignore non-periodic endpoints */
1468                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1469                                         ep_type != ISOC_IN_EP &&
1470                                         ep_type != INT_IN_EP)
1471                                 continue;
1472
1473                         /* Added or changed endpoint */
1474                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1475                                         le32_to_cpu(ep_ctx->ep_info));
1476                         /* Number of packets and mult are zero-based in the
1477                          * input context, but we want one-based for the
1478                          * interval table.
1479                          */
1480                         bw_info->mult = CTX_TO_EP_MULT(
1481                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1482                         bw_info->num_packets = CTX_TO_MAX_BURST(
1483                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1484                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1485                                         le32_to_cpu(ep_ctx->ep_info2));
1486                         bw_info->type = ep_type;
1487                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1488                                         le32_to_cpu(ep_ctx->tx_info));
1489                 }
1490         }
1491 }
1492
1493 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1494  * Useful when you want to change one particular aspect of the endpoint and then
1495  * issue a configure endpoint command.
1496  */
1497 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1498                 struct xhci_container_ctx *in_ctx,
1499                 struct xhci_container_ctx *out_ctx,
1500                 unsigned int ep_index)
1501 {
1502         struct xhci_ep_ctx *out_ep_ctx;
1503         struct xhci_ep_ctx *in_ep_ctx;
1504
1505         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1506         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1507
1508         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1509         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1510         in_ep_ctx->deq = out_ep_ctx->deq;
1511         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1512 }
1513
1514 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1515  * Useful when you want to change one particular aspect of the endpoint and then
1516  * issue a configure endpoint command.  Only the context entries field matters,
1517  * but we'll copy the whole thing anyway.
1518  */
1519 void xhci_slot_copy(struct xhci_hcd *xhci,
1520                 struct xhci_container_ctx *in_ctx,
1521                 struct xhci_container_ctx *out_ctx)
1522 {
1523         struct xhci_slot_ctx *in_slot_ctx;
1524         struct xhci_slot_ctx *out_slot_ctx;
1525
1526         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1527         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1528
1529         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1530         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1531         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1532         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1533 }
1534
1535 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1536 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1537 {
1538         int i;
1539         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1540         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1541
1542         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1543
1544         if (!num_sp)
1545                 return 0;
1546
1547         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1548         if (!xhci->scratchpad)
1549                 goto fail_sp;
1550
1551         xhci->scratchpad->sp_array =
1552                 pci_alloc_consistent(to_pci_dev(dev),
1553                                      num_sp * sizeof(u64),
1554                                      &xhci->scratchpad->sp_dma);
1555         if (!xhci->scratchpad->sp_array)
1556                 goto fail_sp2;
1557
1558         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1559         if (!xhci->scratchpad->sp_buffers)
1560                 goto fail_sp3;
1561
1562         xhci->scratchpad->sp_dma_buffers =
1563                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1564
1565         if (!xhci->scratchpad->sp_dma_buffers)
1566                 goto fail_sp4;
1567
1568         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1569         for (i = 0; i < num_sp; i++) {
1570                 dma_addr_t dma;
1571                 void *buf = pci_alloc_consistent(to_pci_dev(dev),
1572                                                  xhci->page_size, &dma);
1573                 if (!buf)
1574                         goto fail_sp5;
1575
1576                 xhci->scratchpad->sp_array[i] = dma;
1577                 xhci->scratchpad->sp_buffers[i] = buf;
1578                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1579         }
1580
1581         return 0;
1582
1583  fail_sp5:
1584         for (i = i - 1; i >= 0; i--) {
1585                 pci_free_consistent(to_pci_dev(dev), xhci->page_size,
1586                                     xhci->scratchpad->sp_buffers[i],
1587                                     xhci->scratchpad->sp_dma_buffers[i]);
1588         }
1589         kfree(xhci->scratchpad->sp_dma_buffers);
1590
1591  fail_sp4:
1592         kfree(xhci->scratchpad->sp_buffers);
1593
1594  fail_sp3:
1595         pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
1596                             xhci->scratchpad->sp_array,
1597                             xhci->scratchpad->sp_dma);
1598
1599  fail_sp2:
1600         kfree(xhci->scratchpad);
1601         xhci->scratchpad = NULL;
1602
1603  fail_sp:
1604         return -ENOMEM;
1605 }
1606
1607 static void scratchpad_free(struct xhci_hcd *xhci)
1608 {
1609         int num_sp;
1610         int i;
1611         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1612
1613         if (!xhci->scratchpad)
1614                 return;
1615
1616         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1617
1618         for (i = 0; i < num_sp; i++) {
1619                 pci_free_consistent(pdev, xhci->page_size,
1620                                     xhci->scratchpad->sp_buffers[i],
1621                                     xhci->scratchpad->sp_dma_buffers[i]);
1622         }
1623         kfree(xhci->scratchpad->sp_dma_buffers);
1624         kfree(xhci->scratchpad->sp_buffers);
1625         pci_free_consistent(pdev, num_sp * sizeof(u64),
1626                             xhci->scratchpad->sp_array,
1627                             xhci->scratchpad->sp_dma);
1628         kfree(xhci->scratchpad);
1629         xhci->scratchpad = NULL;
1630 }
1631
1632 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1633                 bool allocate_in_ctx, bool allocate_completion,
1634                 gfp_t mem_flags)
1635 {
1636         struct xhci_command *command;
1637
1638         command = kzalloc(sizeof(*command), mem_flags);
1639         if (!command)
1640                 return NULL;
1641
1642         if (allocate_in_ctx) {
1643                 command->in_ctx =
1644                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1645                                         mem_flags);
1646                 if (!command->in_ctx) {
1647                         kfree(command);
1648                         return NULL;
1649                 }
1650         }
1651
1652         if (allocate_completion) {
1653                 command->completion =
1654                         kzalloc(sizeof(struct completion), mem_flags);
1655                 if (!command->completion) {
1656                         xhci_free_container_ctx(xhci, command->in_ctx);
1657                         kfree(command);
1658                         return NULL;
1659                 }
1660                 init_completion(command->completion);
1661         }
1662
1663         command->status = 0;
1664         INIT_LIST_HEAD(&command->cmd_list);
1665         return command;
1666 }
1667
1668 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1669 {
1670         if (urb_priv) {
1671                 kfree(urb_priv->td[0]);
1672                 kfree(urb_priv);
1673         }
1674 }
1675
1676 void xhci_free_command(struct xhci_hcd *xhci,
1677                 struct xhci_command *command)
1678 {
1679         xhci_free_container_ctx(xhci,
1680                         command->in_ctx);
1681         kfree(command->completion);
1682         kfree(command);
1683 }
1684
1685 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1686 {
1687         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1688         int size;
1689         int i;
1690
1691         /* Free the Event Ring Segment Table and the actual Event Ring */
1692         if (xhci->ir_set) {
1693                 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
1694                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
1695                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
1696         }
1697         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1698         if (xhci->erst.entries)
1699                 pci_free_consistent(pdev, size,
1700                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1701         xhci->erst.entries = NULL;
1702         xhci_dbg(xhci, "Freed ERST\n");
1703         if (xhci->event_ring)
1704                 xhci_ring_free(xhci, xhci->event_ring);
1705         xhci->event_ring = NULL;
1706         xhci_dbg(xhci, "Freed event ring\n");
1707
1708         xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
1709         if (xhci->cmd_ring)
1710                 xhci_ring_free(xhci, xhci->cmd_ring);
1711         xhci->cmd_ring = NULL;
1712         xhci_dbg(xhci, "Freed command ring\n");
1713
1714         for (i = 1; i < MAX_HC_SLOTS; ++i)
1715                 xhci_free_virt_device(xhci, i);
1716
1717         if (xhci->segment_pool)
1718                 dma_pool_destroy(xhci->segment_pool);
1719         xhci->segment_pool = NULL;
1720         xhci_dbg(xhci, "Freed segment pool\n");
1721
1722         if (xhci->device_pool)
1723                 dma_pool_destroy(xhci->device_pool);
1724         xhci->device_pool = NULL;
1725         xhci_dbg(xhci, "Freed device context pool\n");
1726
1727         if (xhci->small_streams_pool)
1728                 dma_pool_destroy(xhci->small_streams_pool);
1729         xhci->small_streams_pool = NULL;
1730         xhci_dbg(xhci, "Freed small stream array pool\n");
1731
1732         if (xhci->medium_streams_pool)
1733                 dma_pool_destroy(xhci->medium_streams_pool);
1734         xhci->medium_streams_pool = NULL;
1735         xhci_dbg(xhci, "Freed medium stream array pool\n");
1736
1737         xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
1738         if (xhci->dcbaa)
1739                 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
1740                                 xhci->dcbaa, xhci->dcbaa->dma);
1741         xhci->dcbaa = NULL;
1742
1743         scratchpad_free(xhci);
1744
1745         xhci->num_usb2_ports = 0;
1746         xhci->num_usb3_ports = 0;
1747         kfree(xhci->usb2_ports);
1748         kfree(xhci->usb3_ports);
1749         kfree(xhci->port_array);
1750         kfree(xhci->rh_bw);
1751
1752         xhci->page_size = 0;
1753         xhci->page_shift = 0;
1754         xhci->bus_state[0].bus_suspended = 0;
1755         xhci->bus_state[1].bus_suspended = 0;
1756 }
1757
1758 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1759                 struct xhci_segment *input_seg,
1760                 union xhci_trb *start_trb,
1761                 union xhci_trb *end_trb,
1762                 dma_addr_t input_dma,
1763                 struct xhci_segment *result_seg,
1764                 char *test_name, int test_number)
1765 {
1766         unsigned long long start_dma;
1767         unsigned long long end_dma;
1768         struct xhci_segment *seg;
1769
1770         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1771         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1772
1773         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1774         if (seg != result_seg) {
1775                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1776                                 test_name, test_number);
1777                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1778                                 "input DMA 0x%llx\n",
1779                                 input_seg,
1780                                 (unsigned long long) input_dma);
1781                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1782                                 "ending TRB %p (0x%llx DMA)\n",
1783                                 start_trb, start_dma,
1784                                 end_trb, end_dma);
1785                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1786                                 result_seg, seg);
1787                 return -1;
1788         }
1789         return 0;
1790 }
1791
1792 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1793 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1794 {
1795         struct {
1796                 dma_addr_t              input_dma;
1797                 struct xhci_segment     *result_seg;
1798         } simple_test_vector [] = {
1799                 /* A zeroed DMA field should fail */
1800                 { 0, NULL },
1801                 /* One TRB before the ring start should fail */
1802                 { xhci->event_ring->first_seg->dma - 16, NULL },
1803                 /* One byte before the ring start should fail */
1804                 { xhci->event_ring->first_seg->dma - 1, NULL },
1805                 /* Starting TRB should succeed */
1806                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1807                 /* Ending TRB should succeed */
1808                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1809                         xhci->event_ring->first_seg },
1810                 /* One byte after the ring end should fail */
1811                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1812                 /* One TRB after the ring end should fail */
1813                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1814                 /* An address of all ones should fail */
1815                 { (dma_addr_t) (~0), NULL },
1816         };
1817         struct {
1818                 struct xhci_segment     *input_seg;
1819                 union xhci_trb          *start_trb;
1820                 union xhci_trb          *end_trb;
1821                 dma_addr_t              input_dma;
1822                 struct xhci_segment     *result_seg;
1823         } complex_test_vector [] = {
1824                 /* Test feeding a valid DMA address from a different ring */
1825                 {       .input_seg = xhci->event_ring->first_seg,
1826                         .start_trb = xhci->event_ring->first_seg->trbs,
1827                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1828                         .input_dma = xhci->cmd_ring->first_seg->dma,
1829                         .result_seg = NULL,
1830                 },
1831                 /* Test feeding a valid end TRB from a different ring */
1832                 {       .input_seg = xhci->event_ring->first_seg,
1833                         .start_trb = xhci->event_ring->first_seg->trbs,
1834                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1835                         .input_dma = xhci->cmd_ring->first_seg->dma,
1836                         .result_seg = NULL,
1837                 },
1838                 /* Test feeding a valid start and end TRB from a different ring */
1839                 {       .input_seg = xhci->event_ring->first_seg,
1840                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1841                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1842                         .input_dma = xhci->cmd_ring->first_seg->dma,
1843                         .result_seg = NULL,
1844                 },
1845                 /* TRB in this ring, but after this TD */
1846                 {       .input_seg = xhci->event_ring->first_seg,
1847                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1848                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1849                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1850                         .result_seg = NULL,
1851                 },
1852                 /* TRB in this ring, but before this TD */
1853                 {       .input_seg = xhci->event_ring->first_seg,
1854                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1855                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1856                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1857                         .result_seg = NULL,
1858                 },
1859                 /* TRB in this ring, but after this wrapped TD */
1860                 {       .input_seg = xhci->event_ring->first_seg,
1861                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1862                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1863                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1864                         .result_seg = NULL,
1865                 },
1866                 /* TRB in this ring, but before this wrapped TD */
1867                 {       .input_seg = xhci->event_ring->first_seg,
1868                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1869                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1870                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1871                         .result_seg = NULL,
1872                 },
1873                 /* TRB not in this ring, and we have a wrapped TD */
1874                 {       .input_seg = xhci->event_ring->first_seg,
1875                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1876                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1877                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1878                         .result_seg = NULL,
1879                 },
1880         };
1881
1882         unsigned int num_tests;
1883         int i, ret;
1884
1885         num_tests = ARRAY_SIZE(simple_test_vector);
1886         for (i = 0; i < num_tests; i++) {
1887                 ret = xhci_test_trb_in_td(xhci,
1888                                 xhci->event_ring->first_seg,
1889                                 xhci->event_ring->first_seg->trbs,
1890                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1891                                 simple_test_vector[i].input_dma,
1892                                 simple_test_vector[i].result_seg,
1893                                 "Simple", i);
1894                 if (ret < 0)
1895                         return ret;
1896         }
1897
1898         num_tests = ARRAY_SIZE(complex_test_vector);
1899         for (i = 0; i < num_tests; i++) {
1900                 ret = xhci_test_trb_in_td(xhci,
1901                                 complex_test_vector[i].input_seg,
1902                                 complex_test_vector[i].start_trb,
1903                                 complex_test_vector[i].end_trb,
1904                                 complex_test_vector[i].input_dma,
1905                                 complex_test_vector[i].result_seg,
1906                                 "Complex", i);
1907                 if (ret < 0)
1908                         return ret;
1909         }
1910         xhci_dbg(xhci, "TRB math tests passed.\n");
1911         return 0;
1912 }
1913
1914 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1915 {
1916         u64 temp;
1917         dma_addr_t deq;
1918
1919         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1920                         xhci->event_ring->dequeue);
1921         if (deq == 0 && !in_interrupt())
1922                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1923                                 "dequeue ptr.\n");
1924         /* Update HC event ring dequeue pointer */
1925         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1926         temp &= ERST_PTR_MASK;
1927         /* Don't clear the EHB bit (which is RW1C) because
1928          * there might be more events to service.
1929          */
1930         temp &= ~ERST_EHB;
1931         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1932                         "preserving EHB bit\n");
1933         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1934                         &xhci->ir_set->erst_dequeue);
1935 }
1936
1937 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1938                 __le32 __iomem *addr, u8 major_revision)
1939 {
1940         u32 temp, port_offset, port_count;
1941         int i;
1942
1943         if (major_revision > 0x03) {
1944                 xhci_warn(xhci, "Ignoring unknown port speed, "
1945                                 "Ext Cap %p, revision = 0x%x\n",
1946                                 addr, major_revision);
1947                 /* Ignoring port protocol we can't understand. FIXME */
1948                 return;
1949         }
1950
1951         /* Port offset and count in the third dword, see section 7.2 */
1952         temp = xhci_readl(xhci, addr + 2);
1953         port_offset = XHCI_EXT_PORT_OFF(temp);
1954         port_count = XHCI_EXT_PORT_COUNT(temp);
1955         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
1956                         "count = %u, revision = 0x%x\n",
1957                         addr, port_offset, port_count, major_revision);
1958         /* Port count includes the current port offset */
1959         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
1960                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1961                 return;
1962         port_offset--;
1963         for (i = port_offset; i < (port_offset + port_count); i++) {
1964                 /* Duplicate entry.  Ignore the port if the revisions differ. */
1965                 if (xhci->port_array[i] != 0) {
1966                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
1967                                         " port %u\n", addr, i);
1968                         xhci_warn(xhci, "Port was marked as USB %u, "
1969                                         "duplicated as USB %u\n",
1970                                         xhci->port_array[i], major_revision);
1971                         /* Only adjust the roothub port counts if we haven't
1972                          * found a similar duplicate.
1973                          */
1974                         if (xhci->port_array[i] != major_revision &&
1975                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
1976                                 if (xhci->port_array[i] == 0x03)
1977                                         xhci->num_usb3_ports--;
1978                                 else
1979                                         xhci->num_usb2_ports--;
1980                                 xhci->port_array[i] = DUPLICATE_ENTRY;
1981                         }
1982                         /* FIXME: Should we disable the port? */
1983                         continue;
1984                 }
1985                 xhci->port_array[i] = major_revision;
1986                 if (major_revision == 0x03)
1987                         xhci->num_usb3_ports++;
1988                 else
1989                         xhci->num_usb2_ports++;
1990         }
1991         /* FIXME: Should we disable ports not in the Extended Capabilities? */
1992 }
1993
1994 /*
1995  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1996  * specify what speeds each port is supposed to be.  We can't count on the port
1997  * speed bits in the PORTSC register being correct until a device is connected,
1998  * but we need to set up the two fake roothubs with the correct number of USB
1999  * 3.0 and USB 2.0 ports at host controller initialization time.
2000  */
2001 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2002 {
2003         __le32 __iomem *addr;
2004         u32 offset;
2005         unsigned int num_ports;
2006         int i, j, port_index;
2007
2008         addr = &xhci->cap_regs->hcc_params;
2009         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2010         if (offset == 0) {
2011                 xhci_err(xhci, "No Extended Capability registers, "
2012                                 "unable to set up roothub.\n");
2013                 return -ENODEV;
2014         }
2015
2016         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2017         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2018         if (!xhci->port_array)
2019                 return -ENOMEM;
2020
2021         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2022         if (!xhci->rh_bw)
2023                 return -ENOMEM;
2024         for (i = 0; i < num_ports; i++) {
2025                 struct xhci_interval_bw_table *bw_table;
2026
2027                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2028                 bw_table = &xhci->rh_bw[i].bw_table;
2029                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2030                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2031         }
2032
2033         /*
2034          * For whatever reason, the first capability offset is from the
2035          * capability register base, not from the HCCPARAMS register.
2036          * See section 5.3.6 for offset calculation.
2037          */
2038         addr = &xhci->cap_regs->hc_capbase + offset;
2039         while (1) {
2040                 u32 cap_id;
2041
2042                 cap_id = xhci_readl(xhci, addr);
2043                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2044                         xhci_add_in_port(xhci, num_ports, addr,
2045                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2046                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2047                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2048                                 == num_ports)
2049                         break;
2050                 /*
2051                  * Once you're into the Extended Capabilities, the offset is
2052                  * always relative to the register holding the offset.
2053                  */
2054                 addr += offset;
2055         }
2056
2057         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2058                 xhci_warn(xhci, "No ports on the roothubs?\n");
2059                 return -ENODEV;
2060         }
2061         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2062                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2063
2064         /* Place limits on the number of roothub ports so that the hub
2065          * descriptors aren't longer than the USB core will allocate.
2066          */
2067         if (xhci->num_usb3_ports > 15) {
2068                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2069                 xhci->num_usb3_ports = 15;
2070         }
2071         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2072                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2073                                 USB_MAXCHILDREN);
2074                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2075         }
2076
2077         /*
2078          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2079          * Not sure how the USB core will handle a hub with no ports...
2080          */
2081         if (xhci->num_usb2_ports) {
2082                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2083                                 xhci->num_usb2_ports, flags);
2084                 if (!xhci->usb2_ports)
2085                         return -ENOMEM;
2086
2087                 port_index = 0;
2088                 for (i = 0; i < num_ports; i++) {
2089                         if (xhci->port_array[i] == 0x03 ||
2090                                         xhci->port_array[i] == 0 ||
2091                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2092                                 continue;
2093
2094                         xhci->usb2_ports[port_index] =
2095                                 &xhci->op_regs->port_status_base +
2096                                 NUM_PORT_REGS*i;
2097                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2098                                         "addr = %p\n", i,
2099                                         xhci->usb2_ports[port_index]);
2100                         port_index++;
2101                         if (port_index == xhci->num_usb2_ports)
2102                                 break;
2103                 }
2104         }
2105         if (xhci->num_usb3_ports) {
2106                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2107                                 xhci->num_usb3_ports, flags);
2108                 if (!xhci->usb3_ports)
2109                         return -ENOMEM;
2110
2111                 port_index = 0;
2112                 for (i = 0; i < num_ports; i++)
2113                         if (xhci->port_array[i] == 0x03) {
2114                                 xhci->usb3_ports[port_index] =
2115                                         &xhci->op_regs->port_status_base +
2116                                         NUM_PORT_REGS*i;
2117                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2118                                                 "addr = %p\n", i,
2119                                                 xhci->usb3_ports[port_index]);
2120                                 port_index++;
2121                                 if (port_index == xhci->num_usb3_ports)
2122                                         break;
2123                         }
2124         }
2125         return 0;
2126 }
2127
2128 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2129 {
2130         dma_addr_t      dma;
2131         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2132         unsigned int    val, val2;
2133         u64             val_64;
2134         struct xhci_segment     *seg;
2135         u32 page_size;
2136         int i;
2137
2138         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2139         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2140         for (i = 0; i < 16; i++) {
2141                 if ((0x1 & page_size) != 0)
2142                         break;
2143                 page_size = page_size >> 1;
2144         }
2145         if (i < 16)
2146                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2147         else
2148                 xhci_warn(xhci, "WARN: no supported page size\n");
2149         /* Use 4K pages, since that's common and the minimum the HC supports */
2150         xhci->page_shift = 12;
2151         xhci->page_size = 1 << xhci->page_shift;
2152         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2153
2154         /*
2155          * Program the Number of Device Slots Enabled field in the CONFIG
2156          * register with the max value of slots the HC can handle.
2157          */
2158         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2159         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2160                         (unsigned int) val);
2161         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2162         val |= (val2 & ~HCS_SLOTS_MASK);
2163         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2164                         (unsigned int) val);
2165         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2166
2167         /*
2168          * Section 5.4.8 - doorbell array must be
2169          * "physically contiguous and 64-byte (cache line) aligned".
2170          */
2171         xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
2172                         sizeof(*xhci->dcbaa), &dma);
2173         if (!xhci->dcbaa)
2174                 goto fail;
2175         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2176         xhci->dcbaa->dma = dma;
2177         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2178                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2179         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2180
2181         /*
2182          * Initialize the ring segment pool.  The ring must be a contiguous
2183          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2184          * however, the command ring segment needs 64-byte aligned segments,
2185          * so we pick the greater alignment need.
2186          */
2187         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2188                         SEGMENT_SIZE, 64, xhci->page_size);
2189
2190         /* See Table 46 and Note on Figure 55 */
2191         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2192                         2112, 64, xhci->page_size);
2193         if (!xhci->segment_pool || !xhci->device_pool)
2194                 goto fail;
2195
2196         /* Linear stream context arrays don't have any boundary restrictions,
2197          * and only need to be 16-byte aligned.
2198          */
2199         xhci->small_streams_pool =
2200                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2201                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2202         xhci->medium_streams_pool =
2203                 dma_pool_create("xHCI 1KB stream ctx arrays",
2204                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2205         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2206          * will be allocated with pci_alloc_consistent()
2207          */
2208
2209         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2210                 goto fail;
2211
2212         /* Set up the command ring to have one segments for now. */
2213         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
2214         if (!xhci->cmd_ring)
2215                 goto fail;
2216         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2217         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2218                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2219
2220         /* Set the address in the Command Ring Control register */
2221         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2222         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2223                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2224                 xhci->cmd_ring->cycle_state;
2225         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2226         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2227         xhci_dbg_cmd_ptrs(xhci);
2228
2229         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2230         val &= DBOFF_MASK;
2231         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2232                         " from cap regs base addr\n", val);
2233         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2234         xhci_dbg_regs(xhci);
2235         xhci_print_run_regs(xhci);
2236         /* Set ir_set to interrupt register set 0 */
2237         xhci->ir_set = &xhci->run_regs->ir_set[0];
2238
2239         /*
2240          * Event ring setup: Allocate a normal ring, but also setup
2241          * the event ring segment table (ERST).  Section 4.9.3.
2242          */
2243         xhci_dbg(xhci, "// Allocating event ring\n");
2244         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
2245         if (!xhci->event_ring)
2246                 goto fail;
2247         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2248                 goto fail;
2249
2250         xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
2251                         sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
2252         if (!xhci->erst.entries)
2253                 goto fail;
2254         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2255                         (unsigned long long)dma);
2256
2257         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2258         xhci->erst.num_entries = ERST_NUM_SEGS;
2259         xhci->erst.erst_dma_addr = dma;
2260         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2261                         xhci->erst.num_entries,
2262                         xhci->erst.entries,
2263                         (unsigned long long)xhci->erst.erst_dma_addr);
2264
2265         /* set ring base address and size for each segment table entry */
2266         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2267                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2268                 entry->seg_addr = cpu_to_le64(seg->dma);
2269                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2270                 entry->rsvd = 0;
2271                 seg = seg->next;
2272         }
2273
2274         /* set ERST count with the number of entries in the segment table */
2275         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2276         val &= ERST_SIZE_MASK;
2277         val |= ERST_NUM_SEGS;
2278         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2279                         val);
2280         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2281
2282         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2283         /* set the segment table base address */
2284         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2285                         (unsigned long long)xhci->erst.erst_dma_addr);
2286         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2287         val_64 &= ERST_PTR_MASK;
2288         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2289         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2290
2291         /* Set the event ring dequeue address */
2292         xhci_set_hc_event_deq(xhci);
2293         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2294         xhci_print_ir_set(xhci, 0);
2295
2296         /*
2297          * XXX: Might need to set the Interrupter Moderation Register to
2298          * something other than the default (~1ms minimum between interrupts).
2299          * See section 5.5.1.2.
2300          */
2301         init_completion(&xhci->addr_dev);
2302         for (i = 0; i < MAX_HC_SLOTS; ++i)
2303                 xhci->devs[i] = NULL;
2304         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2305                 xhci->bus_state[0].resume_done[i] = 0;
2306                 xhci->bus_state[1].resume_done[i] = 0;
2307         }
2308
2309         if (scratchpad_alloc(xhci, flags))
2310                 goto fail;
2311         if (xhci_setup_port_arrays(xhci, flags))
2312                 goto fail;
2313
2314         return 0;
2315
2316 fail:
2317         xhci_warn(xhci, "Couldn't initialize memory\n");
2318         xhci_mem_cleanup(xhci);
2319         return -ENOMEM;
2320 }